DIGITAL LAB - IMPORTANT QUESTIONS

1. Implement a 4:1 mux and 1:4 demux using logic gates.

2. Implement a flipfop to solve race around condition. (Hint: Masterslave JK ff).
3. Realize the function, F=Ӆm (0,2,4,6,10,12,13,15) using universal gates only.
(Hint: POS function, draw TT, draw kmap, solve & find out eqns, apply double bar on obtained
eqn, just aply de-morgans law to get eqn using universal gate only, draw the circuit).
4. Realize the function, F = Ʃm (1,3,5,7,9,11,12,15) using universal gates only.
(Hint: SOP function, draw TT, draw kmap, solve & find out eqns, apply double bar on obtained
eqn, just aply de-morgans law to get eqn using universal gate only, draw the circuit).
5. Implement a full subtractor circuit using universal gates & verify the output.
(Hint: draw TT, draw kmap, solve & find out eqns of difference & borrow, apply double bar on
obtained eqn, just aply de-morgans law to get eqn using universal gate only, draw the circuit).
6. Implement half subtractor circuit using universal gates & verify the output.
(Hint: draw TT, draw kmap, solve & find out eqns of difference & borrow, apply double bar on
obtained eqn, just aply de-morgans law to get eqn using universal gate only, draw the circuit).
7. Implement a set reset flipfop verify the output. Also realize the circuit using Verilog.
(Hint: SR ff)
8. Implement a circuit to prove De-Morgan’s law and verify the output.
(Hint: write the theorems, draw following, output of both circuit should be same.)

9. Write a Verilog code to prove De-Morgan’s law and verify the output.
(Hint: same as above, write Verilog code for both ckts & chk o/p)
10. Design and implement a full adder using 2 half adder.
(Hint: Hardware, draw circuit of FA given in part B, draw FA truthtable, draw kmap & find sum & carry
equations)

11. Write a verilog code to implement a 8:1 mux and verify its output.

(Hint: draw TT, ckt dia, write eqn given below, write code using eqn in dataflow model)
 12. Write a verilog code to implement a circuit to implement the function, F = AB’CD + ABC’D
+ A’BCD and check its output for any 3 input combinations.
13. Implement a toggle and delay flipfop using logic gates and verify its output. (Hint: T & D FF)
14. Design a 2bit comparator circuit to check whether A>B and A<B.
15. Design a 2bit comparator circuit to check whether A=B and A>B
16. Write a verilog code to implement a 2 bit comparator circuit to check whether A<B and
A=B.
17. Consider 3 input switches, A, B & C and an output led, F. Design a circuit to obtain the
following conditions:
a) when A, B & C is ON, F is ON
b) when A & B is OFF & C is ON, F is ON
c) when A is OFF, B & C is ON, F is ON
d) all other conditions, F is OFF.
(Hint: draw TT using given conditions, since 3 switches, take 3 input variables, since 1
led, take 1 output variable, put 1 for ON condition & 0 for OFF conditions, draw kmap,
solve, find eqn & draw the circuit).
18. Write a verilog code to implement a comparator & check its output conditions.
19. Write a verilog code to implement a 1:4 demux & draw its output waveform.
20. Write a verilog code to implement a 4:1 mux in structural modelling & draw its output
waveform.
21. Write a verilog code to implement the function, Y= Ʃm (2,3,6,7,10,11) & draw its output
waveform.
22. Write a verilog code to implement the given function using universal gate only & draw its
output waveform.
Y= Ӆm (0,2,3,6,7,10,11,13)
23. Write a verilog code to implement a half adder in structural and behavioural modelling &
draw its output waveform.
24. Write a verilog code to implement a 8:1 mux.
(Hint: draw TT & circuit given in above Q11, write following code)

Behavioural model pgm

module Mux(d0,d1,d2,d3,d4,d5,d6,d7,S,Y);
input d0,d1,d2,d3,d4,d5,d6,d7;
input [2:0] S; // array declaration select line is 3 bit- S0,S1,S2
output reg Y;
always@(S)
begin
case(S)
3'b000:Y=d0; // 3- bit size, b means - binary, value - 000
3'b001:Y=d1;
3'b010:Y=d2;
3'b011:Y=d3;
3'b100:Y=d4;
3'b101:Y=d5;
3'b110:Y=d6;
3'b111:Y=d7;
endcase
 end
endmodule

25. Implement a twisted ring counter using D ff. (Hint: Johnson counter)
26. Implement a circuit to shift a 1 in every clock cycle. (Hint: ring counter)
27. Design a counter to obtain the count 8,4,2,1,8,4,…
(Hint:4 bit ring counter: 1000,0100,0010,0001,1000…..)
28. Design a counter to obtain the count 0,8,12,14,15,7,…
(Hint:4 bit johnson counter: 0000,1000,1100,1110,1111,0111,…..)
29. Design a counter to obtain the count 4,2,1,4,2…
(Hint:3 bit ring counter: 100,010,001,100,…..)
30. Design a counter to obtain the count 0,4,6,7,3,1,0,…
(Hint:3 bit johnson counter: 000,100,110,111,011,001,000…..)
31. Design a 3 bit asynchronous up-down counter using JK FF.
32. Design a mod 9 asynchronous counter using D FF.
(Hint: count from 0 to 8, 4 FF required, draw TT & state diagram 0 to 8, from “9 -1001” onwards,
o/p should be 0000, so take Q0 & Q3 output of counter to a nand gate & connect o/p of nand gate to
clear input of all D FFs).

33. Design mod 7 synchronous counter using D FF.

(Hint: count from 0 to 6, only 3 FF required, draw TT, kmap, solve to get eqns for D0, D1 & D2,
draw ckt).
34. Design an asynchronous decade down counter using JK FF.
(Hint: count from 0 to 9, 4 FF required, connect Qbar output of each FF to next FF clk input for
getting down counter).
35. Design 3bit synchronous down counter using JK FF.
(Hint: count from 7 to 0, only 3 FF required, draw TT, kmap, solve to get eqns for J0, K0,J1,K1 &
J2,K2, draw ckt).