= \ = \ Gate-level Minimization Gote-Level Minimization The map mathad, Fourroriable map, Five-Voriatle map, prt of ews timplification, Don't-care conditions, NAND ond NO? lmplamernation. Other Two-tevel inglamactations, Exelusive-OR function. . _LEARNING OBJECTIVES - Use of karnough map to simplify Boolean expresins (upto 5 variables) NANO ond NOR implementation Y Other Two-level implementation: — Exclutive- OR function : (INTRODUCTION Kornaugh mops methods are used to simplify Boolean expressions and reduce number of variables. |42 24 THE MAP MI |ETHOD, Qi. Expiain K-maps in detall? Ans: Model Papers2, Q4(b) K- Map: Karnaugh map or K-map is a pictorial representation of a truth table. Itis a simple and straight forward method of minimizing Boolean expressions. ‘The K-map consists of squares and each square specifies a minterm or maxterm of the expression that is to be simplified. Thus, the minimized expression obtained from K-map also consists either sum of products or product of sums form at expression. Depending on the number of input variables, the number of squares in the K-map can be obtained as, number of squares = 2", n= number of input variables. For two-variable K-map, number of squares, =2e4 For three-variable K-map, numbers of squares, =2 z For four-variable K-map, numbers of squares, 16 ‘Two Variable K-map: For two input variables, there will be four minterms. Each minterm specifies a square in the K-map. Hence, the two variable K-map consists “of four squares. Figure I(a) shows the representation of two variable K-map. The relation between squares and the input variables “x” and ‘y’ is as shown in figure 1(b). Figure (1) In figure 1(b), the variable ‘x" is available in complemented form in row ‘0° and uncomplemented form in row “1”. In the same way, the variable ‘y” is available in complemented, form in column ‘0° and ‘uncomplemented form in column ‘I*, For example, the Boolean expression, ‘f= y+ xyisrepresented in two variable K-map as shown in figure (2). ‘ y Sin Ko im, ° 1 mf xf 1 DIGITAL ELECTRONICS LINTU-HYDERABAp, FOUR\VARIABLE MAP, FIVE.V > SUMS SIMPLIFICATION, DON'T-CARE CONDITIONS Three Variable K-Map For three input variables, there will be eis *) minterms. Each minterm specifies a square in ty K-map, Hence, the three variable K-map consists eight squares. Figure 3(a) shows the representation of, three variable K-Map. In the K-Map, the minterms are arranged in a sequence similar to gray code ( the code iy which only one bit will change from one column to th next adjacent column), instead of in a binary sequence ‘The relation between squares and the input variables ‘| ‘y’ and ‘2’ is shown in figure 3(b). 2 x\ bo ol fi x{o] xyz | zz xye] mg] | 5] {of xvz | zy: [xx [ sz mlm fafo| xf tfre | ve | oe | we (a) _-__ For example, the Boolean expression , f= 17 is represented in three variable K-map as shown in figure (4). yz *\\ 00 or mm, 0 ot im, [m,_| m, ; ; ‘ ve Figure (4) ‘| ‘Therules for simplification of Boolean expr | using K-map by grouping together a : ‘ones or zeros are mentioned below, "Cells 1. Grouping has to be done by ine! cells containing a one (ie for signs 8aiacent zero (ie, for maxterms) interms) oF 2: Grouping must be either hori but not diagonal 3. Grouping must contain2*cels(ie.int, 93) ice., a group will contain two 1's, fs 23 Tete. fours, ight 4. Preference must be given to large gro, sible) to obtain minimized Boolean = Gif pos- 8 cell group instead of 4 cell gg, es8ion sroup instead of 2 cell group), 4 cell 5. Allone's or 2r0'sinthe K-MEP MUSt be in gues fone group. rae ‘Ontal or vertical,Gate-level Minimization NIT a2. Ans: (2) minterms. Each minterm specifies a square in the K-map. Hence, the four variable K-map consists of sixteen squares. ! The representation of four variable K-map is shown in figure (1). m, | m, m, i m, | m, ™, M. | Ms | Ms | Me ™ m, | Mo Figure (1) In the K-map, the minterms are arranged in a sequence similar to gray code with only one bit change between two adjacent rows (or) columns. The relation tetween squares and the input variables ‘w”, x’, ‘y' and ‘2 is shown in figure (2). OL wry al ™ | ™ m | ™ wget [wy | waye_| wat | 7% nf ™: | ™ m | wo) aya! | vny'z | veo _| voy! io (areca | eee | a way’ | wx'y'z | weve | OT + Figure (2) «The mapping procedure of four variable K-map issimitarto three vmable K-map. Moreoves, inthis fou Yatiable mapping itis assumned that top, bottom. right and Let edges lie on a surface and touches each other 10 form adjacent squares ne Example: Minterms mand m, forms a pait- — aan 43 ‘Overlapping of groups is allow Q3,__ Explainin detail about five variable K-maj 7, Inthe K-map, the left most cell in a row can be Ans: grouped with the ht most cell andthe top cell ‘+ A five-variable K-map has 2° = 32 numbers of ina column can be grouped with the bottom cell, Se eee Ina K-map, the number of po earee ae s. , roups must be as |g is fo te sninimonn a posible such that it doesn't violate | 4 6¥€ variable K-map is forme y using S69 Gree rile : four variable maps as show in igure. = Ae 1 Keo oe = four Variable K-map peBR Geos’ ve pe DE Be or ve For answer refer Unit-2, Q.No, 2. bev _oL 10 Cr rive Variable Kemap : els wo 16] 17] 19] 18 For answer refér Unit-2, Q.No. 3. als] 1] 6 Be | 20 zu} 23] 22. Explain four variable K-map. pe uf ial asf asf is] BC [28] 29) 31] 30 BC 10 to} BC 10] 24} 2s} 27] 26) For four input variables, there will be sixteen |” — Figure To differentiate between two maps, variable A is placed at the top of the maps. ‘The map at the left hand side’has A value as 0 ‘and map at the right hand side has A value as 1. ‘The grouping of terms is done by identifying the adjacency. ‘The best way to perform mapping in five variable K-map is by conSidering that the two maps are superimposed on one another. ‘Thus, it becomes very easy to identify the adjacency between the maps. Explain in brief about, (a) Grouping of two adjacent ones (pair) (b) Grouping of four adjacent ones (quad) Grouping of eight adjacent ones (octet). : (c) Ans: @) a >I Grouping of Two Adjacent Ones (Pair): A ‘group of two adjacent cells of a K-map forms a « Dair. It eliminates one variable in simplification. by K-map. Example: Figure (1) represents the grouping of. ‘two adjacent ones in three variable K-map. BC. BE Be gc ou rd 0 10 0 o| xBC) Be qT Pair (1) (AB) [Pair 0) z Pair (2)~ In figure (2), four group of pairs are formed. But out of these four pairs only threé pairs are required and fourth pair formed by minterms (5, 7) isnot required because the minterms 5 and 7 are already paired with mintems) 1 and 6 respectively. The simplified expression for three variable K-map is, y~AB+BC+AB 3... Figure (3) represents the grouping of two adjacent ones in four variable K-map. coed ‘cp CD cp 00 OL i 10 | | 7 | 0 ABO! 4 | pot} o.‘| | AB : | ww] 4 | { | <.y=BCD+BCD ie ee i aedMinimization > “og of Four Adjacent Ones (Qu Wes evo variables in simplification of Er Broup of four adjacent cells limi He ‘ po! ae (4) presents the grouping of fur adjacent ones in thee varia i BoBE Be Be Be aA\_® ot ono les K-map. Fololololo f°]? atl) fa [a Pitta 2 a. Figure (4) y =A BC+BC+BC+8C) = 4(B(E+0)+3(C+0) =A (B()+B() = 4 (B+B) =A(1) 2. Figure (5) represents different examples of quads in four variable K-map. cea tcp OD cD t co {co a\_@ o_o a\_oo| or St. [50 7 yy 4 | Ro) o | o Jf) | obey om] i ilo | o fhe = 55 4] 5| 7 6 4 s 7 6 eo] 0 0 1 ° o] o T [*] ° al] fs] ae Bll al hs ven! o~| ozs fa] | o alo [ta ta Le - tal 3} 3} a B10} 9 ° fi i 10) 1 o | o 1 i" o D> om oto 2 E ope a cpcD Cp cD cD o1_ii__10 o | o 0 AB 1) 3) 2 ABoo s[. a] ane o| oo o jo 0 ot 5} 7] 6 ABOL 0} ol o ns) 14 BEL ? 0 T ° ABIL Tit pH} as Ju} T 10 t 8} 9) | dil prop AC Orley Wer B10] 9 *|] 1 >ADNICS LINTU-HY! DIGITAL ELECTRO! DER rik group of eight adjacent cells in Kemap forms sy > fe (©) Grouping of Eight Adjacent Ones (OF 1 reduces four variables to a single variable. ele variable K-map. Figure (6) illusteate the various examples of octets in four ae ad wm @ co & 1 __0 un 10 3 2 av\_20__o ~ i T 7 3 pale xB} 9 | o | o | o z asl Pp _< |__| i zoo} o | fr | t ot, wolf fe a rm ya) tye” A ie apnfle foo fr fa apt] o ° iil 10 2 7 ut of 8 yy ° sie] ‘leo lo | o amo} o | (a (b) or Gea i > ow o co 83% cD oO uo] Ap\__00__ ol au ™T 372 7 rT 3 eels B00} 4 o fo fa espa alana] alaespsi esa | wee ma] o fo} o | o won| i} foo fo |ya a) as) a “jal af asl | od ABI 0 oO o 0 ABIL] 1 0 a 1 * sacra eels | Fos a) 10) fp a fa ; Biol 1 Gallet i DB 5 ©. . @ Figure (6): Forma f(i, J, k,l) = £(4, 6, 7, 5, 3, 15). Ans: The given Boolean expression is, Y = Em(3, 4, 5,.6, 7, 15) As the given Boolean expression contains the highest product term as 15’, four variables. Thus, the given four variable Boolean expression can be simplific mm of Octets in K-map Q5._ Simplify the following Boolean expression using 4 variable maps. Ch oto ‘ pop in oof Of 3 2 Lei] 7] 1+> ij ot| a" STP a6 1 > jkl ute ols ap? woL_8} 9] ul 10 Therefore, the simpliied Boolean expression is, Rij O™ y+ T+ jt, Ee he ab "which can be represented it d using four variable Km?05% given Boolean function is, PUA, B.C, D, EY= EO, 2.4, 6,9, 13,21, 23, 25,29, 31) asthe given expression isa function af five v gsi FUE: bles, which can be simplified using five variable K-map 4 Aso + . ‘ Bone cae poe AT! ool 1 rp ABS oleae eee 00 an tel 1719] 1g Aalst a] Us - ot play 5 Fi 2o| |" 21] _aslfa3p" ACE 1 u 5 1 . ts isl 2el(P]2o} "sall so sil"| of _ul_ io] to y wpe <—L2ltbs| ar] ad Figure ‘The simplified expression is given as, . f= ABE + BDE+ACE a. Define SOP with example. ‘This expression has three sum terms, with one, nan ‘wo, and three literals. The product is an AND operation sumof Products (SOP) Following steps are used in K-map for SOP. The sum of products (SOP) is a Boolean | 1+ Define the given expression in canonical form. expression containing AND terms, called product terms, | 2. Dawa K-map in which all maxterms are marked wih one of mote literals each. The sum denotes the 0's in the K-map cell. Mark remaining cells with ‘ORing of these terms. Vs. : Brample: F=y' tay +ay2! 3. Then group the cells that have large number of F 0's following the grouping rules. The expression has three product terms, with Pete eee, ove, two, and three literals, Their sum is, in effect, an | 4 Obtain the Boolean expression of each group. (OR operation, 5. Derive the Boolean expression for the output. It Felling Steps are Used in K-map for SOP is obtained by combining the product terms ofall individual groups. |. Define the given expression in canonical form.. | peample 1: Y= (4' +B) + (A'+B)+ (A+B) 2. DrawaK-map in which all minterms are marked 4 B 1'sin the K-map cell. Mark remaining cells with. X_2 0s. o| @ [Ho : 3. Then group the cells that have large number of 1 1's following the grouping rules. aja {0} 4 Obtain the Boolean expression of each group. 2 2 Derive the Boolean expression for the output. It | _\ Simplified expression is obtained by combining the product terms ofall | Example 2 , : ~~ individual groups. P=(A+ B+ C)+(A+B+C)+ 08. "Define POS with example. (A+B + OHA'+B HC) a SS oo or 10 Products of Sum (POS) san easel cons. + Product of sums is a Boolean expression se 2s OT Id nsning OR terms, called sum terms. Each term may $716 Nyy Number of literals. The product denotes the : yor} a |e fe) Ding of these terms. Mi Exampl Simplified expression is, Y= (4+ C)(A'+B) nor rie ty bz ; SPECTRUM ALL-IN-ONE JOURNAL FOR ENGI JEERING STUDENTSDIGITAL ELECTRONICS [JNTU-HYDERAR,, 8 eee oer Example 3 Fld, BCD) = n(3, 8,7, 8, 10, 11, 12.13) toa to of tf tf Plato oat 0] | , P 12 ) 10 ut v 5 (t+ C+D)(A+C+D)(B+C+D)(A+B+O) EE RONEN CH DYATB +O) as. Ans: @ implify the following Boolean function into, @ ) ‘sum-of-products form and Product-of-sums form and implement the simplified functions using AND, OR gates. F(A, B, C, D) = (0, 1, 2, 5, 8, 9, 10). Mode! Paper2, a4) ‘The given Boolean expression is,. (4, B, C.D) =¥ (0, 1,2, 5,8,9, 10) ‘Sum of Products Form ‘The simplified sum of product expression for the above function can be obtained using 4-variable K-map as shown below. ‘ACD fu r 3) 3 76 0 2a] as] wih) | Hl st Jol ufo Pepe Then, the simplified sum of product expression is represented as, The implementation of simplified 4, B, C, _D) using AND and OR gates'is as shown in figure (1). (Foe ond FABRE) BC Figure (1) Products of Sum The product of sum expression of the given Boolean expression is, tA; B,C, D) = (3, 4, 6, 7, U1, 12, 13, 14, 15) ‘The above expression can be minimized using 4-variable K-map as shown below. cp ABN 00 ol_ul__10 fo] tol alt |s| 2} 7a 0 ol fo or tal si tall 6 a 0 fol fro} fea-s 13. 1s, 14 0 ‘ 10 . 8 9 uu 10 Y aD ‘i i Then, the simplified product of sum expression is represented as, ‘The implementation of simplified f(A, B, C, D) using AND and OR gates is shown in figure (2) A BOC Ds } lz i B+D A+B | Figure (2)goto-level Minimization Gon't care map ent cor nor at 1c binations for which the value of function gee fede called don tear gombin er y scopy xcified functions. an ies wich doesnot have any effect stem, on its occurrence are relerred as «Map Entries (o") Don'rcare conditions. yisdented by dor® ord symbol enue of don"t care can be Wor | formaxterm dais sity the following Boolean funct ait. Teter with don’t care conditions d, ABC.0) =Em(0,6,8,13, 14) + Ea, 4,10) Model Paper-1, 4a) Jutyug-21, (R18), 23 MB] espectively ansi The given Boolean function is, FIA, B, C, D) = £(0, 6, 8, 13, 14) dd, B, C,D) = 3(2,4, 10) Ans: Given Boolean function is, ‘The complete Boolean fur F(A, B, C,D) = 310, 6, 8, 13, 14) + EA2, SOP Form Equation (1) is in standard SOP form. Hence, it can be simplified using 4-variable K-map as shown in figure. cp AB See ee) BD aBcD cD Figure +. The simplified expression is, +ABC D+ Gi Reduce the following function using K-map. F(A, B, C, D, E) = Zm(1, 4, 8, 10, 14, 20, 22, 24, 25) + d(0, 12, 16, 17). (A,B, C, D, E) = 2m (14,8, 10, 11, 20, 22,24,28,26) + d(0, 12, 16,17) ‘ ‘This function can be simplified using S-variable K-map as shown in figure. Se A=0 pe DE DE pe DE peDE DE pe bE . itp <2) a 10 oN Leo io TLL e BE 00 0 1 3 2 BE 00 I 19 3 Fc of Mem ahs ‘steal ae aad Ben} i BCI 12] B 15 J} 28} 29) 31 3 Bt10| 1 fot pewlfr | a 78 9} fail 19} oe 2a]__|2s}" 27] 26 nay ¥ acp* : ADE ABCD Figure ci AT ABCD 2Q0,22)= AB CE 20,4,8,12)= 2D * The simplified expression in sum of product form iss AeTD+AC D+A D E+BCD50 DIGITAL ELECTRONICS [JNTU-HYDep, Q13. Write the advantages and disadvantages of K-may Ans: Advantages 1, K-map is very simple and fast in simplifying expressions upto four variables, 2. Ido not require Boolean laws. 3. Is suitable for minimization of SOP and POS forms of expressions, 4. Its suitable for fast identification of prime implicants and essential prime implicants. 5. Itprovides visual method for logic simplification Disadvantages 1, Coniplexity increases as the number of variables increases. y 2. Its not used for computer reduction 2.2 "NAND AND NOR IMPLEMENTATION .Q14. Give the symbolic representations of NAND gate and other basic gates with NAND gate. Ans: Mode Papert, a4(b) Figure (1) depicts two NAND gate equivalent ‘graphic symbols. The AND-invert symbol is made up of an AND graphic symbol and a tiny circle negation indicator calleda bubble. A NAND gate can also be seen as an OR graphic symbol with a bubble in front of it in each input. The NAND gate's invert-OR symbol follows. both to.DeMorgan's theorem and the convention that complementation is'indicated by the negation. eG xity'+2'= (xyz)! ED a! 2 z (0) AND‘avert 1b) Invert OR Figure (1) Figure (2) represents the basic gates using NAND sates. Inverter x AND y— ny gto OR [ — Qyy=xy y—Pe Figur 2) i ea, Write the procedure for two lew mentation of Boolean functic NAND gate. Explain with in exanpthy "| Initially, the Boolean function is simp expressed in terms of sum-of-produers using K-map. 2. In the nest step, AND-OR diagram simplified Boolean funtion i dav, Ty level of this circuit consist of AND gates _ produces product term, andthe secon consists of OR gate which gives sum term.” ta ly, the two level implementation of Boge funetion using NAND gates is performed replacing the AND gates with NAND gate. AND-invert graphic symbols) and the OR gx’ with and invert-OR graphic symbol The two level implementation of a Boole, function using NAND gate requires the function ty in sum of product form. Example Consider the Boolean function, F=AB+CD z (i The function implemented in AND and OR ge is shown in figure (1). OF =e) Figure (1) ‘The AND gates are replaced by NAND gatesse! the OR gate is replaced by an OR-invert graphic symta| as shown in figure (2). ast a— co pv Figure (2) . The Boolean function can be depicted replacing the AND-OR invert graph symbol io ft Q) with NAND gate as shown in figure (3) a PS ; pe Figure (3) $$ itGote-level Minimization e fy tho following Boolean functions, 2 Sig four variable Karnaugh map stnod and imploment the simplified jon using NAND gates, c,D)=2(0, 2, 4, 5, 6, 7, 8, 10, 13, 18) we functl FAB: 2 Novs0ee.20,(R1), 038) M9) ans? Given Boo dB. C.D) = 210, 2,4, $, 6,7, 8, 10,13, 15) Jean expression is, of above function using 4-variable simplifca expen i 25 f11S, o so ee J 2 sh : 3 —a- + mt TY ' a q 15] 14] . : 1 > BD Fe a 1 ite = >BD asp al sk)! ny . 1 > ABCD 12] 13] 15) 14] : 1 to 8 9 u 10) The simplified function is given as, F(A, B,C, D)= A BC+ ABD + ABD+ABCD Q18. Find F in POS form for F(A, B, C, D) = TI(4, 3, 7, 14, 15) + d(0, 2, 5). Ans: ‘Aug sSep.-2, (R18), Q3(a) MI7] The given Boolean function is, - F(A, B, CD) =11(1,3, 7, 11, 15) +4 (0, 2, 5) ‘The given Boolean function in POS form can be simplified using a 4-variable k-map as, cD AN’ o_o 0 0 | CE eb ace WS a ~ Io “Leen a[ “sll |} 6 il “ile vp] sth his} is a 0 wos} of nt 10 ‘The cells, 0, 1, 2 and 3 form a quad and given. 4 output as 4 + B. ‘+ Thecells 3, 7, 11 and 15 form a quad and given output as C+D +, The simplified output of Function, F in POS to implement an example. multilevel NAND circuit Ans: To implement a multilevel circuit, initially, the Boolean function is expressed in terms of AND, OR and complement operations then, the function is implemented by asing AND anid OR gates. Ifrequired, itcean be converted into an all-NAND circuit. ‘The general procedure for converting a multilevel AND-OR diagram into an all-NAND diagram using mixed notation is as follows: _ ed tinsmy 52 Convert all AND gates to NAND gates with AND-invert graphic symbols. 2. Convert all OR gates to NAND gates with invert- OR graphic symbols. 3. Check all of the bubble in the figure. Insert an inverter (a one-input NAND gate) or complement the input literal for each bubble that is not complemented, by other small circle along the same Tine. For example, consider the Boolean function, , F = (AB'+ 4'B)(C+D) as »— act B c > (a) AND.OR Gate as a — . as () HAND Gate Figure Q20. Give the symbolic representations of NOR gate and other basic gates with NOR gate. Ans: The NOR operation is the dual of the NAND operation. Figure (1) depicts two NOR gate equivalent graphic symbols. The NOR operation is defined by the OR-invert symbol as an OR followed by a complement. The invert-AND sign performs an AND operation after complementing each input. Based to DeMorgan's theorem, the two symbols represent the same NOR operation and are logically identical x (xtytz) x. x'y'z' = (xtytz)’ : pS y 4 (a) ORAnvert (b) Invert AND Figure (1) Figure (2) represents the basic gates using NOR gates. Inventerx —De————* “ sy xt on $e ety * Ye O+yy xy y Figure (2) AND DIGITAL ELECTRONICS [UNTU-HYDERa, ‘Q21. Write the procedure for two le mentation of Boolean function, gates. 1 vel ny i us “Ng Noy 1, Initially the function is simplified and ex interms ofproduct-of-sum form by wing Inthe next step, the OR-AND diagram fy simplified Boolean function is drawn, ot level of circuit consists of OR gates which ¢™ sum term, andthe second level consists of gates whtich gives product term, 3, Finally, the two level implementation of Bool function using NOR gates is performed replacing the OR gates with NOR gates ge! ORinvert graphic symbols) and the AND gay is replaced with an invert-AND graphic syn Explain about the twolevelimplementatay of the Boolean function using NOR gates Ans: A two-level implementation of the Boole: function using NOR gates require the function tot expressed in terms of productof-sums form, which be obtained using K-map. 4 ThePOS terms are implemented with OR guest first level for sum terms and AND gates atsesm level for product term. 4 The OR gates are converted to NOR gates wit OR invert graphic symbols. 4 The AND gates are converted to NOR gates wi invert-AND graphic symbol. > The variable E is complemented to compensit for the third bubble atthe input of seconde! gate, Example: Consider the Boolean function, F=(4+B)(C+DE ~() ‘The OR-AND diagram of equation (1) sassbo*™ in figure (1). (a+ s—D— spe pocucaiees| Figure (1): OR-AND Ga Q [D— is ‘The NOR implementation of the equation () as shown in figure (2). iat Figure (2}: NOR Implementation of the Boles” Fue Fe(k+B)(C+D)E aw11-2: Gate-level Minimization Explain the. procedure to Imi 25: uitilevel NOR circuit with an can ample, 7 Meas ast : apart, as ‘to implement a multilevel circuit intieny _ poolean funtion is expressed in tems of ANS? 3 and complement operations then, the fnetion mented bY using AND and OR gates, Irrequred be converted into an all-NOR circuit, : ‘The general procedure forconverting amuhievel anp-OR dingram into an allsNAND diay Ataton is a follows Convert all AND gates to NOR gates with inverte AND graphic symbols, Convert all OR gates to NOR gates with OR- invert graphic symbols, Check all of the bubble in the figure. Insert an inverter (a one-input NOR gate) or complement the input literal for each bubble that is not complemented by other small circle along the same Tine. : : For example, consider the Boolean function, F=(A4B)(C+D)E Figure (1) shows the NOR implementation. =Pal i_S imple inca gram using goo> F Figure (1) Consider the Boolean function, F=(4B+AB)(C+D) This conversion of AND-OR diagrain intoaNOR diagram is as shown in figure (2). th > Ly Figu 24, Implement the following Boolean function F, using the two-level form logic (a) NAND-AND (b) AND-NOR (ce) OR-NAND F(A, B,C, D) = £(0, 4, 8, 9, 10, 14, 12, 14). ns: * model Paper-2, 05(8) The given function is, FA, B,C, D) = E (0,4, 8, 9.210 ne oh In order to implement the above function SEND-AND, AND.NOR and OR-NAND, weave fo —Plfy it using K-map as shown below, @ ) © 53 FU, B,C,D)= AB+AD +CD NAND-AND Implementation: The simplified function can be represented as, FA, B, C.D) = AB+AD+C D = (AB)(AD)AE D) ‘The implementation of above function using NAND-AND logic is shown in figure (1). a af > F Cpt Figure (1) AND-NOR Implemeniation: The simplified function can be represented as, F(A, B,C,D) ‘The implementation of above function using AND-NOR logic is shown in figure (2). (4B).(AD).(C D) Figure (2) OR-NAND Implementation: The simplified function can be represented as, Fld, B,C,D)= AB+AD+C D = (AB).(AD).(C D) FIA, B,C, D) = (4+B)(A+D)(C+D) The implementation ofabove function using OR- NAND logic is shown in figure (3). =p, oR Figure (3)DIGITAL ELECTRONICS [JNTU-HYDER,, cuit for . AND Se, multiple level NAND 25. Draw tt 025. the following expressio! ee " "+ CD" (A+B) (aB' + CDE + BC 2 Ans: NovJ0c-20, (R18), 4a) M7] (3. NANDand ‘The given Boolean expression is, 4. NOR. alae nrmor al Depending on the type of gates used ig and second levels total 16 two-level combina = Afi + CDE.+ BCU +1) Fe ABE sgt possible, They are as shown in table below, = ABE + CDE +BC[y 1+x=1] revel Combinations ‘Thus, pee rek AND. ‘OR NAND NOR AND.AND | ORAND | NAND-AND [ Nora ‘AND-oR | OR-OR | NAND-OR | NoRoy (ABE).(CDE).(BC) | AND-NAND| OR-NAND | NAND-NAND | NOR-Nang] (ABE+CDE+BC) + Then the above simplified Boolean expression | | aND-NOR | OR-NOR | NAND-NOR | NoR:No can be implemented using multiple-level NAND circuit as shown in figure (1). Table ‘Table depicts the total sixteen combination og of which eight combinations are in degenerate forma remaining eight are in non-degenerate form. - () Degenerate Form =. The combinations which degenerate to a sing ‘operation are said to be in degenerate form. Example: AND-AND implementation. In this implementation, at both the levéls AN) gate is used. Thus, the output will be the AND func of all input variables. (ii) Non-degenerate Form i tations. implement ‘The combinations which does not degeness Ans: a single operation are said to be in non-degenerate &) “There are many two level implementations based E ee : con the typeof gates used in fist and second level. The ee San oa pov of gates whichare sed fordierenttwolevel The output of this implementation isin entations are, product form, which is nota single operation. about t implem 27. Exp! \ND-OR-Invert and OR-AND-INVERT implementation. Ans: : _ : AND-OR-INVERT Implementation ‘To implement an AND-OR INVERT function, the Boolean expression has tobe expressed in terns") ‘of-product form. When the complement of the function (i.e., F') is expressed in the sum of product form theo it? be easily implemented by using AND-OR gates. The normal output F can be generated by passing (F') the output inverter gate, which complements the Function and gives the desired output functign (ie., ‘The NAND-AND and AND-NOR forms are used to perform the AND-OR-INVERT function. Example: Consider the Boolean function,65 Se] Ae — u

° 9 =(AB+CD+E)" (©)NAND-AND 5 0 ire (1): ANO-ORANVERT Circuits, F = (AB + CD + Ey’ All three cireuits shown in figure (1) implement the same function. Figure 1(b) is formed by replacing. «equivalent graphic symbol of NOR gate, and figure 1(c) is formed by moving the bubble from the second level gate input terminal to the first level input terminal. : Thus, by observing all the outputs of the circuits shown in figure (1), i is clear that, all circuits implement tie AND-OR-INVERT function, : ie, F = (AB +CD+ Ey OR-AND-INVERT Implementation : To implement OR-AND-INVERT function, the Boolean function has to te expressed in terms of product-of-sum form. When the complement of the function is expressed in product of sum form, then F’' can be implemented by using OR-AND gates. Finally, when F * is given to the inverter gate it gives the complement of F''ie., (F") = F) and F is obtained at the output. The two forms OR-NAND and NOR-OR performs the OR-AND-INVERT function. Example : Consider the Boolean function, F=[(A +B) (C+D) E},, which is implemented by using OR-NAND and NOR-OR circuits as shown in figure (2), ' - avy ye B, . 2 Ss Heid Fo aay (cHDy+E) poe |e © ‘ © ? aot Scat) > B «cry! co F = (A+B)'4C+D)4E'] D. (A+BXC+D)EY o Figure ( Fol From figure 2(a),2(b) and 2(c),itean be noticéd that, al circuit ie, F = [4 +B) (C+D) ET c D. E (C+D) 056 Q28. Draw logic diagrams to implement the following Boolean expression, (a) Y=A+B+B(A+C) (b) Y= A(B EX-OR D)+C" (ce) Y=(A'+ BY (C+D) (d) Y= [(A + BY) (C+ D)) Ans: @) Y=A+B+B(A+C) The given Boolean expression is, Y=A+B+B(4+C) The implementation of above function is shown in figure (1), je eee eoeeee, 2 E ae j Jiracy imey Figure (1) 7 (b) Y=A(@BEX-OR D)+C' The given Boolean expression is, Y=A4(BEX-ORD)+C The implementation of above funetion i shown in figure (2), A. \ AB © D) B (B @ D). “ » D c ” Figure (2) @ Y=(A'+B)(C+D) ‘The given Boolean expression is, Y= (C+ B) (C+D) ‘The implementation of above function is shown in figure 3). ADT ca 9 a—f [}t c (+p) D Figure (3) @ Y=((A+B)(C'+D)). The given Boolean expression is, DIGITAL ELECTRONICS [JNTU-Hy, The implementation of above fun, figure (4), Figure (a) zB. Without reducing, implement thetaisa. expressions in AO! logic and then com! them into NAND logic and NOR fogie (), A+BC+(A+B'C)+D ji) A+BIC+(B+Cy +B. B G D Ans: ‘The given Boolean function is, F=A+BC+A+ BC +D The above function can be implemented ws AOI logic as shown in figure (a). {7 {BC ny Be Figure (a) Conversion of above AOI Logic into NAND Logic Step-4 : Add bubble tothe output of each AND gate and all the inputs oF OR gate as show m in figure (b). ¥=(4+B)(C+D)Figure (d) conversion into NOR Logic ep Add bubble 12 ‘ouput ofeach OR gate and all the inputs of AND gate as shown in figure (e). Bo——_4 Figure (e) Step-2 : An inverter is either added or subtracted on each line to which a bubble is added in step-1. The inverter isadded or subtracted in order to maintain the polarity of signal unchanged with respect to the original diagram. Figure (t) Stép-3: Replace bubbled AND gates and NOT gates by NOR gates as shown in figure (g). A58 DIGITAL ELECTRONICS [JNTU-HYDERA, (@®__ The given function is, Fx A+BC+BFC)+ BC The above function can be implemented using AOI logic as shown in figure (h), A B BHON OFT co Bc Bo Be te+__| Figure th) Conversion Into NAND Logic Step-1 : Add bubble to the output of each AND gate and to all inputs of OR gate, which is shown in figure (), Ao : co Ly 5 se : BE t-—__ Figure (i) ‘Step-2 : An inverter is either added or subtracted on each line to which a bubble is added in step-1. The invenet is added or subtracted in order to maintain the polarity of signal unchanged with respect to the original diagram, Ao—po—_* ’ Figure (j) Step-3 : Replace bubbled NOR and NOT gates by NAND gates as shown in figure (k). x Figure tk)12: Gate-lovel Minimization 59 we jon into NOR Logic com aaa ‘ 2 up Adz bubble all he nut oF each AND gate and ouput ofall OR gate as shown in igure (D- B Bee, pec ‘ “ c — BC = 2 : Be t-___] Figure (t) siep-2: An inverter is either added or subtracted on each line to which a bubble is added in step-1. The inverter js added or subtracted in order to maintain the polarity of signal unchanged with respect to the original diagram. ape TSS: ee >) - Figure m) i Step-3 : Replace bubbled AND gates and NOT gates by NOR gates as shown in figure (n). F cs Figure (a) i . Boolean equation for output of an X-OR gate? What Is symbol for it? re : ‘Model Paper-t, a(b) ; that consists of two or more inputs but one output. EX-OR gate performs itput. The logic symbol of X-OR gate is as shown in figure, EX-OR gate is a special logic gate ‘culo - operation between input to get ou60 is shown in table, The truth table of Ty peasey — 4 0 ot 1 " ry} o 1 1a 0 Table ‘The X-OR gate output is high only if one of the input is 1 otherwise, its output is low ie., 0. For odd number of 1's, output Q31. What is the unique characteristics of the XOR gate? Ans: XOR (Exclusive OR) Gate ‘An XOR gate has two inputs‘and one output. Characteristics of NOR Gate ‘There are seven properties of XOR gate. They areas follows, Property 1 A@A=0 ‘When two inputs aresame, the output generated is logic 0. Example 0e0 181 Property 2 A@A When two inputs are different, the output generated is logic 1. Example oe1 160 Property 3 A@1 = A(EX-ORas inverter) ‘The output of the EX-OR gate generated when one input is connected to logic one is the complement of the other input. Input [16 ‘I = |r connected, ‘complement of to logic 1 el ia =.9) the other input Other input Property 4 A® 0=4 (EX-OR as non-inverter) When one input of EX-OR gate is grounded (ogic 0), the resultant output will be the other input. y DIGITAL ELECTRONICS [JNTU- HYDERARAy Other input Inputis fo @. 0 =i0 grounded { t Output isthe (logic) [O'@ 1 = 1f other inpuy Property 5 EX-OR as modulo 2 adder. As the truth table for EX-OR is similar to thy, the modulo-2 adver, it ean be used a8 a modulo 2 ayy ' 0@0=0 o+1=t 0@1=1 = 180-1 1+1=0 1@1=0 Modulo? adder EX-OR Property 6 (PQ) ® (PR) = P(Q® R) Property 7 IfP® Q=R, then P@R=0 Q@R=Pand : P@Q@R=0 Q32. Show that the dual of the exclusive-ORis equal to its complement. i Nov Dec.-20, (R18), 030) 8 ive-OR An: The characteristic equation of exch as, . A @®B= AB+AB oll ‘The dual of equation (1) is obtained interchanging AND and OR operations. ¥,=(4 @B)= (A+B) (448) ‘Then, the complement of equation (1) ist 4 90)= a - (aa) = (+8) (448) ¥,= (A+B) (A+B) a From equations (2) and (3), itis proved ths" of exclusive-OR is eqial to its complement. Bek A as; Q33. Design an even parity generator generates an even parity bit for input string of 3-bits. Ans: Even Parity Generator Fi " ion __._Aneven party generator generates # BE bit (1) for odd number of one’s and a low pasiY foreven number of one's in the sequence.61 table below. Parity Bit Output P Table: Truth Table From the above table, cuiput parity bit is *O° else the inary sequence. itis observed that ifthe input sequence contains an even number of ones, then the © Parity bit 1 is appended to the input inorder to make the input sequence as even The expression for P, (even parity bit) is obtained by using k-maps as, For P, Here, the grouping of min terms is not Possible. ‘Therefore, parity bit P, can be expressed as, P= (1,2,4,7) = A BC+ABC+ AB C+ ABC = ABC+AB C42 BC+A8C = A(BC+B C)+A(BC+BC) = A(BOC)+A(BOC) AGBOC)+A(BOC) — (way+y=x@y) * P=ASBOC The logical implementation of even parity generator is as shown in figure. is B ae P.=A@B@C 7 Cc Figure: bit Even P ty Generator %4. Construct a 4-bit even parity generator circult using gates. Ans: Parity bit is an additional bit appended to a given binary sequence to make the number of I's even or dd, Parity bit is either “0” or “I? and it depends on the number of 1's in the input sequence. To generate an even tly binary sequence, the parity bit must be ‘O* when'there are even number of 1's in the input sequence. If there *® 04d number af 1's in the given sequence append the parity bit as 1" to make the even number of I°s in 4-bii f ; “2 input together with the parity bit. i quence to make the number of 1's even is shown in table boy ‘The parity bits generated for a 4-bit input binary sequence . —s62 DIGITAL ELECTRONICS [JNTI input Sequence IYDE; In HHH oc cc ccc al> lw ee moon Hoe Hola te He mio mie a elmio el She. | Table bit) is obtained by using k-maps. ‘The expression for P, (even pari For P, Here, the grouping of minterms is not possible. Therefore, parity bit'P_ can be expressed as 3 >= DU1,2,4,7,8, 11,13, 14) ABCD+4 BCD+ABC D+ABcD+Ai © D+ABCD+ ABCD + ABCD = 4 B(CD+CD)+AB(C D+ Cb)+AB(CD+T D)+4B(CD+CD) 4 B(C@D)+AB(COD)+AB(COD)+AB(C@D) = (C@D)[A B+AB]* (CO D)\(AB+ AB) = (C@D\\408)+(COD\(4@8) | P= (A@BY(C@D)+(A@B)\(COD) Al) €, Oy = (xOy) On further simplification, the equation (1) is minimized to = (A®B)@(C@D) CoXy+Fx=x@y) A®BOCO@D| The logical implementation of even parity generator is as shown in figure. : A ASB a@poc B ‘ ¢ », } D - A@BOC@D . | Figure: 4-bit Even Parity Generator : j Q35. With neat circuit diagram explain the working of a 4-bit odd parity generator. > Ans: ee Mode! Paper ‘The function of a 4-bit odd parity generator is to set the parity bit to I (ie., P= 1) when there are even of 1's in the 4-bit word. Thus, the total number of 1's inthe transmitted word (including the parity bit) wil be ‘Hence, a parity generator, which generates a high parity bit for even number of 1's in the word and low patilY for odd number of 1's is known as odd parity generator. Note ene. EYE” Parity generator’ generates a high parity bit for odd number of 1"s and a low parity bit fo" ql number of 1’s in the word, . | A Se cJN ee truth table for a 63 Parity bit P i Miove lane ors ele ite S!oe Table the output function of the 4-bi e SOP form as, 'ion of the 4-bit odd parity generator can be represented in ; P=2(0, 3,5, 6,9, 10, 12, 15) ; From the above truth table, Itis simplified using K-map as follows, : ip it 0 er . Gate-lovel MinimizationDIGITAL ELECTRONICS [JNTu. DER, a ty L VERY: SHORT. QUESTIONS aan So Se ONS) (VSQg) eae el Q1. Define K-map. Ans: 4 Moda Papas Karnaugh map or K-map isa pictorial representation ofa truth table which offers «simple and forward method of minimizing Boolean expression. iy Q2. What are don't cares? Ans: Mode! Parma ay The combinations for which the value of funtion i not specified are called don’t cate combina, incompletely specified functions. 3. What do 1's and 0's on the SOP K-map. Ans: On the SOP k-map, the I’s represent the true minterms and the 0's represent. Q4, Whats a prime implicant in k-map? Ans: ‘An implicant which is not a subset of another implicant of the function is known as “prime implicant’ QS. Whatis an essential implicant? Ans: : ‘An implicant which includes minimum one cell and cannot be grouped under any othe as “essential implicant”. Q6. What is two-level logic? Ans: The two-level logi one in which each input passes through two.gates to reach the output. It involvesS and POS forms of realization : Q7. The binary number designations of the two rows and columns of the k-map are in which code? Why? Ans: E Model Papert." In Gray code to ensure that two physically adjacent squares are really adjacent ic, thier minters oF mater differ in only variables. . r “ Q8, What are the codes of binary numbers of the rows and columns of a four-variable pee spor. oH Ans: ‘Model Paper The codes of rows and columns of a four-variable k-map are in order 00, 01, 1 and 10.» Q9. What is a’parity bit? An ott og even oF Parity bit is an additional bit appended to a given binary sequence to make the number of 1,5 €¥" —<