LAB # 6

STATE MACHINES
The class of circuits in which the outputs depend on the past behaviour of the circuit, as well as on the
present values of inputs. They are called sequential circuits. In most cases a clock signal is used to
control the operation of a sequential circuit; such a circuit is called a synchronous sequential circuit.
Synchronous sequential circuits are realized using combinational logic and one or more flip-flops. The
general structure of such a circuit is shown in Figure given below.

Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function of
the inputs and the state of the storage elements. Because the state of the storage elements is a function
of previous inputs, the outputs of a sequential circuit depend not only on present values of inputs, but
also on past inputs, and the circuit behaviour must be specified by a time sequence of inputs and internal
states.
There are two models of sequential circuits: the Mealy model and the Moore model. . In the Mealy
model, the output is a function of both the present state and the input. In the Moore model the output is
a function of only the present state. A circuit may have both types of outputs. The two models of a
sequential circuit are commonly referred to as a finite state machine, abbreviated FSM. (For detail see
article 6.1 and 6.2 of the textbook: Digital Design by M. Morris Mano & Michael D. Ciletti).

Moore and Mealy State Machines:

There are two general methods to design a clocked sequential circuit:

Moore machine: In this method, the outputs of the circuit depend only on present state. Figure given
below shows the structure of a Moore machine. A combinational logic circuit generates next state base
on the present state and inputs. The outputs are computed by a combinational logic which maps the
present state to the outputs. The state register outputs are updated at the edge of the clock signal.
Therefore, outputs signals change with respect to the edge of the clock.

Mealy machine: Figure given below shows the block diagram of a mealy machine. In mealy
machines, the output depends on both the present state and inputs. The outputs can change when inputs
change independent of the clock signal.
A sequence detector: In this section, a sequence detector that detects the “11” sequence is
designed with both Mealy and Moore state machines.

State Diagram:

The first step in designing a finite state machine is to determine how many states are needed and which
transitions are possible from one state to another. There is no set procedure for this task. The designer
must think carefully about what the machine has to accomplish. A good way to begin is to select one
particular state as a starting state; this is the state that the circuit should enter when power is first turned
on or when a reset signal is applied.

Moore State Diagram:

The conceptually simplest method is to use a pictorial representation in the form of a state diagram,
which is a graph that depicts states of the circuit as nodes (circles) and transitions between states as
directed arcs. The state diagram in Figure given below defines the behavior that corresponds to our
specification. States A, B, and C appear as nodes in the diagram. Node A represents the starting state,
and it is also the state that the circuit will reach after an input w = 0 is applied. In this state the output z
should be 0, which is indicated as A/z=0 in the node. The circuit should remain in state A as long as w
= 0, which is indicated by an arc with a label w = 0 that originates and terminates at this node. The first
occurrence of w = 1 (following the condition w = 0) is recorded by moving from state A to state B. This
transition is indicated on the graph by an arc originating at A and terminating at B. The label w = 1 on
this arc denotes the input value that causes the transition. In state B the output remains at 0, which is
indicated as B/z=0 in the node. When the circuit is in state B, it will change to state C if w is still equal
to 1 at the next active clock edge. In state C the output z becomes equal to 1. If w stays at 1 during
subsequent clock cycles, the circuit will remain in state C maintaining z = 1. However, if w becomes 0
when the circuit is either in state B or in state C, the next active clock edge will cause a transition to
state A to take place.

Moore State Diagram

Mealy State Machine:

The diagram indicates that if the machine is in state A, it will remain in state A if w = 0 and the output
will be 0. This is indicated by an arc with the label w = 0/z = 0. When w becomes 1, the output stays at
0 until the machine moves to state B at the next active clock edge. This is denoted by the arc from A to
B with the label w = 1/z = 0. In state B the output will be 1 if w = 1, and the machine will remain in
state B, as indicated by the label w=1/z=1 on the corresponding arc. However, if w = 0 in state B, then
the output will be 0 and a transition to state A will take place at the next active clock edge. A key point
to understand is that during the present clock cycle the output value corresponds to the label on the arc
emanating from the present-state node.

Mealy State Diagram

Codes:

Moore: Mealy:

Simulation Results:
Moore State Machine Results:

Mealy State Machine Results:

Home Task:

Design a sequence detector that detects the “111” sequence by using both Mealy and Moore state
machines.