Professional Documents
Culture Documents
ebook download CMOS Past, Present and Future 1st Edition - eBook PDF all chapter
ebook download CMOS Past, Present and Future 1st Edition - eBook PDF all chapter
ebook download CMOS Past, Present and Future 1st Edition - eBook PDF all chapter
https://ebooksecure.com/download/electric-utility-resource-
planning-past-present-and-future-ebook-pdf/
http://ebooksecure.com/product/ebook-pdf-american-foreign-policy-
past-present-and-future-eleventh-edition/
https://ebooksecure.com/download/understanding-mobility-as-a-
service-maas-past-present-and-future-ebook-pdf/
https://ebooksecure.com/download/advanced-biofuel-technologies-
present-status-challenges-and-future-prospects-ebook-pdf/
Production Processes of Renewable Aviation Fuel:
Present Technologies and Future Trends 1st edition -
eBook PDF
https://ebooksecure.com/download/production-processes-of-
renewable-aviation-fuel-present-technologies-and-future-trends-
ebook-pdf/
http://ebooksecure.com/product/ebook-pdf-criminological-theory-
past-to-present-essential-readings-6th-edition/
http://ebooksecure.com/product/ebook-pdf-traditions-encounters-a-
global-perspective-of-the-past-from-1500-to-the-present-2-5th-
edition/
http://ebooksecure.com/product/cmos-vlsi-design-a-circuits-and-
systems-perspective-4th-edition/
https://ebooksecure.com/download/pan-genomics-applications-
challenges-and-future-prospects-ebook-pdf/
CMOS Past, Present, and Future
Related titles
Germanium-Based Technologies: From Materials & Devices
(ISBN 978-0-08-044953-1)
Sputtering Materials for VLSI and Thin Film Devices
(ISBN 978-0-8155-1593-7)
High Performance Silicon Imaging: Fundamentals and Applications of CMOS and CCD
sensors
(ISBN 978-0-85709-598-5)
Millimeter-Wave Digitally Intensive Frequency Generation in CMOS
(ISBN 978-0-12-802207-8)
Woodhead Publishing Series in Electronic
and Optical Materials
Henry H. Radamson
Jun Luo
Eddy Simoen
Chao Zhao
An imprint of Elsevier
Woodhead Publishing is an imprint of Elsevier
The Officers’ Mess Business Centre, Royston Road, Duxford, CB22 4QH, United Kingdom
50 Hampshire Street, 5th Floor, Cambridge, MA 02139, United States
The Boulevard, Langford Lane, Kidlington, OX5 1GB, United Kingdom
This book and the individual contributions contained in it are protected under copyright by the
Publisher (other than as may be noted herein).
Notices
Knowledge and best practice in this field are constantly changing. As new research and experience
broaden our understanding, changes in research methods, professional practices, or medical treatment
may become necessary.
Practitioners and researchers must always rely on their own experience and knowledge in evaluating
and using any information, methods, compounds, or experiments described herein. In using such
information or methods they should be mindful of their own safety and the safety of others, including
parties for whom they have a professional responsibility.
To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume
any liability for any injury and/or damage to persons or property as a matter of products liability, negligence
or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained
in the material herein.
Contributors ix
Preface xi
Acknowledgments xiii
3 Strain engineering 41
H.H. Radamson
3.1 Introduction 41
3.2 Basic definitions of strain type and design 41
3.3 Strain design in MOSFETs 44
3.4 Methods to induce strain in the CMOS structure 47
3.5 Embedded Si1 yCy(eSi1 yCy) for nMOS 54
References 64
Further reading 67
We are in some way or other affected by the enormous impact of integrated electronics
and integrated circuits (ICs). They have changed virtually all aspects of our social and
professional lives. CMOS is the main unit in ICs and its design and structure have
undergone an evolution for many decades to follow the historical Moore’s Law.
This book is written in a notably understandable language for readers and provides
a good insight from the basics of CMOS to its development toward the advanced tran-
sistor structures.
The book is dedicated to the students and researchers in the field of electrical engi-
neering, who desire to learn more about the CMOS technology.
This page intentionally left blank
Acknowledgments
Professor Anders Hallen from KTH is acknowledged for his scientific discussions.
Many contributors from the Chinese Academy of Sciences have been involved
with this book. Our special gratitude to Dr. Huilong Zhu, Dr. Huaxiang Yin, and
Dr. Jiang Yan for their remarkable contributions and discussions to the all-last
high-k/metal gate integration part. We express our appreciation to Miss Dan Zhang,
Mr. Ningyuan Duan, Miss Shujuan Mao, Mr. Jinbiao Liu, and Miss Xuewei Zhao for
their valuable help.
This page intentionally left blank
Basics of metal–oxide–
semiconductor field-effect 1
transistor (MOSFET)
H.H. Radamson
Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, PR China;
University of Chinese Academy of Sciences (UCAS), Beijing, PR China
1.1 Introduction
MOSFETs are the brick units of integrated circuits (ICs) which are used in many
devices in our daily life. They are being used for analog and digital applications.
The latter application is for a logic device where the transistor acts as a switch and
the performance is qualified with switching speed and switching energy. Since the
MOSFET structure has been downscaled in size according to Moore’s law, the density
and switching speed of transistors have enhanced exponentially where the switching
energy has reduced in a similar manner. This evolution of MOSFET structures finally
resulted that the planar design was abandoned to three-dimensional (3D) one provid-
ing a remarkably better control on the parasitic resistances and capacitances.
The idea of operational field effect transistors (FETs) extends to a US patent sub-
mitted by Julius Edgar in 1925; meanwhile, the discovery of MOSFETs by Dawon
Kahng and Martin Atalla at Bell labs emerged late in the 1950s. In the beginning,
the gate material in the transistors was usually metals, for example, Al, which led
to a “Metal Oxide Semiconductor” abbreviation for such devices. However, later,
heavily doped poly-Si was used as the standard gate material due to its high thermal
stability without reacting with gate oxide. Nowadays, the new research introduces the
metal gate material to be reused when SiO2 gate oxide was substituted with more
advanced high-k dielectrics.
The first ICs based on MOS were commercially announced by General Microelec-
tronics in 1964. Although this step was a large technological development, it took
almost a decade to solve the fundamental yield and reliability issues allowing
MOS as the main component in IC technology.
The main benefit of MOSFET in IC production has been that the transistor needs
practically no input current to manipulate the carrier current compared to the bipolar
transistor. The channel conductance can be controlled by an applied voltage to the gate
terminal in different operation modes.
MOSFETs operate through four-terminal contacts: gate (G), source (S), drain (D),
and substrate body (B) as shown in Fig. 1.1. The body terminal could be connected to
the source, resulting in a three-terminal device.
Circuit symbols
N-channel P-channel
MOSFET MOSFET
G G
S D S D
Fig. 1.1 Figure illustrates a cross section of 2D planar MOSFET (left) and 3D FinFET (right).
The circuit symbols have also been shown for nMOSFETs and pMOSFETs.
modification was to improve the carrier transport in the channel region. Chapter 3
covers in detail the most important techniques to induce strain in the MOSFET
structure.
In transistors, the quality of gate oxide determines the leakage current. There is a
need to decrease the resistance in MOSFETs’ contacts and silicide layer is applied
prior to the metal contact for this purpose. Both the gate oxide and silicide layers were
modified in 90-nm technology node and beyond. For example, the gate oxide was
silicon oxide for many decades until, in the 45-nm technology node, it was replaced
by high-k material. In order to avoid any damage on high-k oxide due to high-
temperature annealing steps, the process flow of the transistor was modified to the
high-k-last process where these materials are deposited after thermal treatments. In
such cases, a dummy gate of silicon oxide is initially formed and the transistor is
processed. Afterward, the dummy gate is removed and the real gate containing
high-k materials is formed.
During the past 40 years, the MOSFET’s size has been shrunk to follow an inter-
national technological road map semiconductor (ITRS) to increase the density of tran-
sistors and to decrease the power consumption. In this evolution of MOSFET in 2003
in the 22-nm technology node, the conventional 2D transistor architecture was
replaced by 3D structure, the so-called trigate design [1]. Trigate transistors were later
renamed FinFETs, which were already defined by other research groups a few years
before [2]. The main structures of a (two-dimensional) 2D and (three-dimensional) 3D
MOSFET are defined in Fig. 1.1 as follows:
In order to study the performance of a transistor, different notations have to be
defined. The source, drain, and gate for transistors in Fig. 1.1 are written shortly as
S, D, and G, whereas other important notations are as follows:
VTH: Threshold voltage
VDS: Voltage between D and S terminals
Vov: Vov ¼ VGS VTH
Cox: Oxide capacitance
μe or μh: Channel mobility
kn: Coefficient of conductance
CGS, CGD: Capacitances between S, D, and G
rDS: Resistance between D/S (rDS ¼ 1/gDS)
VDD: Supply voltage
VGS: Voltage between G and S terminals
Vox: Voltage over oxide
VG: Gate voltage
gDS: Conductance between D/S
gm: Transconductance
Gint: Intrinsic gain (Gint ¼ gm/gDS)
RS, RD, and RG: Resistances of S, D, and G
In order to provide a better understanding of 2D-to-3D transition, the process flow of
these transistors is shown in Fig. 1.2. The major differences between 2D and 3D
processing are the formation of Si fin in FinFETs, S/D formation, and the
planarization step [3].
4 CMOS Past, Present and Future
Fig. 1.2 Process flow for the bulk FinFETs and planar MOSFETs where additional processes
for FinFETs are highlighted.
cSi
3.1 eV qyg =4.0 eV
qySi = cSi + (Ec - Ef)
Ec
Ec Ef Ec
Ec Ef Ef Vfb
Ev Ef
Ev Ev
Ev
Fig. 1.3 (A) The energy band diagram of a p-type silicon substrate with a formed gate when no
applied gate voltage is applied and (B) with a gate voltage equal to Vfb.
Basics of metal–oxide–semiconductor field-effect transistor (MOSFET) 5
electron energy barrier. In a similar way, the energy barrier for holes is defined and is
estimated to be 4.8 eV. Owing to these energy barriers, Holes and electrons are not
able to move through the SiO2 gate dielectric. It is also expected an energy barrier
of 3.1 eV at the interface between the polysilicon gate and SiO2.
In general, a relationship for the applied voltages in a MOSFET can be written as:
where for a flat-band situation VG ¼ Vfb and ϕs ¼ Vox ¼ 0; therefore, a simple form of
Eq. (1.1) is written as: Vox ¼ VG Vfb.
To study the performance of a MOSFET, a special type of electrical measurement
can be performed when a MOS capacitance configuration is established. There are
three biasing modes when the gate voltages vary over a range of measurement: accu-
mulation, depletion, and inversion as shown in Fig. 1.4A–C.
Ec
qVox fs = 2fB
3.1 eV
qVox Ei
Ec, Ef qfB
Ef
qVG Ev
Ev E0 qVG = qVT
Ec, Ef
qVG Depletion
qfs Ev region
Fig. 1.4 (A) Accumulation, (B) depletion, and (C) inversion operation modes for a MOSFET.
6 CMOS Past, Present and Future
1.2.1 Accumulation
This occurs when the gate voltage is more negative than the thermal potential for the
p-doped Si substrate. The charge density in the channel region is dependent on the
applied gate voltage. An electric field is constituted inside the oxide region where
the direction of the field is dependent on the amount of applied gate voltage.
Qacc
Vox ¼ (1.2)
Cox
1.2.2 Depletion
When the gate voltage is increased (VG is more positive for p-type and more negative
for n-type doped Si), the charge distribution changes and the energy bands bend down-
ward. As a result, a depletion region with a depth of Wdep is formed. At the surface, the
electron density (or hole density for n-type doped Si) is stills light. The voltage over
the gate oxide can be written as
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Qacc qN a Wdep qNa2εs ϕs
Vox ¼ ¼ ¼ (1.3)
Cox Cox Cox
2
qN a Wdep
ϕs ¼ (1.4)
2εs
By inserting the Vox and ϕs expression in the original equation for gate voltage:
2
qN a Wdep qN Wdep
VG ¼ Vfb + ϕs + Vox ¼ Vfb + + a (1.5)
2εs Cox
1.2.3 Inversion
By further increase of VG, the energy band bends more and EF could be located in the
vicinity of Ec. This situation leads to a threshold where the p-type doped semicon-
ductor is inverted to N-type (or vice versa for n-type doped Si) at the interface of the
semiconductor and gate oxide. The threshold voltage is usually reached when the
surface electron (or hole) concentration (ns) approaches the same doping level as
in the bulk (Na). A simple rule can be applied to obtain threshold voltage and that
is when the surface potential satisfies the condition: ϕs(TH) ¼ 2ϕB (N-type body :
ϕs(TH) ¼ 2ϕB).
Basics of metal–oxide–semiconductor field-effect transistor (MOSFET) 7
Therefore, the main equation of gate voltage for threshold voltage (VG ¼ VT) is as
follows:
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
qNa2εs 2ϕB
VTH ¼ Vfb + 2ϕB + (1.6)
Cox
The gate voltage in the vicinity of threshold voltage is also known as the weak inver-
sion region.
A summery of all operation modes (as described in Fig. 1.4) including strong inversion
is illustrated in Fig. 1.5.
In a transistor, no carrier transport occurs between the source and drain terminals
(ID ¼ 0) when no gate voltage is applied. As an example, in a MOS transistor, if the
gate terminal is set to a positive voltage and VGS > VTH, then a graded voltage is
formed across the channel region, leading to channel conductance, which becomes
100 Inversion
Flatband
Qs/QTH
10 Depletion
0.1
−20 −10 0 10 20 30 40
fs/VTH
8 CMOS Past, Present and Future
large enough to allow electron transport in the channel. It is important to mention here
that the condition VDS < VGS VTH has to be satisfied in order to avoid a pinch through
a situation in the transistor. In the situation where VGS controls the conductance of the
channel and the channel operates as a variable resistor, conductance between the
source and drain (gDS) is written as
1 1
gDS ¼ ¼ kn VGS VTH VDS (1.8)
rDS 2
where rDS is the resistance between drain and source. As a result, the induced charge
(Q) in the channel region can be expressed as
The channel current can also be obtained by carrier mobility (μe), the formed electric
field (εy) along the channel direction (y), channel length (W), and charge (Q) in the
channel, according to
or
W 1 2
ID ¼ μn ε0 εox ðVGS VTH ÞVDS VDS (1.12)
toc L 2
μn Cox W
IDðsatÞ ¼ ðVGS VTH Þ2 (1.13)
2L
Eq. (1.12) shows that ID is a quadratic function of VDS with a maximum point at VTH.
This equation is used for transistor characterization where the channel mobility can be
obtained from the electrical measurements.
An nMOS transistor has three operating modes with the following conditions as
illustrated in Fig. 1.6:
1. Cutoff: It occurs when VGS < VTH and the channel current ID ¼ 0 A
This is the state when the transistor is in the turnoff mode. A more detailed study using
the Fermi-Dirac distribution shows that some electrons with thermal energy at the
source can move inside the channel region and flow to the drain. This causes a
Basics of metal–oxide–semiconductor field-effect transistor (MOSFET) 9
Linear
(triode)
Saturation
VGS
VGS<VTH
Cutoff VDS
Fig. 1.6 I-V curves of an n-channel MOSFET in different operation modes [4].
VGS VTH
ID ffi ID0 e nV T (1.14)
CD
n¼1+ (1.15)
Cox
where CD and COX are the capacitance of the depletion layer and oxide layer, respec-
tively. Since the subthreshold voltage I-V is exponentially dependent on threshold
voltage, it makes it vulnerable to any change in the transistor structure such as gate
oxide thickness, transistor body doping, and junction depth.
2. Triode or linear mode occurs when the condition is 0 < VDS < VGS VTH and the conduc-
tance is large and the carrier transport is established along the transistor channel with a cur-
rent of ID.
3. Saturation mode: It occurs when VGS > VTH and VDS VGS VTH. This is also a voltage con-
trolled current source and ID can be rewritten as ID ¼ (1/2) kn (VGS VTH)2.
It is worth mentioning here that all the above equations for currents and voltages for an
nMOS transistor can be written with a reversed sign for pMOS. This means that VTH,
VSG, VDS, and VOV become negative and, for example, conditions for saturation mode
become: VGS < VTH and VDS < VGS VTH.
one gate works as the input for the next gate. The cascaded transistors need a resto-
ration of the signals to guarantee that a logic gate can reliably distinguish whether an
input signal is on logic state 1/0. As an example, a NAND component consists of
CMOS logic gates where an n-FET is connected to the ground and a p-FET is con-
nected to the positive supply voltage VDD. Such an Si CMOS circuit has excellent per-
formance of signal restoration offering low static power dissipation. This point is
crucial for complex logic ICs since power dissipation and the generated self-heating
are main problems. Thus, an FET-based successor for Si CMOS logic needs transistors
which are able to switch off fast. One of the figures of merit (FOM) of a transistor is
how the switching occurs, thus Ion/Ioff ratio has to be high. MOSFETs have to show an
Ion/Ioff ratio within 104–107 for logic application. Another FOM for MOSFETs is the
subthreshold swing (S) during switching. This FOM is measured in the mV/decade
and expresses how the VGS has to be changed to make a change in ID by a factor
of 10 as shown in Fig. 1.7.
The subthreshold voltage is defined as
dVG kB T εSi tox
S¼ 1+ (1.16)
d log 10 ID q log 10 e εox wd
In Eq. (1.16), εSi is the dielectric constant of silicon (11.9) and wd is the drain depletion
layer width. T is the absolute temperature, kB is Boltzmann’s constant, q is the electron
charge in absolute value, and e is the exponential number. It is clear from Eq. (1.16) that
S has a lower limit value of about 0.06 V/decade at room temperature. It therefore con-
stitutes a lower limit for the threshold voltage of scaled logic transistors, as a gate volt-
age swing of a few kBT/q is required to switch the device from off to on.
If a dc VGS is applied to the transistor on an on-state operating mode, then a small
RF signal will have to be amplified. This is the situation when a small variation of VG
occurs; the number of carriers in the channel as well as the drain current is changed.
The amplification behavior of MOSFET is characterized in terms of the unilateral
power gain (U), the intrinsic gain (Gint), and the current gain (h21). In general, all these
parameters are dependent on frequency as shown in Fig. 1.8.
Iog ID
ION
Subthreshold swing, S
[mV/dec ]
IOff
VG
VTH VDD
Fig. 1.7 Figure illustrates the ID(VG) curve to estimate the subthreshold voltage.
Basics of metal–oxide–semiconductor field-effect transistor (MOSFET) 11
RF MOSFET [7].
fmax = 140 GHz
30
20 h21(−20 dB/dec)
fT = 110 GHz
10
0
1 10 100
Frequency (GHz)
Ri
Rs
The most important FOM of RF transistors are the cutoff frequency (fT) and the
maximum frequency of oscillation (fmax).fT is defined as the frequency when the mag-
nitude of h21 has dropped to unity (0 dB) and at fmax when the unilateral power gain is
unity. Both fT and fmax determine the frequency limits where the transistor’s amplify-
ing performance is degraded. The frequency characteristics of MOSFETs are
described by the small signal equivalent circuit as shown in Fig. 1.9.
There are both intrinsic and extrinsic parts for a transistor. The intrinsic part covers
the gate and the channel region and it contains CGS, CGD, gm, rDS (see the notations in
Fig. 1.1) together with an intrinsic resistance Ri as shown in the figure. The extrinsic
elements are RG, RS, and RD. The fT and fmaxfor the intrinsic part are obtained from the
following expressions [8]:
gm
fT ð intÞ ¼ (1.17)
2π ðCGS + CGD Þ
12 CMOS Past, Present and Future
gm
fmax ð intÞ ¼ pffiffiffiffiffiffiffiffiffiffiffiffi (1.18)
4π CGS gDS Ri
For RF transistors, high fT and fmax are mainly desired and the transistor can be
designed for this purpose.
where hv(0)i is the average velocity of carriers at the source side and Cox(VG VT) is
the charge density. When the channel length becomes smaller, hv(0)i can be set to
thermal velocity (vT) since the carriers are thermally injected from source [10]. vT
is given by
sffiffiffiffiffiffiffiffiffiffiffiffi
2kB TL
vT ¼ (1.20)
πm∗t
where TL denotes the lattice temperature. The drain current in nanotransistors can be
rewritten as
sffiffiffiffiffiffiffiffiffiffiffiffi
2kB TL
Id ¼ WCox ðvG vTH Þ (1.21)
πm∗t
This indicates that the drive current is increased by reducing the effective mass of the
carrier (or inducing strain) [11].
In order to develop the discussion to a more detailed level, more knowledge about
how MOSFETs function has to be provided. Fig. 1.10A and B illustrates how during
the evolution of the MOSFET structure the parasitic capacitance and resistances are
changed. In general, in an optimized MOSFET, all the undesired resistances and
capacitances have to be minimized [5].
The downscaling of transistors leads to an increase in leakage current as a result of
the smaller gate length. For industrial applications, CMOS technology has to ensure a
negligible dissipated power in the standby state. Therefore, the leakage power of
Basics of metal–oxide–semiconductor field-effect transistor (MOSFET) 13
8 1400
Intrinsic channel
capacitance 7 Channel 1200
Resistance (Ohm-mm)
Capacitance (F/mm)
resistance
6 1000
5 Parasitics 800
dominate!
Total parasitic 4 600
capacitance 3 Parasitic 400
resistance
2 200
1 0
120 100 80 60 40 20 0 120 100 80 60 40 20 0
Technology node (nm) Technology node (nm)
(A) (B)
Fig. 1.10 (A and B) The evolution of the parasitic components over different technology nodes.
transistors has to be controlled for logic application. In principle, there are no limita-
tions for reducing the size of transistors but practically the leakage current rises for
planar transistors with a gate length of 20 nm [6].
In nanotransistors, the body of transistor is very thin causing the external resistance
becomes comparable in magnitude to the channel resistance.
The rapid increase in parasitics in nanotransistors is due to the small space between
neighboring devices (a few tens of nanometers) to increase the density. In the chip, the
S/D and contact size are also scaled down to be compatible with the transistor size.
The S/D contacts and the gate are a few nanometers apart; also, the contact size will
lead to magnification of the parasitic problems.
The problem with parasitic resistances is a fundamental issue for integration of
nanotransistors in logic circuits. This occurs due to the small S/D volume compared
to the transistor body which is 5–10 nm thick [12,13]. This problem is even more
severe in integration of carbon nanotubes or graphene ribbons as channel material
where the transistor body is only one atomic layer [14].
Another issue with downscaling of MOSFETs is the control of the carrier transport
through the channel. This problem occurs when the drain voltage decreases source-to-
channel barrier height and allows an off-state leakage. This phenomenon is known as
drain-induced barrier lowering (DIBL) or short channel effect (SCE).
Although control of SCE is a large problem for 2D transistors, this issue had
no impact on 3D transistors. For almost 40 years, MOSFETs were manufactured
in planar form until 2003 when Intel introduced 3D design, the so-called multigate
field effect transistor (MuGFET). MuGFETs are fully depleted transistors and they
are categorized to include double gate, Trigate, FinFETs, π-gate, Ω-gate, and the
gate-all-around (GAA) transistors. Gate control was continually improved in
the MuGFET group starting with double gate to the GAA transistors as shown
in Fig. 1.11. The benefits of MUGFETs compared to the 2D MOSFETs are as
follows:
1. The problem with doping of the body compared to MOSFETs is solved
2. MuGFETs have a remarkably higher drive current
3. The problem of the random dopant fluctuation is reduced
14 CMOS Past, Present and Future
Fig. 1.11 Schematics of different transistor designs starting from the classical to advanced
three-dimensional transistors.
The two important points for the performance of MUGFETs are the thickness of BOX
to control the transport through the channel and the doping level in the body for a
designed threshold voltage. At first, by reducing the BOX thickness, DIBL is
decreased. The strategy of BOX thickness in downscaling of the transistors is dem-
onstrated in Fig. 1.12A and B. This is crucial to increase the control of carrier transport
as well as high drain current [15].
Following this design, FinFETs were introduced. The distinguishable difference of
a FinFET structure with other transistors is that the body of the device is a thin fin of Si
(SiGe, Ge, or III–V material) where its thickness is the effective channel length of the
transistor. Therefore, all categories of these transistors are also known as multigate
FETs (MUGFETs).
In principle, MUGFET shave a number of parallel nanowires (the so-called fingers)
with a joint gate electrode. In such structures, the drive current drive could be
increased by increasing the number of fingers of the transistor. The most benefit of
3D transistors is that by wrapping around the transistor gate, a better control over elec-
trical transport through the channel is provided. Therefore, the SCE, which is an
important problem for small gate lengths, is reduced, resulting in a decrease in the
leakage current in the transistor. This leakage phenomenon emerges drastically for
gate lengths smaller than 20 nm [6].
The performance of FinFETs depends strongly on physical dimensions (length,
width, and height), and shape as well as on the crystal orientation of the fin and body
doping concentration.
The width of the fin is directly coupled to the short channel effect, whereas the
height is limited to the etch process. Fig. 1.13 shows the impact of the fin dimensions
on DIBEL. The figure shows that careful attention has to be paid on one side on the
link of fin width to gate length of transistor but also the fin height [16]. The optimum
shape is obtained when the width and height of fins have to be less than a half and one-
fifth of the gate length, respectively.
Basics of metal–oxide–semiconductor field-effect transistor (MOSFET) 15
TBOX = 145 nm 8 12 nm
Tsi (nm)
24 nm
150 7
22 nm
6 BOX = 10 nm
100
Tox > 1.2 nm
TBOX = 10 nm 5
with GP
50
4 BOX = 50 nm
1020cm−3
0 3
0 5 10 15 10 20 30
TSOI (nm) Gate length (nm)
Fig. 1.12 (Left) The impact of oxide thickness of SOI wafer on transistors’ DIBL whereas
(right) the correlation between Si cap layer thickness with transistors’ gate lengths.
Tri-Gate FET
Lg relaxed fin dimensions
Gate WSi > Lg/2; HSi > Lg/5
Lg
FinFET
hSi Si Narrow fin
WSi ~ Lg/2
0.5
Gate
hSi Si
UTB FET
0.0 wSi Ultra thin SOI
0.5 1.0 1.5 2.0
WSi / Leff HSi ~ Lg/5
Fig. 1.13 Correlation of FinFETs’ width and height to the gate length and the impact on DIBIL.
The shape of fins depends on processing and it determines the transistor’s perfor-
mance. For example, a triangle fin is usually desired not only due to its high structural
strength for manufacturing, but also because such fins have a higher area-to-volume
ratio compared to rectangular ones.
Since its conduction in Si depends on the crystal orientation, the optimum mobility
is obtained in (100) and (110) direction for nFETs and pFETs, respectively [17]. From
a practical point of view, when the fins are formed in // or ┴ to the wafer flat, the tran-
sistor channel is oriented along (110) planes, otherwise a rotation at 45 degrees makes
a (100) oriented channel as shown in Fig. 1.14 [17].
Another random document with
no related content on Scribd:
the act.
"Not at all, I'm just issuing a fair warning that the signs that say:
'DANGER! HIGH-VOLTAGE!' are not there for appearance."
"Sounds like a threat to me."
"Have I threatened you? It sounds to me as though I were more than
anxious for your welfare. Any threat of which you speak is utterly
without grounds, and is a figment of your imagination; based upon
distrust of Venus Equilateral, and the personnel of Venus Equilateral
Relay Station."
Kingman shut up. He went down the list, marking off items here and
there. While he was marking, Channing scribbled a circuit and listed
the parts. He handed it over as Kingman finished.
"This is your circuit?" asked the lawyer skeptically.
"Yes."
"I shall have to ask for an explanation of the symbols involved."
"I shall be happy to present you with a book on essential radio
technique," offered Channing. "A perusal of which will place you in
possession of considerable knowledge. Will that suffice?"
"I believe so. I cannot understand how; being uncertain of your steps
a few minutes ago, you are now presenting me with a circuit of your
intended experiment."
"The circuit is, of course, merely symbolic. We shall change many of
the constants before the day is over—in fact, we may even change
the circuit."
"I shall require a notice before each change so that I may pass upon
the legal aspects."
"Walt," said Don, "will you accompany me to a transparency
experiment on the Ninth Level?"
"Be more than glad to," said Walt. "Let's go!"
They left the office quickly, and started for Joe's. They had not
reached the combined liquor vending and restaurant establishment
when the communicator called for Channing. It was announcing the
arrival of Barney Carroll, so instead of heading for Joe's, they went
to the landing stage at the south end of the station to greet the
Visitor.
"Barney," said Don, "of all the companies, why did you pick on Terran
Electric?"
"Gave us the best deal," said the huge, grinning man.
"Yeah, and they're getting the best of my goat right now."
"Well, Jim and I couldn't handle anything as big as the power
transmission set-up. They paid out a large slice of jack for the
complete rights. All of us are well paid now. After all, I'm primarily
interested in Martian artifacts, you know."
"I wonder if they had lawyers," smiled Walt wryly.
"Probably. And, no doubt, the legals had a lot to do with the fall of the
Martian civilization."
"As it will probably get this one so wound up with red tape that
progress will be impossible—or impractical."
"Well, Barney, let's take a run up to the lab. We can make paper-talk
even if Brother Kingman won't let us set it to soldering iron. There
are a lot of things I want to ask you about the tube."
They sat around a drawing table and Channing began to sketch.
"What I'd hoped to do is this," he said, drawing a schematic design.
"We're not interested in power transmission, but your gadget will do
a bit of voltage amplification because of its utter indifference to the
power-line problem of impedance matching. We can take a relay
tube and put in ten watts, say, across ten thousand ohms. That
means the input will be somewhat above three hundred volts. Now, if
our output is across a hundred thousand ohms, ten watts will give us
one thousand volts. So we can get voltage amplification at the
expense of current—which we will not need. Unfortunately, the relay
tube as well as the rest of the system will give out with the same kind
of power that it is impressed with—so we'll have amplification of
driver radiation. Then we'll need a detector. We haven't been able to
get one either yet, but this is a start, providing that Terran Electric will
permit us to take a deep breath without wanting to pass on it."
"I think you may be able to get amplification," said Barney. "But to do
it, you'll have to detect it first."
"Huh?"
"Sure. Before these darned things will work, this in-phase anode
must be right on the beam. That means that you'll require a feedback
circuit from the final stage to feed the in-phase anodes. Could be
done without detection, I suppose."
"Well, for one thing, we're going to get some amplification if we
change the primary anode—so. That won't permit the thing to handle
any power, but it will isolate the output from the input and permit
more amplifications. Follow?"
"Can we try it?"
"As soon as I get Terran Electric's permission."
"Here we go again!" groaned Walt.
"Yeah," said Don to Barney, "now you'll see the kind of birds you sold
your gadget to."
They found Kingman and Farrell in conference. Channing offered his
suggestion immediately, and Kingman looked it over, shaking his
head.
"It is not permitted to alter, change, rework, or repair tubes owned by
Terran Electric," he said.
"What are we permitted to do?" asked Channing.
"Give me your recommendation and I shall have the shop at Terran
Electric perform the operation."
"At cost?"
"Cost plus a slight profit. Terran Electric, just as Venus Equilateral, is
not in business from an altruistic standpoint."
"I see."
"Also," said Kingman severely, "I noticed one of your men changing
the circuit slightly without permission. Why?"
"Who was it?"
"The man known as Thomas."
"Charles Thomas is in charge of development work," said Channing.
"He probably noted some slight effect that he wanted to check."
"He should have notified me first—I don't care how minute the
change. I must pass on changes first."
"But you wouldn't know their worth," objected Barney.
"No, but Mr. Farrell does, and will so advise me."
Wes looked at Channing. "Have you been to the Ninth Level yet?"
"Nope," said Channing.
"May I accompany you?"
Channing looked at Farrell critically. The Terran Electric engineer
seemed sincere, and the pained expression on his face looked like
frustrated sympathy to Don. "Come along," he said.
Walt opened the anode-coupler circuit, and the needle of the output
ammeter slammed across the scale and wound the needle halfway
around the stop pin. The shunt, which was an external, high-
dissipation job, turned red, burned the paint off of its radiator fins,
and then proceeded to melt. It sputtered in flying droplets of molten
metal. Smoke spewed from the case of the ammeter, dissipating in
the vacuum of the blister.
Walt closed the coupler circuit.
"Whammo!" he said. "Mind blowing a hundred-amp meter?"
"No," grinned Don. "I have a thousand-amp job that I'll sacrifice in
the same happy-hearted fashion. Get an idea of the power?"
"Voltmeter was hanging up around ten thousand volts just before the
amp-meter went by."
"Um-m-m. Ten thousand volts at a hundred amps. That is one million
watts, my friends, and no small potatoes. To run the station's
communicating equipment we need seven times that much. Can we
do it?"
"We can. I'll have Warren start running the main power bus down
here and we'll try it. Meanwhile, we've got a healthy cable from the
generator room; we can run the non-communicating drain of the
station from our plaything here. That should give us an idea. We can
use a couple of million watts right there. If this gadget will handle it,
we can make one that will take the whole load without groaning. I'm
calling Warren right now. He can start taking the load over from the
generators as we increase our intake. We'll fade, but not without a
flicker."
Walt hooked the output terminals of the tube to the huge cable
blocks, using sections of the same heavy cable.
Warren called: "Are you ready?"
"Fade her in," said Walt. He kept one eye on the line voltmeter and
opened the anode-coupler slightly. The meter dipped as Warren
shunted the station load over to the tube circuit. Walt brought the line
voltage up to above normal, and it immediately dropped as Warren
took more load from the solar intake. This jockeying went on for
several minutes until Warren called: "You've got it all. Now what?"
"Start running the bus down here to take the communications load,"
said Don. "We're running off of an eight hundred thousand mile
cathode now, and his power output is terrific. Or better, run us a
high-tension line down here and we'll save silver. We can ram ten
thousand volts up there for transformation. Get me?"
"What frequency?"
"Yeah," drawled Channing, "have Chuck Thomas run us a control
line from the primary frequency standard. We'll control our frequency
with that. O.K.?"
"Right-o."
Channing looked at the set-up once more. It was singularly
unprepossessing, this conglomeration of iron and steel and plastic.
There was absolutely nothing to indicate that two and one-third
million watts of power coursed from Sol, through its maze of anodes,
and into the electric lines of Venus Equilateral. The cathodes and
dynode glowed with their usual dull red glow, but there was no
coruscating aura of power around the elements of the system. The
gimbals that held the big tube slid easily, permitting the tube to rotate
freely as the selsyn motor kept the tube pointing at Sol. The supply
cables remained cool and operative, and to all appearances the set-
up was inert.
"O.K., fellows," said Channing, "this is it—"
He was interrupted by the frantic waving of Kingman, from the other
side of the air lock.
"I feel slightly conscious-stricken," he said with a smile that showed
that he didn't mean it at all. "But let us go and prepare the goat for
shearing."
Kingman's trouble was terrific, according to him. "Mr. Channing," he
complained, "you are not following our wishes. And you, Mr. Farrell,
have been decidedly amiss in your hobnobbing with the engineers
here. You were sent out as my consultant, not to assist them in their
endeavors."
"What's your grief?" asked Channing.
"I find that your laboratory has been changing the circuits without
having previously informed me of the proposed change," complained
Kingman. "I feel that I am within my rights in removing the tubes
brought here. Your investigations have not been sanctioned—" He
looked out through the air lock. "What are you doing out there?"
"We have just succeeded in taking power from the sun," said Don.
He tried to keep his voice even, but the exultation was too high in
him, and his voice sounded like sheer joy.
"You have been—" Kingman did a double-take. "You what?" he
yelled.
"Have succeeded in tapping Sol for power."
"Why, that's wonderful!"
"Thank you," said Don. "You will no doubt be glad to hear that Wes
Farrell was instrumental in this program."
"Then a certain part of the idea is rightfully the property of Terran
Electric," said Kingman.
"I'm afraid not," said Don. "Dr. Farrell's assistance was not
requested. Though his contribution was of great value, it was given
freely. He was not solicited. Therefore, since Terran Electric was not
consulted formally, Dr. Farrell's contribution to our solar power beam
can not be considered as offering a hold on our discovery."
"This is true, Dr. Farrell?"
"I'm afraid so. You see, I saw what was going on and became
interested, academically. I naturally offered a few minor suggestions
in somewhat the same manner as a motorist will stop and offer
another motorist assistance in changing a tire. The problem was
interesting to me and as a problem, it did not seem to me—"
"Your actions in discussing this with members of the Venus
Equilateral technical staff without authorization will cost us plenty,"
snapped Kingman. "However, we shall deal with you later."
"You know," said Farrell with a cheerfully malicious grin, "if you had
been less stuffy about our tubes, they might be less stuffy about my
contribution."
"Ah, these non-legal agreements are never satisfactory. But that is to
be discussed later. What do you intend to do with your invention, Dr.
Channing?"
Channing smiled in a superior manner. "As you see, the device is
small. Yet it handles a couple of million watts. An even smaller unit
might be made that would suffice to supply a home, or even a
community. As for the other end, I see no reason why the size might
not be increased to a point where it may obsolete all existing power-
generating stations."
Kingman's complexion turned slightly green. He swallowed hard.
"You, of course, would not attempt to put this on the market
yourself."
"No?" asked Channing. "I think you'll find that Venus Equilateral is as
large, if not larger, than Terran Electric, and we have an enviable
reputation for delivering the goods. We could sell refrigerators to the
Titan colony, if we had the V-E label on them and claimed they were
indispensable. Our escutcheon is not without its adherents."
"I see," said Kingman. His present volubility would not have jogged a
jury into freeing the armless wonder from a pick-pocketing charge.
"Is your invention patentable?"
"I think so. While certain phases of it are like the driver tube, which,
of course, is public domain, the applications are quite patentable. I
must admit that certain parts are of the power transmission tube, but
not enough for you to claim a hold. At any rate, I shall be busy for the
next hour, transmitting the details to Washington, so that the
Interplanetary Patent Office may rule on it. Our Terran legal
department has a direct line there, you know, and they have been
directed to maintain that contact at all costs."
"May I use your lines?"
"Certainly. They are public carriers. You will not be restricted any
more than any other man. I am certain that our right to transmit
company business without waiting for the usual turn will not be
contested."
"That sounds like a veiled threat."
"That sounds like slander!"
"Oh, no. Believe me. But wait, Dr. Channing. Is there no way in
which we can meet on a common ground?"
"I think so. We want a free hand in this tube proposition."
"For which rights you will turn over a nominal interest in solar
power?"
"Forty percent," said Channing.
"But we—"
"I know, you want control."
"We'd like it."
"Sorry. Those are our terms. Take 'em or leave 'em."
"Supposing that we offer you full and unrestricted rights to any or all
developments you or we make on the Martian transmission tubes?"
"That might be better to our liking."
"We might buck you," said Kingman, but there was doubt in his
voice.
"Yes? You know, Kingman, I'm not too sure that Venus Equilateral
wants to play around with power except as a maintenance angle.
What if we toss the solar beam to the public domain? That is within
our right, too."
Kingman's green color returned, this time accompanied with beads
of sweat. He turned to Farrell. "Is there nothing we can do? Is this
patentable?"
"No—Yes," grinned Farrell.
Kingman excused himself. He went to the office provided for him and
began to send messages to the Terran Electric Company offices at
Chicago. The forty-minute wait between message and answer was
torture to him, but it was explained to him that light and radio crossed
space at one hundred and eighty-six thousand miles per second and
that even an Act of Congress could do nothing to help him hurry it.
Meanwhile, Channing's description tied up the Terran Beam for
almost an hour at the standard rate of twelve hundred words per
minute. Their answers came within a few minutes of one another.
Channing tossed the 'gram before Kingman. "Idea definitely
patentable," said the wire.