A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_PM+ICH7-M core logic
3
2005-08-26 3

REV:0.2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 1 of 48
A B C D E
 A B C D E

Compal confidential
Model:HAQAA
NAPA
File Name : LA-3011P

1 Fan Control
Mobile Yonah 1
page 4
uFCPGA-479 CPU Thermal Sensor Clock Generator Accelerometer
ICS9LPRS325AKLFT LIS3L02AQ3TR
page 4,5,6
ADM1032AR
LCD CONN page 4 page 15 page 28
page 17
F SB
H_A#(3..31) 533/667MHz H_D#(0..63)
DDR2 -400/533/667 DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
nVIDIA G72/G73 PCI-E x 16 page 13,14

ATI M52/M54 page 18

Intel Calistoga MCH Dual Channel
945PM USB conn x1
CRT / TV-OUT PCBGA 1466 (Docking) page 34 (port 6)
page 7,8,9,10,11,12
page 16
USB2.0 HUB / FingerPrinter UPEK TCS3C/TCD42A
USBx1
FP Conn page 38 (port 0) page 38

2
PCI-E BUS 2

USB conn x2
DMI page 24 (port 4,5)
(port 1)

Mini Express Card BT Conn

10/100/1000 LAN page 24
(port 7)
82562GX/82573E/82573V page 28

PCI BUS USB2.0 USB conn x2

page 26,27
(Sub Board) page 24 (port 2,3)

Intel ICH7-M Azalia

MDC1.5
page 37
RJ45/11 CONN CardBus Controller mBGA-652
page 26
TI PCI7412 page 19,20,21,22
Audio CKT AMP & Audio Jack
page 22,23 ALC861 page 29 TPA0232 page 30

3 Slot 0 1394 port 5in1 Slot SATA HDD Connector 3

page 23 page 22 page 22 SATA Master
page 19
LED LPC BUS
page 36 PATA Slave
PATA ODD Connector
page 19
RTC CKT.
page 19
TPM1.2
Docking SLB9635TT1.2 Super I/O
page 34
page 38
LPC47N217&207
page 33,38
ENE KB910QF
CIR
page 25 page 33
Power On/Off CKT.
page 37 FIR
page 33

DC/DC Interface CKT.

4 page 39 Touch Pad Int.KBD BIOS 4

page 37 page 37 page 35

Power Circuit DC/DC

Page,40,41,42,43,44,45,46
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 2 of 48
A B C D E
 5 4 3 2 1

Voltage Rails Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%
Power Plane Description S0-S1 S3 S5 Ra/Rc/Re 100K +/- 1%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
VIN Adapter power supply (18.5V) N/A N/A N/A
B+ AC or battery power rail for power circuit N/A N/A N/A
0 0 0 V 0 V 0.100 V
D D

+CPU_CORE Core voltage for CPU ON OFF OFF

1 8.2K +/- 1% 0.216 V 0.250 V 0.289 V
+VCCP 1.05V power rail for Processor I/O and MCH/ICH core power ON OFF OFF
2 18K +/- 1% 0.436 V 0.503 V 0.538 V
+0.9VS 0.9V switched power rail for DDRII Vtt ON OFF OFF
3 33K +/- 1% 0.712 V 0.819 V 0.875 V
+1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF
4 56K +/- 1% 1.036 V 1.185 V 1.264 V
+1.8V 1.8V power rail for DDRII ON ON OFF
5 100K +/- 1% 1.453 V 1.650 V 1.759 V
+1.8VS 1.8V switched power rail ON OFF OFF
6 200K +/- 1% 1.935 V 2.200 V 2.341 V
+2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF
7 NC 2.500 V 3.300 V 3.300 V
+2.5VALW 3.3V always on power rail ON ON ON*
+3VALW 3.3V always on power rail ON ON ON*
BOARD ID Table
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
Board ID PCB Revision
+5VS 5V switched power rail ON OFF OFF
0 0.1
+RTC_VCC RTC power ON ON ON
1 0.2
2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3
4
C C
5
6
Internal PCI Devices 7
DEVICE Bus PCI Device ID IDSEL #
L AN 1 D8 AD24 SKU ID Table
Azal ia 0 D27 AD11
SKU ID SKU
PCI-E 0 D28 AD12
0
USB1.1/2.0 0 D29 AD13
1
PCI to PCI (DMI to PCI) 0 D30 AD14
2
AC97 MODEM 0 D30 AD14
3
AC97 Audio 0 D30 AD14
4
PATA/SATA 0 D31 AD15
5
LPC I/F 0 D31 AD15
6
SMBUS 0 D31 AD15
7
CPU I/F 0 D31 AD15
B
D MA 0 D31 AD15 B

PMU 0 D31 AD15 BTO Option Table

External PCI Devices BTO Item BOM Structure

DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ PM@
VGA GM@
CARD BUS D6 AD22 2 A BCD
82573G@
LAN 82573L@
82573@
82562@
INT MIC. 45MIC@

I2C / SMBUS ADDRESSING DOCKING WD@

WOD@
CIR CIR@
DEVICE HEX ADDRESS FIR@
FIR
DDR SO-DIMM 0 A0 10100000 217@
A
DDR SO-DIMM 1 A4 10100100 SUPER I/O SI207@ A

CLOCK GENERATOR (EXT.) D2 11010010 Battery 45@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 3 of 48
5 4 3 2 1
 5 4 3 2 1

This shall place near CPU

+VCCP
7 H_A#[3..31] H_D#[0..63] 7
JP22A

H_A#3 H_D#0 XDP_TDI R79 56_0402_5%

H_A#4
H_A#5
J4
L4
A3#
A4#
YONAH D0#
D1#
E22
F24 H_D#1
H_D#2 XDP_TMS R77
1 2

56_0402_1%
M3 A5# D2# E26 1 2
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4 XDP_TDO R76 56_0402_5%
M1 A7# D4# F23 1 2
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 XDP_BPM#5 R75 56_0402_5%
J1 A9# D6# E25 1 2
D H_A#10 H_D#7 D
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8 +3VS XDP_TRST# R80 1 2 56_0402_5%
H_A#12 A11# D8# H_D#9
H_A#13
H_A#14
P2
L1
P4
A12#
A13#
D9#
D10#
G24
J24
J23
H_D#10
H_D#11
Thermal Sensor ADM1032ARM XDP_TCK R78 1 2 56_0402_5%

H_A#15 A14# D11# H_D#12

P1 A15# D12# H26
H_A#16 R1 F26 H_D#13 1
A16# D13#

1
H_A#17 Y2 K22 H_D#14
H_A#18 A17# D14# H_D#15 C148 R116
U5 A18# D15# H25
H_A#19 R3 N22 H_D#16 0.1U_0402_16V4Z @ 10K_0402_5%
H_A#20 A19# D16# H_D#17 2
W6 A20# D17# K25 1
H_A#21 U4 P26 H_D#18 C163
A21# D18#

2
H_A#22 Y5 R23 H_D#19 U8
H_A#23 A22# D19# H_D#20 2200P_0402_50V7K H_THERMDA
U2 A23# D20# L25 2 D+ VDD1 1
H_A#24 H_D#21 2
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 H_THERMDC 3 6
H_A#26 A25# D22# H_D#23 D- ALERT#
T3 A26# D23# M23
H_A#27 W3 P25 H_D#24 8 4
A27# D24# 25,28,34 EC_SMB_CK2 SCLK THERM#
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23 25,28,34 EC_SMB_DA2 7 SDATA GND 5
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28
7 H_REQ#[0..4] Y1 A31# D28# R24
L26 H_D#29 ADM1032ARM_RM8
H_REQ#0 D29# H_D#30 +5VS
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31
H_REQ#2 REQ1# D31# H_D#32
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33 B+ 1 2
H_REQ#4 REQ3# D33# H_D#34
L5 REQ4# D34# V24
V26 H_D#35 C362
H_ADSTB#0 D35# H_D#36 0.01U_0402_25V4Z 10U_1206_16V4Z
7 H_ADSTB#0 L2 ADSTB0# D36# W25
H_ADSTB#1 V4 U23 H_D#37 2 1
7 H_ADSTB#1 ADSTB1# D37# +3VS

1
2
5
6
U25 H_D#38 C6
C D38# H_D#39 D C
U22

P
D39# H_D#40 G Q29
D40# AB25 25 EN_DFAN1 3 +IN
W22 H_D#41 1 FAN1_ON 3
D41# OUT

2
Y23 H_D#42 2 S
CLK_CPU_BCLK A22 D42# H_D#43 -IN U2A SI3456DV-T1_TSOP6 R429
15 CLK_CPU_BCLK BCLK0 D43# AA26

4
G
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44 LM358A_SO8 10K_0402_5%
15 CLK_CPU_BCLK# BCLK1 D44# H_D#45
D45# Y22

4
AC26 H_D#46
D46#

1
AA24 H_D#47 R2 JP16
H_ADS# D47# H_D#48 FAN1
7 H_ADS# H1 ADS# D48# AC22 1 2 1
H_BNR# E2 AC23 H_D#49
7 H_BNR# BNR# D49# 2

1000P_0402_50V7K
H_BPRI# H_D#50 100K_0402_5%

C371 10U_0805_10V4Z

150U_D2_6.3VM
7 H_BPRI# G5 BPRI# D50# AB22 3

1
H_BR0# F1 AA21 H_D#51 1 1 1
7 H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52 R1 D30 @ ACES_85205-0300
7 H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53 +
7 H_DRDY# DRDY# D53#
R114 H_HIT# G6 AD20 H_D#54 150K_0402_5% 1N4148_SOD80
7 H_HIT# HIT# D54# 2 2
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55
7 H_HITM# HITM# D55# 2

2
H_IERR# H_D#56

C374
+VCCP 1 2 D20 IERR# D56# AF23
H_LOCK# H4 AD24 H_D#57 @
7 H_LOCK# LOCK# D57#
H_RESET# H_D#58

C372
7 H_RESET# B1 RESET# D58# AE21
AD21 H_D#59
D59# H_D#60
7 H_RS#[0..2] D60# AE25
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62
F4 RS1# D62# AF22 25 FAN_SPEED1
H_RS#2 G3 AF26 H_D#63 5 1
H_TRDY# RS2# D63# +IN
7 H_TRDY# G2 TRDY# OUT 7
6 @ C373
H_DINV#0 -IN U2B 1000P_0402_50V7K
DINV0# J26 H_DINV#0 7
H_DINV#1 LM358A_SO8 2
DINV1# M26 H_DINV#1 7
XDP_BPM#0 AD4 V23 H_DINV#2
BPM0# DINV2# H_DINV#2 7
XDP_BPM#1 AD3 AC20 H_DINV#3
BPM1# DINV3# H_DINV#3 7
XDP_BPM#2 AD1
B XDP_BPM#3 BPM2# B
AC4 BPM3# H_DSTBN#[0..3] 7
H23 H_DSTBN#0
DBRESET# DSTBN0# H_DSTBN#1
20 DBRESET# C20 DBR# DSTBN1# M24
H_DBSY# E1 W24 H_DSTBN#2
7 H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3
19 H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] 7
H_DPRSTP# E5 G22 H_DSTBP#0 Placement near to ICH7
19,46 H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1 R255
7 H_DPWR# DPWR# DSTBP1#
XDP_BPM#4 AC2 MISC Y25 H_DSTBP#2 1 2 H_FERR# 2 1
R115 XDP_BPM#5 AC1 PRDY# DSTBP2# H_DSTBP#3 +VCCP @ 56_0402_5% C212 @ 180P_0402_50V8J
PREQ# DSTBP3# AE24
1 2 H_PROCHOT# D21
+VCCP 56_0402_5% PROCHOT#
19 H_PWRGOOD H_PW RGOOD D6
H_CPUSLP# PWRGOOD
7 H_CPUSLP# D7 SLP#
XDP_TCK AC5
XDP_TDI TCK H_A20M# H_SMI#
AA6 TDI A20M# A6 H_A20M# 19 2 1
XDP_TDO AB3 A5 H_FERR# C159 @ 180P_0402_50V8J
TDO FERR# H_FERR# 19
R111 1 2 @1K_0402_5% TEST1 C26 C4 H_IGNNE# H_INIT# 2 1
TEST1 IGNNE# H_IGNNE# 19
R112 1 2 51_0402_5% TEST2 D25 B3 H_INIT# C145 @ 180P_0402_50V8J
TEST2 INIT# H_INIT# 19
XDP_TMS AB5 C6 H_INTR H_NMI 2 1
TMS LINT0 H_INTR 19
XDP_TRST# AB6 B4 H_NMI C160 @ 180P_0402_50V8J
TRST# LINT1 H_NMI 19
LEGACY CPU H_A20M# 2 1
THERMAL C161 @ 180P_0402_50V8J
H_THERMDA A24 D5 H_STPCLK# H_INTR 2 1
THERMDA DIODE STPCLK# H_STPCLK# 19
H_THERMDC A25 A3 H_SMI# C144 @ 180P_0402_50V8J
THERMDC SMI# H_SMI# 19
H_THERMTRIP# C7 H_IGNNE# 2 1
7,19 H_THERMTRIP# THERMTRIP# C139 @ 180P_0402_50V8J
H_THERMDA, H_THERMDC routing together. H_STPCLK# 2 1
FOX_PZ47903-2741-42_YONAH C137 @ 180P_0402_50V8J
Trace width / Spacing = 10 / 10 mil H_PW RGOOD 2 1
C134 @ 180P_0402_50V8J
H_CPUSLP# 2 1
C138 @ 180P_0402_50V8J
A +VCCP A

+VCCP
Placement near to CPU side
1

R117
R118 H_DPSLP# 1 2

@ 56_0402_5% @ 56_0402_5%
R110 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2

H_DPRSTP# 1 2 2005/06/01 2006/06/01 Title

Issued Date Deciphered Date
B

@ 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
H_PROCHOT# 3 1 OCP# Size Document Number Rev
E

OCP# 20 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Q13 0.2
C

@ MMBT3904_SOT23
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 4 of 48
5 4 3 2 1
 5 4 3 2 1

+VCCP +VCC_CORE
Length match within 25 mils JP22B JP22C
D D
The trace width 18 mils space

1
46 VCCSENSE VCCSENSE AF7 AB26 AE18 K1
+VCC_CORE VCCSENSE VSS VCC VSS
7 mils 46 VSSSENSE VSSSENSE AE7 VSSSENSE VSS AA25 AE17 VCC VSS J2
R89 R86 AD25 AB15 M2
V_CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
VSS AE26 AA15 VCC VSS N1
1 2 VCCSENSE B26 AB23 AD15 T1
+1.5VS VCCA VSS VCC VSS
2

0.01U_0402_16V7K
VSS AC24 AC15 VCC VSS R2
R85

10U_0805_10V4Z
+VCCP K6 VCCP VSS AF24 AF15 VCC VSS V2
100_0402_1% J6 AE23 AE15 W1
VCCP VSS VCC VSS
1

1 2 VSSSENSE 1 1 M6 AA22 AB14 A26

VCCP VSS VCC VSS

C141

C143
R90
2K_0402_1%
N6
T6
VCCP
VCCP
YONAH VSS
VSS
AD22
AC21
AA13
AD14
VCC
VCC
VSS
VSS
D26
C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
2 2
K21 VCCP VSS AB19 AF14 VCC VSS B24
2

J21 VCCP VSS AA19 AE13 VCC VSS A23

M21 VCCP VSS AD19 AB12 VCC VSS D23

Close to CPU pin AD26

Close to CPU pin N21
T21
VCCP
VCCP
VSS
VSS
AC19
AF19
AA12
AD12
VCC
VCC
YONAH VSS
VSS
E24
B21
within 500mils. R21 VCCP VSS AE19 AC12 VCC VSS C22
within 500mils. V21 VCCP VSS AB16 AF12 VCC VSS F22

POWER, GROUNG, RESERVED SIGNALS AND NC

W21 VCCP VSS AA16 AE12 VCC VSS E21
V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
46 H_PSI# H_PSI# AE6 AB13 AD10 F19
PSI# VSS VCC VSS
VSS AA14 AD9 VCC VSS E19
CPU_VID0 AD6 AD13 AC10 B16
46 CPU_VID0 VID0 VSS VCC VSS
CPU_VID1 AF5 AC14 AC9 A16
46 CPU_VID1 VID1 VSS VCC VSS
CPU_VID2 AE5 AF13 AF10 D16
46 CPU_VID2 VID2 VSS VCC VSS
CPU_VID3 AF4 AE14 AF9 C16
46 CPU_VID3 VID3 VSS VCC VSS
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_VID4 AE3 AB11 AE10 POWER, GROUND F16
C 46 CPU_VID4 VID4 VSS VCC VSS
CPU_VID5 AF2 AA11 AE9 E16 C
46 CPU_VID5 VID5 VSS VCC VSS
CPU_VID6 AE2 AD11 AB7 B13
46 CPU_VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
133 0 0 1 VSS AF11 AD7 VCC VSS D13
V_CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
CPU_BSEL0 B22 AA8 A20 E14
15 CPU_BSEL0 BSEL0 VSS VCC VSS
166 0 1 CPU_BSEL1 B23 AD8 F20 B11
1 15 CPU_BSEL1
CPU_BSEL2 C21
BSEL1 VSS
AC8 E20
VCC VSS
A11
15 CPU_BSEL2 BSEL2 VSS VCC VSS
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+VCC_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 VCC VSS AE4 F17 VCC VSS E8
AF20 VCC VSS AB1 E18 VCC VSS G26
Resistor placed within AE20 VCC VSS AA2 E17 VCC VSS K26
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

AB18 VCC VSS AD2 B15 VCC VSS J25

0.5" of CPU pin.Trace
1

AB17 VCC VSS AE1 A15 VCC VSS M25

should be at least 25 AA18 VCC VSS B6 D15 VCC VSS N26
R96
R579

R571

R105

AA17 VCC VSS C5 C15 VCC VSS T26

mils away from any AD18 F5 F15 R25
VCC VSS VCC VSS
other toggling signal. AD17 VCC VSS E6 E15 VCC VSS V25
2

AC18 VCC VSS H6 B14 VCC VSS W26

AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
B B
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 B9 VCC VSS M22
AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

FOX_PZ47903-2741-42_YONAH FOX_PZ47903-2741-42_YONAH

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 5 of 48
5 4 3 2 1
 5 4 3 2 1

D +VCC_CORE D

1 1 1 1 1 1 1 1
C506 C505 C504 C503 C502 C501 C115 C116
Place these capacitors on L8
(North side,Secondary Layer) 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 2 2

+VCC_CORE

1 1 1 1 1 1 1 1
C107 C108 C109 C110 C111 C112 C113 C114
Place these capacitors on L8
(North side,Secondary Layer) 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 2 2

+VCC_CORE

1 1 1 1 1 1 1 1
C530 C529 C528 C527 C526 C525 C135 C136
Place these capacitors on L8
(Sorth side,Secondary Layer) 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 2 2
@ @ @ @

C C
+VCC_CORE

1 1 1 1 1 1 1 1
C149 C150 C151 C152 C153 C154 C155 C156
Place these capacitors on L8
(Sorth side,Secondary Layer) 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 2 2
@ @ @ @ @ @ @ @
Mid Frequence Decoupling

+VCC_CORE

330U_D_2VM 330U_D_2VM @ 330U_D_2VM

ESR <= 1.5m ohm

South Side Secondary North Side Secondary
1 1 1 1 1 1 1 1
C172 + C173 + C171 + C532 + C129 + C523 + C491 + + C490
Capacitor > 1980uF
330U_D_2VM @ 330U_D_2VM
2 2 2 2 2 2 2 2
B B

330U_D_2VM 330U_D_2VM 330U_D_2VM

+VCCP

1 1
330U_D2E_2.5VM_R9

1 1 1 1 1 1 Place these inside

C522 + C531 + C513 C515 C517 C512 C514 C516 socket cavity on L8
330U_D2E_2.5VM_R9 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
(North side
2 2 2 2 2 2 2 2 Secondary)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU Bypass capacitors
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 6 of 48
5 4 3 2 1
 5 4 3 2 1

4 H_D#[0..63] H_A#[3..31] 4 Description at page11.

U6A U6B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_TXN0 MCH_CLKSEL0
J1 HD1# HA4# C9 20 DMI_TXN0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 15
H_D#2 H1 E11 H_A#5 DMI_TXN1 AF39 K18 MCH_CLKSEL1
HD2# HA5# 20 DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 15
H_D#3 J6 G11 H_A#6 DMI_TXN2 AG35 J18 MCH_CLKSEL2
HD3# HA6# 20 DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL2 15
H_D#4 H3 F11 H_A#7 DMI_TXN3 AH39 F18 CFG3 PAD T16
HD4# HA7# 20 DMI_TXN3 DMIRXN3 CFG3
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD T20
D H_D#6 HD5# HA8# H_A#9 CFG4 CFG5 @ D
G1 HD6# HA9# F9 CFG5 F15 CFG5 11
H_D#7 G2 H11 H_A#10 DMI_TXP0 AC35 E18 CFG6 @ PAD T14
HD7# HA10# 20 DMI_TXP0 DMIRXP0 CFG6
H_D#8 K9 J12 H_A#11 DMI_TXP1 AE39 D19 CFG7
HD8# HA11# 20 DMI_TXP1 DMIRXP1 CFG7 CFG7 11
H_D#9 K1 G14 H_A#12 DMI_TXP2 AF35 D16 CFG8 @ PAD T18
HD9# HA12# 20 DMI_TXP2 DMIRXP2 CFG8
H_D#10 H_A#13 DMI_TXP3 CFG9

DMI
K7 HD10# HA13# D9 20 DMI_TXP3 AG39 DMIRXP3 CFG9 G16 CFG9 11
H_D#11 J8 J14 H_A#14 E16 CFG10 @ PAD T17
H_D#12 HD11# HA14# H_A#15 CFG10 CFG11
H4 HD12# HA15# H13 CFG11 D15 CFG11 11
H_D#13 J3 J15 H_A#16 DMI_RXN0 AE37 G15 CFG12 @
HD13# HA16# 20 DMI_RXN0 DMITXN0 CFG12 CFG12 11
H_D#14 K11 F14 H_A#17 DMI_RXN1 AF41 K15 CFG13
HD14# HA17# 20 DMI_RXN1 DMITXN1 CFG13 CFG13 11
H_D#15 H_A#18 DMI_RXN2

CFG
G4 D12 AG37 C15 CFG14 PAD T21
HD15# HA18# 20 DMI_RXN2 DMITXN2 CFG14
H_D#16 T10 A11 H_A#19 DMI_RXN3 AH41 H16 CFG15 PAD T15
HD16# HA19# 20 DMI_RXN3 DMITXN3 CFG15
H_D#17 W11 C11 H_A#20 G18 CFG16 @
HD17# HA20# CFG16 CFG16 11
H_D#18 T3 A12 H_A#21 H15 CFG17 @ PAD T22
H_D#19 HD18# HA21# H_A#22 DMI_RXP0 CFG17 CFG18
U7 HD19# HA22# A13 20 DMI_RXP0 AC37 DMITXP0 CFG18 J25 CFG18 11
H_D#20 U9 E13 H_A#23 DMI_RXP1 AE41 K27 CFG19 @
HD20# HA23# 20 DMI_RXP1 DMITXP1 CFG19 CFG19 11
H_D#21 U11 G13 H_A#24 DMI_RXP2 AF37 J26 CFG20
HD21# HA24# 20 DMI_RXP2 DMITXP2 CFG20 CFG20 11
H_D#22 T11 F12 H_A#25 DMI_RXP3 AG41
HD22# HA25# 20 DMI_RXP3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL 15
H_D#25 T8 C12 H_A#28 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# 13 M_CLK_DDR0 SM_CK0 G_CLKN CLK_MCH_3GPLL# 15
H_D#26 T4 A14 H_A#29 M_CLK_DDR1 AR1
HD26# HA29# 13 M_CLK_DDR1 SM_CK1
H_D#27 W7 C14 H_A#30 M_CLK_DDR2 AW7 A27 GMCH_A27

CLK
HD27# HA30# 14 M_CLK_DDR2 SM_CK2 D_REF_CLKN CLK_MCH_DREFCLK# 15
H_D#28 U5 D14 H_A#31 M_CLK_DDR3 AW40 A26 GMCH_A26
HD28# HA31# 14 M_CLK_DDR3 SM_CK3 D_REF_CLKP CLK_MCH_DREFCLK 15
H_D#29 T9
H_D#30 HD29# M_CLK_DDR#0 GMCH_C40
W6 HD30# 13 M_CLK_DDR#0 AW35 SM_CK0# D_REF_SSCLKN C40 MCH_SSCDREFCLK# 15
H_D#31 T5 M_CLK_DDR#1 AT1 D41 GMCH_D41
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] 4 13
14
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#2 AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP MCH_SSCDREFCLK 15
H_D#33 AA9 G8 H_REQ#1 M_CLK_DDR#3 AY40 H32 MCH_CLKREQ#
HD33# HREQ#1 14 M_CLK_DDR#3 SM_CK3# CLK_REQ# MCH_CLKREQ# 15
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE0_DIMMA
W3 HD35# HREQ#3 F8 13 DDR_CKE0_DIMMA AU20 SM_CKE0
H_D#36 H_REQ#4 DDR_CKE1_DIMMA

DDR MUXING
Y3 HD36# HREQ#4 A8 13 DDR_CKE1_DIMMA AT20 SM_CKE1
H_D#37 Y7 DDR_CKE2_DIMMB BA29 A3
C HD37# 14 DDR_CKE2_DIMMB SM_CKE2 NC0
H_D#38 W5 DDR_CKE3_DIMMB AY29 A39 C
HD38# 14 DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 4 NC2
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS0_DIMMA# AW13 A40
HD40# HADSTB#1 H_ADSTB#1 4 13 DDR_CS0_DIMMA# SM_CS0# NC3
H_D#41 W2 DDR_CS1_DIMMA# AW12 AW1
HD41# 13 DDR_CS1_DIMMA# SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# DDR_CS2_DIMMB# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# 15 14 DDR_CS2_DIMMB# SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK DDR_CS3_DIMMB# AW21 AY1
HD43# HCLKP CLK_MCH_BCLK 15 14 DDR_CS3_DIMMB# SM_CS3# NC6
H_D#44 AA2 BA1
HD44# H_DSTBN#[0..3] 4 NC7

NC
H_D#45 AA6 K4 H_DSTBN#0 M_OCDOCMP0 AL20 BA2
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_OCDOCMP1 SM_OCDCOMP0 NC8
AA10 HD46# HDSTBN#1 T7 AF10 SM_OCDCOMP1 NC9 BA3
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 M_ODT0 NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBP#[0..3] 4 13 M_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 H_DSTBP#0 +1.8V M_ODT1
AB4 HD49# HDSTBP#0 K3 13 M_ODT1 BA12 SM_ODT1 NC12 BA41
H_D#50 AC9 T6 H_DSTBP#1 M_ODT2 AY20 C1
HD50# HDSTBP#1 14 M_ODT2 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 M_ODT3 AU21 AY41
HD51# HDSTBP#2 14 M_ODT3 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 R520 1 SMRCOMPN NC15
AB3 HD53# 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+VCCP H_D#54 AC2 1 2 SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 R515 80.6_0402_1% SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 4 NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
HD56# HDINV#1 H_DINV#1 4 SM_VREF0
H_D#57 AC1 U3 H_DINV#2 V_DDR_MCH_REF AK41
HD57# HDINV#2 H_DINV#2 4 SM_VREF1
H_D#58 H_DINV#3
54.9_0402_1%

54.9_0402_1%

AD7 HD58# HDINV#3 AB10 H_DINV#3 4 RESERVED1 T32

1

H_D#59 AC6 R32

HD59# RESERVED2
R82

R81

H_D#60 AB5 20 PM_BMBUSY# PM_BMBUSY# G28 F3

H_D#61 HD60# H_RESET# R676 PM_EXTTS#0 PM_BMBUSY# RESERVED3
AD10 HD61# HCPURST# B7 H_RESET# 4 13,14 DDR_TS 1 2 @ 0_0603_1% F25 PM_EXTTS0# RESERVED4 F7
H_D#62 H_ADS# R495 2 @ 0_0402_5% PM_EXTTS#1

RESERVED
PM
AD4 HD62# HADS# E8 H_ADS# 4 20,46 DPRSLPVR 1 H26 PM_EXTTS1# RESERVED5 AG11
H_D#63 AC8 E7 H_TRDY# 4,19 H_THERMTRIP# H_THERMTRIP# G6 AF11
HD63# HTRDY# H_TRDY# 4 PM_THERMTRIP# RESERVED6
2

H_XSCOMP/H_YSCOMP trace J9 H_DPWR# 20,25 PWROK PWROK AH33 H7

L width and spacing is 5/20.
HDPWR#
HDRDY# H8 H_DRD Y#
H_DEFER#
H_DPWR# 4
H_DRDY# 4 17,18,19,25,26,28,38 PLT_RST# 2 1 PLTRST_R# AH34
PWROK
RSTIN#
RESERVED7
RESERVED8 J19
J13 C3 R40 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# 4 RESERVED9
H_VREF K13 D4 H_HITM# 18 MCH_ICH_SYNC# K28 A34
HVREF1 HHITM# H_HITM# 4 ICH_SYNC# RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# 4 RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
B HXSCOMP HLOCK# H_LOCK# 4 RESERVED12 B
H_YRCOMP Y1 C7 H_BR0# A35
HYRCOMP HBREQ0# H_BR0# 4 RESERVED13
H_YSCOMP U1 C6 H_BNR#
HYSCOMP HBNR# H_BNR# 4
H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# 4 +3VS
H_SWNG1 W1 A7 H_DBSY# PM@
HYSWING HDBSY# H_DBSY# 4
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# 4
24.9_0402_1%

24.9_0402_1%

V_DDR_MCH_REF
1

Layout Note: R481

trace width and
R72

R73

B4 H_RS#0 PM_EXTTS#0 2 1
HRS0# H_RS#1 Route as short 10K_0402_5%
HRS1# E6 spacing is 20/20.
D6 H_RS#2 as possible
HRS2# R494
H_RS#[0..2] 4
2

PM_EXTTS#1 2 1
CALISTOGA_FCBGA1466~D +1.8V 10K_0402_5%

PM@

1
M_OCDOCMP0
R83 M_OCDOCMP1

Layout Note: 100_0402_1%

40.2_0402_1%

40.2_0402_1%
2
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /

1
V_DDR_MCH_REF
13,14 V_DDR_MCH_REF
0.1U_0402_16V4Z

H_SWNG1 trace width and spacing is 18/20.

1

R503

R519
1 R74
+VCCP +VCCP

2
100_0402_1%
C101

+VCCP
2
2
221_0603_1%

221_0603_1%
1

1
100_0402_1%

@ @
1

R87
R557
R517

A A
2

H_SWNG0 H_SWNG1
2

H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

1 1 Stuff R531 & R532 for A1 Calistoga

1

200_0402_1%

R84
R549

1
R518

C473

C482

C100

2
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 7 of 48
5 4 3 2 1
 5 4 3 2 1

D D

U6D U6E
DDR_A_D[0..63] 13 DDR_B_D[0..63] 14
DDR_A_BS#0 AU12 AJ35 DDR_A_D0 DDR_B_BS#0 AT24 AK39 DDR_B_D0
13 DDR_A_BS#0 SA_BS0 SA_DQ0 14 DDR_B_BS#0 SB_BS0 SB_DQ0
DDR_A_BS#1 AV14 AJ34 DDR_A_D1 DDR_B_BS#1 AV23 AJ37 DDR_B_D1
13 DDR_A_BS#1 SA_BS1 SA_DQ1 14 DDR_B_BS#1 SB_BS1 SB_DQ1
DDR_A_BS#2 BA20 AM31 DDR_A_D2 DDR_B_BS#2 AY28 AP39 DDR_B_D2
13 DDR_A_BS#2 SA_BS2 SA_DQ2 14 DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
13 DDR_A_DM[0..7] AK35 DDR_A_D5 14 DDR_B_DM[0..7] AK38 DDR_B_D5
DDR_A_DM0 SA_DQ5 DDR_A_D6 DDR_B_DM0 SB_DQ5 DDR_B_D6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDR_A_DM1 AM35 AH31 DDR_A_D7 DDR_B_DM1 AR38 AP41 DDR_B_D7
DDR_A_DM2 SA_DM1 SA_DQ7 DDR_A_D8 DDR_B_DM2 SB_DM1 SB_DQ7 DDR_B_D8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDR_A_DM3 AN22 AP33 DDR_A_D9 DDR_B_DM3 BA31 AV41 DDR_B_D9
DDR_A_DM4 SA_DM3 SA_DQ9 DDR_A_D10 DDR_B_DM4 SB_DM3 SB_DQ9 DDR_B_D10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDR_A_DM5 AL9 AP31 DDR_A_D11 DDR_B_DM5 AH8 AV38 DDR_B_D11
DDR_A_DM6 SA_DM5 SA_DQ11 DDR_A_D12 DDR_B_DM6 SB_DM5 SB_DQ11 DDR_B_D12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDR_A_DM7 AH4 AM36 DDR_A_D13 DDR_B_DM7 AN4 AR40 DDR_B_D13
SA_DM7 SA_DQ13 DDR_A_D14 SB_DM7 SB_DQ13 DDR_B_D14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDR_A_D15 AY38 DDR_B_D15
SA_DQ15 DDR_A_D16 SB_DQ15 DDR_B_D16
SA_DQ16 AK26 SB_DQ16 BA38
13 DDR_A_DQS[0..7] AL27 DDR_A_D17 14 DDR_B_DQS[0..7] AV36 DDR_B_D17
DDR_A_DQS0 SA_DQ17 DDR_A_D18 DDR_B_DQS0 SB_DQ17 DDR_B_D18
AK33 SA_DQS0 SA_DQ18 AM26 AM39 SB_DQS0 SB_DQ18 AR36
DDR_A_DQS1 AT33 AN24 DDR_A_D19 DDR_B_DQS1 AT39 AP36 DDR_B_D19
DDR_A_DQS2 SA_DQS1 SA_DQ19 DDR_A_D20 DDR_B_DQS2 SB_DQS1 SB_DQ19 DDR_B_D20
AN28 SA_DQS2 SA_DQ20 AK28 AU35 SB_DQS2 SB_DQ20 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B

DDR_A_DQS3 AM22 AL28 DDR_A_D21 DDR_B_DQS3 AR29 AU36 DDR_B_D21
C DDR_A_DQS4 SA_DQS3 SA_DQ21 DDR_A_D22 DDR_B_DQS4 SB_DQS3 SB_DQ21 DDR_B_D22 C
AN12 SA_DQS4 SA_DQ22 AM24 AR16 SB_DQS4 SB_DQ22 AP35
DDR_A_DQS5 AN8 AP26 DDR_A_D23 DDR_B_DQS5 AR10 AP34 DDR_B_D23
DDR_A_DQS6 SA_DQS5 SA_DQ23 DDR_A_D24 DDR_B_DQS6 SB_DQS5 SB_DQ23 DDR_B_D24
AP3 SA_DQS6 SA_DQ24 AP23 AR7 SB_DQS6 SB_DQ24 AY33
DDR_A_DQS7 AG5 AL22 DDR_A_D25 DDR_B_DQS7 AN5 BA33 DDR_B_D25
SA_DQS7 SA_DQ25 DDR_A_D26 SB_DQS7 SB_DQ25 DDR_B_D26
SA_DQ26 AP21 SB_DQ26 AT31
13 DDR_A_DQS#[0..7] AN20 DDR_A_D27 14 DDR_B_DQS#[0..7] AU29 DDR_B_D27
DDR_A_DQS#0 SA_DQ27 DDR_A_D28 DDR_B_DQS#0 SB_DQ27 DDR_B_D28
AK32 SA_DQS0# SA_DQ28 AL23 AM40 SB_DQS0# SB_DQ28 AU31
DDR_A_DQS#1 AU33 AP24 DDR_A_D29 DDR_B_DQS#1 AU39 AW31 DDR_B_D29
DDR_A_DQS#2 SA_DQS1# SA_DQ29 DDR_A_D30 DDR_B_DQS#2 SB_DQS1# SB_DQ29 DDR_B_D30
AN27 SA_DQS2# SA_DQ30 AP20 AT35 SB_DQS2# SB_DQ30 AV29
DDR_A_DQS#3 AM21 AT21 DDR_A_D31 DDR_B_DQS#3 AP29 AW29 DDR_B_D31
DDR_A_DQS#4 SA_DQS3# SA_DQ31 DDR_A_D32 DDR_B_DQS#4 SB_DQS3# SB_DQ31 DDR_B_D32
AM12 SA_DQS4# SA_DQ32 AR12 AP16 SB_DQS4# SB_DQ32 AM19
DDR_A_DQS#5 AL8 AR14 DDR_A_D33 DDR_B_DQS#5 AT10 AL19 DDR_B_D33
DDR_A_DQS#6 SA_DQS5# SA_DQ33 DDR_A_D34 DDR_B_DQS#6 SB_DQS5# SB_DQ33 DDR_B_D34
AN3 SA_DQS6# SA_DQ34 AP13 AT7 SB_DQS6# SB_DQ34 AP14
DDR_A_DQS#7 AH5 AP12 DDR_A_D35 DDR_B_DQS#7 AP5 AN14 DDR_B_D35
SA_DQS7# SA_DQ35 DDR_A_D36 SB_DQS7# SB_DQ35 DDR_B_D36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDR_A_D37 AM16 DDR_B_D37
SA_DQ37 DDR_A_D38 SB_DQ37 DDR_B_D38
13 DDR_A_MA[0..13] SA_DQ38 AL14 14 DDR_B_MA[0..13] SB_DQ38 AP15
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
DDR_A_MA3 SA_MA2 SA_DQ41 DDR_A_D42 DDR_B_MA3 SB_MA2 SB_DQ41 DDR_B_D42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
DDR_A_MA5 SA_MA4 SA_DQ43 DDR_A_D44 DDR_B_MA5 SB_MA4 SB_DQ43 DDR_B_D44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
DDR_A_MA7 SA_MA6 SA_DQ45 DDR_A_D46 DDR_B_MA7 SB_MA6 SB_DQ45 DDR_B_D46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
DDR_A_MA9 SA_MA8 SA_DQ47 DDR_A_D48 DDR_B_MA9 SB_MA8 SB_DQ47 DDR_B_D48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
DDR_A_MA11 SA_MA10 SA_DQ49 DDR_A_D50 DDR_B_MA11 SB_MA10 SB_DQ49 DDR_B_D50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
DDR_A_MA13 SA_MA12 SA_DQ51 DDR_A_D52 DDR_B_MA13 SB_MA12 SB_DQ51 DDR_B_D52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
B SA_DQ53 DDR_A_D54 SB_DQ53 DDR_B_D54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
13 DDR_A_CAS# AY13 SA_CAS# SA_DQ56 AG7 14 DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
13 DDR_A_RAS# DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
SA_RAS# SA_DQ57 14 DDR_B_RAS# SB_RAS# SB_DQ57
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
13 DDR_A_WE# SA_WE# SA_DQ58 14 DDR_B_WE# SB_WE# SB_DQ58
T7 PAD SA_RCVENIN# AK23 AF6 DDR_A_D59 T19 PAD SB_RCVENIN# AK16 AK3 DDR_B_D59
SA_RCVENOUT# SA_RCVENIN# SA_DQ59 DDR_A_D60 SB_RCVENOUT# SB_RCVENIN# SB_DQ59 DDR_B_D60
T6 PAD AK24 SA_RCVENOUT# SA_DQ60 AG9 T13 PAD AK18 SB_RCVENOUT# SB_DQ60 AT4
AH6 DDR_A_D61 AK5 DDR_B_D61
SA_DQ61 DDR_A_D62 SB_DQ61 DDR_B_D62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63

CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D

PM@ PM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 8 of 48
5 4 3 2 1
 5 4 3 2 1

PCIE_MTX_C_GRX_N[0..15]
17 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
17 PCIE_MTX_C_GRX_P[0..15]
PCEI_GTX_C_MRX_N[0..15]
17 PCIE_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]
D 17 PCIE_GTX_C_MRX_P[0..15] D

+3VS

GM@ PEGCOMP trace width

R56 2 1 2.2K_0402_5% LDDC_CLK L and spacing is 18/25 mils. +1.5VS_PCIE
GM@ R472
R57 2 1 2.2K_0402_5% LDDC_DATA U6C 24.9_0402_1%
H27 D40 PEGCOMP 1 2
R483 1 2.2K_0402_5% GMCH_CRT_CLK SDVOCTRL_DATA EXP_COMPI
2 H28 SDVOCTRL_CLK EXP_COMPO D38

R60 1 2 2.2K_0402_5% GMCH_CRT_DATA F34 PCEI_GTX_C_MRX_N0

GMCH_TXOUT0+ EXP_RXN0 PCEI_GTX_C_MRX_N1
17 GMCH_TXOUT0+ B37 LA_DATA0 EXP_RXN1 G38
R480 1 2 10K_0402_5% LCTLB_DATA GMCH_TXOUT1+ B34 H34 PCEI_GTX_C_MRX_N2
17 GMCH_TXOUT1+ LA_DATA1 EXP_RXN2
@ GMCH_TXOUT2+ A36 J38 PCEI_GTX_C_MRX_N3
17 GMCH_TXOUT2+ LA_DATA2 EXP_RXN3
R478 1 2 10K_0402_5% LCTLA_CLK L34 PCEI_GTX_C_MRX_N4
@ GMCH_TXOUT0- EXP_RXN4 PCEI_GTX_C_MRX_N5
17 GMCH_TXOUT0- C37 LA_DATA#0 EXP_RXN5 M38
GMCH_TXOUT1- B35 N34 PCEI_GTX_C_MRX_N6
17 GMCH_TXOUT1- LA_DATA#1 EXP_RXN6
GMCH_TXOUT2- A37 P38 PCEI_GTX_C_MRX_N7
17 GMCH_TXOUT2- LA_DATA#2 EXP_RXN7
R34 PCEI_GTX_C_MRX_N8
GMCH_TZOUT0+ EXP_RXN8 PCEI_GTX_C_MRX_N9
17 GMCH_TZOUT0+ F30 LB_DATA0 EXP_RXN9 T38
GMCH_TZOUT1+ D29 V34 PCEI_GTX_C_MRX_N10

LVDS
17 GMCH_TZOUT1+ LB_DATA1 EXP_RXN10
GMCH_TZOUT2+ F28 W38 PCEI_GTX_C_MRX_N11
17 GMCH_TZOUT2+ LB_DATA2 EXP_RXN11
Y34 PCEI_GTX_C_MRX_N12
GMCH_TZOUT0- EXP_RXN12 PCEI_GTX_C_MRX_N13
17 GMCH_TZOUT0- G30 LB_DATA#0 EXP_RXN13 AA38
R484 1 2 100K_0402_5% GMCH_ENBKL GMCH_TZOUT1- D30 AB34 PCEI_GTX_C_MRX_N14
17 GMCH_TZOUT1- LB_DATA#1 EXP_RXN14
GMCH_TZOUT2- F29 AC38 PCEI_GTX_C_MRX_N15
17 GMCH_TZOUT2- LB_DATA#2 EXP_RXN15
R55 1 2 1.5K_0402_1% LIBG
GMCH_TXCLK+ A32 D34 PCEI_GTX_C_MRX_P0
C 17 GMCH_TXCLK+ LA_CLK EXP_RXP0
R69 1 2 75_0402_1% GMCH_TV_COMPS GMCH_TXCLK- A33 F38 PCEI_GTX_C_MRX_P1 C
17 GMCH_TXCLK- LA_CLK# EXP_RXP1
GMCH_TZCLK+ E26 G34 PCEI_GTX_C_MRX_P2
17 GMCH_TZCLK+ LB_CLK EXP_RXP2
R68 1 2 150_0402_1% GMCH_TV_LUMA GMCH_TZCLK- E27 H38 PCEI_GTX_C_MRX_P3
17 GMCH_TZCLK- LB_CLK# EXP_RXP3
J34 PCEI_GTX_C_MRX_P4

PCI-EXPRESS GRAPHICS
R67 150_0402_1% GMCH_TV_CRMA EXP_RXP4 PCEI_GTX_C_MRX_P5
1 2 D32 LBKLT_CTL EXP_RXP5 L38
25 GMCH_ENBKL GMCH_ENBKL J30 M34 PCEI_GTX_C_MRX_P6
R8 LBKLT_EN EXP_RXP6
1 2100K_0402_5% GMCH_ENVDD LCTLA_CLK H30 LCTLA_CLK EXP_RXP7 N38 PCEI_GTX_C_MRX_P7
LCTLB_DATA H29 P34 PCEI_GTX_C_MRX_P8
LDDC_CLK LCTLB_DATA EXP_RXP8 PCEI_GTX_C_MRX_P9
17 GMCH_LCD_CLK G26 LDDC_CLK EXP_RXP9 R38
LDDC_DATA G25 T34 PCEI_GTX_C_MRX_P10
17 GMCH_LCD_DATA LDDC_DATA EXP_RXP10
GMCH_ENVDD F32 V38 PCEI_GTX_C_MRX_P11
17 GMCH_ENVDD LVDD_EN EXP_RXP11
LIBG B38 W34 PCEI_GTX_C_MRX_P12
LIBG EXP_RXP12 PCEI_GTX_C_MRX_P13
C35 LVBG EXP_RXP13 Y38
C33 AA34 PCEI_GTX_C_MRX_P14
LVREFH EXP_RXP14 PCEI_GTX_C_MRX_P15
C32 LVREFL EXP_RXP15 AB38

F36 C400 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0

GMCH_TV_COMPS EXP_TXN0 C36 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
A16 TVDAC_A EXP_TXN1 G40
GMCH_TV_LUMA C18 H36 C384 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
16 GMCH_TV_LUMA TVDAC_B EXP_TXN2
GMCH_TV_CRMA A19 J40 C25 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
16 GMCH_TV_CRMA TVDAC_C EXP_TXN3 C398 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4

TV
EXP_TXN4 L36
2 1 TV_REFSET J20 M40 C38 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
R504 4.99K_0402_1% TV_IREF EXP_TXN5 C382 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
EXP_TXN6 N36
2 1 B16 P40 C27 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
R505 0_0402_5% TV_IRTNA EXP_TXN7 C396 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
B18 TV_IRTNB EXP_TXN8 R36
B19 T40 C40 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
TV_IRTNC EXP_TXN9 C380 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
EXP_TXN10 V36
J29 W40 C29 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
TV_DCONSEL1 EXP_TXN11 C394 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
K30 TV_DCONSEL0 EXP_TXN12 Y36
AA40 C42 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
EXP_TXN13 C387 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
EXP_TXN14 AB36
AC40 C31 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
B GMCH_CRT_CLK EXP_TXN15 B
16 GMCH_CRT_CLK C26 DDCCLK
GMCH_CRT_DATA C401 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0

CRT
16 GMCH_CRT_DATA C25 DDCDATA EXP_TXP0 D36
F40 C35 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
EXP_TXP1 C385 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
16 GMCH_CRT_VSYNC H23 VSYNC EXP_TXP2 G36
G23 H40 C24 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
16 GMCH_CRT_HSYNC HSYNC EXP_TXP3
E23 J36 C399 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
16 GMCH_CRT_B BLUE EXP_TXP4
2 1 D23 L40 C37 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
R493 150_0402_1% BLUE# EXP_TXP5 C383 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
16 GMCH_CRT_G C22 GREEN EXP_TXP6 M36
2 1 B22 N40 C26 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
R498 150_0402_1% GREEN# EXP_TXP7 C397 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
16 GMCH_CRT_R A21 RED EXP_TXP8 P36
2 1 B21 R40 C39 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
R502 150_0402_1% RED# EXP_TXP9 C381 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
EXP_TXP10 T36
V40 C28 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
EXP_TXP11 C395 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
1 2 J22 CRT_IREF EXP_TXP12 W36
R499 255_0402_1% Y40 C41 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
EXP_TXP13 C388 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
EXP_TXP14 AA36
AB40 C30 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
EXP_TXP15

CALISTOGA_FCBGA1466~D

PM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 9 of 48
5 4 3 2 1
 5 4 3 2 1

+2.5VS
D D
U6H

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+VCCP H22
VCC_SYNC +2.5VS
1 1 1 1
AC14 VTT0

C416

C418

C427

C430
AB14 VTT1 VCCTX_LVDS0 B30 +2.5VS
W14 VTT2 VCCTX_LVDS1 C30
+1.5VS_PCIE R467 2 2 2 2
V14 VTT3 VCCTX_LVDS2 A30
0_0805_5%
T14
R14
VTT4
VTT5 VCC3G0 AB41 W=40 mils 10U_0805_6.3V6M 2 1 +1.5VS
P14 VTT6 VCC3G1 AJ41
N14 VTT7 VCC3G2 L41 1 1
1 C405 1 C406

220U_D2_4VM
M14 VTT8 VCC3G3 N41
L14 R41 + C23 + C379
VTT9 VCC3G4
AD13 VTT10 VCC3G5 V41
AC13 Y41 10U_0805_6.3V6M
VTT11 VCC3G6 2 2 2 2
AB13 VTT12
1 1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL +3VS_TVDACC +3VS +3VS_TVDACB +3VS +3VS_TVDACA +3VS
330U_D2E_2.5VM_R9

Y13 VTT14 VCCA_3GBG G41 +2.5VS

C497 + C511 + W13 H41 @ 220U_D2_4VM R508 R62 R511
VTT15 VSSA_3GBG
V13 VTT16 2 1 2 1 2 1

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
330U_D2E_2.5VM_R9 U13 L14 BLM11A601S_0603 0_0805_5% 0_0805_5% 0_0805_5%
2 2 VTT17 +2.5VS_CRTDAC

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
T13 VTT18 VCCA_CRTDAC0 E21 1 2 +2.5VS

2200P_0402_50V7K
R13 VTT19 VCCA_CRTDAC1 F21 1 1 1 1 1 1

0.1U_0402_16V4Z
N13 VTT20 VSSA_CRTDAC2 G21

C55

C57
C461

C460

C464

C465
M13 VTT21 1 1
L13 VTT22 2 2 2 2 2 2

C457

C456
AB12 VTT23 VCCA_DPLLA B26 +1.5VS_DPLLA
@ AA12 C39 +1.5VS_DPLLB
VTT24 VCCA_DPLLB 2 2
Y12 VTT25 VCCA_HPLL AF1 +1.5VS_HPLL
W12 VTT26
V12 VTT27
U12 VTT28 VCCA_LVDS A38 +2.5VS
T12 VTT29 VSSA_LVDS B39
C
R12 VTT30 C
P12 VTT31
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL
4.7U_0805_10V4Z

2.2U_0805_16V4Z

L12 VTT34 VCCA_TVBG H20 +3VS_TVBG

R11 VTT35 VSSA_TVBG G20
1 1 P11 VTT36
C480

C438

N11 VTT37
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA
R10 VTT39 VCCA_TVDACA1 F19
2 2
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACB
N10 VTT41 VCCA_TVDACB1 D20
M10
P9
N9
VTT42
VTT43
VCCA_TVDACC0
VCCA_TVDACC1
E20
F20
+3VS_TVDACC
PCI-E/MEM/FSB PLL decoupling
VTT44
M9 VTT45
R8 VTT46 VCCD_HMPLL0 AH1 +1.5VS
P8 VTT47 VCCD_HMPLL1 AH2
N8 +1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
VTT48 R41 R42 R58
M8 VTT49
P7 A28 1 2 2 1 0.022U_0402_16V7K 2 1
VTT50 VCCD_LVDS0 0.5_0805_1% 0_0805_5% 0_0805_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N7 VTT51 VCCD_LVDS1 B28
M7 VTT52 VCCD_LVDS2 C28
R6 VTT53 1 1 1 1 1 1
P6 D21 +1.5VS_TVDAC C34 C462 C449 C53
VTT54 VCCD_TVDAC

C43

C44
M6 VTT55 VCCDQ_TVDAC H19
MCH_A6 A6 0.022U_0402_16V7K
VTT56 2 2 2 2 2 2
0.47U_0603_10V7K

R5 VTT57 VCCHV0 A23 +3VS

P5 VTT58 VCCHV1 B23
0.1U_0402_16V4Z

1 N5 VTT59 VCCHV2 B25

C93

M5 1 1 10U_0805_6.3V6M 10U_0805_6.3V6M
VTT60 C453
P4 VTT61 VCCAUX0 AK31
N4 VTT62 VCCAUX1 AF31
2 @ @
C450

M4 AE31 10U_0805_6.3V6M
VTT63 VCCAUX2 2 2
R3 VTT64 VCCAUX3 AC31
B P3 VTT65 VCCAUX4 AL30 B
+1.5VS_MPLL +1.5VS_HPLL
N3 VTT66 VCCAUX5 AK30
0.22U_0603_10V7K

M3 AJ30 R550 R560

VTT67 VCCAUX6 +1.5VS
R2 VTT68 VCCAUX7 AH30 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
P2 AG30 0_0805_5% 0_0805_5%
VTT69 VCCAUX8
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 M2 VTT70 VCCAUX9 AF30
MCH_D2
C425

D2 VTT71 VCCAUX10 AE30

AB1 VTT72 VCCAUX11 AD30 1 1 1 1 1
0.22U_0603_10V7K

R1 AC30 C483 C494

VTT73 VCCAUX12
MCH_AB1

2
C470

C484

C493
1 P1 VTT74 VCCAUX13 AG29
C102

N1 AF29 10U_0805_6.3V6M 10U_0805_6.3V6M

VTT75 VCCAUX14 2 2 2 2 2
0.47U_0603_10V7K

M1 VTT76 VCCAUX15 AE29

VCCAUX16 AD29
2
1 VCCAUX17 AC29
C103

VCCAUX18 AG28
VCCAUX19 AF28
VCCAUX20 AE28
2 AH22
VCCAUX21
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
AF13 P19 +3VS_TVBG +3VS +1.5VS_DPLLB +1.5VS_DPLLA
VCCAUX36 VCCAUX27 R70
AE13 VCCAUX37 VCCAUX28 P16
+1.5VS AF12 AH15 2 1 R470 R59
VCCAUX38 VCCAUX29 0_0805_5%
AE12 VCCAUX39 VCCAUX30 P15 40mA Max. 2 1 +1.5VS 40mA Max. 2 1 +1.5VS
2200P_0402_50V7K

0_0805_5% 0_0805_5%
0.1U_0402_16V4Z

AD12 VCCAUX40 VCCAUX31 AH14

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
1 1

330U_D2E_2.5VM_R9
1 1
C77

330U_D2E_2.5VM_R9
CALISTOGA_FCBGA1466~D 1 1
C81

C417

C419

C434
PM@ + +
2 2

C441
2 2 2 2
A A

GM@ GM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 10 of 48
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

CFG[3:17] have internal pull up

U6F CFG[19:18] have internal pull down

+VCCP +1.5VS +VCCP U6G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
AC27 AF27 W33 AT41 VCCSM_LF4 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 VCCSM_LF5
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2

0.47U_0603_10V7K

0.47U_0603_10V7K
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved
D D

C32
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)

C33
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34 0 = Lane Reversal Enable
2 2
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation (Default)*
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30 0 = Calistoga *
(Acc ording to Intel Napa Schematic Checklist & CRB
C454

C467

C475

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30

Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30 CFG11 Rev 1.301 document 2.2Kohm pull-down resistor request)
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 1 = Reserved
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29 11 = Normal Operation *(Default)
AB25 AG17 M31 AL29 +1.8V
VCC_NCTF22 VCCAUX_NCTF22 VCC22 VCC_SM22
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 0 = 1.05V *(Default)
10U_0805_6.3V6M U25 AA17 U30 AH28 CFG18 1 = 1.5V
VCC_NCTF27 VCCAUX_NCTF27 VCC27 VCC_SM27
1U_0603_10V4Z

T25 W17 T30 AJ27 1 1 1 1

P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C424

C481

C431

C452
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
C485 C466 AC24 R17 N30 AY26
VCC_NCTF31 VCCAUX_NCTF31 VCC31 VCC_SM31 2 2 2 2
C435

AB24 AG16 M30 AW26 0 = No SDVO Device Present *

2 2 2
AA24
VCC_NCTF32
VCC_NCTF33
VCCAUX_NCTF32
VCCAUX_NCTF33 AF16 L30
VCC32
VCC33
P O W E R VCC_SM32
VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
10U_0805_6.3V6M U24 AB16 V29 AJ26
VCC_NCTF37 VCCAUX_NCTF37 VCC37 VCC_SM37
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is
C C
R24 Y16 R29 AJ25 CFG20
AD23
VCC_NCTF39 VCCAUX_NCTF39
W16 P29
VCC39 VCC_SM39
AH25 operational. *(Default)
VCC_NCTF40 VCCAUX_NCTF40 VCC40 VCC_SM40
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 VCC_NCTF42 VCCAUX_NCTF42 U16 L29 VCC42 VCC_SM42 AH24
330U_D2E_2.5VM_R9 simu.
330U_D2E_2.5VM_R9

T23 VCC_NCTF43 VCCAUX_NCTF43 T16 AB28 VCC43 VCC_SM43 BA23

R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_10V7K
AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22
1 1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22
C99 C492

C54
+ + R22 AC15 R28 AU22
VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22
2 R513
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 7 CFG5 1 2 @ 2.2K_0402_5%
2 2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
@ T21 W15 L28 AK22 R507 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 7 CFG7
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22
AD20 U15 N27 AK21 R509 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55 VCC55 VCC_SM55 7 CFG9
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R514 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 7 CFG11
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19
R20 N26 AW19 R512 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 7 CFG12
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19
V19 AE26 N25 AU19 1 1 R510 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 7 CFG13
U19 AE25 M25 AT19 C92 C52
VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62 R506
T19 VCC_NCTF63 VSS_NCTF3 AE24 L25 VCC63 VCC_SM63 AR19 7 CFG16 1 2 @ 2.2K_0402_5%
1 AD18 VCC_NCTF64 VSS_NCTF4 AE23 P24 VCC64 VCC_SM64 AP19
C495 2 2 10U_0805_6.3V6M
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
+ AB18 AE21 M24 AJ19 10U_0805_6.3V6M
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66
AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18
Y18 VCC_NCTF68 VSS_NCTF8 AE19 AA23 VCC68 VCC_SM68 AJ17
2
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
330U_D2E_2.5VM_R9 V18 AC17 P23 AJ16
B VCC_NCTF70 VSS_NCTF10 VCC70 VCC_SM70 +3VS B
U18 VCC_NCTF71 VSS_NCTF11 Y17 N23 VCC71 VCC_SM71 AH16
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
L23 VCC73 VCC_SM73 AY15
+VCCP R479 2 @ 1K_0402_5%

0.47U_0603_10V7K
AC22 VCC74 VCC_SM74 AW15 7 CFG18 1
+1.8V R482
M19 VCC100 AB22 VCC75 VCC_SM75 AV15 7 CFG19 1 2 @ 1K_0402_5%
L19 AR6 Y22 AU15 1 R490 1 2 @ 1K_0402_5%
VCC101 VCC_SM100 VCC76 VCC_SM76 7 CFG20
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15

C71
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 VCCSM_LF2 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 VCCSM_LF1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_10V7K

0.47U_0603_10V7K

L16 VCC110 N21 VCC85 VCC_SM85 AH12

M21 VCC86 VCC_SM86 AG12 Place near pin BA15
1 1 L21 VCC87 VCC_SM87 AK11
CALISTOGA_FCBGA1466~D AC20 BA8
VCC88 VCC_SM88
C104

C105

AB20 VCC89 VCC_SM89 AY8

Y20 VCC90 VCC_SM90 AW8
PM@ 2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA_FCBGA1466~D
A A

PM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 11 of 48
5 4 3 2 1
 5 4 3 2 1

U6I U6J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23
V35 VSS84 VSS184 AC23 PM@
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21

CALISTOGA_FCBGA1466~D
A A

PM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 12 of 48
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
8 DDR_A_DQS#[0..7] V_DDR_MCH_REF 7,14

8 DDR_A_D[0..63] JP19

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D7 1 1
8 DDR_A_DM[0..7] VSS DQ4
DDR_A_D0 DDR_A_D1

C11

C17
5 DQ0 DQ5 6
8 DDR_A_DQS[0..7] DDR_A_D4 7 8
DQ1 VSS DDR_A_DM0
9 VSS DM0 10
DDR_A_DQS#0 2 2
8 DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D6
15 VSS DQ7 16
DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D12 D
19 DQ3 DQ12 20
21 22 DDR_A_D13
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
27 28
Place near JP27 DDR_A_DQS#1 29
VSS VSS
30 M_CLK_DDR0
M_CLK_DDR0 7
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 7
33 VSS VSS 34
DDR_A_D10 35 36 DDR_A_D9
DDR_A_D11 DQ10 DQ14 DDR_A_D15
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D21 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D16
DQ17 DQ21
47 VSS VSS 48
DDR_A_DQS#2 DDR_TS
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
49 DQS2# NC 50 DDR_TS 7,14
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C59

C95

C72

C56

C89

C65

C87

C64

C78
53 VSS VSS 54
DDR_A_D22 55 56 DDR_A_D18
DDR_A_D19 DQ18 DQ22 DDR_A_D23
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2 2
59 VSS VSS 60
DDR_A_D25 61 62 DDR_A_D29
DDR_A_D24 DQ24 DQ28 DDR_A_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D27 73 74 DDR_A_D26
DDR_A_D30 DQ26 DQ30 DDR_A_D31
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
8 DDR_A_BS#2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 90
Place one cap close to every 2 pullup DDR_A_MA9 91
A12 A11
92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 8
DDR_A_BS#0 107 108 DDR_A_RAS#
8 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 8
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9VS 8 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
8 DDR_A_CAS# CAS# ODT0 M_ODT0 7
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
M_ODT1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7 M_ODT1 119 NC/ODT1 NC 120

121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D35 123 124 DDR_A_D36
DDR_A_D32 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
DDR_A_D34
C463

C468

C472

C474

C476

C477

C478
C62

C70

C73

C79

C85

C91

133 VSS DQ38 134

DDR_A_D39 135 136 DDR_A_D38
DDR_A_D33 DQ34 DQ39
137 DQ35 VSS 138
139 140 DDR_A_D40
DDR_A_D45 VSS DQ44 DDR_A_D44
141 DQ40 DQ45 142
B DDR_A_D41 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D47
DDR_A_D43 DQ42 DQ46 DDR_A_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D52 157 158 DDR_A_D48
DDR_A_D53 DQ48 DQ52 DDR_A_D49
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
+0.9VS NC,TEST CK1 M_CLK_DDR1 7
Layout Note: 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 7
DDR_A_DQS#6 167 168
RP34 RP32 56_0404_4P2R_5%
Pla ce these resistor DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
DDR_A_MA5 1 4 4 1 DDR_A_BS#2 closely JP27,all 171 172
VSS VSS
DDR_A_MA8 2 3 3 2 DDR_CKE0_DIMMA trace length Max=1.5" DDR_A_D51 173 DQ50 DQ54 174 DDR_A_D50
DDR_A_D55 175 176 DDR_A_D54
RP35 56_0404_4P2R_5% RP8 56_0404_4P2R_5% DQ51 DQ55
177 VSS VSS 178
DDR_A_MA1 1 4 4 1 DDR_A_MA6 DDR_A_D56 179 180 DDR_A_D60
DDR_A_MA3 DQ56 DQ60
2 3 3 2 DDR_A_MA7 DDR_A_D61 181 DQ57 DQ61 182 DDR_A_D57
183 VSS VSS 184
RP17 56_0404_4P2R_5% RP33 56_0404_4P2R_5% DDR_A_DM7 185 186 DDR_A_DQS#7
DDR_CS0_DIMMA# 1 DM7 DQS7#
4 4 1 DDR_A_MA9 187 VSS DQS7 188 DDR_A_DQS7
DDR_A_RAS# 2 3 3 2 DDR_A_MA12 DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
RP36 56_0404_4P2R_5% RP11 56_0404_4P2R_5% 193 194 DDR_A_D63
DDR_A_BS#0 VSS DQ63
1 4 4 1 DDR_A_MA2 14,15 CLK_SMBDATA
CLK_SMBDATA 195 SDA VSS 196
DDR_A_MA10 2 3 3 2 DDR_A_MA4 CLK_SMBCLK 197 198
14,15 CLK_SMBCLK SCL SAO
+3VS 199 VDDSPD SA1 200
RP37 56_0404_4P2R_5% RP14 56_0404_4P2R_5%

1
10K_0402_5%

10K_0402_5%
DDR_A_CAS# 1 4 4 1 DDR_A_BS#1 1
DDR_A_WE# 2 3 3 2 DDR_A_MA0 C126 TYCO_1565618-4
A A

R104

R101
RP38 56_0404_4P2R_5% RP20 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2
0.1U_0402_16V4Z
2
SO-DIMM A
3 4 1 DDR_A_MA13

2
M_ODT1 1 4 3 2 M_ODT0

56_0404_4P2R_5% RP5 56_0404_4P2R_5%

4 1 DDR_A_MA11
2 DDR_CKE1_DIMMA
3 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 13 of 48
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
8 DDR_B_DQS#[0..7]

8 DDR_B_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF 7,13
8 DDR_B_DM[0..7] JP20

2.2U_0805_16V4Z

0.1U_0402_16V4Z
8 DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D1
8 DDR_B_MA[0..13] 5 DQ0 DQ5 6
DDR_B_D5

C12

C18
7 DQ1 VSS 8
9 10 DDR_B_DM0
DDR_B_DQS#0 VSS DM0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D2
15 VSS DQ7 16
D DDR_B_D7 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 22
Place near JP26 DDR_B_D8 23
VSS DQ13
24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 7
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 7
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
DDR_B_D21 DDR_B_D16
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
43 DQ16 DQ20 44
1 1 1 1 1 1 1 1 1 1 1 DDR_B_D17 45 46 DDR_B_D20
DQ17 DQ21
C60

C58

C97

C94

C84

C67

C75

C66

C82

220U_D2_4VM

220U_D2_4VM
47 VSS VSS 48
+ C415 + C106 DDR_B_DQS#2 49 50 DDR_TS
DQS2# NC DDR_TS 7,13
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
2 2 DDR_B_D22 DDR_B_D18
55 DQ18 DQ22 56
DDR_B_D23 57 58 DDR_B_D19
DQ19 DQ23
59 VSS VSS 60
DDR_B_D24 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
7 DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB 7
81 VDD VDD 82
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
8 DDR_B_BS#2 85 86
Place one cap close to every 2 pullup 87
BA2 NC/A14
88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS DDR_B_MA9
89 A12 A11 90
DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9VS A10/AP BA1 DDR_B_BS#1 8
DDR_B_BS#0 107 108 DDR_B_RAS#
8 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 8
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
8 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 7
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
8 DDR_B_CAS# CAS# ODT0 M_ODT2 7
DDR_CS3_DIMMB# DDR_B_MA13
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7 DDR_CS3_DIMMB# 115 NC/S1# NC/A13 116

117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
7 M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D37 123 124 DDR_B_D33
DDR_B_D36 DQ32 DQ36 DDR_B_D32
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
DDR_B_DQS#4 DDR_B_DM4
C61

C68

C76

C83

C88

C96

C63

C69

C74

C80

C86

C90

C98

129 DQS4# DM4 130

DDR_B_DQS4 131 132
DQS4 VSS DDR_B_D38
133 VSS DQ38 134
DDR_B_D35 135 136 DDR_B_D39
DDR_B_D34 DQ34 DQ39
137 DQ35 VSS 138
139 140 DDR_B_D44
B DDR_B_D40 VSS DQ44 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D43
DDR_B_D47 DQ42 DQ46 DDR_B_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D49
DDR_B_D53 DQ48 DQ52 DDR_B_D52
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
+0.9VS 163 164 M_CLK_DDR2
closely JP26,all NC,TEST CK1 M_CLK_DDR2 7
165 166 M_CLK_DDR#2
VSS CK1# M_CLK_DDR#2 7
RP15 RP10 56_0404_4P2R_5% trace length Max=1.5" DDR_B_DQS#6 167 DQS6# VSS 168
DDR_B_MA1 1 4 4 1 DDR_B_MA9 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_MA3 DDR_B_MA12 DQS6 DM6
2 3 3 2 171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP18 56_0404_4P2R_5% RP6 56_0404_4P2R_5% 5/16 DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_BS#0 1 4 4 1 DDR_CKE3_DIMMB 177 178
DDR_B_MA10 DDR_B_MA11 DDR_B_D60 VSS VSS DDR_B_D56
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP16 56_0404_4P2R_5% RP13 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_MA0 1 4 4 1 DDR_B_MA5 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_BS#1 DDR_B_MA8 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D58 189 190
RP19 56_0404_4P2R_5% RP9 56_0404_4P2R_5% DDR_B_D59 DQ58 VSS DDR_B_D62
DDR_B_RAS# DDR_B_MA7
5/16 191 DQ59 DQ62 192
DDR_B_D63
1 4 4 1 193 VSS DQ63 194
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6 CLK_SMBDATA 195 196
13,15 CLK_SMBDATA SDA VSS
CLK_SMBCLK 197 198 R106
13,15 CLK_SMBCLK SCL SAO
RP21 56_0404_4P2R_5% RP12 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_CAS# 1 4 4 1 DDR_B_MA4

1
DDR_B_WE# DDR_B_MA2 10K_0402_5%

10K_0402_5%
2 3 3 2 1
A RP23 C127 QUASAR CA0228-200N22 A

R103
56_0404_4P2R_5% RP22 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
M_ODT3
3 4 1 M_ODT2
DDR_B_MA13
0.1U_0402_16V4Z
2
SO-DIMM B
1 4 3 2

2
56_0404_4P2R_5% RP7
4 1 DDR_B_BS#2
DDR_CKE2_DIMMB
3 2 Security Classification Compal Secret Data Compal Electronics, Inc.
56_0404_4P2R_5%
Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 14 of 48
5 4 3 2 1
 5 4 3 2 1

+CK_VDD_MAIN1

+3VS 1 2
R235 0_0805_5% 1 1 1 1
C193 C185 C535 C166
FSLC FSLB FSLA CPU SRC PCI
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz
2 2 2 2

+CK_VDD_MAIN2
0 0 1 133 100 33.3
R125
+3VS 1 2 1 2 CK_VDD_REF
R129 0_0805_5% 1 1 1 1_0805_1% 0 1 1 166 100 33.3
C142 C147 C146 +CK_VDD_DP U9
D 1 2 CK_VDD_48 D
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R124 R126
2 2 2 2.2_0805_1% +VDDAD
1 VDDSRC VDDA 7 2 1 +3VS
49 0_0805_5%
+CK_VDD_DP VDDSRC
R127
5/20 54 VDDSRC GNDA 8
+VDDAD
65 VDDSRC
1 2 +CK_VDD_MAIN1
+3VS
0_0805_5% 1 1 1 1 25 H_STP_PCI# 1
PCI_SRC_STOP# H_STP_PCI# 20
C165 C182 C536 C537 30 C167
VDDPCI H_STP_CPU#
36 VDDPCI CPU_STOP# 24 H_STP_CPU# 20
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 0.1U_0402_16V4Z 2
12 VDDCPU
C168 11 MCH_BCLK 1 2 CLK_MCH_BCLK
CPUCLKT1LP CLK_MCH_BCLK 7
1 2 CK_VDD_REF 18 R132 0_0402_5%
VDDREF MCH_BCLK# 1 CLK_MCH_BCLK#
CPUCLKC1LP 10 2 CLK_MCH_BCLK# 7
22P_0402_50V8J 1 2 C157 1 2 CK_VDD_48 40 R133 0_0402_5%
VDD48
+VCCP

1
C194 0.1U_0402_16V4Z 14 CPU_BCLK 1 2 CLK_CPU_BCLK
CPUCLKT0LP CLK_CPU_BCLK 4
Y1 CLK_XTAL_IN 20 R130 0_0402_5%
14.31818MHZ_20P_6X1430004201 X1 CPU_BCLK# 1 CLK_CPU_BCLK#
13 2
CPUCLKC0LP CLK_CPU_BCLK# 4 Place these components
2

R131 0_0402_5%

2
@ R601 1 2 CLK_XTAL_OUT 19
1K_0402_5% 22P_0402_50V8J C158 R209 12_0402_5% X2
CPUCLKT2_ITP/SRCCLKT10LP 6 near each pin within 40
R602 CLK_Rd 20 CLK_48M_ICH CLK_48M_ICH 2 1
8.2K_0402_5%
22 CLK_48M_CB
CLK_48M_CB 2 1 FSA 41 USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP 5 mils.
1

FSA 2 1 1 2 R223 12_0402_5%

MCH_CLKSEL0 7
FSB 45 CLK_CPU_BCLK 2 1
R599 FSLB/TEST_MODE/24Mhz R120 49.9_0402_1%
5 CPU_BSEL0 1 2 SRCCLKT9LP 3
R603 1K_0402_5% 20 CLK_14M_ICHCLK_14M_ICH 2 1 F SC 23 CLK_CPU_BCLK# 2 @ 1
0_0402_5% R166 33_0402_5% REF0/FSLC/TEST_SEL R121 49.9_0402_1%
Reserve for ICS954305 SRCCLKC9LP 2
1

CLK_Ra @ 33_0402_5% 2 1 R192 @

38 CLK_PCI_TCG
R598 22 CLK_PCI_PCM 33_0402_5% 2 1 R194 PCI_PCM 34 72 CLK_MCH_BCLK 2 1
PCICLK4/FCTSEL1 CLKREQ9# R122 49.9_0402_1%
C C
@ 1K_0402_5% 33_0402_5% 2 1 R188 PCI_EC 33 70 CLK_MCH_BCLK# 2 @ 1
25 CLK_PCI_EC SEL_48M/PCICLK3 SRCCLKT8LP R123 49.9_0402_1%
2

33 CLK_PCI_USB20 33_0402_5% 2 1 R187 PCI_MINI 32 69 @

SEL_24M/PCICLK2 SRCCLKC8LP
R158 2 1 12_0402_5% 27 71
33,38 CLK_PCI_SIO SEL_PCI6/PCICLK1 CLKREQ8#
*0:CLKREQ5# for Pin 29 @ 10K_0402_5%
2 1 R165
+VCCP 66 PCIE_SATA 1 2 CLK_PCIE_SATA
SRCCLKT7LP CLK_PCIE_SATA 19
33,38 CLK_14M_SIO CLK_14M_SIO 2 1 R EF1 22 R151 0_0402_5% CLK_PCIE_GMCH 1 2
R142 33_0402_5% SEL_PCI5/REF1 PCIE_SATA# CLK_PCIE_SATA# R226 49.9_0402_1%
SRCCLKC7LP 67 1 2 CLK_PCIE_SATA# 19
2

R143 0_0402_5% CLK_PCIE_GMCH# 1 @ 2

R587 7 CLK_MCH_DREFCLK CLK_MCH_DREFCLK 1 2 MCH_DREFCLK 43 38 CLKREQ7# 2 1 SATA_CLKREQ# SATA_CLKREQ# 20 R227 49.9_0402_1%
@ R218 GM@ 33_0402_5% DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1 R594 0_0402_5% @
1K_0402_5% 7 CLK_MCH_DREFCLK# CLK_MCH_DREFCLK# 1 2 MCH_DREFCLK# 44 63 CLK_PCIE_VGA 1 2
R219 GM@ 33_0402_5% DOTC_96MHz/27MHz_spread SRCCLKT6LP R228 49.9_0402_1%
1

FSB 1 2 64 CLK_PCIE_VGA# 1 @ 2
MCH_CLKSEL1 7 SRCCLKC6LP
CLK_PCI_ICH 2 R207 1 PCI_ ICH 37 R229 49.9_0402_1%
18 CLK_PCI_ICH ITP_EN/PCICLK_F0
1 2 R588 33_0402_5% 62 @
5 CPU_BSEL1 CLKREQ6#
R593 1K_0402_5% CLK_PCIE_SATA 1 2
0_0402_5% CLK_ENABLE# 39 60 MCH_3GPLL 1 2 CLK_MCH_3GPLL R152 49.9_0402_1%
46 CLK_EN# VTT_PWRGD#/PD SRCCLKT5LP CLK_MCH_3GPLL 7
1

CLK_Rb R167 0_0402_5% CLK_PCIE_SATA# 1 @ 2

R586 R119 61 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# R144 49.9_0402_1%
SRCCLKC5LP CLK_MCH_3GPLL# 7
2 1 9 R160 0_0402_5% @
@ 0_0402_5% GND CLKREQ5# MCH_CLKREQ#
CLKREQ5#/PCICLK6 29 2 1 MCH_CLKREQ# 7
CLK_Re Reserve for ICS954305 & R need change to 475ohm 0_0402_5% R172 0_0402_5%
2

SRCCLKT4LP 58 1 2 CLK_PCIE_MCARD 28
13,14 CLK_SMBCLK CLK_SMBCLK 16 R182 0_0402_5% CLK_MCH_3GPLL 1 2
SMBCLK R168 49.9_0402_1%
SRCCLKC4LP 59 1 2 CLK_PCIE_MCARD# 28
R178 0_0402_5% CLK_MCH_3GPLL# 1 @ 2
57 2 1 MINI_CLKREQ# R161 49.9_0402_1%
+VCCP CLKREQ4# MINI_CLKREQ# 28
CLK_SMBDATA 17 R189 0_0402_5% @
13,14 CLK_SMBDATA SMBDAT
55 P CIE_ICH 1 2 CLK_PCIE_ICH CLK_PCIE_MCARD 1 2
SRCCLKT3LP CLK_PCIE_ICH 20
+3VS R201 0_0402_5% R183 49.9_0402_1%
2

B 4 56 PCIE_ICH# 1 2 CLK_PCIE_ICH# CLK_PCIE_MCARD#1 @ 2 B

GNDSRC SRCCLKC3LP CLK_PCIE_ICH# 20
R149 R196 0_0402_5% R179 49.9_0402_1%
15 28 PCI_CLK5 1 2 0_0402_5% @
GNDCPU CLKREQ3#/PCICLK5 CLK_PCI_TCG 38
R159 @ 1K_0402_5% R580 R581 R186 CLK_PCIE_ICH 1 2
8.2K_0402_5% 21 52 1 2 CLK_PCIE_LAN R202 49.9_0402_1%
GNDREF SRCCLKT2LP CLK_PCIE_LAN 26
1

F SC 2 1 1 2 2.2K_0402_5% 2.2K_0402_5% R214 0_0402_5% CLK_PCIE_ICH# 1 @ 2

MCH_CLKSEL2 7
2N7002_SOT23 Q37 31 53 1 2 CLK_PCIE_LAN# R197 49.9_0402_1%
GNDPCI SRCCLKC2LP CLK_PCIE_LAN# 26
1 2 R148 R215 0_0402_5% @
5 CPU_BSEL2
R157 1K_0402_5% 35 26 CLKREQ2# 2 1 LAN_CLKREQ#
GNDPCI CLKREQ2# LAN_CLKREQ# 26
@ 0_0402_5% 1 3 CLK_SMBDATA R171 0_0402_5%
D

20,26,28 ICH_SMBDATA
1

CLK_Rc 42 50 1 2 CLK_PCIE_VGA CLK_MCH_DREFCLK 1 2

GND48 SRCCLKT1LP CLK_PCIE_VGA 17
R150 R212 0_0402_5% R224 49.9_0402_1%
68 51 1 2 CLK_PCIE_VGA# CLK_MCH_DREFCLK#1 @ 2
CLK_PCIE_VGA# 17
G

GNDSRC SRCCLKC1LP
2

0_0402_5% R213 0_0402_5% R225 49.9_0402_1%

CLK_Rf +3VS 46 CLKREQ1# CLK_PCIE_LAN 1 @ 2
CLKREQ1#
2

73 GM@ R230 49.9_0402_1%

THRM_PAD CLK_PCIE_GMCH CLK_PCIE_LAN# 1 @
74 THRM_PAD LCD100/96/SRC0_TLP 47 1 2 MCH_SSCDREFCLK 7 2
2

75 R210 0_0402_5% R231 49.9_0402_1%

G

THRM_PAD CLK_PCIE_GMCH#
76 THRM_PAD LCD100/96/SRC0_CLP 48 1 2 MCH_SSCDREFCLK# 7 @
20,26,28 ICH_SMBCLK 1 3 CLK_SMBCLK R211 0_0402_5%
GM@
D

2N7002_SOT23
ICS9LPRS325AKLFT_MLF72 Reserve for ICS954305
+3VS Q38
1:24M *0:test Mode 1:48M *0:CLKREQ7# CLKREQ7# 2 R595 1@ 10K_0402_5%
for Pin 45 for Pin 38 +3VS
1

+3VS +3VS +3VS +3VS CLKREQ1# 2 R592 1@ 10K_0402_5%

R239
*1:PCICLK3 for Pin28 CLKREQ2# 2 R164 1@ 10K_0402_5%
1

@ 10K_0402_5% 10K_0402_5%2 R141 1 R EF1

R238 R193 R217 R216 CLKREQ5# 2 R173 1@ 10K_0402_5%
2

CLK_ENABLE#
@ 10K_0402_5% @ 10K_0402_5% @ 10K_0402_5% @ 10K_0402_5% PCI_CLK5 2 R180 1@ 10K_0402_5%
A A
1

R222 PCI_ ICH PCI_MINI PCI_PCM PCI_EC

1

300_0402_5%
R208 R200 R199 R206
1 2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
J10
Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title
1

JUMP_43X79
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
2

for Pin 6,5 for Pin 43,44/47,48 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
2

1:CPU ITP *0:SRC 10 1:27M/SRC0 *0:DOT 96M/LCD100 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 15 of 48

5 4 3 2 1
 A B C D E

CRT Connector Match with Docking resistor to 150ohm

+5VS D_CRT_R R6 1 2 470_0402_1%
D_CRT_G R18 1 2 470_0402_1% Near to JP45
D_CRT_B R434 1 2 470_0402_1%

U3
1
C376
2 0.1U_0402_16V4Z
CRT CONNECTOR +5VS
D25
+R_CRT_VCC
F1
+CRT_VCC

1
W D@ D29 D27 D28 2 1 1 2

25,34,42 DOCKIN#
DOCKIN# 1 SEL
VCC 16
D_CRT_R +2.5VS
CH491D_SC59 1
1A_6VDC_MINISMDC110 C360
CRT Conn.
15 OE# 1B1 2 D_CRT_R 34
5 D_CRT_G
2B1 D_CRT_G 34
11 D_CRT_B DAN217_SC59 DAN217_SC59 DAN217_SC59 0.1U_0402_16V4Z
3B1 D_CRT_B 34

3
2
1
17 VGA_CRT_R 4 1A 4B1 14 @ @ @ 1
1 2 7 JP15
9 GMCH_CRT_R 2A
R28 GM@ 0_0402_5% 9 CRT_R 6
3A
12 4A 1B2 3 11
6 CRT_G D VI_R 1
17 VGA_CRT_G 2B2
9 GMCH_CRT_G 1 2 3B2 10 7
R29 GM@ 0_0402_5% 13 CRT_B L13 12
4B2 CRT_R DVI_G
17 VGA_CRT_B 8 GND 1 2 2
1 2 FCM2012C-800_0805 8
9 GMCH_CRT_B
R30 GM@ 0_0402_5% W D@ FSAV330MTC_TSSOP16 13

1
L10 DVI_B 3
R9 R21 R441 CRT_G 1 2 9
FCM2012C-800_0805 14
Close to VGA conn. 4
150_0402_1% 150_0402_1% L11 1 10

2
150_0402_1% CRT_B 1 2 15
FCM2012C-800_0805 C357 5
2 TYCO_1470801-1
+5VS 1 1 1
C364 C365 C369 1 1 1
VGA_CRT_R 1 2 CRT_R C368 C366 C361 DSUB_12_DATA
R16 WOD@ 0_0402_5% 1 2 2 1 6P_0402_50V8K 6P_0402_50V8K 220P_0402_50V7K
VGA_CRT_G 2 2 2
1 2 CRT_G C375 0.1U_0402_16V4Z R433 10K_0402_5% @ 6P_0402_50V8K DSUB_15_CLK
R22 WOD@ 0_0402_5% 6P_0402_50V8K 2 2 2 @ 6P_0402_50V8K

5
1
VGA_CRT_B 1 2 CRT_B @ 6P_0402_50V8K 1 1
R448 WOD@ 0_0402_5%

OE#
P
2 4 D_CRT_HSYNC C367 C356
17 VGA_CRT_HSYNC A Y D_CRT_HSYNC 34
Pop with No-Docking 2 2

G
1 2 U37
9 GMCH_CRT_HSYNC
R38 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

3
+5VS 68P_0402_50V8K 68P_0402_50V8K
2 2
1 2 D_CRT_HSYNC 1 2 HSYNC
C370 0.1U_0402_16V4Z L12 FCM1608C-121T_0603

5
1
D_CRT_VSYNC 1 2 VSYNC

OE#
P
2 4 D_CRT_VSYNC L9 FCM1608C-121T_0603
17 VGA_CRT_VSYNC A Y D_CRT_VSYNC 34

G
1 2 U36 1 1
9 GMCH_CRT_VSYNC
R39 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5 C363 C358

3
Close to VGA conn. 10P_0402_50V8J 10P_0402_50V8J
2 2
+5VS
+3VS 0_0402_5% 2 1 R431
1

0_0402_5%GM@ R27 R430

1 2 R427 4.7K_0402_5%
9 GMCH_CRT_DATA
2

2
2
G

4.7K_0402_5%
VGA_DDC_DATA 3 1 DSUB_12_DATA
17 VGA_DDC_DATA +3VS
S

Q32
2

BSS138_SOT23
G

2
G
VGA_DDC_CLK 3 1 DSUB_15_CLK
17 VGA_DDC_CLK
VGA_DDC_DATA 3 1 D_DDC_DATA
S

D_DDC_DATA 34
Q31

D
3 BSS138_SOT23 Q33 3
1 2 BSS138_SOT23 GM@
9 GMCH_CRT_CLK
R26
0_0402_5% GM@ 2 1
0_0402_5% PM@ R432
Close to VGA conn. +3VS
1 2 C133
@ 22P_0402_50V8J
17 VGA_TV_LUMA

2
G
1 2 L2 1 2
9 GMCH_TV_LUMA
R34 GM@ 0_0402_5% FBM-11-160808-121T_0603 VGA_DDC_CLK 3 1 D_DDC_CLK
D_DDC_CLK 34

D
L1 Q30
17 VGA_TV_CRMA 1 2
FBM-11-160808-121T_0603 TV-OUT
JP23
Conn. BSS138_SOT23 GM@
9 GMCH_TV_CRMA 1 2
1

R35 GM@ 0_0402_5% 1 2 C130 CRMA_1 4 1. Y ground 2 1

4
1

R113 @ 22P_0402_50V8J LUMA_1 3 6 2. C ground 0_0402_5% PM@ R428

R107 3 6
2 2 5 5 3. Y (luminance+sync)
Close to VGA conn. C128 C140 1 4. C (crominance)
150_0402_1% C131 C132 1
100P_0402_25V8K 100P_0402_25V8K
2

150_0402_1% ALLTO_C10877-104A1-L_4P
2

100P_0402_25V8K 100P_0402_25V8K

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title
CRT & TVout Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 16 of 48
A B C D E
 5 4 3 2 1

+3VS
LCD POWER CIRCUIT VGA BOARD Conn.

1
R33

D2 4.7K_0402_5% JP18
B+ 1 2 +1.8VS

2
VGA_ENVDD R3 1 2PM@ 0_0402_5% BKOFF# 1 2 DISPOFF#
25 BKOFF# 3 4
GMCH_ENVDD R15 5 6
9 GMCH_ENVDD 1 2GM@ 0_0402_5%
7 8
RB751V_SOD323
9 10
11 12
+3VALW 13 14
D U4 PCIE_MTX_C_GRX_N[0..15] D
9 PCIE_MTX_C_GRX_N[0..15] +1.5VS 15 16

5
1
SN74AHCT1G125GW_SOT353-5
PCIE_MTX_C_GRX_P[0..15] 17 18

P
OE#
+LCDVDD 9 PCIE_MTX_C_GRX_P[0..15] 19 20
2 A Y 4 21 22
1 PCEI_GTX_C_MRX_N[0..15]
9 PCIE_GTX_C_MRX_N[0..15] 23 24

G
25 26
1

2
C7 PCEI_GTX_C_MRX_P[0..15]
9 PCIE_GTX_C_MRX_P[0..15] 27 28

3
0.01U_0402_16V7K
2 +3VS 29 30
R25 +2.5VS 31 32
300_0402_5% +3VS
R7 33 34
35 36
1 2

1
100_0402_5% Q35 VGA_LCD_CLK
37 38

3
D S
VGA_LCD_DATA
39 40 +5VALW
Q4 AO3413_SOT23
G
2 2 41 42
2N7002_SOT23 G VGA_TZCLK- VGA_TXCLK-
VGA_TZCLK+ 43 44 VGA_TXCLK+
S 1
D
45 46
3

1
2

+LCDVDD
VGA_TZOUT0- 47 48 VGA_TXOUT0-
R14 C386 VGA_TZOUT0+ 49 50 VGA_TXOUT0+
2 51 52
100K_0402_5% 0.047U_0402_16V7K VGA_TZOUT1- 53 54 VGA_TXOUT1-
1 1 55 56
1

C404 C389 VGA_TZOUT1+ VGA_TXOUT1+

57 58
4.7U_0805_10V4Z 0.1U_0402_16V4Z VGA_TZOUT2- 59 60 VGA_TXOUT2-
2 2 VGA_TZOUT2+ 61 62 VGA_TXOUT2+
63 64
PCEI_GTX_C_MRX_P0 65 66 PCIE_MTX_C_GRX_P0
LCD/PANEL BD. Conn. PCEI_GTX_C_MRX_N0 67
69
68
70
PCIE_MTX_C_GRX_N0

PCEI_GTX_C_MRX_P1 71 72 PCIE_MTX_C_GRX_P1
PCEI_GTX_C_MRX_N1 73 74 PCIE_MTX_C_GRX_N1
B+ B+ 75 76
JP3 PCEI_GTX_C_MRX_P2 77 78 PCIE_MTX_C_GRX_P2
C
PCEI_GTX_C_MRX_N2 79 80 PCIE_MTX_C_GRX_N2 C
DISPOFF# 1 2 DAC_BRIG +3VS 81 82
3 4 DAC_BRIG 25 83 84
+LCDVDD INVT_PWM PCEI_GTX_C_MRX_P3 PCIE_MTX_C_GRX_P3
5 6 INVT_PWM 25 85 86
PCEI_GTX_C_MRX_N3 PCIE_MTX_C_GRX_N3
LCD_DATA 7 8 LCD_CLK 87 88
9 10 PCEI_GTX_C_MRX_P4 89 90 PCIE_MTX_C_GRX_P4
TXCLK+ 11 12 TZCLK- PCEI_GTX_C_MRX_N4 91 92 PCIE_MTX_C_GRX_N4
TXCLK- 13 14 TZCLK+ 93 94
15 16 1 95 96
2 C378 PCEI_GTX_C_MRX_P5 PCIE_MTX_C_GRX_P5
TXOUT2+ 17 18 TZOUT1- PCEI_GTX_C_MRX_N5 97 98 PCIE_MTX_C_GRX_N5
C45 TXOUT2- 19 20 TZOUT1+ 0.1U_0402_16V4Z 99 100
TXOUT1- 21 22 TZOUT2+ 2 PCEI_GTX_C_MRX_P6 101 102 PCIE_MTX_C_GRX_P6
4.7U_0805_10V4Z 23 24 103 104
1 TXOUT1+ TZOUT2- PCEI_GTX_C_MRX_N6 PCIE_MTX_C_GRX_N6
TXOUT0- 25 26 TZOUT0+ 105 106
TXOUT0+ 27 28 TZOUT0- PCEI_GTX_C_MRX_P7 107 108 PCIE_MTX_C_GRX_P7
29 30 PCEI_GTX_C_MRX_N7 109 110 PCIE_MTX_C_GRX_N7
111 112
ACES_88242-3000 PCEI_GTX_C_MRX_P8 113 114 PCIE_MTX_C_GRX_P8
PCEI_GTX_C_MRX_N8 115 116 PCIE_MTX_C_GRX_N8
117 118
PCEI_GTX_C_MRX_P9 119 120 PCIE_MTX_C_GRX_P9
PCEI_GTX_C_MRX_N9 121 122 PCIE_MTX_C_GRX_N9
123 124
PCEI_GTX_C_MRX_P10 125 126 PCIE_MTX_C_GRX_P10
PCEI_GTX_C_MRX_N10 127 128 PCIE_MTX_C_GRX_N10
129 130
PCEI_GTX_C_MRX_P11 131 132 PCIE_MTX_C_GRX_P11
PCEI_GTX_C_MRX_N11 133 134 PCIE_MTX_C_GRX_N11
135 136
0_0402_5% PM@ PCEI_GTX_C_MRX_P12 137 138 PCIE_MTX_C_GRX_P12
LCD_CLK R449 VGA_LCD_CLK PCEI_GTX_C_MRX_N12 139 140 PCIE_MTX_C_GRX_N12
2 1 141 142
LCD_DATA 2 1 R450 VGA_LCD_DATA
0_0402_5% PM@ PCEI_GTX_C_MRX_P13 143 144 PCIE_MTX_C_GRX_P13
B B
PCEI_GTX_C_MRX_N13 145 146 PCIE_MTX_C_GRX_N13
TXOUT0- R461 1 147 148
2PM@ 0_0402_5% VGA_TXOUT0- TZOUT0- R440 1 2PM@ 0_0402_5% VGA_TZOUT0-
149 150
TXOUT0+ R460 1 2PM@ 0_0402_5% VGA_TXOUT0+ TZOUT0+ R439 1 2PM@ 0_0402_5% VGA_TZOUT0+ PCEI_GTX_C_MRX_P14 PCIE_MTX_C_GRX_P14
PCEI_GTX_C_MRX_N14 151 152 PCIE_MTX_C_GRX_N14
TXOUT1- R463 1 153 154
2PM@ 0_0402_5% VGA_TXOUT1- TZOUT1- R435 1 2PM@ 0_0402_5% VGA_TZOUT1-
155 156
TXOUT1+ R462 1 2PM@ 0_0402_5% VGA_TXOUT1+ TZOUT1+ R436 1 2PM@ 0_0402_5% VGA_TZOUT1+ PCEI_GTX_C_MRX_P15 PCIE_MTX_C_GRX_P15
PCEI_GTX_C_MRX_N15 157 158 PCIE_MTX_C_GRX_N15
TXOUT2- R464 1 VGA_TXOUT2- TZOUT2- VGA_TZOUT2- 159 160
2PM@ 0_0402_5% R438 1 2PM@ 0_0402_5% 161 162
TXOUT2+ R468 1 2PM@ 0_0402_5% VGA_TXOUT2+ TZOUT2+ R437 1 2PM@ 0_0402_5% VGA_TZOUT2+ CLK_PCIE_VGA VGA_DDC_CLK
15 CLK_PCIE_VGA 163 164 VGA_DDC_CLK 16
CLK_PCIE_VGA# VGA_DDC_DATA
15 CLK_PCIE_VGA# 165 166 VGA_DDC_DATA 16
TXCLK- R469 1 2PM@ 0_0402_5% VGA_TXCLK- TZCLK- R451 1 2PM@ 0_0402_5% VGA_TZCLK-
TXCLK+ R471 1 167 168
2PM@ 0_0402_5% VGA_TXCLK+ TZCLK+ R452 1 2PM@ 0_0402_5% VGA_TZCLK+
16 VGA_CRT_R
VGA_CRT_R
169 170
VGA_TV_LUMA
VGA_TV_LUMA 16
VGA_CRT_G 171 172 VGA_TV_CRMA
16 VGA_CRT_G 173 174 VGA_TV_CRMA 16
VGA_CRT_B 175 176 VGA_CRT_VSYNC
16 VGA_CRT_B 177 178 VGA_CRT_VSYNC 16
0_0402_5% GM@ VGA_CRT_HSYNC
179 180 VGA_CRT_HSYNC 16
LCD_CLK 2 1 R457 GMCH_LCD_CLK
GMCH_LCD_CLK 9 7,18,19,25,26,28,38 PLT_RST# 181 182
LCD_DATA 2 1 R458 GMCH_LCD_DATA SUSP#
GMCH_LCD_DATA 9 25,29,32,35,39,44,45 SUSP# 183 184 DVI_DET# 34
0_0402_5% GM@ VGA_ENVDD
185 186 DVI_SCLK 34
VGA_ENBKL
25 VGA_ENBKL 187 188 DVI_SDATA 34
TZOUT0- R447 1 2GM@ 0_0402_5% GMCH_TZOUT0- 9 189 190
TXOUT0- R45 1 2GM@ 0_0402_5% TZOUT0+ R446 1 2GM@ 0_0402_5%
GMCH_TXOUT0- 9 GMCH_TZOUT0+ 9 34 DVI_TXC+ 191 192 DVI_TXD1+ 34
TXOUT0+ R44 1 2GM@ 0_0402_5% GMCH_TXOUT0+ 9 34 DVI_TXC- 193 194 DVI_TXD1- 34
TZOUT1- R442 1 2GM@ 0_0402_5% GMCH_TZOUT1- 9 195 196
TXOUT1- R47 1 2GM@ 0_0402_5% TZOUT1+ R443 1 2GM@ 0_0402_5%
GMCH_TXOUT1- 9 GMCH_TZOUT1+ 9 34 DVI_TXD0+ 197 198 DVI_TXD2+ 34
TXOUT1+ R46 1 2GM@ 0_0402_5% GMCH_TXOUT1+ 9 34 DVI_TXD0- 199 200 DVI_TXD2- 34
TZOUT2- R445 1 2GM@ 0_0402_5% GMCH_TZOUT2- 9
TXOUT2- R48 1 2GM@ 0_0402_5% TZOUT2+ R444 1 2GM@ 0_0402_5% ACES_88386-1K71
GMCH_TXOUT2- 9 GMCH_TZOUT2+ 9
TXOUT2+ R49 1 2GM@ 0_0402_5% GMCH_TXOUT2+ 9
TZCLK- R454 1 2GM@ 0_0402_5% GMCH_TZCLK- 9
TXCLK- R50 1 2GM@ 0_0402_5% TZCLK+ R455 1 2GM@ 0_0402_5%
A GMCH_TXCLK- 9 GMCH_TZCLK+ 9 A
TXCLK+ R51 1 2GM@ 0_0402_5% GMCH_TXCLK+ 9

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title
VGA / LCD CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 17 of 48
5 4 3 2 1
 5 4 3 2 1

D D

+3VS

R328 1 2 8.2K_0402_5% PCI_DEVSEL#

R616 1 2 8.2K_0402_5% PCI_STOP#

R617 1 2 8.2K_0402_5% PCI_TRDY#

R615 1 2 8.2K_0402_5% PCI_FRAME# 22,33 PCI_AD[0..31] U21B

PCI_AD0 E18 D7 PCI_REQ0#
R619 1 AD0 REQ0#
2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 AD1 GNT0# E7
PCI_AD2 A16 C16 PCI_REQ1#
R343 1 2 8.2K_0402_5% PCI _IRDY# PCI_AD3 F18
AD2 PCI REQ1#
D16
PCI_AD4 AD3 GNT1# PCI_REQ2#
E16 AD4 REQ2# C17 PCI_REQ2# 22
R334 1 2 8.2K_0402_5% PCI_SERR# PCI_AD5 A18 D17 PCI_GNT2#
AD5 GNT2# PCI_GNT2# 22
PCI_AD6 E17 E13 PCI_REQ3#
R622 1 PCI_PERR# PCI_AD7 AD6 REQ3#
2 8.2K_0402_5% A17 AD7 GNT3# F13
PCI_AD8 A15 A13 PCI_REQ4#
R325 1 PCI_REQ4# PCI_AD9 AD8 REQ4# / GPIO22 ICH_GPIO48 +3VS
2 8.2K_0402_5% C14 AD9 GNT4# / GPIO48 A14
PCI_AD10 E14 C8 PCI_REQ5#
R618 1 AD10 GPIO1 / REQ5#
2 8.2K_0402_5% PCI_REQ3# PCI_AD11 D14 AD11 GPIO17 / GNT5# D8

5
PCI_AD12 B12 U18
PCI_AD13 AD12 PCI_CBE#0 PCI_PCIRST#
C13 B15 PCI_CBE#0 22,33 1

P
PCI_AD14 AD13 C/BE0# PCI_CBE#1 B PCI_RST#
G15 AD14 C/BE1# C12 PCI_CBE#1 22,33 Y 4 PCI_RST# 22,25,26,33,38
PCI_AD15 G13 D12 PCI_CBE#2 2
AD15 C/BE2# PCI_CBE#2 22,33 A

G
PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 22,33
PCI_AD17 C11 @ TC7SH08FU_SSOP5
AD17

3
PCI_AD18 D11 A7 PCI _IRDY# R299
C AD18 IRDY# PCI_IRDY# 22
PCI_AD19 A11 E10 PCI_PAR 0_0402_5% C
AD19 PAR PCI_PAR 22
PCI_AD20 A10 B18 PCI_PCIRST# 2 1
PCI_AD21 AD20 PCIRST# PCI_DEVSEL#
F11 AD21 DEVSEL# A12 PCI_DEVSEL# 22
+3VS PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# 22 +3VS
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# 22
R355 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP#
AD25 STOP# PCI_STOP# 22

5
PCI_AD26 A8 F14 PCI_TRDY# U17
AD26 TRDY# PCI_TRDY# 22,33
R352 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME# PCI_PLTRST# 1
PCI_FRAME# 22,33

P
PCI_AD28 AD27 FRAME# B PLT_RST#
C7 AD28 Y 4 PLT_RST# 7,17,19,25,26,28,38
R348 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD29 B6 C26 PCI_PLTRST# 2
AD29 PLTRST# A

G
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH 15
R346 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 TC7SH08FU_SSOP5
AD31 PME#

3
R630 1 2 8.2K_0402_5% PCI_PIRQE# R296
@ 0_0402_5%
R646 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQA# A3
Interrupt I/F G8 PCI_PIRQE# 2 1
22 PCI_PIRQA# PIRQA# GPIO2 / PIRQE#
PCI_PIRQB# B4 F7 PCI_PIRQF#
22 PCI_PIRQB# PIRQB# GPIO3 / PIRQF#
R634 1 2 8.2K_0402_5% PCI_PIRQG# PCI_PIRQC# C5 F8 PCI_PIRQG#
22 PCI_PIRQC# PIRQC# GPIO4 / PIRQG#
PCI_PIRQD# B5 G7 PCI_PIRQH#
22 PCI_PIRQD# PIRQD# GPIO5 / PIRQH#
R650 1 2 8.2K_0402_5% PCI_PIRQH#

R643 1 2 8.2K_0402_5% PCI_REQ0# AE5

MISC AE9
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8
R306 1 2 8.2K_0402_5% PCI_REQ1# AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R303 1 2 8.2K_0402_5% PCI_REQ2# AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# 7
R624 1 2 8.2K_0402_5% PCI_REQ5# Place closely pin A9
ICH7_BGA652~D
R318 1 2 8.2K_0402_5% ICH_GPIO48
CLK_PCI_ICH
B B

2
R336

@10_0402_5%

1
1
C254

@ 8.2P_0402_50V
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 18 of 48
5 4 3 2 1
 5 4 3 2 1

C308 2 1 10P_0402_50V8K ICH_RTCX1 +5V_SATA +5V_IDE

J5
2 2 1 1

1
32.768KHZ_12.5P_1TJS125BJ2A251 Y2 JP26
2 1 R386 @ JUMP_43X118
NC IN +5VS
GND 1
3 4 10M_0402_5% 2 SATA_TXP0
NC OUT U21A A+ SATA_TXN0 J6
LPC_AD[0..3] 25,33,38 A- 3

2
GND 4 2 2 1 1
LPC_AD0 SATA_RXN0

RTC
AB1 RTXC1 LAD0 AA6 B- 5
C291 2 1 10P_0402_50V8K ICH_RTCX2 AB2 AB5 LPC_AD1 6 SATA_RXP0 JUMP_43X118
RTCX2 LAD1 LPC_AD2 B+
LAD2 AC4 GND 7
+RTCVCC R385 1 2 ICH_RTCRST# AA3 Y6 LPC_AD3
RTCRST# LAD3

LPC
D 20K_0402_5% D
R641
ICH_INTVRMEN W4 AC3 LPC_DRQ#0 J4
CMOS_CLR1 INTVRMEN LDRQ0# LPC_DRQ#0 33
+RTCVCC 1 2 SM_INTRUDER# Y5 AA5 LPC_DRQ#1 8 2 1 +3VS
+3VALW INTRUDER# LDRQ1# / GPIO23 LPC_DRQ#1 38 VCC3.3 2 1
1 2 1M_0402_5% 9
1 2 VCC3.3 +5VS
U31 AB3 LPC_FRAME# 10 JUMP_43X118
LFRAME# LPC_FRAME# 25,33,38 VCC3.3

3
@ 8 1 EEP_CS W1 11
JUMP_43X79 VCC CS EEP_SK EE_CS GND
1 7 NC SK 2 Y1 EE_SHCLK 2 1 R279 10K_0402_5% +3VS GND 12 +5VS 1 2 2 @ AOS 3401_SOT23
C498 C283 6 3 EEP_DOUT Y2 AE22 EC_GA20 13 R351 @240K_0402_5%
NC DI EE_DOUT A20GATE EC_GA20 25 GND
1U_0603_10V4Z EEP_DIN

LAN
5 4 W3 AH28 H_A20M# 14
GND DO EE_DIN A20M# H_A20M# 4 VCC5

CPU
1 2 15 C275 Q24
2 AT93C46-10SI-2.7_SO8 H_CPUSLP_R# VCC5
26 LCI_CLK V3 LAN_CLK CPUSLP# AG27 PAD T29 VCC5 16 +5V_SATA 1 2

1
@ 0.1U_0402_16V4Z 82562@ 17 +5V_IDE
DPRSLP# R271 2 GND
26 LCI_RSTSYNC U3 LAN_RSTSYNC TP1 / DPRSTP# AF24 1 0_0402_5% H_DPRSTP# 4,46 RESERVED 18 @ 1U_0603_10V4Z 1

1
C602 R649 AH25 H_DPSLP# 19
TP2 / DPSLP# H_DPSLP# 4 GND
2 1 1 2 U5 R251 2 1 56_0402_5% +VCCP 20 C270 C274
26 LCI_RXD0 LAN_RXD0 VCC12
@ 10_0402_5% V4 AG26 H_FERR# 21 R345 @0.1U_0402_16V4Z
26 LCI_RXD1 LAN_RXD1 FERR# H_FERR# 4 VCC12 2
@ 10P_0402_25V8K T5 22
26 LCI_RXD2 LAN_RXD2 VCC12
37 ACZ_BITCLK_MDC 33_0402_5% 1 2 R383 AG24 H_PW RGOOD @ 10K_0402_5%
GPIO49 / CPUPWRGD H_PW RGOOD 4

2
26 LCI_TXD0 U7 LAN_TXD0
29 ICH_BITCLK_AUDIO 33_0402_5% 1 2 R384 V6 AG22 H_IGNNE# SUYIN_127043FB022G208ZR_22P_RV @ 10U_0805_10V4Z
26 LCI_TXD1 LAN_TXD1 IGNNE# H_IGNNE# 4

1
26 LCI_TXD2 V7 LAN_TXD2 INIT3_3V# AG21
37 ACZ_SYNC_MDC 33_0402_5% 1 2 R380 AF22 H_INIT#
INIT# H_INIT# 4 +3VS +VCCP
AF25 H_INTR
INTR H_INTR 4
29 ICH_SYNC_AUDIO 33_0402_5% 2 1 R368
ACZ_BITCLK

AC-97/AZALIA
U1 R274 2 1 10K_0402_5% 2
33_0402_5% 1 ACZ_BCLK IDE_RESET# 20
37 ACZ_RST#_MDC 2 R381 ACZ_S YNC R6 ACZ_SYNC RCIN# AG23 EC_KBRST#
EC_KBRST# 25
Q23

1
@ DTC124EK_SC59
29 ICH_RST_AUDIO# 33_0402_5% 2 1 R369 ACZ_RST# R5 AF23 H_SMI# R267
ACZ_RST# SMI# H_SMI# 4
AH24 H_NMI
NMI H_NMI 4

3
ACZ_SDIN0 T2 56_0402_5%
29 ICH_AC_SDIN0 ACZ_SDIN0
ACZ_SDIN1 T3 AH22 H_STPCLK# Reserve for test
37 ACZ_SDIN1 ACZ_SDIN1 STPCLK# H_STPCLK# 4

2
T1 +5VS Place component's closely IDE CONN.
ACZ_SDIN2 THRMTRIP_ICH#
THERMTRIP# AF26 1 R266 2 H_THERMTRIP# 4,7
29 ICH_SDOUT_AUDIO 33_0402_5% 2 1 R371 ACZ_SDOUT T4 24.9_0402_1%
ACZ_SDOUT
C 37 ACZ_SDOUT_MDC 33_0402_5% 2 1 R370 DA0 AH17 PD_A0 ***Must be placed close to AF26 pin within 2" 1 1 1 1 C
25 PHDD_LED# AF18 AE17 PD_A1 C293 C290 C289 C281
SATALED# DA1 PD_A2
DA2 AF17
R311 2 1 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3VS 2 2 2 2
SATA_RXN0_C AF3 AE16 PD_CS#1
+3VALW +RTCVCC 20K_0402_5% SATA_RXP0_C SATA0RXN DCS1# PD_CS#3
AE3 SATA0RXP DCS3# AD16
SATA_TXN0_C AG2
SATA_TXP0_C SATA0TXN

SATA
AH2 SATA0TXP PD_D0
DD0 AB15
ODD CONN
1

AF7 AE14 PD_D1

SATA2RXN DD1 C179
R621 R620 AE7 AG13 PD_D2
SATA2RXP DD2 PD_D3 CD_AGND
AG6 SATA2TXN DD3 AF13 2 1 CD_AGND 29
@ 332K_0402_1% 332K_0402_1% AH6 AD14 PD_D4 10U_0805_10V4Z
SATA2TXP DD4 PD_D5
DD5 AC13
2

15 CLK_PCIE_SATA# CLK_PCIE_SATA# AF1 AD12 PD_D6 JP24

ICH_INTVRMEN CLK_PCIE_SATA AE1 SATA_CLKN DD6 PD_D7 INT_CD_R
15 CLK_PCIE_SATA SATA_CLKP DD7 AC12 29 INT_CD_L 1 2 INT_CD_R 29
AE12 PD_D8 3 4
DD8
1

R333 AH10 AF12 PD_D9 ODD_RST# 5 6 PD_D8

R623 SATARBIASN DD9 PD_D10 PD_D7 PD_D9
1 2 AG10 SATARBIASP DD10 AB13 7 8
AC14 PD_D11 PD_D6 9 10 PD_D10
@ 0_0402_5% 24.9_0402_1% DD11 PD_D12 PD_D5 PD_D11
DD12 AF14 11 12
AH13 PD_D13 PD_D4 13 14 PD_D12
DD13
2

AH14 PD_D14 PD_D3 15 16 PD_D13

4.7K_0402_5% 2 1 R315 PD_IO RDY AG16
IDE DD14
AC15 PD_D15 PD_D2 17 18 PD_D14
+3VS IORDY DD15
8.2K_0402_5% 2 1 R304 PD_IRQ AH16 PD_D1 19 20 PD_D15
PD_DACK# IDEIRQ +3VS PD_D0 PD_DREQ
AF16 DDACK# 21 22
PD_IOW# AH15 AE15 PD_DREQ 23 24 PD_IOR#
DIOW# DDREQ

1
PD_IOR# AF15 PD_IOW# 25 26
DIOR# R108 PD_IO RDY PD_DACK#
27 28
PD_IRQ 29 30
ICH7_BGA652~D 10K_0402_5% PD_A1 31 32 PDIAG# R109 1 2 100K_0402_5% +5VS
PD_A0 33 34 PD_A2

2
C282 3900P_0402_50V7K PD_CS#1 35 36 PD_CS#3
SATA_TXN0_C 1 2 SATA_TXN0 SHDD_LED# 37 38 W=80mils
25 SHDD_LED# +5VS
+5VS 39 40 +5VS
B C279 3900P_0402_50V7K +5VS 41 42 B
+5VS
SATA_TXP0_C 1 2 SATA_TXP0 43 44 2 1
+5VS 1 2 SEC_CSEL 45 46
R95 2 1@ 4.7K_0402_5% 47 48 C524 0.1U_0402_16V4Z
R93 470_0402_5% 49 50

Near ICH7 side. 53 54

RTC Battery +5VS

OCTEK_CDR-50JD1

- BATT1 + +RTCBATT
1 1 1 1
C219 3900P_0402_50V7K 2 1 +RTCBATT C518 C519 C520 C521
SATA_RXN0_C 1 2 SATA_RXN0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C221 3900P_0402_50V7K 2 2 2 2
SATA_RXP0_C 1 2 SATA_RXP0 45@ RTCBATT
1

D17 Place component's closely ODD CONN.

Near Device side. +RTCVCC
BAS40-04_SOT23
3

+CHGRTC +3VALW
1
C310

5
0.1U_0402_16V4Z U32
2 PLT_RST# 1

P
7,17,18,25,26,28,38 PLT_RST# B
4 ODD_RST#
Y
20 ODDRST# 2 A

G
A @ TC7SH08FU_SSOP5 A

3
2 1
R391 33_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(2/4)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 19 of 48
5 4 3 2 1
 5 4 3 2 1

Place closely pin B2 Place closely pin AC1

CLK_48M_ICH CLK_14M_ICH
+3VA +3VA

1
R367 R655

1
2

2
R273 R269 @ 10_0402_5% @ 10_0402_5%
R256 R254

2
2.2K_0402_5% 2.2K_0402_5% U21C
10K_0402_5% 10K_0402_5% R268 1 1

2
ICH_SMBCLK 1 2 0_0402_5% ICH_SMB_CLK C22 AF19 R672 1 2 100_0402_5% C313 C605
15,26,28 ICH_SMBCLK SMBCLK GPIO21 / SATA0GP

1
D ICH_SMBDATA ICH_SMB_DATA D
15,26,28 ICH_SMBDATA 1 2 0_0402_5% B22 SMBDATA GPIO19 / SATA1GP AH18 R673 1 2 100_0402_5%
R272 LINKALERT# R674 100_0402_5% @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C

SMB
SATA
GPIO
A26 LINKALERT# GPIO36 / SATA2GP AH19 1 2
ICH_SMLINK0 R295 100_0402_5% 2 2
B25 SMLINK0 GPIO37 / SATA3GP AE19 1 2
ICH_SMLINK1 A25 SMLINK1

AC1 CLK_14M_ICH
CLK14 CLK_14M_ICH 15

Clocks
EC_SWI# A28 B2 CLK_48M_ICH
25 EC_SWI# RI# CLK48 CLK_48M_ICH 15
SB_SPKR A19
29 SB_SPKR SPKR
SUS_STAT# A27 C20 ICH_SUSCLK T31 PAD
38 SUS_STAT# SUS_STAT# SUSCLK
4 DBRESET# DBRESET# A22 SYS_RST# PM_SLP_S3#

SYS
SLP_S3# B24 PM_SLP_S3# 25
PM_BMBUSY# AB18 D23 SLP_S4#
7 PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# SLP_S5#
SLP_S5# F22
OCP# B23
4 OCP# GPIO11 / SMBALERT#
AA4 PWROK R640
PWROK PWROK 7,25

POWER MGT
H_STP_PCI# AC20 1 2 10K_0402_5%
15 H_STP_PCI# GPIO18 / STPPCI#
H_STP_CPU# DPRSLPVR

GPIO
15 H_STP_CPU# AF21 GPIO20 / STPCPU# GPIO16 / DPRSLPVR AC22 DPRSLPVR 7,46

27 LAN_DISABLE# A21 C21 ICH_LOW_BAT#

GPIO26 TP0 / BATLOW# DPRSLPVR 2 1
B21 C23 PBTN_OUT# R284
35 SB_INT_FLASH_SEL# GPIO27 PWRBTN# PBTN_OUT# 25
E23 100K_0402_5%
+3VS GPIO28
LAN_RST# C19 LAN_RST# 27
10K_0402_5% PM_CLKRUN# AG18
33,38 PM_CLKRUN# GPIO32 / CLKRUN# EC_RSMRST#
R249 1 2 LINKALERT# Y4
RSMRST# EC_RSMRST# 25,26,27
AC19 R645 10K_0402_5%
10K_0402_5% GPIO33 / AZ_DOCK_EN#
19 IDE_RESET# U2 GPIO34 / AZ_DOCK_RST# 1 2
R281 1 2 SIRQ
R614 0_0402_5%
1 2 SB_PCIE_WAKE# F20 E20 EC_SCI#
25,26,28 PCIE_WAKE# WAKE# GPIO9 EC_SCI# 25
8.2K_0402_5% SIRQ AH21 A20
C 22,25,33,38 SIRQ SERIRQ GPIO10 ACIN 25,36,40,43
R297 1 2 PM_CLKRUN# 25 EC_THERM#
EC_THERM# AF20 THRM# GPIO12 F19 BT_DET#
BT_DET# 24
C
E19 EC_LID_OUT#
GPIO13 EC_LID_OUT# 25
R365 2 1 BT_DET# 25,46 VGATE R276 1 2 AD22 R4 NVM_PORT 26
VRMPWRGD GPIO14
GPIO15 E22 SPK_SEL 25
100K_0402_5% 0_0402_5% R3 ODDRST# 19
GPIO24 EC_FLASH#
AC21 GPIO6 GPIO GPIO25 D20 EC_FLASH# 35
+3VA AC18 AD21 SATA_CLKREQ#
GPIO7 GPIO35 / SATAREQ# SATA_CLKREQ# 15
EC_SMI# E21 AD20 Shutdown# 23
25 EC_SMI# GPIO8 GPIO38 +3VA
GPIO39 AE20

ICH7_BGA652~D Need update symbol 1 2 C187

10K_0402_5% 0.1U_0402_16V4Z
R275 1 2 DBRESET#

5
U11
10K_0402_5% 1 SLP_S4#

P
B
R264 1 2 OCP# U21D
25 PM_SLP_S5# 4 Y
PCIE_RXN1 F26 V26 DMI_RXN0 2 SLP_S5#
26 PCIE_RXN1 PERn1 DMI0RXN DMI_RXN0 7 A

G
8.2K_0402_5% PCIE_RXP1 F25 V25 DMI_RXP0
26 PCIE_RXP1 PERp1 DMI0RXP DMI_RXP0 7
2 EC_SWI# PCIE_C_TXN1 DMI_TXN0

DIRECT MEDIA INTERFACE

R245 1 26 PCIE_TXN1 0.1U_0402_16V7K 2 1 C201 E28 U28 TC7SH08FU_SSOP5
PETn1 DMI0TXN DMI_TXN0 7

3
26 PCIE_TXP1 0.1U_0402_16V7K 2 1 C200 PCIE_C_TXP1 E27 U27 DMI_TXP0
PETp1 DMI0TXP DMI_TXP0 7
8.2K_0402_5%
R280 2 1 ICH_LOW_BAT# PCIE_RXN2 H26 Y26 DMI_RXN1
28 PCIE_RXN2 PERn2 DMI1RXN DMI_RXN1 7
PCIE_RXP2 H25 Y25 DMI_RXP1
28 PCIE_RXP2 PERp2 DMI1RXP DMI_RXP1 7
28 PCIE_TXN2 0.1U_0402_16V7K 2 1 C203 PCIE_C_TXN2 G28 W28 DMI_TXN1
PETn2 DMI1TXN DMI_TXN1 7
10K_0402_5% 28 PCIE_TXP2 0.1U_0402_16V7K 2 1 C202 PCIE_C_TXP2 G27 W27 DMI_TXP1
PETp2 DMI1TXP DMI_TXP1 7
R626 1 2 SPI_CS#
DMI_RXN2

PCI-EXPRESS
K26 PERn3 DMI2RXN AB26 DMI_RXN2 7
K25 AB25 DMI_RXP2
PERp3 DMI2RXP DMI_RXP2 7
10K_0402_5% J28 AA28 DMI_TXN2
PETn3 DMI2TXN DMI_TXN2 7
R625 1 2 SPI_MOSI J27 AA27 DMI_TXP2
PETp3 DMI2TXP DMI_TXP2 7
M26 AD25 DMI_RXN3
B PERn4 DMI3RXN DMI_RXN3 7 B
10K_0402_5% M25 AD24 DMI_RXP3
PERp4 DMI3RXP DMI_RXP3 7
R382 1 2 SPI_MISO L28 AC28 DMI_TXN3 RP29
PETn4 DMI3TXN DMI_TXN3 7
L27 AC27 DMI_TXP3 USB_OC#4 4 5
PETp4 DMI3TXP DMI_TXP3 7 +3VA
1K_0402_5% USB_OC#5 3 6
R285 1 2 SB_PCIE_WAKE# P26 AE28 CLK_PCIE_ICH# USB_OC#6 2 7
PERn5 DMI_CLKN CLK_PCIE_ICH# 15
P25 AE27 CLK_PCIE_ICH USB_OC#7 1 8
PERp5 DMI_CLKP CLK_PCIE_ICH 15
N28 PETn5
N27 C25 R610 24.9_0402_1% Within 500 mils 10K_1206_8P4R_5%
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
T25 RP28
PERn6 USB20_N0 USB_OC#3
T24 PERp6 USBP0N F1 USB20_N0 38 4 5
R28 F2 USB20_P0 USB_OC#0 3 6
PETn6 USBP0P USB20_P0 38
R27 G4 USB20_N1 USB_OC#1 2 7
PETp6 USBP1N USB20_N1 28
G3 USB20_P1 USB_OC#2 1 8
USBP1P USB20_P1 28
R2 H1 USB20_N2
SPI_CLK USBP2N USB20_N2 24
SPI_CS# P6 H2 USB20_P2 10K_1206_8P4R_5%
SPI_CS# USBP2P USB20_P2 24
USB20_N3
SPI
P1 SPI_ARB USBP3N J4 USB20_N3 24
J3 USB20_P3
USBP3P USB20_P3 24
SPI_MOSI P5 K1 USB20_N4
SPI_MOSI USBP4N USB20_N4 24
SPI_MISO P2 K2 USB20_P4
SPI_MISO USBP4P USB20_P4 24
L4 USB20_N5
USBP5N USB20_N5 24
L5 USB20_P5
USBP5P USB20_P5 24
USB_OC#0 D3 M1 USB20_N6
OC0# USBP6N USB20_N6 34
USB_OC#1 C4 M2 USB20_P6
USB_OC#2 D5
OC1# USB USBP6P
N4 USB20_N7
USB20_P6 34
OC2# USBP7N USB20_N7 24
USB_OC#3 D4 N3 USB20_P7
OC3# USBP7P USB20_P7 24
USB_OC#4 E5
USB_OC#5 OC4# R656 22.6_0402_1%
C3 OC5# / GPIO29
USB_OC#6 A2 D2 USBRBIAS 1 2
USB_OC#7 OC6# / GPIO30 USBRBIAS#
B3 OC7# / GPIO31 USBRBIAS D1
Within 500 mils
A ICH7_BGA652~D A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 20 of 48
5 4 3 2 1
 5 4 3 2 1

+3VA +3VALW
J8
2 2 1 1
+VCCP
U21F JUMP_43X118 U21E
A4 VSS[0] VSS[98] P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 B8 VSS[3] VSS[101] R12
Vcc1_05[4] L16 1 1 B11 VSS[4] VSS[102] R13
+1.5VS ICH_V5REF_SUS F6 L17 C198 C567 + C218 B14 R14
V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z 330U_D2E_2.5VM_R9 D
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
2 2 2
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
+5VS +3VS AB22 P11 B28 R18
1 1 1 Vcc1_5_B[3] Vcc1_05[9] VSS[9] VSS[107]
C209 + C548 C547 C545 AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z VSS[10] VSS[108]
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
1

AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C27 VSS[12] VSS[110] T13

R338 D14 2 2 2 2
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 D10 VSS[13] VSS[111] T14
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 VSS[14] VSS[112] T15
100_0402_5% CH751H-40_SC76 0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
220U_D2_4VM Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
AD27 Vcc1_5_B[10] Vcc1_05[16] V12 D21 VSS[16] VSS[114] T17
2

AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 VSS[17] VSS[115] U4

ICH_V5REF_RUN Place closely pin D26 V16 E1 U12
Vcc1_5_B[12] Vcc1_05[18] VSS[18] VSS[116]
1 1 D27 V17 E2 U13
C579 C570 D28,T28,AD28. D28
Vcc1_5_B[13] Vcc1_05[19]
V18 E4
VSS[19] VSS[117]
U14
Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
0.1U_0402_16V4Z 0.1U_0402_16V4Z E25 U6 +3VS E15 U16
2 2 Vcc1_5_B[16] Vcc3_3 / VccHDA VSS[23] VSS[120]
E26 Vcc1_5_B[17] 1 F3 VSS[24] VSS[121] U17
F23 R7 +VCCP C587 F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA +3VA VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 VSS[26] VSS[123] U25
G22 AE23 C553 0.1U_0402_16V4Z F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
+5VALW +3VA H23 0.1U_0402_16V4Z G1 V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 2 G2 VSS[31] VSS[128] V24
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G5 VSS[32] VSS[129] V27
1

K22 AB20 1 C552 G6 V28

R337 D15 Vcc1_5_B[26] Vcc3_3[5] C572 0.1U_0402_16V4Z VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 VSS[34] VSS[131] W6
L22 Vcc1_5_B[28] Vcc3_3[7] AD13 1 2 G14 VSS[35] VSS[132] W24
10_0402_5% CH751H-40_SC76 L23 AD18 0.1U_0402_16V4Z G18 W25
Vcc1_5_B[29] Vcc3_3[8] 2 C199 VSS[36] VSS[133]
M22 Vcc1_5_B[30] Vcc3_3[9] AG12 G21 VSS[37] VSS[134] W26
2

ICH_V5REF_SUS M23 AG15 4.7U_0805_10V4Z G24 Y3

Vcc1_5_B[31] Vcc3_3[10] VSS[38] VSS[135]
N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
C C
1 N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
C588 P22 A5 +3VS H3 Y28
Vcc1_5_B[34] Vcc3_3[12] VSS[41] VSS[138]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P23 Vcc1_5_B[35] Vcc3_3[13] B13 H4 VSS[42] VSS[139] AA1
0.1U_0402_16V4Z R22 B16 1 1 1 H5 AA24
2 Vcc1_5_B[36] Vcc3_3[14] VSS[43] VSS[140]
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25

C573

C577

C596
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C551 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VA K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] C558 C565 VSS[55] VSS[152]

C591

C590
V23 Vcc1_5_B[49] VccSus3_3[2] A24 L13 VSS[56] VSS[153] AC2
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 Vcc3_3[1] VccSus3_3[7] K3 +3VA M4 VSS[62] VSS[159] AD4
R241 R250 K4 1 1 M5 AD7
+1.5VS_DMIPLL VccSus3_3[8] C589 C597 VSS[63] VSS[160]
0.01U_0402_16V7K

1 2 1 2 AG28 VccDMIPLL VccSus3_3[9] K5 M12 VSS[64] VSS[161] AD8

10U_0805_10V4Z

VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11

0.5_0805_1% 0_0805_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C210

AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C546

AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C592 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M27 VSS[71] VSS[168] AE8
B 0.1U_0402_16V4Z B
AF6 Vcc1_5_A[7] VccSus3_3[17] M7 M28 VSS[72] VSS[169] AE11
2
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
+1.5VS Place closely pin AG5. AD2 VccSATAPLL Vcc1_5_A[20] AC17 N6 VSS[76] VSS[173] AE24
0.1U_0402_16V4Z

N11 VSS[77] VSS[174] AE25

+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z

1 Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

C600

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8

AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11
C578

1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27

2 C251 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N17 VSS[83] VSS[180] AF28
2 C568 0.1U_0402_16V4Z
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 ICH_K7 PAD T34 N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 C28 ICH_C28 @ PAD T28 N26 AG11
Vcc1_5_A[17] VccSus1_05[2] ICH_G20 VSS[87] VSS[184]
AH9 Vcc1_5_A[18] VccSus1_05[3] G20 PAD T30 P3 VSS[88] VSS[185] AG14
@ P4 VSS[89] VSS[186] AG17
+3VA Place closely pin AG9. E3 VccSus3_3[19] Vcc1_5_A[26] A1 @
+1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C599 C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
1 J6 C586 P15 AH3
0.1U_0402_16V4Z C606 ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
T36 PAD AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 ICH_ Y7 0.1U_0402_16V4Z
T33 PAD Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
@ P24 VSS[96] VSS[193] AH23
2
@ V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2]
W2 ICH7_BGA652~D
ICH_SUSLAN VccSus3_3/VccLAN3_3[3]
+3VA W7 VccSus3_3/VccLAN3_3[4]
1 ICH7_BGA652~D
C583
A A
0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(4/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 21 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS
CHB1608U301_0603
0.01U_0402_16V7K 1 2

L15 +VCC_5IN1
1 1 1 1 1
C563 C561 C560 C559 C556
+AVDD_7411
+3VS 10U_0805_10V4Z 0.1U_0402_16V4Z
CHB1608U301_0603 2 2 2 2 2 R260 100K_0402_5%
2 1 0.1U_0402_16V4Z 0.01U_0402_16V7K MSBS_SDCMD_SMWE# 1 2
C550 0.01U_0402_16V7K 0.1U_0402_16V4Z
L16 1 1 1 1 1 1 2 +VDDPLL R262 100K_0402_5%
C555 C554 C564 C566 C569 0.1U_0402_16V4Z SMRE 1 2
+3VS
D 0.1U_0402_16V4Z 10U_0805_10V4Z 1 2 R261 100K_0402_5% D
2 2 2 2 2 C549 1U_0603_10V4Z SDWP#_SMCE# 1 2
0.1U_0402_16V4Z 0.01U_0402_16V7K
0.01U_0402_16V7K 1 1 1 1 2 R263 22K_0402_5%
SM_RB 1 2
C538 C542 C539 C544 C541

U15

U19
P13
P14

P15

K19

W8
1U_0603_10V4Z

K1

P1
U13B 2 2 2 2 1
0.1U_0402_16V4Z 0.01U_0402_16V7K

VCCP
VCCP
AVDD_33
AVDD_33
AVDD_33

VDDPLL_33
VDDPLL_15

VR_PORT
VR_PORT
PCI_AD[0..31] M1 PCI_AD31
18,33 PCI_AD[0..31] AD31
M2 PCI_AD30
PCI_CBE#[0..3] AD30 PCI_AD29 R176 33_0402_5%
18,33 PCI_CBE#[0..3] AD29 M3
M6 PCI_AD28 MSCLK_SDCLK_SMELWP# 1 2 MSCLK_SDCLK
MC_PWRON# AD28 PCI_AD27
C8 MC_PWR_CTRL_0 AD27 M5
SM_RB F8 N1 PCI_AD26
MC_PWR_CTRL_1/SM_R/B# AD26 PCI_AD25 R175
AD25 N2
N3 PCI_AD24 1 2 SMELWP#
AD24 PCI_AD23
AD23 P3
SD_CD# E9 R1 PCI_AD22 33_0402_5%
MS_CD# SD_CD# AD22 PCI_AD21
A8 MS_CD# AD21 R2
B8 P5 PCI_AD20
SM_CD# AD20
R3 PCI_AD19
place near Chip 7411
AD19 PCI_AD18
AD18 T1
T2 PCI_AD17
MSCLK_SDCLK_SMELWP# AD17 PCI_AD16
A7 MS_CLK/SD_CLK/SM_EL_WP# AD16 W4
MSBS_SDCMD_SMWE# E8 W7 PCI_AD15
MSD3_SDD3_SMD3 MS_BS/SD_CMD/SM_WE# AD15 PCI_AD14
B6 MS_DATA3/SD_DAT3/SM_D3 AD14 R8
MSD2_SDD2_SMD2 A6 U8 PCI_AD13
MSD1_SDD1_SMD1 MS_DATA2/SD_DAT2/SM_D2 AD13 PCI_AD12
C7 MS_DATA1/SD_DAT1/SM_D1 AD12 V8
MSD0_SDD0_SMD0 PCI_AD11
B7 MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD11
AD10
W9
V9
U9
PCI_AD10
PCI_AD9
5 in 1 CardReader Conn.
AD9 PCI_AD8
C AD8 R9 C
V10 PCI_AD7 JP29
SMRE AD7 PCI_AD6
A4 SD_CLK/SM_RE# AD6 U10 +VCC_5IN1 41 XD-VCC SD-VCC 15 +VCC_5IN1
SDCMD_SMALE C5 R10 PCI_AD5 9
SDD0_SMD4 SD_CMD/SM_ALE AD5 PCI_AD4 MSD0_SDD0_SMD0 MS-VCC
C6 SD_DAT0/SM_D4 AD4 W11 33 XD-D0
SDD1_SMD5 A5 V11 PCI_AD3 MSD1_SDD1_SMD1 34 4 IN 1 CONN 16 MSCLK_SDCLK
SDD2_SMD6 SD_DAT1/SM_D5 AD3 PCI_AD2 MSD2_SDD2_SMD2 XD-D1 SD_CLK MSD0_SDD0_SMD0
B5 SD_DAT2/SM_D6 AD2 U11 35 XD-D2 SD-DAT0 19
SDD3_SMD7 E6 P11 PCI_AD1 MSD3_SDD3_SMD3 36 20 MSD1_SDD1_SMD1
SDWP#_SMCE# SD_DAT3/SM_D7 AD1 PCI_AD0 SDD0_SMD4 XD-D3 SD-DAT1 MSD2_SDD2_SMD2
E7 SD_WP/SM_CE# AD0 R11 37 XD-D4 SD-DAT2 11
SDD1_SMD5 38 12 MSD3_SDD3_SMD3
SDD2_SMD6 XD-D5 SD-DAT3 MSBS_SDCMD_SMWE#
G5 SC_PWR_CTRL 39 XD-D6 SD-CMD 13
P2 PCI_CBE#3 SDD3_SMD7 40 21 SD_CD#
SMCLE C/BE3# PCI_CBE#2 XD-D7 SD-CD-SW
B4 SM_CLE C/BE2# U5 SD-CD-COM 22
XD_CD# PCI_CBE#1 MSBS_SDCMD_SMWE# SDWP#_SMCE#
A3 XD_CD#/SM_PHYS_WP#
PCI7412 C/BE1#
C/BE0#
V7
W10 PCI_CBE#0 SMELWP#
SDCMD_SMALE
30
31
29
XD-WE
XD-WP
SD-WP-SW
SD-WP-COM
43
44

XD_CD# XD-ALE MSCLK_SDCLK

PAR U7 PCI_PAR 18 23 XD-CD MS-SCLK 8
R608 1 2 1K_0402_5% P12 R6 PCI_FRAME# 18,33 SM_RB 25 4 MSD0_SDD0_SMD0
R220 1 TEST0 FRAME# XD-R/B MS-DATA0
15 CLK_48M_CB 2 0_0402_5% F1 CLK_48 TRDY# W5 PCI_TRDY# 18,33 SMRE 26 XD-RE MS-DATA1 3 MSD1_SDD1_SMD1
+3VS R605 1 2 4.7K_0402_5% P17 V5 PCI_IRDY# 18 SDWP#_SMCE# 27 5 MSD2_SDD2_SMD2
PHY_TEST_MA IRDY# SMCLE XD-CE MS-DATA2 MSD3_SDD3_SMD3
STOP# V6 PCI_STOP# 18 28 XD-CLE MS-DATA3 7
MS_CD#
1U_0603_10V4Z

2 DEVSEL# U6 PCI_DEVSEL# 18 MS-INS 6

1

1 PCI_AD22 MSBS_SDCMD_SMWE#
C231

R289

R290
56.2_0603_1%

56.2_0603_1%

IDSEL N5 2 R258 32 XD-GND MS-BS 2

R609 6.34K_0402_1% R7 100_0402_5% 24 14
PERR# PCI_PERR# 18 XD-GND SD-GND
1 2 T18 R0 SERR# W6 PCI_SERR# 18 SD-GND 17
1
T19 R1 REQ# L3 PCI_REQ2# 18 42 N.C. MS-GND 1
TYCO_1470383-2 XTPBIAS0 R13 L2 18 10
TPBIAS0 GNT# PCI_GNT2# 18 N.C. MS-GND
2

XTPA0+
4 4 XTPA0-
V14 TPA0P CLK_PCI_PCM TAITW_R007-530-L3
6 G 3 3 W14 TPA0N PCLK L1 CLK_PCI_PCM 15
5 G 2 2 XTPB0+ V13 K3 PCI_RST# PCI_RST# 18,25,26,33,38
XTPB0- TPB0P PRST#
1 1 XTPBIAS1
W13 TPB0N GRST# K5
56.2_0603_1%

5.1K_0603_1% 56.2_0603_1%

W17 TPBIAS1 RI_OUT#/PME# L5

1

JP25 XTPA1+
R287

R288

V16 R606
XTPA1- TPA1P
B W16 TPA1N SUSPEND# J5 1 2 +3VS B
XTPB1+ V15 43K_0402_5% CLK_48M_CB CLK_PCI_PCM
XTPB1- TPB1P
W15 TPB1N SPKROUT H3 PCM_SPK 29

1
CPS R12 CPS
2

G1 R205 R253
MFUNC0 PCI_PIRQA# 18

1
220P_0402_50V7K

X_OUT R18 H5
XO MFUNC1 PCI_PIRQB# 18
1

X_IN R591 @ 10_0402_5% @ 10_0402_5% +VCC_5IN1

C224

1 R19 XI MFUNC2 H2 PCI_PIRQC# 18

R301

H1 33K_0603_1%
MFUNC3 SIRQ 20,25,33,38

2
+3VS J1
MFUNC4 PCI_PIRQD# 18 2 1

2
J2 5IN1_LED C191 C206
2 MFUNC5 5IN1_LED 36

2
J3 2 1 +3VS R310
MFUNC6
2

R607 1 2 CPS R604 10K_0402_5% @ 10P_0402_50V8J @ 15P_0402_50V8J

4.7K_0402_5% 1 2 470_0402_5%
SCL G2 1 2
CLOSE TO CHIP SDA G3 1 R234 2 300_0402_5%

1 1
R600 300_0402_5%
VSSPLL

D
AGND
AGND
AGND

VR_EN# K2
Q21 2 MC_PWRON#
G
CLOSE TO CHIP
2

PCI7412@ PCI7412ZHK_PBGA257 1 S 2N7002_SOT23

R14
U13
U14

R17

3
C204 +3VS
R248 0.1U_0402_16V4Z
1

+VDDPLL +VCC_5IN1
56.2_0603_1%

56.2_0603_1%
1U_0603_10V4Z

1K_0402_5%
C232

R293

R294

2
2
1

2
R298 U16
10K_0402_5% 1 8
1 GND OUT
2

2 IN OUT 7
XTPBIAS1 3 6
IN OUT

1
XTPA1+ MC_PWRON# 4 5 1 1
34 XTPA1+ EN# FLG
XTPA1-
34 XTPA1-
XTPB1+ G528_SO8 C227 C220
34 XTPB1+
XTPB1- 0.1U_0402_16V4Z C222 4.7U_0805_10V4Z
34 XTPB1- 2 2
56.2_0603_1%

5.1K_0603_1% 56.2_0603_1%

A A
1

18P_0402_50V8J C562 X_OUT 1U_0603_10V4Z

R291

R292

X2
24.576MHz_16P_3XG-24576-43E1
2

1
220P_0402_50V7K

1
C228

R302

18P_0402_50V8J C540 X_IN

1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCI7412
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 22 of 48
5 4 3 2 1
 5 4 3 2 1

+S1_VCC +3VS
CardBus Power Switch

U45 +S1_VCC 1 2
13 40mil C594 0.1U_0402_16V4Z
VCC
VCC 12
9 11 C593 0.1U_0402_16V4Z
12V VCC
1 2
C595 10U_0805_10V4Z

A15

P10
F12
F14

L14
+S1_VPP

J19

J14
1 2

P6
P8
F6
F9

L6
J6
U13A 20mil C582 0.01U_0402_25V4Z
+5VS 10 1 2

VCCB
VCCB

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D S1_D10 VPP C580 1U_0603_10V4Z D
C10 CAD31/D10
S1_D9 A10 0.1U_0402_16V4Z C574 5
S1_D1 CAD30/D9 5V
F11 CAD29/D1 DATA/VD2/VPPD1 B9 VPPD1 6 5V
S1_D8 E11 A9 4.7U_0805_10V4Z C576
CAD28/D8 CLOCK/VD1/VCCD0# VCCD0#
S1_D0 C11 C9 1
CAD27/D0 LATCH/VD3/VPPD0 VPPD0 VCCD0 VCCD0#
S1_A0 B13 2
CAD26/A0 VCCD1 VCCD1#
S1_A1 C13 15
CAD25/A1 +3VS VPPD0 VPPD0
S1_A2 A14 14
CAD24/A2 VPPD1 VPPD1
S1_A3 B14
S1_A4 CAD23/A3 0.1U_0402_16V4Z C575
B15 CAD22/A4 3 3.3V
S1_A5 E14 4 8
CAD21/A5 3.3V OC

SHDN
S1_A6 A16 4.7U_0805_10V4Z C571

GND
S1_A25 CAD20/A6
D19 CAD19/A25

2
S1_A7 E17 B10 S1_D2
S1_A24 CAD18/A7 RSVD/D2 R629 TPS2211AIDBR_SSOP16
F15 CAD17/A24 RSVD/VD0/VCCD1# C4 VCCD1#

16
S1_A17 H19 D1 10K_0402_5%
CAD16/A17 RSVD

2
S1_IOWR# J17 E1
S1_A9 CAD15/IOWR# RSVD R174
J15 CAD14/A9 RSVD E2

1
S1_IORD# J18 E3 43K_0402_5% R670 0_0402_5%
S1_A11 CAD13/IORD# RSVD
K15 CAD12/A11 RSVD F2 2 1 Shutdown# 20
S1_OE# K17 F3
CAD11/OE# RSVD

1
S1_CE2# K18 F5 ***
S1_A10 CAD10/CE2# RSVD JP11
L15 CAD9/A10 RSVD G6
S1_D15 L18 H17 S1_A18 1
S1_D7 CAD8/D15 RSVD GND
L19 CAD7/D7 RSVD M19 S1_D14 GND 35
S1_D13 M17 2 S1_D3
S1_D6 CAD6/D13 DATA3 S1_CD1#
M18 CAD5/D6 CD1# 36
S1_D12 S1_D4
S1_D5
N19
M15
CAD4/D12 NC A2
A17
Near to PCMCIA slot. DATA4 3
37 S1_D11
S1_D11 CAD3/D5 NC DATA11 S1_D5
N17 CAD2/D11 NC A18 DATA5 4
S1_D4 N18 B1 38 S1_D12
S1_D3 CAD1/D4 NC +S1_VCC DATA12 S1_D6
P19 CAD0/D3 NC B2 DATA6 5
C S1_D13 C
NC B3 DATA13 39
S1_D7
S1_REG#
S1_A12
E13
E18
CC/BE3#/REG# PCI 7412 NC
NC
B17
B18
B19
1
C223
1
C225
DATA7
DATA14
6
40
7
S1_D14
S1_CE1#
S1_A8 CC/BE2#/A12 NC CE1# S1_D15
H18 CC/BE1#/A8 NC C1 DATA15 41
S1_CE1# L17 C2 10U_0805_10V4Z 0.1U_0402_16V4Z 8 S1_A10
CC/BE0#/CE1# NC 2 2 ADD10 S1_CE2#
NC C3 CE2# 42
S1_A13 H14 C16 9 S1_OE#
S1_A23 CPAR/A13 NC OE# S1_VS1
E19 CFRAME#/A23 NC C17 VS1# 43
S1_A22 G15 C18 10 S1_A11
S1_A15 CTRDY#/A22 NC ADD11 S1_IORD#
F17 CIRDY#/A15 NC C19 IORD# 44
S1_A20 G18 D2 11 S1_A9
S1_A21 CSTOP#/A20 NC ADD9 S1_IOWR#
F19 CDEVSEL#/A21 NC D3 IOWR# 45
S1_A19 H15 D17 +S1_VPP 12 S1_A8
S1_A14 CBLOCK#/A19 NC ADD8 S1_A17
G19 CPERR#/A14 NC D18 ADD17 46
S1_WAIT# C12 E5 13 S1_A13
S1_INPACK# CSERR#/WAIT# NC ADD13 S1_A18
C14 CREQ#/INPACK# NC N14 1 1 ADD18 47
S1_WE# G17 P18 C233 C230 14 S1_A14
S1_BVD1 CGNT#/WE# NC ADD14 S1_A19
A12 CSTSCHG/BVD1(STSCHG#/RI#) NC T3 ADD19 48
R596 S1_WP A11 T17 10U_0805_10V4Z 0.1U_0402_16V4Z 15 S1_WE#
S1_A16_C S1_A16 CCLKRUN#/WP(IOIS16#) NC 2 2 WE# S1_A20
1 2 F18 CCLK/A16 NC U1 ADD20 49
33_0402_5% S1_RDY# E12 U2 16 S1_RDY#
CINT#/READY(IREQ#) NC READY S1_A21
NC U3 ADD21 50
S1_RST C15 U4 17 S1_VCC
CRST#/RESET NC VCC +S1_VCC
NC U12 VCC 51
S1_BVD2 B12 U16 18
CAUDIO/BVD2(SPKR#) NC VPP S1_VPP
NC U17 VPP 52 +S1_VPP
S1_CD1# N15 U18 19 S1_A16_C
S1_CD2# CCD1#/CD1# NC ADD16 S1_A22
B11 CCD2#/CD2# NC V1 ADD22 53
S1_VS1 A13 V2 20 S1_A15
S1_VS2 CVS1/VS1# NC ADD15 S1_A23
B16 CVS2/VS2# NC V3 ADD23 54
V4 21 S1_A12
B NC ADD12 S1_A24 B
NC V12 ADD24 55
C543 E10 V17 22 S1_A7
S1_CD1# A_USB_EN# NC ADD7 S1_A25
2 1 NC V18 ADD25 56
V19 23 S1_A6
100P_0402_25V8K NC ADD6 S1_VS2
NC W2 VS2# 57
W3 24 S1_A5
C183 NC ADD5 S1_RST
NC W12 RESET 58
2 1 S1_CD2# W18 25 S1_A4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC ADD4 S1_WAIT#
WAIT# 59
100P_0402_25V8K 26 S1_A3
PCI7412ZHK_PBGA257 ADD3 S1_INPACK#
INPACK# 60
F7
F10
F13
G14
H6
K6
K14
M14
N6
P7
P9

27 S1_A2
ADD2 S1_REG#
REG# 61
28 S1_A1
ADD1 S1_BVD2
BVD2 62
29 S1_A0
ADD0 S1_BVD1
BVD1 63
PCI7412@ 30 S1_D0
DATA0 S1_D8
DATA8 64
31 S1_D1
DATA1 S1_D9
DATA9 65
32 S1_D2
DATA2 S1_D10
DATA10 66
33 S1_WP
WP S1_CD2#
CD2# 67
GND 34
GND 68

SANTA_130602-2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCI7412
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 23 of 48
5 4 3 2 1
 5 4 3 2 1

USB CONN. 1
+USB_VCCC
W=60mils
+USB_VCCC
1
1 1
C117 + C118 C120
150U_D2_6.3VM
+5VALW +USB_VCCC 0.1U_0402_16V4Z 1000P_0402_50V7K
D D
U43 2 2 2
1 GND OUT 8
2 7 ***
IN OUT JP21
3 IN OUT 6
1 4 EN# FLG 5 1 VCC
C508 2
20 USB20_N4 D-
G528_SO8 3
20 USB20_P4 D+
4.7U_0805_10V4Z 4
2 GND
SUYIN_2537A-04G5T

2
USB_EN# D32
+5VALW 25 USB_EN#
PSOT24C_SOT23
@
Place on the left side
1 C510 C509

1
C611 +

@ 150U_D2_6.3VM 2 2.2P_0402_50V8C 2.2P_0402_50V8C

USB CONN.2
2 port in right side +USB_VCCA
C
W=60mils C
+5VALW +USB_VCCA
ACES_87213-1000
1
1 1 1 1
2 C355 + C350 C351
2 USB_EN# 150U_D2_6.3VM
3 3
4 0.1U_0402_16V4Z 1000P_0402_50V7K
4 2 2 2
5 5 USB20_N2 20
6 ***
6 USB20_P2 20 +5VALW +USB_VCCA
7 7
8 U35 JP14
8 USB20_N3 20
9 9 USB20_P3 20 1 GND OUT 8 1 VCC
10 10 2 IN OUT 7 20 USB20_N5 2 D-
3 IN OUT 6 20 USB20_P5 3 D+
1 4 EN# FLG 5 4 GND
JP34 C359
G528_SO8 SUYIN_2537A-04G5T

2
4.7U_0805_10V4Z
2 D26
PSOT24C_SOT23
@
USB_EN# Place on the rear side
C353 C352
Bluetooth Conn.

1
2.2P_0402_50V8C 2.2P_0402_50V8C
+3VS
B +5VS B

JP7
1

1 1
R92
100K_0402_5% C122 BT_DET# 2
1U_0603_10V4Z 20 BT_DET# 3
2 4
3

+3VS
S
5
2

G
2 6
Q12
7
1

1 SI2301BDS_SOT23 C119 0.1U_0402_16V4Z BT_RESET#

BT_WAKE_UP 8
25 BT_WAKE_UP 9
5

C121 D
U7
10
1

0.1U_0402_16V4Z +BT_VCC 1
25,28 KILL_SW#
P

2 B BT_RESET# 11
25 BT_PWR 2 Y 4 12
W=40mils 25 BT_RST# 2 A 25 BT_DETACH 13
G

1 28 WLAN_BT_CLK 14
Q10 TC7SH08FU_SSOP5
15
3

DTC124EK_SC59 C123 @
20 USB20_P7 16
3

4.7U_0805_10V4Z
2 20 USB20_N7 17
28 WLAN_BT_DATA 18
R88 0_0402_5%
19
+BT_VCC 20
(MAX=200mA) ACES_87151-2005
C124
(Top Contact)
0.1U_0402_16V4Z
A Bluetooth Connector A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title
USB & BT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 24 of 48
5 4 3 2 1
 5 4 3 2 1

+LDO3_EC
+LDO3_EC
+LDO3_EC @ +LDO3

2
J3 EC_CIR@
KBA[0..19] R320 2 1
KBA[0..19] 35 2 1
R198 Change to 0 ohm 0_0402_5%
ADB[0..7] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 JUMP_43X118
ADB[0..7] 35
1 1 C237 1 1 2 2 0_0603_5% +3VALW

1
C217 1 J2
C239 C214 C181 C192 2 1
1000P_0402_50V7K C189 2 1
1000P_0402_50V7K 1 1
L3 2 2 2 2 1 1 C238 C243 JUMP_43X118
2

ECAGND
1 2 ECAGND 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
FBM-L11-160808-800LMT_0603 0.1U_0402_16V4Z 1U_0603_10V4Z
2 2
D For EC Tools D

JP12

123
136
157
166

161

159
KSI[0..7] 1

16
34
45

95

96
KSI[0..7] 36,37 1 +5VALW
U14 2 E51_RXD
LPC_AD0 KSO[0..15] 2 E51_TXD
19,33,38 LPC_AD0 15 KSO[0..15] 36,37 3

VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCA

AGND

VCCBAT

BATGND
C213 LPC_AD1 LAD0 KSO0 3
19,33,38 LPC_AD1 14 LAD1 GPOK0/KSO0 49 4 4
@ 22P_0402_50V8J LPC_AD2 13 50 KSO1
19,33,38 LPC_AD2 LAD2 GPOK1/KSO1
2 1 R259 2 1 @ 33_0402_5% LPC_AD3 10 51 KSO2 @ ACES_85205-0400
19,33,38 LPC_AD3 LAD3 GPOK2/KSO2
9 52 KSO3
19,33,38 LPC_FRAME#
LRST# LFRAME# LPC Interface GPOK3/KSO3 KSO4
165 LRST#/GPIO2C GPOK4/KSO4 53

ENE-KB910-B4
18 56 KSO5
15 CLK_PCI_EC LCLK GPOK5/KSO5
7 57 KSO6
20,22,33,38 SIRQ SERIRQ GPOK6/KSO6
DOCKIN# 25 58 KSO7 Analog Board ID definition,
16,34,42 DOCKIN# CLKRUN#/GPIO0C * GPOK7/KSO7
EC_HDPPD 24 59 KSO8
PM@ 28 EC_HDPPD LPCPD#/GPIO0B * GPOK8/KSO8 KSO9 Please see page 3.
GPOK9/KSO9 60
R243 1 2 0_0402_5% FR D# 150 61 KSO10
17 VGA_ENBKL 35 FRD# RD# GPOK10/KSO10
FW R# 151 64 KSO11 +3VALW

Internal Keyboard
35 FWR# WR# GPOK11/KSO11
GM@ FSEL# 173 65 KSO12
35 FSEL# MEMCS# GPOK12/KSO12
R233 1 2 0_0402_5% ENBKL SELIO# 152 66 KSO13
9 GMCH_ENBKL IOCS# GPOK13/KSO13
ADB0 138 67 KSO14
D0 GPOK14/KSO14

2
ADB1 139 68 KSO15
R316 1 0_0402_5% LRST# ADB2 D1 GPOK15/KSO15 R162
18,22,26,33,38 PCI_RST# 2 140 D2 GPOK16/KSO16 153
ADB3 141 154 KSO17 Ra 100K_0402_5%
D3 GPOK17/KSO17 KSO17
R317 1 2 @ 0_0402_5% ADB4 144
7,17,18,19,26,28,38 PLT_RST# D4
+3VALW ADB5 145 71 KSI0
D5 GPIK0/KSI0 EC_PLAYBTN# 37

1
ADB6 KSI1 AD_BID0

X-BUS Interface
146 D6 GPIK1/KSI1 72 EC_STOPBTN# 37

2
ADB7 147 73 KSI2
D7 GPIK2/KSI2 EC_FRDBTN# 36,37

2
+3VALW R308 KBA0 124 74 KSI3 1
10K_0402_5% A0 GPIK3/KSI3 EC_REVBTN# 36,37
SKU ID definition, KBA1 125 77 KSI4 R169 C184
KBA2 A1/XIOP_TP GPIK4/KSI4 KSI5 18K_0402_1%
126 A2 GPIK5/KSI5 78 Rb
Please see page 3. KBA3 127 79 KSI6 0.1U_0402_16V4Z
1 A3 GPIK6/KSI6 2
2

C KBA4 KSI7 C
128 A4/DMRP_TP GPIK7/KSI7 80

1
R140 KBA5 131
100K_0402_1% PME# KBA6 A5/EMWB_TP INVT_PWM +3VALW
Rc 33,38 PME# 132 A6 GPOW0/PWM0 32 INVT_PWM 17
KBA7 133 33 BEEP#
A7 GPOW1/PWM1 BEEP 29
KBA8 143 36 PWR_SUSP_LED#
A8 FAN2PWM/GPOW2/PWM2 PWR_SUSP_LED# 36
1

2
SKU_ID KBA9 142 37 ACOFF
A9 GPOW3/PWM3 ACOFF 42
KBA10 135 Pulse Width GPOW4/PWM4 38 USB_EN# R247
+3VALW A10 USB_EN# 24 10K_0402_5%
C180 1 2 0.1U_0402_16V4Z KBA11 134 39 EC_ON
A11 GPOW5/PWM5 EC_ON 37,43
KBA12 130 40 EC_LID_OUT#
A12 GPOW6/PWM6 EC_LID_OUT# 20
Rd R155 2 1 0_0402_5% KBA13 129 43 EC_MUTE
A13 FAN1PWM/GPOW7/PWM7 EC_MUTE 30

1
KBA14 121 D10
A14
2

R154 2 1 8.2K_0402_1% KBA15 120 2 ON /OFF

A15 GPWU0 ON/OFF 37
@ KBA16 113 26 2 1
100K_0402_5% A16 GPWU1 ACIN 20,36,40,43
R153 2 1 18K_0402_1% KBA17 112 29 KILL_SW#
R232 A17 GPWU2 KILL_SW# 24,28
@ KBA18 104 30 PM_SLP_S3#
A18 GPWU3 PM_SLP_S3# 20 RB751V_SOD323
R136 2 1 33K_0402_1% KBA19 103 Wake Up Pin 44 PM_SLP_S5#
A19 GPWU4 PM_SLP_S5# 20
1

@ IE_BTN# 108 76
36 IE_BTN# A20/GPIO23 GPWU5 CIR_IN 33
R137 2 1 56K_0402_1% 105 172 PME#
20 SPK_SEL E51CS#/GPIO20/ISPEN TIN1/GPWU6
@ 176 R309 1 2
TIN2/FANFB2/GPWU7 PCIE_WAKE# 20,26,28
R138 2 1 100K_0402_1% KB_CLK 110 @ 0_0402_5% 2 1 ECAGND
34 KB_CLK PSCLK1
@ KB_DATA 111 81 BATT_TEMPA C178 0.01U_0402_16V7K
34 KB_DATA PSDAT1 GPIAD0/AD0 BATT_TEMPA 41
R139 2 1 200K_0402_1% PS_CLK 114 82 SKU_ID
34 PS_CLK PSCLK2 GPIAD1/AD1
@ PS_DATA 115 83 BATT_AOVP
34 PS_DATA
TP_CLK PSDAT2PS2 Interface GPIAD2/AD2 BATT_AOVP 42
37 TP_CLK 116 PSCLK3 GPIAD3/AD3 84
TP_DATA 117 Analog To Digital 87
37 TP_DATA PSDAT3 GPIAD4/AD4
GPIAD5/AD5 88
EC_SMB_CK1 163 89 AD_BID0
35,41 EC_SMB_CK1 SCL1 GPIAD6/AD6
+LDO3_EC EC_SMB_DA1 164 90 1 2
35,41 EC_SMB_DA1 SDA1 GPIAD7/AD7 100K_0402_5% ADP_I 42
EC_SMB_CK2 169 SMBus R191
4,28,34 EC_SMB_CK2 SCL2
1 2 IE_BTN# EC_SMB_DA2 170 99 DAC_BRIG 1 2
4,28,34 EC_SMB_DA2 SDA2 GPODA0/DA0 DAC_BRIG 17
R236 10K_0402_5% 100 BT_PWR C186 0.22U_0402_10V4Z
GPODA1/DA1 BT_PWR 24
B 8 101 IREF B
42 DKN_B+_ON GPIO04 GPODA2/DA2 IREF 42
EC_SCI# 20 102 EN_DFAN1#
20 EC_SCI# GPIO07 GPODA3/DA3 EN_DFAN1 4
BT_RST# 21 Digital To Analog 1
24 BT_RST# GPIO08 GPODA4/DA4 PWROK 7,20
BT_WAKE_UP 22 42
24 BT_WAKE_UP GPIO09 GPODA5/DA5 G_BEEP 30
ENBKL 27 47
GPIO0D GPODA6/DA6 Docking_Ctrl 42
+LDO3_EC BKOFF# 28 174 AUD_SUDMUT_P3# CRY1 1 R319 2 CRY2
17 BKOFF# GPIO0E GPODA7/DA7 AUD_SUDMUT_P3# 34
RP25 FSTCHG 48 @ 20M_0603_5%
42 FSTCHG GPIO10
1 8 MODE# EC_SMI# 62 85 PWR_LED#
20 EC_SMI# GPIO13 * GPIO18/XIO8CS# PWR_LED# 36
2 7 FR D# R145 1 2 DPCONF_S5P_R 63 86 WL_LED
34 DPCONF_S5P GPIO14 * GPIO19/XIO9CS# WL_LED 36
3 6 SELIO# 5.6K_0402_5% 69 91 HDD_LED#
28 WL_OFF# GPIO15 * GPIO1A/XIOACS# HDD_LED# 36
4 5 FSEL# 70 GPIO 92 BATT_LOW_LED#
20 EC_SWI# GPIO16 * GPIO1B/XIOBCS# BATT_LOW_LED# 36
75 Expanded I/O * GPIO1C/XIOCCS# 93 BATT_CHGI_LED#
32 S4_LATCH GPIO17 BATT_CHGI_LED# 36
10K_0804_8P4R_5% 109 94
+5VALW 32 S4_DATA GPIO24 * GPIO1D/XIODCS# VGATE 20,46
+5VS LID_SW# 118 97 HDPACT
37 LID_SW# GPIO25 * GPIO1E/XIOECS# HDPACT 28
RP27 RP24 MODE# 119 98 HDPINT HDPINT 28 1 1
36 MODE# GPIO26 * GPIO1F/XIOFCS#
1 8 EC_SMB_CK1 1 8 KB_CLK SYSON 148 C248 C247
32,36,39,44 SYSON GPIO27

4
2 7 EC_SMB_DA1 2 7 KB_DATA SUSP# 149 171 FAN_SPEED1 1 R329 2 0_0402_5%
17,29,32,35,39,44,45 SUSP# GPIO28 GPIO2E/TOUT1/FANFB1 FAN_SPEED1 4
EC_SMB_CK2 6 PS_CLK VR_ON 1394_PHYRST_S3P X1

10P_0402_50V8J

10P_0402_50V8J
3 6 3 46 VR_ON 155 12 1394_PHYRST_S3P 34

OUT
IN
EC_SMB_DA2 GPIO29 DPLL_TP/GPIO06/FANFB3 2 2
4 5 4 5 PS_DATA 34 EJCTSW#
EJCTSW# 156 GPIO2A FANTEST_TP/GPIO05/FAN3PWM 11 1394_DILSON_S3P
1394_DILSON_S3P 34
BT_DETACH 162
24 BT_DETACH GPIO2B
4.7K_0804_8P4R_5% 4.7K_0804_8P4R_5% PBTN_OUT# 168 175 EC_THERM#
20 PBTN_OUT# GPIO2D TOUT2/GPIO2F EC_THERM# 20
Timer Pin

NC

NC
PADS_LED# 55 3
37 PADS_LED# FnLock#/GPIO12 * E51IT0/GPIO00 EC_RSMRST# 20,26,27
C207 0.1U_0402_16V4Z CAPS_LED# 54 4 SHDD_LED#
+5VS 37 CAPS_LED# CapLock#/GPIO011 * E51IT1/GPIO01 SHDD_LED# 19

3
2 1 NUM_LED# 23 106 E51_RXD 1 2 ALI/MH#
37 NUM_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK ALI/MH# 41
41 107 E51_TXD R242 0_0402_5%
19 PHDD_LED# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
2 1 TP_CLK +3VALW 2 1 19 ECRST# MISC
4.7K_0402_5% R257 R252 47K_0402_5% 5 158 CRY2
19 EC_GA20 GA20/GPIO02 XCLKI
2 1 TP_DATA 19 EC_KBRST# 6 KBRST#/GPIO03 XCLKO 160 CRY1 32.768KHZ_12.5P_1TJS125BJ2A251
4.7K_0402_5% R265 31
GND
GND
GND
GND
GND
GND

ECSCI#
A A
KB910Q B4_LQFP176
17
35
46
122
137
167

1 2 ENBKL
+3VALW R221 @ 120K_0402_5%

2 1 KBA1 1 2 DPCONF_S5P_R
1K_0402_5% R277 R146 10K_0402_5%
KBA4
1K_0402_5%
2 1
R282 1 2 1394_DILSON_S3P Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 KBA5 R147 1K_0402_5% 2005/06/01 2006/06/01 Title
1K_0402_5% R286
Issued Date Deciphered Date
2 1 EJCTSW# 1 2 1394_PHYRST_S3P ENE-KB910
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
100K_0402_5% R307 R184 1K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 25 of 48
5 4 3 2 1
 5 4 3 2 1

+3VLAN R425 2 1 200_0402_5%

R426 2 1 200_0402_5%
Tekoa 82573E -> IAMT support only (WoL Support)
***
Vidalia 82573L -> No management *ICH7 SMBALRT# signal reserve* 12
JP13
Amber LED+
82562GZ -> 10/100 support *a 0ohm resistor connect to S0 power*
34 LAN_ACTIVITY#
LAN_ACTIVITY#T=10mil 11 Amber LED-
Must pull high to S0 power SHLD2 16
RJ45_MDI3- 8
U41A for system power good 34 RJ45_MDI3- PR4-
SHLD1 15
20 PCIE_TXP1 F2 N11 R537 1 82573@ 2 3.3K_0603_5% +3VS RJ45_MDI3+ 7
PE_R0p-NC SMB_ALRT#-NC 34 RJ45_MDI3+ PR4+
20 PCIE_TXN1 F1 M11 ICH_SMBDATA
PE_R0n-NC SMB_DATA-NC ICH_SMBDATA 15,20,28
D P11 ICH_SMBCLK RJ45_MDI1- 6 D
SMB_CLK-NC ICH_SMBCLK 15,20,28 34 RJ45_MDI1- PR2-
0.1U_0402_16V7K 2 1 C447 82573@ D1
20 PCIE_RXP1 PE_T0p-NC
0.1U_0402_16V7K 2 1 C448 82573@ C1 C13 LAN_MDI0P RJ45_MDI2- 5
20 PCIE_RXN1 PE_T0n-NC MDIOp-TDP 34 RJ45_MDI2- PR3-
C14 LAN_MDI0N
MDIOn-TDN LAN_MDI1P RJ45_MDI2+
15 CLK_PCIE_LAN G1 PE_CLKp-NC MDI1p-RDP E13 34 RJ45_MDI2+ 4 PR3+
G2 E14 LAN_MDI1N
15 CLK_PCIE_LAN# PE_CLKn-NC MDI1n-RDN
F13 LAN_MDI2P RJ45_MDI1+ 3
MDI2p-NC 34 RJ45_MDI1+ PR2+
PAD~D T3 L3 F14 LAN_MDI2N
PAD~D T2 THERMp-NC MDI2n-NC LAN_MDI3P RJ45_MDI0-
L2 THERMn-NC MDI3p-NC H13 34 RJ45_MDI0- 2 PR1-
H14 LAN_MDI3N 14 Chassis ground
82562@ PAD~D T27 MDI3n-NC RJ45_MDI0+ SHLD2
Only stuff for 82562 bias B12 PHY_TESTp-TOUT 34 RJ45_MDI0+ 1 PR1+
R71 1 2 649_0603_1% B13 B11 13
R540 1 PHY_TESTn-RBIAS100 LED0#-SPEED_LED SHLD1
2 619_0402_1% B14 PHY_TSTPT-RBIAS10 LED1#-ACT_LED C11 LAN_ACTIVITY#
34 LAN_LINK#
LAN_LINK# T=10mil 10
Green LED-
82562@ A12 LAN_LINK#
PAD~D T4 LED2#-LILED
C7 SDP[3]-NC 9 Green LED+
PAD~D T26 C8 M12 R527 1 2 0_0402_5% 82562@ LCI_RXD2
SDP[2]-NC NC-JRXD[2] LCI_RXD2 19
PAD~D T24 B8 N13 R545 1 2 0_0402_5% 82562@ LCI_RXD1 TYCO_3-440470-4
SDP[1]-NC NC-JRXD[1] LCI_RXD1 19
PAD~D T23 A8 P13 R526 1 2 0_0402_5% 82562@ LCI_RXD0
SDP[0]-NC NC-JRXD[0] LCI_RXD0 19
M13 R544 1 2 0_0402_5% 82562@ LCI_RSTSYNC
NC-JRST_SYNC LCI_RSTSYNC 19

27 LAN_SPI_MOSI SPI_MOSI A9
SPI_MOSO NVM_SI-NC R523 1
27 LAN_SPI_MOSO B9 NVM_SO-NC CLK_VIEW-JTXD[2] L14 2 0_0402_5% 82562@ LCI_TXD2
LCI_TXD2 19 34 RJ45_GND
RJ45_GND 1 2 LANGND
27 LAN_SPI_CE# SPI_CE# B10 1 1
SPI_CLK NVM_CE#-NC R543 1
27 LAN_SPI_CLK C9 NVM_SK-NC NC-JXD[1] L13 2 0_0402_5% 82562@ LCI_TXD1
LCI_TXD1 19
C354
1000P_1206_2KV7K C348 C349
Pull high support D3 LAN1_XO K14 M14 R524 1 2 0_0402_5% 82562@ LCI_TXD0 4.7U_0805_10V4Z
XTAL1-XTAL1 NC-JXD[0] LCI_TXD0 19 2 2
When support S5 WOL cold power state LAN1_XI J14
R65 XTAL2-XTAL2
this pin connect to EC +3VLAN 182573@ 2 3.3K_0402_5% NC-JCLK N14 R525 1 2 0_0402_5% 82562@ LCI_CLK
LCI_CLK 19
R66 1 2@ 100_0402_5% C6 0.1U_0402_16V4Z
to be a wake up even AUX_PWR-NC R542 1
C 2 0_0402_5% EC_RSMRST# 20,25,27 Must connect to RSMRST# C

20,25,28 PCIE_WAKE# P10 P5 R541 1 2@ 0_0402_5%

PE_WAKE#-NC LAN_PWR_GOOD-NC PCI_RST# 18,22,25,33,38 (S5 power)
82573@
NVM_TYPE A6 P7
NVM_TYPE-NC PE_RST#-NC PLT_RST# 7,17,18,19,25,28,38
20 NVM_PORT NVM_PORT A5 NVM_PROT-NC
B4 NVM_REQ-NC
1

Connect to GPIO pin for SPI protect NVM_SHRD D3 N10 TP_ALT_CLK125 T25 PAD~D
R63 NVM_SHARED#-NC ALT_CLK125-NC
Pull high -> NVM protect
@ 10K_0402_5% C3
Pull low -> Non protect DOCK_IND-NC
NC-NC1 M9
1

NC-NC2 N9
2

R500 H1 N7
3.3K_0402_5% TEST0-NC NC-NC3
H2 TEST1-NC NC-NC4 L8
82573@ H3 P14
TEST2-NC NC-NC5
J1 TEST3-NC NC-NC6 J13
2

J2 TEST4-NC NC-NC7 M5
J3 TEST5-NC NC-NC8 D11
K1 TEST6-NC +LAN_AVDD25
Pull down L1 TEST7-NC
when with docking M1 TEST8-NC TEST16-NC A14
(Control PHY strength) M3 TEST9-NC TEST15-NC E3
GST5009 for GIGA LAN

2
N2 P9 LAN_CLKREQ#
TEST10-NC TEST14-NC LAN_CLKREQ# 15
P1 M8 R36 R37
TEST11-NC TEST13-NC
TEST12-NC N3 Connect to colck gen
for PCIE clock request
82573@ 82573@
TST1284B for 10/100 LAN
82573E_FBGA196

0_0402_5% 1

0_0402_5% 1
LAN_MDI0P T1
LAN_MDI0N
Close to IC 82573
LAN_MDI1P 82573L@ 1 24
B LAN_MDI1N LAN_MDI0P TCT1 MCT1 RJ45_MDI0+ B
Non stuff when use 82562GZ 2 TD1+ MX1+ 23
LAN_MDI2P LAN_MDI0N 3 22 RJ45_MDI0-
LAN_MDI2N TD1- MX1-
LAN_MDI3P 4 21
LAN_MDI3N LAN_MDI2P TCT2 MCT2 RJ45_MDI2+
5 TD2+ MX2+ 20
LAN_MDI2N 6 19 RJ45_MDI2-
TD2- MX2-
R535 82573@

R534 82573@

R533 82573@

R532 82573@
49.9_0402_1%

49.9_0402_1%
1

1
49.9_0402_1%

49.9_0402_1%

82573@49.9_0402_1%

82573@49.9_0402_1%

82573@49.9_0402_1%

82573@49.9_0402_1%

7 TCT3 MCT3 18
1

LAN_MDI3P 8 17 RJ45_MDI3+
LAN_MDI3N TD3+ MX3+ RJ45_MDI3-
R531

R529

R528

9 TD3- MX3- 16
R530

10 TCT4 MCT4 15
2

LAN_MDI1P 11 14 RJ45_MDI1+
TD4+ MX4+
2

LAN_MDI1N 12 13 RJ45_MDI1-
TD4- MX4-
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1

C19

C20

C21

C22
0.1U_0402_16V4Z

0.1U_0402_16V4Z

R10 R11
82573@C489

82573@C488

C487

C486

0.5u_GST5009 R13 R12

2 2 2 2

1
82573@

0.1U_0402_16V4Z

0.1U_0402_16V4Z 82573@

0.1U_0402_16V4Z 82573@

0.1U_0402_16V4Z
82573@

82573@

1 1 1 1

When use 82573G/L R535,R534,R533, R532 = 49.9ohm

75_0402_1% 2

75_0402_1% 2

75_0402_1% 2

75_0402_1% 2
Y3

82573@
When use 82562GZ R535,R534,R533, R532 = 54.9ohm 2 2 2 2
LAN1_XO 2 1 LAN1_XI
and C489, C488, non-stuff

82573@
1 25MHZ_20PF_1BG25000CK1A 1
C496 C499
A A
NVM_TYPE NVM_SHRD 22P_0402_50V8J 22P_0402_50V8J RJ45_GND
2 2
*10/100 LAN C19,C22 change to 0.01uF (SE068103K80)
1

82573E@ R64 @ R491

1K_0402_5%
Install to use SPI
1K_0402_5%
Install when sharing
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2005/06/10 Deciphered Date 2006/06/01
Flash (Tekoa only) SPI Flash with the ICH7M Intel 82573E/L and 82562GZ
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Stuff for 82573E Use dedicate SPI flash only AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
No-stuff for 82573L DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomLA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 26 of 48
5 4 3 2 1
 5 4 3 2 1

+3VLAN
+LAN_AVDD25
+LAN_VDD12 +LAN_VDD12 +3VLAN

U41B
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 A1 VSS1-NC NC-VCC3.3-1 E1
C446

C458

C445

C459

C469

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 C2 VSS2-NC NC-VCC3.3-2 L4
R487 R488

C436

C442

C432

C443

C437

C433
D2 VSS3-NC NC-VCC3.3-3 E11
2 2 2 2 2 0_0603_5% 0_0603_5%

C402

C407

C413

C408

C414

C403
G4 VSS4-NC NC-VCC3.3-4 E12
2 2 2 2 2 2 82573@ 82562@
D4 VSS5-NC
2 2 2 2 2 2

2
D5 VSS6-NC VCC1.2-NC1 F12
B3 VSS7-NC VCC1.2-NC2 H12
E4 VSS8-VSS VCC1.2-NC3 G12

10U_0805_6.3V4Z

10U_0805_6.3V4Z

0.1U_0402_16V4Z
D E5 VSS9-VSS VCC1.2-NC4 C5 1 1 1 D
E10 VSS10-VSS VCC1.2-NC5 C4

C439

C440

C444
*For 82562GZ stuff 1Kbits EEPROM at ICH7* F11 VSS11-VSS VCC1.2-NC6 A10
F10 VSS12-VSS 2 2 2
Only dedicate SPI support Flash stuff for 82573E G11 VSS13-VSS
G10 VSS14-VSS VCC1.2-VCC3.3-1 G6
+3VLAN +3VALW +3VLAN

C451 82573E@
H10 VSS15-VSS VCC1.2-VCC3.3-2 H6
+3VLAN +3VLAN F5 H7
J9 VSS16-VSS VCC1.2-VCC3.3-3

0.1U_0402_16V4Z
10K_0402_5%

F4 VSS17-VSS VCC1.2-VCC3.3-4 J6
1

2 1 80 mil J7
2 1 VCC1.2-VCC3.3-5
82573E@
R486

10K_0402_5%
1 VCC1.2-VCC3.3-6 J8

1
+LDO3 JUMP_43X118 C10 K4
VSS-VSS1 VCC1.2-VCC3.3-7

R501
D6 VSS-VSS2 VCC1.2-VCC3.3-8 K5
U39 J1 D7 K7
2 VSS-VSS3 VCC1.2-VCC3.3-9
2

SPI_CE# 1 8 2 1 D8 K8
SPI_MOSO R489 CE# VDD 2 1 VSS-VSS4 VCC1.2-VCC3.3-10
2 SO HOLD# 7 E6 VSS-VSS5 VCC1.2-VCC3.3-11 L5

2
47_0402_5% 3 6 @ JUMP_43X118 E7 H8
82573E@ WP# SCK 47_0402_5% 82573E@ VSS-VSS6 VCC1.2-VCC3.3-12
4 VSS SI 5 E8 VSS-VSS7 VCC1.2-VCC3.3-13 J9
R497 SPI_CLK E9 J10
SST25LF040A_SO8 R496 SPI_MOSI VSS-VSS8 VCC1.2-VCC3.3-14
F6 VSS-VSS9 VCC1.2-VCC3.3-15 J11
82573E@ 47_0402_5% F7 K9
82573E@ VSS-VSS10 VCC1.2-VCC3.3-16
F8 VSS-VSS11 VCC1.2-VCC3.3-17 K10
+3VLAN F9 L9
Size: VSS-VSS12 VCC1.2-VCC3.3-18
G7 VSS-VSS13 VCC1.2-VCC3.3-19 L10
U40 IAMT support: G8 K11
SPI_CE# VSS-VSS14 VCC1.2-VCC3.3-20
26 LAN_SPI_CE# 1 CS VCC 8 At last 4Mbits SPI flash G9 VSS-VSS15 VCC1.2-VCC3.3-21 K6
SPI_CLK 2 7 R516 H9 H11
26 LAN_SPI_CLK SK NC ASF2.0 Support: VSS-VSS16 VCC1.2-VCC3.3-22
SPI_MOSI 3 6 2 1 G14 K3
26 LAN_SPI_MOSI DI NC VSS-VSS17 VCC1.2-VCC3.3-23
SPI_MOSO 4 5 @ 10K_0402_5% 64Kbits EEPROM or SPI flash K2 G13
26 LAN_SPI_MOSO DO GND VSS-VSS18 VCC1.2-VCC3.3-24 +LAN_AVDD25 +3VLAN
C E2 C
AT93C46-10SI-2.7_SO8 No magagement: VSS-VSS19
N1 VSS-VSS20
82573L@ 1Kbits EEPROM VCC3.3-NC1 M10 +3VLAN

1
EEPROM stuff for 82573L VCC3.3-NC2 J4
P8 VSS1-VSS VCC3.3-NC3 F3
C12 D9 R485 R492
VSS2-VSS VCC3.3-NC4 0_0603_5% 0_0603_5%
For 82562GZ LAN disable function D13
N12
VSS3-VSS VCC3.3_REG2.5-NC5 A2
M2 +LAN_AVDD25 82573@ 82562@
VSS4-VSS VCC3.3_REG2.5-NC6

2
+3VLAN
Only 82562GZ mode0 stuff
If use mode1,2 no-stuff and +3VLAN B7 J5
+3VLAN @ 200_0402_5% 200_0402_5% NC1-VSS VCC2.5_PCIE-VCC3.3-1

10K_0402_5%
only connect LAN_DISABLE# M6 NC2-VSS VCC2.5_PCIE-VCC3.3-2 G5

1
82562@ (Default Mode 1) L6 H5
signal to Ball L7 NC3-VSS VCC2.5_PCIE-VCC3.3-3
1

R61
Strapping resistor for 82562GZ K12 NC4-VSS VCC2.5_XTAL-VCC3.3-4 K13
1

R522 R556 R552 R554 L11 H4

+3VLAN R555 @ 200_0402_5% Ehanced Mode configuration NC5-VSS VCC2.5_IO-NC1
VCC2.5_IO-NC2 N7
@ 470_0402_5% Populate according table M4
VCC2.5_IO-NC3

2
200_0402_5% B5 G3
EN2.5REG-NC VCC2.5_IO-NC4
2

2
1

82562@ T10 PAD~D A4 B6

CTRL_2.5-NC VCC2.5_IO-NC5
2

R551 R547 1 2 TESTEN J12

@ 100_0402_5% VCC2.5_PHY-NC6
VCC2.5_PHY-NC7 L12
4.7K_0402_5% R558 1 2 ISOL_TCK N4 A11 +3VLAN
T8 PAD~D JTAG_TMS-NC VCC2.5_PHY-VCC3.3
Q36 @ 100_0402_5% T11 PAD~D N5 JTAG_TCK-NC
2

D R539 1 ISOL_TI
(Connect to GPIO) 2 T9 PAD~D P4 JTAG_TDI-NC
LAN_DISABLE# 2 @ 100_0402_5% T12 PAD~D P6 P2
20 LAN_DISABLE# JTAG_TDO-NC VCC3.3-VCC3.3-1
G R553 1 2 ISOL_EXEC N6
@ 2N7002_SOT23S @ 100_0402_5% 82573@ 4.99K_0402_1% VCC3.3-VCC3.3-2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
VCC3.3-VCC3.3-3 A7 1 1 1
3

R538 1 2 ISOL_TI D12 P12

PHY_REF-ISOL_TI VCC3.3-VCC3.3-4
1

ISOL_TCK C471

C479

C455
D14 NC-ISOL_TCK VCC3.3-VCC3.3-5 N8
B R536 R559 R546 R548 ISOL_EXEC 10U_0805_10V4Z B
D10 NC-ISOL_TXE VCC3.3_REG2.5-VCC3.3 A3
200_0402_5% R521 1 2 2 2
2 TESTEN A13 TEST_EN-TEST_EN
82562@ 82573@ 3.3K_0402_5% P3 LAN_CTRL12
CTRL_1.2-NC
2

@ 200_0402_5% LAN_DISABLE# L7 B2
20 LAN_DISABLE# DEVICE_OFF#-AVD10 2.5V_OUT-NC1
@ 200_0402_5% B1 +LAN_AVDD25
200_0402_5% 2.5V_OUT-NC2
82562GZ mode0 LAN_DISABLE# pin
82562@ is used as ADV10 (auto-negotiation 82573E_FBGA196 Use internal regulator
+3VLAN 82573L@
advertise 10M only) please take care thermal
1.2V power supply
+3VLAN
5

82573@ U42
4.7U_0805_10V4Z LAN_DISABLE# 1 Connect to ICH7 LAN reset pin
P

22U_0805_6.3V6M B
Y 4 LAN_RST# 20
1 1 1 1 20,25,26 EC_RSMRST# 2 A
1

R477 C421 C423 C422 C420 TC7SH08FU_SSOP5

3
1

1_2010_5% 82573@ 82573@ 82562@

R43 82573@
2 2 2 2 82562GZ Hardware configuration table (Default Mode 1)
4.7K_0402_5% 22U_0805_6.3V6M 0.1U_0402_16V4Z
Mode TESTEN ISOL_TCK ISOL_TI ISOL_EXEC Mode TESTEN ISOL_TCK ISOL_TI ISOL_EXEC
32

82573@ 82573@
For 82562GZ LAN_RST# signal must Mode0 0 0 0 0 XOR tree 1 0 0 0
2

LAN_CTRL12 1 not be de-asserted sooner than 10ms

Q34 after the Resume power supply reaches Mode1 0 0 1 1 Mode2 1 0 0 1
1/2W Resistor
BCP69_SOT223 its nominal voltage.
Test Mode 1 0 1 0 Mode3 1 0 1 1
2
4

82573@
Isolate 0 1 1 1 Mode4 1 1 0 0
A 40mil A
0.1U_0402_16V4Z +LAN_VDD12 Power down 1 1 1 1 Reserved 1 1 0 1
1 1 1
1

C50
R476 C429 C428
Testing 1 1 1 0
4.7U_0805_10V4Z
2 1_2010_5% 2 2
82573@ 82573@ 0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
2

1 Issued Date 2006/06/01 Title

C426 2005/06/10 Deciphered Date <Title>
10U_0805_10V4Z 82573@ 82573@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
82573@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2 CustomLA-3011P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 27 of 48
5 4 3 2 1
 A B C D E

+3VALW_HDP

37
38
39
40
41
42
43
44
U50

NC
NC
NC
NC
NC
NC
NC
NC
+3VS +1.5VS +3VALW 5 GSENSOR@
Self_Test VDD VOUTX C619 1 0.033U_0402_16V7K
7 ST VOUTX 8 2
C622 6 VOUTY C620 1 2 0.033U_0402_16V7K
22P_0402_50V8J VOUTY VOUTZ C621 1 0.033U_0402_16V7K
1 NC VOUTZ 15 2
1 1 1 1 1 1 1 1 2 XIN 2 GSENSOR@
C211 C271 C278 C215 C226 C261 C234 @ NC GSENSOR@
3 NC NC 20

1
1 1
9 NC NC 21
0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z Y5 10 22
2 2 2 2 2 2 2 8MHZ_20PF_X8A008000IK1H NC NC
11 NC NC 23
@ 12 24 +3VALW_HDP
NC NC

2
1 2 XOUT 13 25
NC NC
17 NC Reserved 27
@ C623 18 29
22P_0402_50V8J NC NC
19 NC NC 30
NC 31
26 RESERVED NC 32
28 RESERVED NC 33
EC_HDPPD 2 R682 1 HDPPD 14 34
25 EC_HDPPD 1K_0402_5% PD NC
16 FS NC 35
GSENSOR@ 4 36
GND NC
LIS3L02AQ3TR_QFN44
GSENSOR@

Mini-Express Card +1.5VS +3VS

***
JP28
20,25,26 PCIE_WAKE# PCIE_WAKE# 1 2
1 2 U51
24 WLAN_BT_DATA 3 3 4 4
24 WLAN_BT_CLK 5 5 6 6
15 MINI_CLKREQ# MINI_CLKREQ# 7 8 HDP_SMB_CK 1 20 HDP_SMB_DA
7 8 Self_Test P3_5/SCL P3_4/SDA
9 9 10 10 2 P3_7 P3_3 19
CLK_PCIE_MCARD# 11 12 +3VALW_HDP R677 2 1 4.7K_0402_5%HDP_RST# 3 18 VOUTX
15 CLK_PCIE_MCARD# 11 12 RESET# P1_0
CLK_PCIE_MCARD 13 14 R678 2 1 4.7K_0402_5% XOUT 4 17 VOUTY
15 CLK_PCIE_MCARD 13 14 XOUT/P4_7 P1_1
15 16 GSENSOR@ 5 16 +3VALW_HDP
15 16 GSENSOR@ R679 2 XIN VSS/AVSS AVCC/VREF VOUTZ
17 17 18 18 1 4.7K_0402_5% 6 XIN/P4_6 P1_2 15
19 20 XMIT_OFF# GSENSOR@ 7 14 1
2 R305 0_0402_5% 19 20 GSENSOR@ R680 2 VCC P1_3 2
21 21 22 22 PLT_RST# 7,17,18,19,25,26,38 1 4.7K_0402_5% 8 MODE P1_4 13 T39 PAD~D C626
20 PCIE_RXN2 PCIE_RXN2 1 2 PCIE_C_RXN2 23 24 +3VALW HDPINT R681 2 1 1K_0402_5% 9 12 T40 PAD~D 0.1U_0402_16V4Z
PCIE_RXP2 23 24 25 HDPINT P4_5 P1_5
20 PCIE_RXP2 1 2 PCIE_C_RXP2 25 25 26 26 GSENSOR@ HDPPD 10 P1_7 P1_6 11 HDPACT HDPACT 25 GSENSOR@
R300 0_0402_5% 2
27 27 28 28
29 29 30 30 ICH_SMBCLK 15,20,26 1 1
PCIE_TXN2 31 32 R5F21172DSP_LSSOP20
20 PCIE_TXN2 31 32 ICH_SMBDATA 15,20,26
PCIE_TXP2 33 34 C624 C625 GSENSOR@ T41 PAD~D
20 PCIE_TXP2 33 34 R283 2
35 35 36 36 10_0402_5% USB20_N1 20
0.1U_0402_16V4Z
37 38 2 1 GSENSOR@ 2 2 0.1U_0402_16V4Z
37 38 USB20_P1 20
39 40 R278 0_0402_5% GSENSOR@
39 40
41 41 42 42
43 43 44 44
45 45 46 46
47 48 +3VALW_HDP +3VALW +3VALW_HDP
47 48 R683
49 49 50 50
51 51 52 52 2 1

53 54 0_0805_5% GSENSOR@ 1 1 1
GND1 GND2 C177 C176 C170
10U_0805_6.3V6M
FOX_AS0B226-S40N-7F~D 0.01U_0402_16V7K GSENSOR@
GSENSOR@ 2 2 2
+3VALW_HDP +5VALW
0.1U_0402_16V4Z
U52 GSENSOR@
1 OUT IN 8
2 SNS FB 7 1
3 6 C627
SHDN TAP
4 GND ERR# 5
0.1U_0402_16V4Z
LP2951CMX-3.3 2 GSENSOR@ R684
@ PLT_RST# 2 1 HDP_RST#
3 +3VALW 7,17,18,19,25,26,38 PLT_RST# 3
@ 0_0402_5%
C235 1 2 0.1U_0402_16V4Z
TIP
5

U20
WL_OFF# 1
25 WL_OFF#
P

B
Y 4 +3VALW
KILL_SW# 2
24,25 KILL_SW# A
G

TC7SH08FU_SSOP5 D13
3

1 2 XMIT_OFF# R685 R686

RB751V_SOD323 2.2K_0402_5% 2.2K_0402_5%
GSENSOR@ GSENSOR@
Q49
2N7002_SOT23

Kill SWITCH 1 3 HDP_SMB_DA

S
4,25,34 EC_SMB_DA2
GSENSOR@
+3VALW

G
2
+3VALW
3

2
D18

G
DAN217_SC59 +3VALW
1 3 HDP_SMB_CK
4,25,34 EC_SMB_CK2
2

S
R402 Q50
1

100K_0402_5% 2N7002_SOT23
4 GSENSOR@ 4
1

KILL_SW#
KILL_SW# 24,25
3

1
3

Security Classification Compal Secret Data Compal Electronics, Inc.

1BS003-1211L_3P SW4
Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/Mini-PCI/Accelerometer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
KS@
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 28 of 48
A B C D E
 A B C D E F G H

+VDDA
28.7K for Module Design (VDDA = 4.702)

1
R404 +5VALW (output = 250 mA)
10K_0402_5% 60mil U33
R401 4 VIN VOUT 5 40mil +VDDA
C330 1 2 1 2
25 BEEP

2
1U_0603_10V4Z 560_0402_5% 1 1 2 6 R397 1 4.85V
C323 C325 DELAY SENSE or ADJ 30K_0402_1%
1 2
C337 1U_0603_10V4Z 7 1 C324
ERROR CNOISE

1
10U_1206_16V4Z 10U_1206_16V4Z
R415 2 2
0.1U_0402_16V4Z 2
1 8 SD GND 3 1 1

1
10K_0402_5% C332
SI9182DH-AD_MSOP8

1
2

2
C341
17,25,32,35,39,44,45 SUSP#
1 2 MONO_IN R396
0.1U_0402_16V4Z 10K_0402_1%
1U_0603_10V4Z

2
1
C 1 2
C333 1 R403 Q25
22 PCM_SPK 2 1 2 2 R407
1U_0603_10V4Z 560_0402_5% B 2SC2411K_SC59 2.4K_0402_5%
E R359 2 1 @ 6.8K_0402_5%

3
R360 2 1 @ 6.8K_0402_5%

C335 1 R406 R358 2

20 SB_SPKR 2 1 2 31 LINE_IN_L 1 1 2 C294 LINEL
1U_0603_10V4Z 560_0402_5% W D@ 1U_0402_6.3V4Z

1
W D@ 6.8K_0402_5%
D16 R361 2 1 1 2 C295 LINER
31 LINE_IN_R
R353 RB751V_SOD323 W D@ 1U_0402_6.3V4Z
10K_0402_5% W D@ 6.8K_0402_5% 1 1

2
C286 C287
WOD@ 1U_0402_6.3V4Z WOD@1U_0402_6.3V4Z
2 2
HD Audio Codec
+AVDD_AC97
2
20mil 0.1U_0402_16V4Z 2
+3VS
L4 1 2 0.1U_0402_16V4Z 40mil 1 1 1
+VDDA
FBM-L11-160808-800LMT_0603 1 1 1 C328
C305 C329 C322 C303
C331 10U_1206_16V4Z
10U_1206_16V4Z 2 2 2

25

38
2 2 2

9
U48 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z

AVDD1

AVDD2

DVDD1

DVDD2
C327 C617
@ 1000P_0402_50V7K @1000P_0402_50V7K
2 2
14 35 AMP_LEFT
30 AMP_LEFT_HP LINE2_L FRONT-OUT-L AMP_LEFT 30
15 36 AMP_RIGHT
30 AMP_RIGHT_HP LINE2_R FRONT-OUT-R AMP_RIGHT 30
16 MIC2_L
17 MIC2_R SURR_OUT_L 39 HP_OUT_L 31
LINEL 23 41
LINE1_L SURR_OUT_R HP_OUT_R 31
1 2
LINER 24 C326 27P_0402_50V8J
R392 20K_0402_5% LINE1_R
19 INT_CD_L 2 1 BIT_CLK 6 ICH_BITCLK_AUDIO 19
R388 2 1 6.8K_0402_5% CD_L_R 1 2 CD_L_RC 18
R390 6.8K_0402_5% C316 1U_0603_10V4Z CD_L R387
2 1 SDATA_IN 8 1 2 33_0402_5% ICH_AC_SDIN0 19
R394 2 1 20K_0402_5% CD_R_R 1 2 CD_R_RC 20
19 INT_CD_R CD_R
C318 1U_0603_10V4Z 2 PAD T5
R393 2 NC
19 CD_AGND 1 20K_0402_5% CD_AGND_R 1 2 CD_AGND_RC19
CD_GND NC 33
3 C317 1U_0603_10V4Z 3
NC 47
MIC1_L 1 2 MIC1_C_L 21 37
30 MIC1_L MIC1_L NC
1

C604 1U_0603_10V4Z 3
R398 R389 MIC1_R MIC1_C_R NC
30 MIC1_R 1 2 22 MIC1_R NC 29
C603 1U_0603_10V4Z
@ 0_0402_5% 6.8K_0402_5% 13 SENSE A
2

MONO_IN 12 30
PC_BEEP MIC2_VREFO

MIC1_VREFO_L 28 10mil MIC1_VREFO_L

19 ICH_RST_AUDIO# 11 RESET#
27 ACZ_VREF 10mil
VREF
19 ICH_SYNC_AUDIO 10 SYNC 1
C319
5
MIC1_VREFO_R 32 10mil MIC1_VREFO_R
19 ICH_SDOUT_AUDIO SDATA_OUT 10U_0805_10V4Z
2
1 2 45 SIDE-SURR-L LINE2_VREFO 31 R688
R658 0_0603_5% 46 SIDE-SURR-R
SENSE B 34 2 1 sensor_B 30
CEN-OUT 43 2
1 2 44 47_0402_5%
R400 0_0603_5% LFE-OUT C628
48 SPDIFO
JDREF 40 1000P_0402_50V7K
1
4 DVSS1 AVSS1 26

1
1 2 7 DVSS2 AVSS2 42
R366 0_0603_5%
ALC861-GR_LQFP48 R399

5.1K_0402_1%
4 2 4
DGND AGND
GND GNDA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/12 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC260D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
LA-3011P 0.2

Date: Thursday, September 15, 2005 Sheet 29 of 48

A B C D E F G H
 A B C D E

@ PSOT24C_SOT23

1
D3
D1
+5VS
@ PSOT24C_SOT23

2
+5VS R660
W=40mil 100K_0402_5%
1 1

2
1 1
SHUTDOWN#
C288 C292 Q26

1
0.1U_0402_16V4Z 4.7U_0805_10V4Z D 2N7002_SOT23
2 2
G
2 EC_MUTE 25 20mil Speaker Conn.
S JP2

3
SPKL+ R19 1 2 0_0603_5% SPK_L+
SPKL- R24 SPK_L- 1
1 2 0_0603_5% 2
U47 ACES_85204-0200
D36
7 PVDD SHUTDOWN# 22
18 15 NBA_PLUG 2 1 JP33
PVDD SE/BTL# G_BEEP 25
19 14 SPKR+ R31 1 2 0_0603_5% SPK_R+
VDD PC-BEEP BYPASS SPKR- R32 1
BYPASS 11 1N4148_SOD80 SPKL- 1 2 0_0603_5% SPK_R-
2
R362 1 2 100K_0402_5% 2 9
VOL_AMP HP/LINE# LOUT- SPKR- ACES_85204-0200
3 VOLUME ROUT- 16
SPKL+ 4 10
SPKR+ LOUT+ LIN
21 ROUT+ RIN 8
1 2 LEFT_2 5
29 AMP_LEFT LLINEIN
C608 1U_0402_6.3V4Z RIGHT_2 23 1
RLINEIN GND
29 AMP_RIGHT 1 2 6 LHPIN GND 12
C616 1U_0402_6.3V4Z 20 13 2 2 2
C607 2 1U_0402_6.3V4Z RHPIN GND
29 AMP_LEFT_HP 1 GND 24
17 C298 C297
C615 2 1U_0402_6.3V4Z CLK C296 1U_0402_6.3V4Z
29 AMP_RIGHT_HP 1
TPA0232PWP_TSSOP24 1U_0402_6.3V4Z1 1 1
1 1U_0402_6.3V4Z
1
C614
2 C609 2
0.047U_0402_16V7K
2
2 0.1U_0402_16V4Z Headphone JACK 1
JP31
5
10mil NBA_PLUG
+5VS 2 1 4
R405 100K_0402_5%
SPKR+ 1 2 HPOUT1_R_2 1 2 HPOUT1_R_3 1 2 HPOUT1_R_4 3

+
C321 150U_D2_6.3VM R421 0_0603_5% L6 FBM-11-160808-700T_0603 6
+5VS SPKL+ 1 2 HPOUT1_L_2 1 2 HPOUT1_L_3 1 2 HPOUT1_L_4 2

+
C320 150U_D2_6.3VM R420 0_0603_5% L5 FBM-11-160808-700T_0603 1

R687 FOX_JA6033L-5S1-TR
Volumn Control VR
2

1 2 C340 C334
29 sensor_B
R410 330P_0402_50V7K 330P_0402_50V7K
3.9K_0603_1% 39.2K_0603_1%

1
D
1

NBA_PLUG 2 Q51
Reserve for noise. G 2N7002_SOT23
1 S

3
C336
1

@ 0.1U_0402_16V4Z
2 0.01W_10KC_EVUTWZB19C14
VR1 MIC1_VREFO_R
D35 MIC1_VREFO_L
R671
25 G_BEEP 2VOL_AMP
1 2 1 2 5
10mil 10mil

1
1
0_0603_5%
3 1N4148_SOD80 +5VS R414 3
Int MIC Conn. R413 4.7K_0402_5% JP32
3

R408 4.7K_0402_5% 5

2
2

1 2 15mil

2
R411 MIC2 INT_MIC_R 4
100K_0402_5% 3.32K_0603_1% 1
45@ 2 15mil MIC1_R 1 2 L8 MIC1_R_1 3
29 MIC1_R
1

D INT_MIC_L FBM-11-160808-700T_0603 6
1

2 Q28 R409 WM-64PCY_2P MIC1_L 1 2 L7 MIC1_L_1 2

6.19K_0603_1% 29 MIC1_L
G 2N7002_SOT23 FBM-11-160808-700T_0603 1
1

D MIC1
S 1 1
3

NBA_PLUG 2 Q27 1 FOX_JA6033L-5S1-TR

1

G 2N7002_SOT23 45@ 2 C338 C339

S 220P_0402_50V7K 220P_0402_50V7K
2 2
3

WM-64PCY_2P

BTL MODE
GAINmax=10dB
GAINmin=-80dB

SE MODE
GAINmax=-6db
GAINmin=-80db

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/25 Deciphered Date 2006/06/01 Title
AMP & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 30 of 48
A B C D E
 5 4 3 2 1

1 2 R627 1 2 R631 1 2 W D@ 10K_0402_5% R638 1 2 W D@ 4.7K_0402_5%

34 LINEIL#
C256 W D@ 1U_0402_6.3V4Z W D@ 1K_0402_5% 1

C264 W D@ 1000P_0402_50V7K +VDDA

W D@ 1U_0402_6.3V4Z
2 C263 1 2
1

4
C285 W D@ 1000P_0402_50V7K 2

V+
-
O 1 LINE_IN_L 29
R647 1 2 R651 1
34 LINEIL 1 2 2 2 W D@ 10K_0402_5% 3 +
+VDDA

V-
C277 W D@ 1K_0402_5% U26A
D W D@ 1U_0402_6.3V4Z W D@ LMV824MTX_TSSOP14 D

11
+DOCK_AUD_VREF R652 1 W2D@ 4.7K_0402_5% +VDDA

4
+DOCK_AUD_VREF
9

V+
R375 - +DOCK_AUD_VREF
O 8
1 2 10 +

V-
1 2 R628 1 2 W D@ 1K_0402_5%R632 1 2 W D@ 10K_0402_5% R639 1 2 W D@ 4.7K_0402_5% W D@ 100K_0402_5% U26C
34 LINEIR#

2
C255 1 1 C307 LMV824MTX_TSSOP14 1

11
W D@ 1U_0402_6.3V4Z W D@ C306
C262 W D@ 1000P_0402_50V7K +VDDA R374 @ 1U_0402_6.3V4Z
W D@ 100K_0402_5%
2 2 0.1U_0402_16V4Z 2

1
1 W D@

4
C284 W D@ 1000P_0402_50V7K 6

V+
W D@ 1K_0402_5% -
O 7 LINE_IN_R 29
R648 1 2 R654
34 LINEIR 1 2 2 1 2 W D@ 10K_0402_5% 5 +

V-
C276 U26B
W D@ 1U_0402_6.3V4Z W D@ LMV824MTX_TSSOP14

11
+DOCK_AUD_VREF R653 1 2
W D@ 4.7K_0402_5%

+VDDA
R378 1 2 W D@ 22K_0402_5%

4
1 2
C312 W D@ 68P_0402_50V8K +VDDA 13

V+
C
- C
O 14
+VDDA C267 1 2 12 +

V-
R379 U26D

4
W D@ 1U_0402_6.3V4Z 1U_0402_6.3V4Z W D@ LMV824MTX_TSSOP14

11
4
W D@ 22K_0402_5% 2 W D@

V+
-
29 HP_OUT_L 1 2 1 2 9 1 1 2 LINEOL 34
V+

C315 - O C268 1U_0402_6.3V4Z

O 8 3 +

V-
+DOCK_AUD_VREF 10 U28A W D@
+
V-

2
2 U28C W D@ LMV824MTX_TSSOP14

11
11

C304 W D@ LMV824MTX_TSSOP14 R339

0.1U_0402_16V4Z 4.7K_0402_5% +VDDA
1 @ W D@

1
R342 2 1 4.7K_0402_5%

4
W D@ 13

V+
+VDDA -
O 14
12 +

V-
U28D

4
W D@ LMV824MTX_TSSOP14

11
6

V+
-
O 7 1 2 LINEOL# 34
+DOCK_AUD_VREF 5 C253 1U_0402_6.3V4Z
+

V-
2 U28B W D@
W D@ LMV824MTX_TSSOP14

11
C258
0.1U_0402_16V4Z
W D@ 1 +VDDA
B B

4
W D@
22K_0402_5%
13

V+
R376 1 -
2 O 14
W D@ 68P_0402_50V8K 12 +

V-
1 2 U27D
C311 +VDDA W D@ LMV824MTX_TSSOP14

11
+VDDA 1 2
C265 1U_0402_6.3V4Z
4

R377 W D@
4

W D@ 1U_0402_6.3V4Z W D@ 22K_0402_5% 2
V+

-
29 HP_OUT_R 1 2 1 2 9 1 1 2 LINEOR 34
V+

C314 - O C266 1U_0402_6.3V4Z

O 8 3 +
V-

+DOCK_AUD_VREF 10 U27A W D@
+
V-

2 U27C W D@ LMV824MTX_TSSOP14
11
11

C302 W D@ LMV824MTX_TSSOP14 R340

0.1U_0402_16V4Z W D@ 4.7K_0402_5%
1 @ W D@ 4.7K_0402_5%
1

R341 2 1

+VDDA
4

6
V+

-
A O 7 1 2 LINEOR# 34 A
+DOCK_AUD_VREF 5 C252 1U_0402_6.3V4Z
+
V-

2 U27B W D@
11

C257 W D@ LMV824MTX_TSSOP14
0.1U_0402_16V4Z
@ 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/04/25 Deciphered Date 2006/06/01 Title
Docking Audio
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROPRIETARY NOTE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 31 of 48
5 4 3 2 1
 A B C D E

RTCVREF RTCVREF RTCVREF RTCVREF

1
D33 C534 0.1U_0402_16V4Z
R590 R585 R584 1 2 ON/OFFBTN#
ON/OFFBTN# 36,37
100K_0402_5% 100K_0402_5% 680K_0402_5% 1N4148_SOT23 2

3
2

5
C195 D7

1
D
1 1

P
Q19 1
1 2 2 A Y 4 1 2 2
C533 1U_0805_16V7K R597 G 2N7002_SOT23

G
10K_0402_5% S 0.1U_0402_16V4Z

1
U44

3
1
D NC7SZ14M5X_SOT23-5
2 Q39
37 S4_LID_SW#
G 2N7002_SOT23 PSOT24C_SOT23
S

1
D

25,36,39,44 SYSON 2
G
Q40 S

3
2N7002_SOT23

RTCVREF 1 2 1 2
R240 C197 1U_0805_16V7K
10K_0402_5%
RTCVREF
U12 C196 0.1U_0402_16V4Z
1 CD1# VCC 14 1 2
2 D1 CD2# 13
25 S4_LATCH 3 CP1 D2 12
RTCVREF 1 2 4 SD1# CP2 11

2
R185 1 5 10
R204 10K_0402_5% C188 Q1 SD2#
6 Q1# Q2 09
10K_0402_5% 7 GND Q2# 08
@ 1U_0805_16V7K
2 2 74LCX74MTC_TSSOP14 2
1
+3VALW 1 2
R246 D9

1
10K_0402_5% D
2 1 D_SET_S4 2 Q18
25 S4_DATA
G 2N7002_SOT23
S
RB751V_SOD323

3
Docking Parallel Port Close to Docking +3VS

+5V_PRN
C49 1 2 @ 220P_0402_50V7K LPTSLCTIN# Clo se to Docking 2
C4
D4 C48 1 2 @ 220P_0402_50V7K LPTINIT# RP3 WD@ 0.1U_0402_16V4Z
3 LPTSLCT 1 3
+5VS 2 1 +5V_PRN 1 8 LPTSLCT 33,34
C47 1 2 @ 220P_0402_50V7K LPTERR# 2 7 LPTPE

26
LPTPE 33,34
217@ RB420D_SOT23 3 6 LPTBUSY U1
LPTBUSY 33,34
1

C46 1 2 @ 220P_0402_50V7K AFD#/3M# 4 5 LPTACK# 2 28

LPTACK# 33,34

VCC
R52 217@ C1+
V+ 27 2 1
2.2K_0402_5% C409 1 2 @ 220P_0402_50V7K LPTACK# 217@ 2.7K_1206_8P4R_5% C5 C2 WD@ 0.1U_0402_16V4Z
RP4 WD@ 0.1U_0402_16V4Z 24
LPTBUSY 1 C1-
C410 1 2 @ 220P_0402_50V7K 1 8 AFD#/3M# 2 1 C2+ V- 3 2 1
2

C51 2 7 LPTERR# LPTERR# 33,34

C3 WD@ 0.1U_0402_16V4Z
1 2 C411 1 2 @ 220P_0402_50V7K LPTPE 3 6 LPTINIT# C1
4 5 LPTSLCTIN# WD@ 0.1U_0402_16V4Z 2 C2-
217@ 220P_0402_50V7K C412 1 1
2 @ 220P_0402_50V7K LPTSLCT
33,38 DTR#1 14 TIN1 TOUT1 9 DTR# DTR# 34
217@ 2.7K_1206_8P4R_5% 13 10 RTS# RTS# 34
33,38 RTS#1 TIN2 TOUT2
217@ C13 1 2 @ 220P_0402_50V7K F D0 RP1 12 11 TXD TXD 34
33,38 TXD1 TIN3 TOUT3
LPTSTB# R53 1 2 33_0402_5% R_LPTSTB# 1 8 F D0 19 4 CTS#
33 LPTSTB# R_LPTSTB# 34 33,38 CTS#1 ROUT1 RIN1 CTS# 34
217@ C14 1 2 @ 220P_0402_50V7K F D1 2 7 F D1 18 5 R I#
33,38 RI#1 ROUT2 RIN2 RI# 34
LPTAFD# R475 1 2 33_0402_5% AFD#/3M# 3 6 F D2 17 6 RXD
33 LPTAFD# AFD#/3M# 34 33,38 RXD1 ROUT3 RIN3 RXD 34
217@ C15 1 2 @ 220P_0402_50V7K F D2 4 5 F D3 16 7 D CD#
33,38 DCD#1 ROUT4 RIN4 DCD# 34
INIT# R474 1 2 33_0402_5% LPTINIT# 15 8 DSR#
33 INIT# LPTINIT# 34 33,38 DSR#1 ROUT5 RIN5 DSR# 34
217@ C16 1 2 @ 220P_0402_50V7K F D3 217@ 2.7K_1206_8P4R_5% 20
SLCTIN# R473 1 33_0402_5% LPTSLCTIN# RP2 ROUTB2
33 SLCTIN# 2 LPTSLCTIN# 34 INVLD# 21
C390 1 2 @ 220P_0402_50V7K F D4 1 8 F D7 23
17,25,29,35,39,44,45 SUSP# FORCEON
C393 2 7 F D6 25
C391 1 F D5 F D5 GND
2 @ 220P_0402_50V7K 3 6 22 FORCEOFF#
217@ 68_1206_8P4R_5% 4 5 F D4
LPD0 4 5 F D0 C392 1 2 @ 220P_0402_50V7K F D6 WD@ MAX3243CAI_SSOP28
33 LPD0 FD0 34
LPD1 3 6 F D1 217@ 2.7K_1206_8P4R_5%
33 LPD1 FD1 34
LPD2 2 7 F D2 1 2 @ 220P_0402_50V7K F D7
33 LPD2 FD2 34
LPD3 1 8 F D3
4 33 LPD3 FD3 34 4
RP30

RP31
LPD7 F D7
33
33
LPD7
LPD6
LPD6
4
3
5
6 F D6
FD7
FD6
34
34
Security Classification Compal Secret Data Compal Electronics, Inc.
33 LPD5
LPD5 2 7 F D5
FD5 34 Issued Date 2005/04/25 Deciphered Date 2006/06/01 Title
LPD4 F D4
33 LPD4 1 8 FD4 34 COM/PARALLEL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
217@ 68_1206_8P4R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 32 of 48
A B C D E
 A B C D E

+3VS

SUPER I/O SMsC LPC47N217 1 1

LPC_AD[0..3]
19,25,38 LPC_AD[0..3]
C245 C300
4.7U_0805_10V4Z 0.1U_0402_16V4Z
+3VS 2 2

1 R372 1 2 10K_0402_5% SIO_PD# 217@ 217@ U30 1

LPC_AD0 10 62 RXD1
LAD0 RXD1 RXD1 32,38
R354 1 2 10K_0402_5% SIO_SMI# LPC_AD1 12 63 TXD1
LAD1 TXD1 TXD1 32,38

SERIAL I/F
LPC_AD2 13 64 DSR#1
LAD2 DSR1# DSR#1 32,38
R364 2 1 100K_0402_5% FIR_DET# LPC_AD3 14 1 RTS#1
LAD3 RTS1# RTS#1 32,38
2 CTS#1
CTS1# CTS#1 32,38
LPC_FRAME# 15 3 DTR#1
19,25,38 LPC_FRAME# LFRAME# DTR1# DTR#1 32,38
LPC_DRQ#0 16 4 RI#1
19 LPC_DRQ#0 LDRQ# RI1# RI#1 32,38
5 DCD#1
DCD#1 32,38

LPC I/F
SIO_RST# DCD1#
18,22,25,26,38 PCI_RST# 17 PCI_RESET#
SIO_PD# 18 37 IRRX
38 SIO_PD# LPCPD# IRRX 38
FIR IRRX2
IRTX2 38 IRTXOUT
IRTXOUT 38
PM_CLKRUN# 19 39 IRMODE
20,38 PM_CLKRUN# CLKRUN# IRMODE/IRRX3 IRMODE 38
CLK_PCI_SIO 20
15,38 CLK_PCI_SIO PCI_CLK
SERIRQ 21 41 INIT#
20,22,25,38 SIRQ SER_IRQ INIT# INIT# 32
SIO_IRQ R350 2 1@ 10K_0402_5% PME# 6 42 SLCTIN#
25,38 PME# IO_PME# SLCTIN# SLCTIN# 32
44 LPD0
PD0 LPD0 32
IRRX R347 1 2 10K_0402_5% CLK_14M_SIO 9 46 LPD1
15,38 CLK_14M_SIO CLK14 PD1 LPD1 32
CLOCK 47 LPD2
PD2 LPD2 32
23 48 LPD3
GPIO40 PD3 LPD3 32
24 49 LPD4

PARALLEL I/F
Agilent IRRX unpop 10K 25
GPIO41 PD4
50 LPD5
LPD4 32
GPIO42 PD5 LPD5 32
Vishay IRRX pop 10K 27 51 LPD6
GPIO43 PD6 LPD6 32
FIR_DET# 28 53 LPD7
38 FIR_DET# GPIO44 PD7 LPD7 32

GPIO
29 55 LPTSLCT
GPIO45 SLCT LPTSLCT 32,34
30 56 LPTPE
GPIO46 PE LPTPE 32,34
31 57 LPTBUSY
GPIO47 BUSY LPTBUSY 32,34
32 58 LPTACK#
GPIO10 ACK# LPTACK# 32,34
SIO_GPIO11 33 59 LPTERR#
GPIO11/SYSOPT ERROR# LPTERR# 32,34
2 SIO_SMI# 34 60 LPTAFD# 2
GPIO12/IO_SMI# ALF# LPTAFD# 32
CLK_14M_SIO SIO_IRQ 35 61 LPTSTB#
GPIO13/IRQIN1 STROBE# LPTSTB# 32
36 GPIO14/IRQIN2
2

+3VS 40
R349 CLK_PCI_SIO GPIO23
@ 10K_0402_5% 8 7 +3VS
VSS VTR
2

22 VSS VCC 11 1

2
43 VSS POWER VCC 26
1

1 R373 R356 52 45 C273

C280 @ 10_0402_5% @ 10K_0402_5% VSS VCC 217@ 0.1U_0402_16V4Z
VCC 54 +3VS
@ 15P_0402_50V8J 2
1

1 Base I/O L-Address LPC47N217-JV_STQFP64

2

1
217@
C309 0 *= 02Eh
@ 15P_0402_50V8J SIO_GPIO11 1 = 04Eh
2
2

R357
217@
1K_0402_5%
Serial Port
for Debug
1

+5VS Port 80 Debug Card Connector **

JP5 JP8

FIR Module L: R POP; FIR Enable

H: R De-POPFIR Disable
RXD1
1
2
3
1
2
18,22
18,22
PCI_CBE#0
PCI_AD6
R572
R573
2
2
2
1
1
1
33_0402_5%
33_0402_5%
20
19
18
20
19
3 3 18,22 PCI_AD4 18 3
TXD1 4 R574 2 1 33_0402_5% 17
4 18,22 PCI_AD2 17
DSR#1 5 R575 2 1 33_0402_5% 16
5 18,22 PCI_AD0 16
RTS#1 6 R576 2 1 33_0402_5% 15
CTS#1 6 18,22 PCI_AD1 R577 33_0402_5% 15
7 7 18,22 PCI_AD3 2 1 14 14
FIR_DET# R363 1 2 1K_0402_5% DTR#1 8 R578 2 1 33_0402_5% 13
FIR@ RI#1 8 18,22 PCI_AD5 R563 33_0402_5% 13
9 9 18,22 PCI_AD7 2 1 12 12
DCD#1 10 R564 2 1 33_0402_5% 11
10 18,22 PCI_AD8 R565 33_0402_5% 11
18,22 PCI_CBE#1 2 1 10 10
@ E&T_96212-1011S R566 2 1 33_0402_5% 9
18,22 PCI_CBE#2 R567 33_0402_5% 9
18,22 PCI_CBE#3 2 1 8 8
R568 33_0402_5% 7
+3VS +IR_ANODE CLK_PCI_USB20_C 7
15 CLK_PCI_USB20 2 1 6 6
R569 33_0402_5%

+3VS
(60mil) R417 @ 4.7_1206_5% CIR +5VS
18,22,25,26,38 PCI_RST# 2
R100 2
1
5
4
5
4
1 2 18,22 PCI_FRAME# 1 33_0402_5% 3 3
1 R99 2 1 33_0402_5% 2
18,22 PCI_TRDY# 2
1 2 (60mil) R98 2 1 33_0402_5% 1
C342 R418 4.7_1206_5% U49 C344 18,22 PCI_AD9 R97 33_0402_5% 1
1
2

1 22U_1206_16V4Z_V1 FIR@ 1 ACES_85201-2005

2 GND CIR@ 4.7U_0805_10V4Z CLK_PCI_USB20_C
C343 R424 IR1 2
GND 2

1
@ 10U_0805_10V4Z 0_1206_5% 1 R423 100_0805_5%
2 FIR@ IRED_A IRTXOUT
2 IRED_C TXD 3 VCC 3 1 2 +5VALW
1

IRRX 4 5 IRMODE R570

+IR_3VS RXD SD/MODE @10_0402_5%
6 VCC MODE 7 ROUT 4 1 2 CIR_IN 25
(30mil) 8 GND

2
1 1 (30mil, 3via) TSOP6238-TR_4P R422 0_0402_5% 1
FIR@ TFDU6102-TR3_8P CIR@
C347 C618 CIR@ C500
4 4
FIR@ 10U_1206_16V4Z FIR@ 0.1U_0402_16V4Z @ 18P_0402_50V8K
2 2 2
SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/04/25 Deciphered Date 2006/06/01 Title
LPC-Super I/O 1000
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 33 of 48
A B C D E
 A B C D E

+3VALW +3VALW +3VALW

W D@ 0.1U_0402_16V4Z

1
C377 2 1 R459
W D@ 10K_0402_5% 100K_0402_5%

5
U38
R456 2 1 DCOCT1# 2

P
I0

2
DOCKIN#
Docking Conn. R453 1 2 DCOCT2# 1 I1
O 4 DOCKIN# 16,25,42

G
JP17A W D@ 10K_0402_5% W D@ TC7SH32FU_SSOP5 JP17B

3
1 245 GND GND 247 249 GND GND 251 1
246 GND GND 248 250 GND GND 252

+DC_IN_S1 241 VCC VCC 242 +DC_IN_S1 243 VCC VCC 244

DKN_B+ 1 S1 S61 61 DKN_B+ DKN_B+ 121 S121 S181 181 DKN_B+

2 S2 S62 62 122 S122 S182 182
DCOCT1# 3 63 EJCTSW# D_EC_SMB_CK2 123 183 D_EC_SMB_DA2
S3 S63 EJCTSW# 25 S123 S183
+5VS 4 S4 S64 64 +5VS +5VS 124 S124 S184 184 +5VS
PS_CLK 5 65 PS_DATA +5VALW 125 185
25 PS_CLK S5 S65 PS_DATA 25 S125 S185
KB_CLK 6 66 KB_DATA TPA1+ 126 186 TPA1-
25 KB_CLK S6 S66 KB_DATA 25 22 XTPA1+ S126 S186 XTPA1- 22
7 S7 S67 67 127 S127 S187 187
1394_PHYRST_S3P 8 68 TPB1+ 128 188 TPB1-
25 1394_PHYRST_S3P S8 S68 22 XTPB1+ S128 S188 XTPB1- 22
DPCONF_S5P 9 69 1394_DILSON_S3P 129 189 USB20_P6
25 DPCONF_S5P S9 S69 1394_DILSON_S3P 25 S129 S189 USB20_P6 20
10 70 130 190 USB20_N6
S10 S70 S130 S190 USB20_N6 20
11 S11 S71 71 131 S131 S191 191
D_DDC_CLK 12 72 D_DDC_DATA 132 192
16 D_DDC_CLK S12 S72 D_DDC_DATA 16 S132 S192
D_CRT_R 13 73 133 193
16 D_CRT_R S13 S73 S133 S193
D_CRT_G 14 74 Pin 73, 74 and 75 for VGA GND AUD_SUDMUT_P3# 134 194 LINEOR
16 D_CRT_G S14 S74 25 AUD_SUDMUT_P3# S134 S194 LINEOR 31
D_CRT_B 15 75 135 195 LINEOR#
16 D_CRT_B S15 S75 S135 S195 LINEOR# 31
D_CRT_VSYNC 16 76 D_CRT_HSYNC LINEOL 136 196 LINEOL#
16 D_CRT_VSYNC S16 S76 D_CRT_HSYNC 16 31 LINEOL S136 S196 LINEOL# 31
DVI_SCLK 17 77 DVI_SDATA LINEIL 137 197 LINEIL#
17 DVI_SCLK S17 S77 DVI_SDATA 17 31 LINEIL S137 S197 LINEIL# 31
18 78 LINEIR# 138 198 LINEIR
S18 S78 31 LINEIR# S138 S198 LINEIR 31
19 S19 S79 79 139 S139 S199 199
20 80 DOCK_ON/OFFBTN# 140 200 RXD
S20 S80 37 DOCK_ON/OFFBTN# S140 S200 RXD 32
21 81 DC D# 141 201 RTS#
S21 S81 32 DCD# S141 S201 RTS# 32
DVI_TXD2+ 22 82 DSR# 142 202 CTS#
17 DVI_TXD2+ S22 S82 32 DSR# S142 S202 CTS# 32
DVI_TXD2- 23 83 TXD 143 203 DTR#
17 DVI_TXD2- S23 S83 32 TXD S143 S203 DTR# 32
2 DVI_TXD1+ 24 84 R I# 144 204 LPTSLCT 2
17 DVI_TXD1+ S24 S84 32 RI# S144 S204 LPTSLCT 32,33
DVI_TXD1- 25 85 LPTPE 145 205 LPTBUSY
17 DVI_TXD1- S25 S85 32,33 LPTPE S145 S205 LPTBUSY 32,33
DVI_TXD0+ 26 86 F D7 146 206 LPTACK#
17 DVI_TXD0+ S26 S86 32 FD7 S146 S206 LPTACK# 32,33
DVI_TXD0- 27 87 F D6 147 207 F D5
17 DVI_TXD0- S27 S87 32 FD6 S147 S207 FD5 32
28 S28 S88 88 148 S148 S208 208
29 S29 S89 89 149 S149 S209 209
DVI_TXC+ 30 90 F D4 150 210 F D3
17 DVI_TXC+ S30 S90 32 FD4 S150 S210 FD3 32
DVI_TXC- 31 91 F D1 151 211 LPTSLCTIN#
17 DVI_TXC- S31 S91 32 FD1 S151 S211 LPTSLCTIN# 32
DVI_DET# 32 92 F D2 152 212 LPTINIT#
17 DVI_DET# S32 S92 32 FD2 S152 S212 LPTINIT# 32
33 93 F D0 153 213 LPTERR#
S33 S93 32 FD0 S153 S213 LPTERR# 32,33
34 94 R_LPTSTB# 154 214 AFD#/3M#
S34 S94 32 R_LPTSTB# S154 S214 AFD#/3M# 32
35 S35 S95 95 155 S155 S215 215
36 S36 S96 96 156 S156 S216 216
37 S37 S97 97 157 S157 S217 217
38 S38 S98 98 158 S158 S218 218
39 S39 S99 99 159 S159 S219 219
40 S40 S100 100 160 S160 S220 220
41 S41 S101 101 161 S161 S221 221
42 S42 S102 102 162 S162 S222 222
43 S43 S103 103 163 S163 S223 223
44 S44 S104 104 164 S164 S224 224
45 S45 S105 105 165 S165 S225 225
46 S46 S106 106 166 S166 S226 226
47 S47 S107 107 167 S167 S227 227
48 S48 S108 108 168 S168 S228 228
49 S49 S109 109 169 S169 S229 229
50 S50 S110 110 170 S170 S230 230
51 S51 S111 111 171 S171 S231 231
52 S52 S112 112 172 S172 S232 232
3 3
173 S173 S233 233
234 LAN_ACTIVITY#
S234 LAN_ACTIVITY# 26
RJ45_MDI3+ 55 115 RJ45_MDI2- +3VALW 175 235 LAN_LINK#
26 RJ45_MDI3+ S55 S115 RJ45_MDI2- 26 S175 S235 LAN_LINK# 26
RJ45_MDI3- 56 236 DCOCT2#
26 RJ45_MDI3- S56 S236
117 RJ45_MDI2+
S117 RJ45_MDI2+ 26
RJ45_GND 178 LAN
26 RJ45_GND L178
MDC1_RING 59 RJ45_MDI0+ 179 239 RJ45_MDI1+
M59 26 RJ45_MDI0+ L179 L239 RJ45_MDI1+ 26
MDC2_TIP 60 MODEM RJ45_MDI0- 180 240 RJ45_MDI1-
M60 26 RJ45_MDI0- L180 L240 RJ45_MDI1- 26
+5VALW +3VALW
2

253 GND GND 254

R23
W D@ 100K_0402_5%
2

W D@ TYCO_1674036 W D@ TYCO_1674036
G
1

1 3 Q6 1394_DILSON_S3P
W D@ 2N7002_SOT23
D

W D@ 4.7K_0402_5%
1 2 +5VALW
2

R17
G

3 1 D_EC_SMB_CK2
4,25,28 EC_SMB_CK2
4.7K_0402_5%
S

Q3
W D@ 2N7002_SOT23 1 2 +5VALW
2

R20 W D@
G

MDC to Docking Conn. 3 1 D_EC_SMB_DA2

4 4,25,28 EC_SMB_DA2 4
S

JP1 Q5
W D@ 2N7002_SOT23
1
MDC1_RING 2
MDC2_TIP 3
4 Security Classification Compal Secret Data Compal Electronics, Inc.
W D@ ACES_87213-0410 2005/06/01 2006/06/01 Title
Issued Date Deciphered Date
Docking
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 34 of 48
A B C D E
 +LDO3_EC +LDO3_EC
C242

1
1 2 R312
100K_0402_5%
SUSP# 17,25,29,32,39,44,45
0.1U_0402_16V4Z

2
INT_FLASH_SEL 1 2

G
SB_INT_FLASH_SEL# 20

5
U22

2
2 1 3 R675 0_0402_5%
EC_FLASH# 20

P
FWE# I0
4 @

S
O
I1 1

G
Q20
TC7SH32FU_SSOP5 2N7002_SOT23

3
FWR# 25

+3VALW
@
C240 1 2 0.1U_0402_16V4Z

2
R314
10K_0402_5% INT_FLASH_EN# R313 1 2
@
@ 100K_0402_5%

4
U19B
+5VALW +5VALW R322 @

OE#
INT_FSEL# 1 2 22_0402_5% 6 5
O I FSEL# 25

1
R335
C244 1 2 0.1U_0402_16V4Z @ SN74LVC125APWLE_TSSOP14
100K_0402_5%
2

1 2
U24 R321 0_0402_5%
8 VCC A0 1
7 2 +3VALW
WP A1
25,41 EC_SMB_CK1 6 SCL A2 3
25,41 EC_SMB_DA1 5 SDA GND 4
AT24C16AN-10SI-2.7_SO8

14
1
U19A

10

13
U19C U19D

P
OE#
3 2

OE#

OE#
O I
9 I O 8 12 I O 11

G
1

@ SN74LVC125APWLE_TSSOP14

7
R326
@ SN74LVC125APWLE_TSSOP14 @ SN74LVC125APWLE_TSSOP14
100K_0402_5%
2

KBA[0..19]
25 KBA[0..19]
ADB[0..7]
25 ADB[0..7]

1MB ROM Socket

1MB Flash ROM JP30
+LDO3_EC KBA16 KBA17
KBA15 1 2
U23
KBA14 3 4
KBA0 KBA13 5 6 KBA19
21 A0 VCC0 31 7 8
KBA1 20 30 1 KBA12 KBA10
KBA2 A1 VCC1 C259 KBA11 9 10 ADB7
19 A2 11 12
KBA3 18 KBA9 ADB6
KBA4 A3 ADB0 0.1U_0402_16V4Z KBA8 13 14 ADB5
17 A4 D0 25 15 16
KBA5 ADB1 2 FWE# ADB4
16 A5 D1 26 17 18
KBA6 15 27 ADB2 RESET# +3VALW
KBA7 A6 D2 ADB3 INT_FLASH_EN# 19 20
14 A7 D3 28 21 22
KBA8 8 32 ADB4 INT_FLASH_SEL
KBA9 A8 D4 ADB5 KBA18 23 24 ADB3
7 A9 D5 33 25 26
KBA10 36 34 ADB6 KBA7 ADB2
KBA11 A10 D6 ADB7 KBA6 27 28 ADB1
6 A11 D7 35 29 30
KBA12 5 KBA5 ADB0
KBA13 A12 KBA4 31 32 FR D#
4 A13 33 34
KBA14 3 10 RESET# 1 2 +LDO3_EC KBA3
KBA15 A14 RP# R344 100K_0402_5% KBA2 35 36 FSEL#
2 A15 NC 11 37 38
KBA16 1 12 KBA1 KBA0
KBA17 A16 READY/BUSY# 39 40
40 A17 NC0 29
KBA18 13 38 @ SUYIN_80065AR-040G2T
KBA19 A18 NC1
37 A19
INT_FSEL# 22
FR D# CE#
25 FRD# 24 OE# GND0 23
FWE# 9 39
WE# GND1

SST39VF080-70_TSOP40 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title
BIOS & EXT. I/O PORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 35 of 48
 5 In 1 Card LED
1 2

D11
R244 100K_0402_5%
+3VALW
(Close to Socket)
2 IE_BTN# 25
INBTN# 1 +3VS
3 51ON#
51ON# 37,40
DAN202U_SC70

1
R665
150_0603_5%
10C/10GC:Green:SC591UYG000

2
10/10C:Blue:SC5191NB000
Green

2
D23
Vivace(SW-DJ) Button HT-191NB_BLUE_0603
LEDB@

1 2 +LDO3_EC

1
R270 100K_0402_5%
D12

1
D
PWR BTN/B Mode_Key 1
2

3 51ON#
MODE# 25
22 5IN1_LED 2
G
Q52
2N7002_SOT23
S

3
JP4 DAN202U_SC70
25,37 KSI2 1
25,37 KSI3 2 +5VALW
25,37 KSI4 3
25,37 KSI5 4 +5VALW
25,37 KSO3 5
INBTN#
PWR_LED0#
PWR_SUSPLED0#
6
7
Battery LED
Mode_Key 8
9 AC-IN LED

2
+3VALW
10
32,37 ON/OFFBTN# 11
12 D19 LEDB@
ACES_85201-1205 SY SON HT-191NB_BLUE_0603
47K Green Amber

2
Q45

1
2
2N7002_SOT23
Green R662 R663

G
300_0603_1% 300_0603_1%

1
Q48 10K 2 1 3 PWR_SUSP_LED#
PWR_SUSP_LED# 25
R664

1
300_0603_1%
R6611 2
@ 0_0402_5% Low Active

3
DTA114YKA_SC59
1

D21
Change from 300 to 120 HT-297UD/NB_BLUE/AMB_0603

1
R667 1 D
2 120_0402_5% PWR_SUSPLED0# LEDB@
20,25,40,43 ACIN 2
G Q46

4
R668 1 2 120_0402_5% PWR_SUSPLED1#
HDD LED S

3
2N7002_SOT23

25 BATT_CHGI_LED# BATT_LOW_LED# 25
+5VS
1

R666
10/10C:Blue/Amber:SC597UDB000
Green 300_0603_1%
10C/10GC:Green/Amber:SC500001900
2
2

+5VALW

D22
Power LED
HT-191NB_BLUE_0603
47K SYSON 25,32,39,44
3

LEDB@ Q7
2

DTA114YKA_SC59 Q8
G
1

2N7002_SOT23
10K 2 1 3 PWR_LED#
25 HDD_LED# PWR_LED# 25 Wireless Lan LED
D

R54 1 2
@ 0_0402_5% Low Active
+5VS
1

Change from 120 to 300

1
R465 1 2 300_0402_5% PWR_LED0#
R669

R466 1 2 300_0402_5% PWR_LED1# 150_0402_5%

2
2
Amber D34
Amber:SC5110UD000
HT-110UD_1204

1
1
D
Amber WL_LED 2
25 WL_LED
G
D20 Q47 S

3
2N7002_SOT23
PWR_SUSPLED1# 3 4

PWR_LED1# 2 1

HT-297UD/NB_BLUE/AMB_0603
LEDB@

Green

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title
MDC/BT/KBD/ON_OFF/LID
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3011P
Date: Thursday, September 15, 2005 Sheet 36 of 48
 INT_KBD CONN.
KSO[0..17]
25,36 KSO[0..17]
KSI[0..7]
25,36 KSI[0..7]

MDC 1.5 Conn. JP10

1 NUM_LED# 25
2 PADS_LED# 25
+3VS 3 CAPS_LED# 25
JP27 1 2 +3VS
4 KSO15 300_0402_5% R135
5 KSO14
1 GND1 RES0 2 6
19 ACZ_SDOUT_MDC ACZ_SDOUT_MDC 3 4 KSO10
IAC_SDATA_OUT RES1 7 KSO11
5 GND2 3.3V 6 8
19 ACZ_SYNC_MDC ACZ_SYNC_MDC 7 8 KSO8
R324 1 ACZ_SDIN1_MDC IAC_SYNC GND3 9 KSO9
19 ACZ_SDIN1 2 9 IAC_SDATA_IN GND4 10 10
19 ACZ_RST#_MDC 33_0402_5% ACZ_RST#_MDC 11 12 ACZ_BITCLK_MDC ACZ_BITCLK_MDC 19 KSO13
IAC_RESET# IAC_BITCLK 11 KSI7
12 KSO3
13 KSO7

GND
GND
GND
GND
GND
GND
14 KSO12
+3VS 15 KSI4
ACES_88018-124G 16 KSI6
17

13
14
15
16
17
18
KSI5
18 KSO6
19 KSO5
1 1 1 Connector for MDC Rev1.5 20
C229 C236 C241 KSI3
21 KSI0
1000P_0402_50V7K @ 4.7U_0805_10V4Z 22 KSO0
2 2 2 23 KSO1
0.1U_0402_16V4Z 24 KSI1
25 KSI2
26 KSO2
27 KSO4
28
29 1 2 +3VS
300_0402_5% R582
30
31
32
33
34 1 2 +3VS
300_0402_5% R583
ACES_88170-3400

100P_1206_8P4C_50V8
KSO8
Reserved power button KSO9
1 8
2 7
KSO13 3 6
SW1 KSI7 4 5

1 3 Power Button CP2

100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
2 4
Lid Switch +LDO3_EC
3

KSI6 1 8 KSI1 1 8
SMT1-05_4P KSI5 2 7 KSI2 2 7
6
5

KSO6 3 6 KSO2 3 6
RTCVREF

2
+3VALW KSO5 4 5 KSO4 4 5
D5 R416
R412 100K_0402_5% CP4 CP6
1

1 2 1 2
100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
2

PSOT24C_SOT23 R419 47K_0402_5%

1
R177 0_0402_5% KSO15 1 8 KSO3 1 8
U34 KSO14 2 7 KSO7 2 7
100K_0402_5% A3212EEH_MLP6 D24 KSO10 3 6 KSO12 3 6
2 LID_SW# KSO11 4 5 KSI4 4 5
LID_SW# 25
1

D6 5 1 L ID 1
VDD OUTPUT CP1 CP3
2 ON/OFF 25 3 S4_LID_SW# 32
ON/OFFBTN# 1
32,36 ON/OFFBTN# 100P_1206_8P4C_50V8
3 51ON# 1 4 2 1 DAN202U_SC70
RTCVREF 51ON# 36,40 NC NC
C345 C346 KSI3 1 8

GND
DAN202U_SC70 KSI0 2 7
KSO0 3 6
2 2 KSO1 4 5

3
1

2 C190 D8 0.1U_0402_16V4Z 10P_0402_25V8K

2

CP5
R163 R156

100K_0402_5% 100K_0402_5% 1 RLZ20A_LL34

TP CONN.
2

WD@ WD@ 1000P_0402_50V7K

1

2 1
G

Q15
1

D
34 DOCK_ON/OFFBTN# 3 1
Q14 2
S

G EC_ON 25,43 JP9

2

2N7002_SOT23 S
+5VS 6
3

WD@ R195
2N7002_SOT23 SW_R 5
1 2
10K_0402_5%
TP Button 25 TP_DATA
SW_L
TP_DATA
4
3
2
1

R170 @ 0_0402_5% SW3 SW2 25 TP_CLK TP_CLK

1
SW_L 1 3 SW_R 1 3 ACES_85201-0605

2 4 2 4

SMT1-05_4P SMT1-05_4P
6
5

6
5
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC/KBD/ON_OFF/LID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2005 Sheet 37 of 48
 5 4 3 2 1

+3VS

SUPER I/O SMsC LPC47N207 Finger printer 1

C507

0.1U_0402_16V4Z
LPC Debug Port LPC_AD[0..3]
2 JP6
19,25,33 LPC_AD[0..3] +3VS 1
0_0402_5%
D +5VALW +3VALW R562 2 D
20 USB20_N0 2 1 3
R561 2 1
20 USB20_P0 4
0_0402_5%
JP35 5

2
1 1 ACES_85201-0505
1
2 2 1 1
3 C260 D31
3 C269 C301 SI207@ 0.1U_0402_16V4Z @ PACDN042_SOT23~D
4 4
SI207@ 0.1U_0402_16V4Z SI207@ 4.7U_0805_10V4Z 2
5 5
CLK_14M_SIO 2 2
6 6

1
7 LPC_AD0
7 LPC_AD1
8 8 +3VS
9 LPC_AD2

17
31
42
60

48
9

5
10 LPC_AD3 U29 RP26
10 LPC_FRAME# DCD#1
11 1 8

3.3V
3.3V
3.3V
3.3V
3.3V

VTR
11 LPC_DRQ#1 RI#1
12 12 2 7
13 PCI_RST# LPC_AD0 64 CTS#1 3 6
13 LPC_AD1 LAD0 DSR#1
14 14 2 LAD1 GPIO10 27 4 5
15 CLK_PCI_SIO LPC_AD2 4 28
15 SERIRQ LPC_AD3 LAD2 GPIO11 SIO_SMI# 4.7K_8P4R_1206_5%
16 16 7 LAD3 GPIO12/IO_SMI# 30 SIO_SMI#
17 32 SIO_IRQ
17 GPIO13/IRQIN1 SIO_IRQ
18 18 GPIO14/IRQIN2 33
19 10 34 RXD1 1 2
19 LPC_CLK_33 GPIO15 R332 SI207@ 1K_0402_5%
20 20 12 LDRQ1# GPIO16 35
LPC_DRQ#1 24 36
19 LPC_DRQ#1 LDRQ0# GPIO17
ACES_85201-2005 LPC_FRAME# 14 38

GPIO
19,25,33 LPC_FRAME# LFRAME# GPIO30
PM_CLKRUN# 16 39

LPC I/F
20,33 PM_CLKRUN# CLKRUN# GPIO31
@ SERIRQ 19 40
20,22,25,33 SIRQ SERIRQ GPIO32
CLK_PCI_SIO 21 41
15,33 CLK_PCI_SIO PCI_CLK GPIO33
PCI_RST# 22 43 FIR_DET#
18,22,25,26,33 PCI_RST# PCIRST# GPIO34 FIR_DET# 33
CLK_14M_SIO 23 44
15,33 CLK_14M_SIO SIO_14M GPIO35
SIO_PD# 25 46
C 33 SIO_PD# LPCPD# GPIO36
PME# 47 61 DTR#1 1 2 C
25,33 PME# IO_PME# GPIO37 R330 SI207@ 10K_0402_5%

63 52 RXD1
DLAD0 RXD1 RXD1 32,33
1 53 TXD1

SERIAL I/F
DLAD1 TXD1 TXD1 32,33
3 54 DSR#1 +3VS
DLAD2 DRSR1# DSR#1 32,33
6 55 RTS#1
+3VALW +3VS DLAD3 RTS1#/SYSOPT0 RTS#1 32,33
56 CTS#1

DLPC I/F
CTS1# CTS#1 32,33
DTR#1
TPM1.2 on board DTR1#/SYSOPT1 57 DTR#1 32,33

2
0.1U_0402_16V4Z 9 58 RI#1
DLPC_CLK_33 RI1# RI#1 32,33
1 2 2 2 11 59 DCD#1 R331
DLDRQ1# DCD1# DCD#1 32,33
C584 C585 C601 C598 13 @ 10K_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z DLFRAME# IRTXOUT
15 DCLKRUN# IRTX2 49 IRTXOUT 33
TPM@ TPM@ TPM@ 18 50 IRRX Base I/O Address
2 1 1 1 TPM@ DSER_IRQ IRRX2 IRRX 33

1
26 51 IRMODE

IR
DSIO_14M IRMODE/IRRX3 IRMODE 33
0.1U_0402_16V4Z 0 *= 02Eh
10
19
24

U46
5

RTS#1 1 = 04Eh

GND0
GND1
GND2
GND3
GND4
GND5
VSB

VDD
VDD
VDD

2
26 LPC_AD0 LPC_AD0 19,25,33
LAD0 LPC_AD1 R327
LAD1 23 LPC_AD1 19,25,33
20 LPC_AD2 LPC_AD2 19,25,33 LPC47N207-JN_STQFP64 SI207@ 1K_0402_5%
LAD2

8
20
29
37
45
62
+3VS T35 PAD 6 17 LPC_AD3 SI207@
GPIO LAD3 LPC_AD3 19,25,33
2 22 LPC_FRAME#
GPIO2 LFRAME# LPC_FRAME# 19,25,33

1
T32 PAD 16 PLT_RST#
LRESET# PLT_RST# 7,17,18,19,25,26,28
1

28 SUS_STAT#
LPCPD# SUS_STAT# 20
R642 27 SIRQ
SERIRQ SIRQ 20,22,25,33
21 CLK_PCI_TCG
LCLK CLK_PCI_TCG 15
4.7K_0402_5%
TPM@ S L B 9 6 3 5 T T 1.2
2

B PM_CLKRUN# B
8 TEST1 CLKRUN# 15 PM_CLKRUN# 20,33
9 TESTB1/BADD R633
1

PP 7 2 1 +3VS
R644 R637
@ 4.7K_0402_5% 0_0402_5% 3 TPM@ 4.7K_0402_5%
TPM@ NC TPM_XTALO
12 NC XTALO 14
1 NC
2

13 TPM_XTALI
XTALI/32K IN
GND
GND
GND
GND

Base I/O Address TPM@ SLB 9635 TT 1.2_TSSOP28 +3VS +3VALW

4
11
18
25

0 = 02Eh
* 1 = 04Eh 0.1U_0402_16V4Z
1 1 1
C299 C272 C581

2 2 2
0.1U_0402_16V4Z

TPM@ C612 0.1U_0402_16V4Z

TPM_XTALI 1 2 18P_0402_50V8J
1

32.768KHZ_12.5P_1TJS125BJ2A251
R657 1
10M_0402_5% IN NC 2
TPM@ 4 3
OUT NC TPM@
2

A Y4 A
TPM_XTALO 1 2

C610 18P_0402_50V8J
TPM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TCG/BIOS ROM/PS2/LED/SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 38 of 48
5 4 3 2 1
 A B C D E

H1 H2 H3 H4 H5 H6
+5VALW H_C295D124 H_C295D124 H_C295D124 H_C295D124 H_C197D157 H_C197D157 H29 H31
H_C126D126N H_s315D138

1
R635 FM1 FM3 FM2 FM4 FM6 FM5

1
1 1 1 1 1 1
47K_0402_5%

2
1 SYSON# H7 H8 H9 H10 H11 H12 1
SYSON#
H_S394D159 H_C236D159 H_S394D165 H_C315D138 H_S394D118 H_S394D118 H32 H33 H34

1
D CF1 CF2 CF11 CF12 CF10 CF9 CF6 CF4 CF5 H_R83x30D67x14 H_R83x30D67x14 H_R63x43D47x28
2 Q43
25,32,36,44 SYSON
G 2N7002_SOT23

1
S

1
CF8 CF3 CF7
+5VALW H13 H14 H15 H16 H17 H18
H_S394D118 H_S394D118 H_S394D118 H_C315D138 H_C315D138 H_S394D118 H35 H36 H37
H_R28x67D28x67NH_R63x43D47x28 H_R83x30D67x14

1
1
R636

1
10K_0402_5%
2

SUSP
45 SUSP
H19 H20 H21 H22 H38 H39
1

D H_C315D138 H_O205X126D205X126N H_O205X126D205X126N H_O205X126D205X126N H_R63x43D47x28 H_R63x43D47x28

2 Q44
17,25,29,32,35,44,45 SUSP#
G 2N7002_SOT23
S
3

1
H23 H24 H25 H26 H27 H28
H_C256D79 H_C197D161 H_C177D126 H_C315D118 H_C315D118 H_C315D118

1
2 2

+5VALW to +5VS Transfer

+3VALW to +3VS Transfer
+3VALW
+5VALW +5VS +3VS
U25 0.1U_0402_16V4Z
U15 0.1U_0402_16V4Z 8 1
D S
8 D S 1 1 7 D S 2

1
C216 1 7 2 C249 6 3 1 1
B+ 10U_0805_10V4Z D S 10U_0805_10V4Z D S C246 C250 R323
6 D S 3 1 1 5 D G 4
1

5 D G 4
C208 C205 R613 2 SI4800DY_SO8 10U_0805_10V4Z 470_0402_5%
2 2 2
1

SI4800DY_SO8 10U_0805_10V4Z
2 2

2
R612 470_0402_5%
220K_0402_5%
2

1
D
RUNON Q22 2 SUSP
2

1 R611 2 RUNON 2N7002_SOT23 G

1

D
S

3
0_0402_5% 1 Q42 2 SUSP
1

D C557 G
SUSP 2 Q41 0.033U_0402_16V7K S
3

G 2N7002_SOT23 2N7002_SOT23
S 2
3

3 3

+1.8V to +1.8VS Transfer

+1.8V
+2.5VS +1.8V +1.5VS +VCCP +1.8VS
U5 0.1U_0402_16V4Z
8 D S 1
1

1 7 D S 2

1
R4 R94 R237 R203 C10 6 3 1 1
10U_0805_10V4Z D S C8 C9 R5
5 D G 4
470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5%
2 SI4800DY_SO8 10U_0805_10V4Z 470_0402_5%
2 2
1 2

1 2

1 2

1 2

2
D D D D
Q2 2 SUSP Q11 2 SYSON# Q17 2 SUSP Q16 2 SUSP

1
G G G G D
S S S S RUNON Q1 2 SUSP
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 G

S

+0.9VS 3
4 4
1

R91

470_0805_5%
1 2

D
Q9 2 SUSP Security Classification Compal Secret Data Compal Electronics, Inc.
G
Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title
S
DC/DC Circuits
3

2N7002_SOT23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 39 of 48
A B C D E
 A B C D

VS

+DC_IN_S1 VIN VIN

1 2
PL1 PF1 PR1 1M_0402_1%

1
DC_IN_S2 1 2 DC_IN_S1 1 2

1
PJP1 VS PR2
1 FBMA-L18-453215-900LMA90T_1812 12A_65V_451012MRL PR3
+ 5.6K_0402_5%
2 61.9K_0402_1% 1 2
+ ACIN 20,25,36,43

2
1

1
PR4

8
3 PC1 PU1A 1K_0402_5%
- PC2
1 1 2 3

P
1
+

2
4 PC3 PC4 PR5 15.4K_0402_1% 1 PACIN
- O PACIN 42
2 -

G
SINGA_2DW-0005-B03

1
@ PR6 LM393DG_SO8 PD3

4
PC5 PC6 PR7
100P_0402_50V8J 20K_0402_1% 0.1U_0402_16V7K 10K_0402_5%

2
RLZ4.3B_LL34

2
1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K

2
PR10
2 1 RTCVREF
VIN 1000P_0402_50V7K
10K_0402_5%
3.3V
Vin Detector

2
PD1
PD2
2 1 PR167 @ 68_1206_5%
BATT
RLS4148_LLDS2
1 2 RLS4148_LLDS2
High 14.57 14.01 13.46

1
Low 14.06 13.51 12.98
1 2

1
68_1206_5%

68_1206_5%
1
PR168 @ 68_1206_5%

PR9
PR8
1538VCC
PQ1 VS

2
2
PR11
2 1 2 3 1 2

200_0603_5%
1

PR12

1
PC7
PR13
100K_0402_5% PC8
2

0.22U_1206_25V7M 0.1U_0603_25V7K 1 2
2

2
TP0610K_SOT23
1 2 1K_1206_5%
36,37 51ON#
PR14 22K_0402_5% PD4
2 1 1 PR15 2
VIN B+
1K_1206_5%
RTCVREF RLS4148_LLDS2
1 PR16 2

1K_1206_5%
PU2
PR17 PR18 3.3V

1
+CHGRTC 1 2 1 2 3 OUT IN 2
PR19
1

560_0603_5% 560_0603_5% 237K_0402_1%

GND
1

PC9
PC10 1U_0805_25V4Z
1
2

2
10U_0805_10V4Z
PR20 PR21
2

1 2 1 2
VL
3 10K_0402_5% 2.2M_0402_5% 3

1
S-812C33AUA-C2NT2G_SOT89-3 PU1B

1
8
PD5 PC11
2 5 PR22 1000P_0402_50V7K

P
+

2
@ PJ1 @ PJ2 41,43 MAINPWON 1 7 O

2
+3VALWP 2 2 1 1 +3VALW +1.5VSP 2 2 1 1 +1.5VS 3 - 6 1 PR23 2 VL 499K_0402_1%

G
42 ACON

1
JUMP_43X118 JUMP_43X118 RB715F_SOT323 34K_0402_1%

4
1
(5A,200mils ,Via NO.= 10) (3.5A,140mils ,Via NO.= 7) PR25

1
PC12 LM393DG_SO8 PC13 237K_0402_1%
@ PJ3 PR24

2
+5VALWP 2 2 1 1 +5VALW

2
@ PJ4 0.1U_0402_16V7K 66.5K_0402_1%
JUMP_43X118 +0.9VSP 2 2 1 +0.9VS
1 PR26

1
D
(5A,200mils ,Via NO.= 10)
JUMP_43X118 1000P_0402_50V7K PQ2 2 1 2 PACIN
(2A,80mils ,Via NO.= 4) G
S

1
PJ5 47K_0402_5%
2 1
+1.8VP 2 1 +1.8V
@ PJ6 Precharge detector
JUMP_43X118 +2.5VSP 2 2 1 +2.5VS 2N7002-7-F_SOT23-3
PJ7 1 PQ3
@ 2
2 2 1 1
JUMP_43X118 14.3V/13.18V for adapter +5VALWP
@ (2A,80mils ,Via NO.= 4)
JUMP_43X118 DTC115EUA_SC70
(8A,320mils ,Via NO.= 16)

3
4 4

@ PJ8
+VCCPP 2 2 1 1 +VCCP
JUMP_43X118
(3.5A,140mils ,Via NO.= 7)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/23 Deciphered Date 2006/06/23 Title
DCIN & DETECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 40 of 48
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 84 degree C
Recovery at 45 degree C

1 1

VMB_A VL VS VL

100K_0603_1%_TH11-4H104FT
PJP2 12A_65V_451012MRL FBMA-L18-453215-900LMA90T_1812
1 BATT_S1 1 2 1 2
1 BATT

2
1K_0402_5% PF2 PR29 PL2 PR27

1
2 ALI/NIMH# 1 PR28 2 1 2
2 +3VALWP
3 AB/I PH1 PC14 47K_0402_1%
3 MAINPWON 40,43

1
4 TS_A 47K_0402_5% 0.1U_0603_25V7K
4

1
5 EC_SMDA PC15 PC16 PR30
5

1
EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7Z

1K_0402_5%
6 6 1 2

2
7 47K_0402_1% PQ4
7

8
PR32 PU3A DTC115EUA_SC70

PR31
1 2 3 + PD6

P
2

@ SUYIN_250005MR007G163ZR 13.7K_0402_1%
100_0402_5%

O 1 2 1 2

2
2
TM_REF1
PR33

100_0402_5%
2 -

G
PR34

LM393DG_SO8 1SS355_SOD323
ALI/MH# 25

4
1

3
1

PR35

0.22U_0805_16V7K
2 1 +3VALWP

1
6.49K_0402_1% PR36 PR37

PC17
22K_0402_1% 2 1 VL

2
1

1
PR38 PC18 100K_0402_1%

2
1K_0402_5%

1
2 2
2

PR39
BATT_TEMPA 25
100K_0402_1%
EC_SMB_DA1 25,35

2
EC_SMB_CK1 25,35
1000P_0402_50V7K

PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
Recovery at 45 degree C

VL VL

100K_0603_1%_TH11-4H104FT

2
3 PH2 PR40 3

47K_0402_1%

PR41

1
1 2
47K_0402_1%
PR42

8
10.7K_0402_1% PU3B
1 2 5 PD7

P
+
O 7 2 1
TM_REF1 6 -

G
1SS355_SOD323

1
PC19 PR43 LM393DG_SO8

4
0.22U_0805_16V7K 22K_0402_1%

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/23 Deciphered Date 2006/06/23 Title
BATTERY CONN /OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 41 of 48
A B C D
 A B C D

Iadp=0~4.7A
P2 P3 B+
PQ5
PQ6 PQ7 AO4407_SO8
AO4407_SO8 AO4407_SO8 PR44 @ PJ9 1 8
VIN 8 1 1 8 2 1 2 2 1 1 B++ 2 7
7 2 2 7 3 6

1
6 3 3 6 0.015_2512_1% JUMP_43X118 PC20 PC21 PC22 5
5 5
4.7U_1206_25V6K 4.7U_1206_25V6K 4.7U_1206_25V6K

4
4

4
1 1

200K_0402_1%
1
PR45
1

3
PR46 PQ8
47K_0402_5% PR47

0.1U_0603_25V7K

2
47K

1
PC23
1 2 VIN
2 PU4
47K

2
1 24 47K_0402_5%
25 ADP_I -INC2 +INC2
2

3
2
1
PR48
PQ9 1K_0402_5%
2 1 2 23 AO4407_SO8
OUTC2 GND
1

PR49 100K_0402_5% PC24 N18 4 ACOFF#

1

1
0.022U_0402_16V7K
3 22 CS 1 2
+INE2 CS

1
DTA144EUA_SC70
PC25

0.1U_0402_16V7K

25.5K_0402_1%
2

PR50 1
4 -INE2 VCC(o) 21 1 2
1

12.7K_0402_1%

5
6
7
8
PC27 PR52 0.1U_0603_25V7K
PR53

PC26
100K_0402_1%

2 ACOFF 25
1

D PQ10

PR51
1 2 1 2 5 FB2 OUT 20
3

2
2 PQ12 10K_0402_5% PQ11

2
G DTC115EUA_SC70 4700P_0402_25V7K
2

2
S 6 19 1 2 DTC115EUA_SC70
VREF VH
3

3
PC28 LXCHRG

0.1U_0402_16V7K
1
2N7002-7-F_SOT23-3 PC30 PR54 0.1U_0603_25V7K PC31

PC29
PD8 1 2 1 2 7 18 1 2
ACOFF#1 1K_0402_5% FB1 VCC
2
CC=0.5~3.0A

2
1

2
D 2N7002-7-F_SOT23-3 1000P_0402_50V7K 0.1U_0603_25V7K 2

1SS355_SOD323
PR57
2
G
8 -INE1 RT 17 1
PR55
2
CV=12.6V(6 CELLS LI-ION)
PACIN 1 2 S 162K_0402_1% 68K_0402_5%
40 PACIN
3

PQ13 1 2 9 16
25 IREF +INE1 -INE3
3K_0402_1% PL3 PR58
PR56 PR60 PC32 1 2 1 2 BATT
40 ACON 1 2 1 10 OUTC1 FB3 15 1 2 1 2
PR59 10K_0402_5% 47K_0402_5% 16UH_LF919AS-160M=P3_3.7A_20% 0.02_2512_1%

0.1U_0402_16V7K
1

4.7U_1206_25V6K

4.7U_1206_25V6K
PC33
ACON 1500P_0402_50V7K

4.7U_1206_25V6K
43K_0402_5%

IREF=1.07*Icharge 11 OUTD CTL 14

1

1
PR61 PD9 PD10

PC35
PR175

+3VALWP
2

PC34

PC36
IREF=0.6V~3.21V
2

12 13 EC31QS04 EC31QS04
-INC1 +INC1

2
100K_0402_1%
1 2

2
2

MB3887PFV-ERE1_SSOP24
PR174
47K_0402_5%
1

2
PQ39
1

PR62 PR63
2 1
4.2V 2 1
DTC115EUA_SC70
PR176
3

150K_0603_0.1% 300K_0603_0.1%
16,25,34 DOCKIN# 1 2 2

3 47K_0402_5% 3

PD13 PQ40 DKN_B+

PQ16 B+
Adapter Iadp PR50 PR51
3

2 1 AO4407_SO8
25 DOCKING_CTRL DTC115EUA_SC70 8 1
1SS355_SOD323 7 2
6 3
+3VALWP 75W 4.7A 25.5K_0402_1% 10K_0402_1% 5
CS

4
1

PR66
UNPOP PR175,PR174,PR176,PQ39,PQ40,PD13
1

VMB_A 27K_0402_1%
PR64 PQ14 B+ 1 2
47K_0402_5%

2
Iadp PR50 PR51
2

2 1 2 PR67
PR65
90W
1

340K_0402_1% PC37 10K_0402_1%

1U_1206_25V7K
W/O DOCKING 5.52A 20K_0402_1% 10K_0402_1%

1
DTC115EUA_SC70
3

1 2

VS

1
FSTCHG 2
PR68
499K_0402_1% UNPOP PR175,PR174,PR176,PQ39,PQ40,PD13
PQ15
25 DKN_B+_ON 2
3

DTC115EUA_SC70
8

PU5A PQ17
OVP voltage : LI
+ 3
P

1 3S3P : 13.5V--> BATT_OVP= 1.5V DTC115EUA_SC70

25 BATT_AOVP
4 4
0

3
- 2
G

LM358ADR_SO8
(BAT_OVP=0.1111 *VMB)
4

PC38
1
8

PU5B PR69 0.01U_0402_25V7Z

Security Classification Compal Secret Data Compal Electronics, Inc.
2

5 PR70
P

+
7 0 Issued Date 2005/06/23 Deciphered Date 2006/06/23 Title
6 2.2K_0402_5% CHARGER
-
2
G

105K_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2

LM358ADR_SO8 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 42 of 48
A B C D
 5 4 3 2 1

+3.3VALWP/+5VALWP

D D
B+++
PJP3

3
B+ 1 1 2 2 B+++
PD11
DAP202U_SOT323
JUMP_43X118
4.7U_1206_25V6K

4.7U_1206_25V6K

2200P_0402_50V7K
@
VL
1

1
PC40

PC41

5
6
7
8
PQ18
PC39

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
B+++

D
D
D
D
+LDO5
2

8
7
6
5

PC42

PC43
2
PQ19

47_0402_5%
PR170

D
D
D
D

2
1

G
S
S
S
PC44

10_1206_5%

PR71
1 2

1
0.1U_0402_16V7K SI4800BDY-T1-E3_SO8

10_1206_5%

4
3
2
1
G

1
S
S
S
SI4800BDY-T1-E3_SO8 @ 0_0805_5% PR74

PR73

1
0_0805_5%

PR72
1
2
3
4
PR75
0_0603_5%

0.1U_0603_25V7K
2

5
6
7
8
1 2 VL

2
2VREF_8734

4.7U_1206_25V6K

D
D
D
D
4.7U_0805_6.3V6K

1U_0603_10V6K

43.2K_0402_1%
118K_0402_1%
8
7
6
5

2
PQ20

1 PC48

G
S
S
S
PQ21

PC45

PR76

PR77
D
D
D
D

2
SI4810BDY-T1-E3_SO8

PC46
SI4810BDY-T1-E3_SO8

4
3
2
1
1
DH_5V

PC47
C C

1
G
S
S
S

2
1
2
3
4
1

PC49

18

20

13

17

2
PL4 0.1U_0603_25V7K PR78 0_0603_5% PU6 LX_3V

499K_0402_1%

499K_0402_1%

2
4.7U_LF919AS-4R7M-P3_5.2A_20% 1 BST_5V14 BST5 PR81

4.7U_LF919AS-4R7M-P3_5.2A_20%
PR79
2 1 2

V+
LD05

TON

VCC
ILIM3 0_0603_5%

PR80
ILIM3 5
16
+5VALWP DH5

1
2

1
LX_5V 15 LX5

1
DL_5V 19 11 ILIM5 PC50 PL5
DL5 ILIM5 PR82
21 0.1U_0603_25V7K
FB5 OUT5 BST_3V
9 FB5 BST3 28 2 1 2 1
VS 1 26 DH_3V
N.C. DH3

2
0_0603_5% DL_3V
10.5K_0402_1%

DL3 24
6 27 LX_3V
SHDN# LX3
2

4 ON5 OUT3 22
1
PR83

3 ON3
PD12 7 FB3
FB3
1 RLZ5.1B_LL34
20,25,36,40 ACIN
1 2 12 SKIP# PGOOD 2 +3VALWP
PC51
1

PR84 PR85

PRO#

6.81K_0402_1%
+

LDO3
8

GND
REF
2

2
1 2 10K_0402_5%
2VREF_8734

PR86
100K_0402_5%

POK
150U_V_6.3VM_R18 2
1

47K_0402_5% 1

23

25

10
MAX8734AEEI+_QSOP28
2

PR172 PC52 PR88 PC53

0.22U_0603_16V7K
6.81K_0402_1%

+
2

1
1
@ 1U_1206_25V7K 0_0402_5% 150U_V_6.3VM_R18
PR87

PC54
1 2
VL 2
2

2
B B

2
1

PR89
10K_0402_1%
806K_0603_1%
1

LDO3P 1 2 +LDO3

1
PR91

1
PR90

4.7U_0805_6.3V6K
1 PR171

PC55
2
0_0805_5%
LDO3P
2

2
PR92 @ 0_0805_5%
0_0402_5%
2 1
40,41 MAINPWON
2

PR93
100K_0402_5%
1

PC56
@RHU002N06_SOT323

1
1

@ 0.047U_0603_16V7K D
2
2

PQ22

G
S
3

RHU002N06_SOT323

@ RHU002N06_SOT323
1

D D
2 AC IN 2
EC_ON 25,37
PQ23

PQ24

G G
S S
3

A A
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/23 Deciphered Date 2006/06/23 Title
+5V/+3V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 43 of 48
5 4 3 2 1
 A B C D

PL6
1 2 B+

4.7U_1206_25V6K

1
FBMA-L18-453215-900LMA90T_1812

4.7U_1206_25V6K
1

1
PR94

PC57

PC58

1
0_1206_5% PC59 PC60

2
1
+5VALW 1

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_0805_6.3V6K
1

2
PD14

1
PR95 PC63

PC61
2
PC62 2.2_0603_5% 2.2U_0805_10V6K

2
DAP202U_SOT323 0.1U_0603_25V7K

1
PQ25

3
8
7
6
5
+1.8VP BST_1.2V-1

D
D
D
D

BST_1.8V-1
SI4800BDY-T1-E3_SO8

14

28
+1.8VP

G
S
S
S
PC64 PU7 PC65

5
6
7
8
1.8U_D104C-919AS-1R8N_9.5A_30% 2 1 12 17 2 1

VIN

VCC
SOFT1 SOFT2

1
2
3
4
DH_1.8V-2 PQ26

D
D
D
D
1 2 LX_1.8V 0.01U_0402_25V7Z 0.01U_0402_25V7Z
PC66 PR96 PR97 PC67
1 PL7 2 1 1 2BST_1.8V-2 6 23 BST_1.5V-2
1 2 2 1
BOOT1 BOOT2
+1.5VSP

8
7
6
5

G
S
S
S
0.1U_0402_16V7K
+ PC68 0_0603_5% 0_0603_5% 0.1U_0402_16V7K SI4800BDY-T1-E3_SO8

D
D
D
D

4
3
2
1
PQ27 1 PR98 DH_1.8V-1 DH_1.5V-1 1 PR99 DH_1.5V +1.5VSP
0.01U_0402_25V7Z

2 5 UGATE1 UGATE2 24 2
2
10K_0402_1%

4.7U_LF919AS-4R7M-P3_5.2A_20%
1

G
S
S
S
0_0603_5% 4 25 0_0603_5% LX_1.5V 1 2
PHASE1 PHASE2 PL8
PR100

PC69

1
2
3
4
SI4810BDY-T1-E3_SO8
2

5
6
7
8
2
PR102 PR103 2

PR101 1 2 ISE_1.8V 7 22 ISE_1.5V 1 2 0.01U_0402_25V

D
D
D
D
ISEN1 ISEN2
2

1
220U_D2_4VM_R15 0_0402_5% 2K_0402_1% 2K_0402_1% PQ28 PC71

6.81K_0402_1%
1
DL_1.8V 2 27 SI4810DY-T1-E3_SO8 PR104
LGATE1 LGATE2

1
PC70

PR105
+
1

G
S
S
S
0_0402_5% 220U_D2_4VM_R15
2

4
3
2
1

2
3 PGND1 PGND2 26
DL_1.5V

9 VOUT1 VOUT2 20
VSE_1.8V 10 19 VSE_1.5V
VSEN1 VSEN2
1 2 8 EN1 EN2 21 1 2
25,32,36,39 SYSON 15 16 SUSP# 17,25,29,32,35,39,45
PG1 PG2/REF
1

1
PR106 PR107 10K_0402_1%

GND

DDR

2
PR108 47K_0402_1% 11 18 PC72
OCSET1 OCSET2

1
PC73
2

2
2

1
10K_0402_1% ISL6227CAZ-T_SSOP28 @ 0.1U_0402_16V7K PR109 PR110

13
1
PR111 @ 0.1U_0402_16V7K 10K_0402_1%
2

@ 0_0402_5% PR113 PR112 @ 0_0402_5%

1
100K_0402_1%

2
100K_0402_1%
1

2
2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/23 Deciphered Date 2006/06/23 Title
+1.8V/+1.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 44 of 48
A B C D
 5 4 3 2 1

PL9

B+ 1 2

FBMA-L18-453215-900LMA90T_1812

D 6269_VCC D

1
PR177

10U_1206_25V6M
10K_0402_5% PHASE_VCCPP

10U_1206_25V6M

2
1
UG_VCCPP

PC76
PR114

PC77
2
1 2 1 2

2
46 PGD_IN
0_0603_5% PC78 0.1U_0603_25V7K
+5VS

1
BOOT_VCCPP
PR169
@4.7_0603_5%

5
6
7
8
17

16

15

14

13
PU8 PQ29

D
D
D
D
2
1 PR1152 6269_VCC

PHASE
GND

PGOOD

UG

BOOT
4.7_0603_5%

G
S
S
S
1 VIN PVCC 12 1 2 PC79
SI4800BDY-T1-E3_SO8

4
3
2
1
6269_VCC 2.2U_0603_6.3V6K

2 11 LG_VCCPP
VCC LG +1.05V

1
PR178 1.8UH_SIL104R-1R8PF_9.5A_30%
PC80 1 2 +VCCPP
@ 0_0402_5%
1 3 FCCM PGND 10 PL10 1

5
6
7
8
2.2U_0603_6.3V6K PR116

2
1 2 PQ30 + PC81
PR173

D
D
D
D
2

C PR117 220U_D2_4VM_R15 C
SI4810BDY-T1-E3_SO8
1 2 0_0402_5% 4 9 1ISEN_VCCPP
2
17,25,29,32,35,39,44 SUSP# EN ISEN 2

COMP

G
S
S
S
11.5K_0402_1%

FSET
0_0402_5%
1

VO
FB

4
3
2
1
PC83
2

8
ISL6269CRZ-T_QFN16

0.1U_0402_16V7K

1
22P_0402_50V8J
1
PR118 PC84

PR119
49.9K_0402_1% 0.01U_0402_25V7Z
PC85

2
2

2
1
57.6K_0402_1%
PC86
6800P_0402_25V7K
2 PR120
1 2

2.26K_0402_1%

1
PR121
3K_0402_1% +1.8V

B +3VALW B
2

1
PJ10

1
+5VALW @ JUMP_43X118
1

2
PJ11
1

JUMP_43X79

2
@
1

PC87 PU9
2

1 VIN VCNTL 6 +3VALWP

2

1U_0603_6.3V6M
2

2 GND NC 5

1
6

1
PU10 PC88 3 7 PC89
PC90 10U_1206_6.3V7K VREF NC 1U_0603_6.3V6M
5
VCNTL

VIN

2
7 22U_1206_6.3V6M PR122 4 8
POK VOUT NC
2

4 1K_0402_1%
PR123 VOUT
TP 9

2
VOUT 3 +2.5VSP
12K_0402_1% 1 APL5331KAC-TRL_SO8
1

1 2 8 2 PR125
5,29,32,35,39,44 SUSP# EN FB
1

PR124 PC92
22U_1206_6.3V6M

+
+0.9VSP
GND

1
PC93 @ 150U_D_6.3VM 0_0402_5% D PQ31
PC91

VIN 9
2
1

1
2.15K_0402_1% 1 2 2
2
2

39 SUSP

1
PC94 G PR126 PC95
1

1U_0603_10V6K S PC96
2

2
1

APL5912-KAC-TRL_SO8 10U_1206_6.3V7K

2
1

0.01U_0402_25V7Z PC97
PR127 @0.1U_0402_16V7K
2

1K_0402_1%
2N7002-7-F_SOT23-3 1K_0402_1% 0.1U_0402_16V7K
A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/23 Deciphered Date 2006/06/23 Title
+VCCPP/+2.5VSP/0.9VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 45 of 48
5 4 3 2 1
 5 4 3 2 1

D
+5VS D

2
CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
5

5
PR128 +CPU_B+

VR_ON
1_0603_5%

25
PL11
1 2 B+

10U_1206_6.3V7K

10U_1206_6.3V7K
1
FBMA-L18-453215-900LMA90T_1812

1U_0603_6.3V6M

10U_1206_6.3V7K
1

1
PR129 0_0402_5% PC98

0.01U_0402_25V7Z

0.01U_0402_25V7Z

PC99

PC100

PC101
+

1
100U_25V_M + PC131

1U_0603_6.3V6M
PC103

PC104
7,20 DPRSLPVR 1 2

1
100U_25V_M

PC102

PC105
2

2
PR130 0_0402_5%
2

2
4,19 H_DPRSTP# 1 2

5
PR131 0_0402_5% PQ32
15 CLK_EN# 1 2 SI7840DP_SO8

0_0402_5%
PR133 0_0402_5%

PR132
+3VS 1 2 4
1U_0603_16V6M

+3VS
1

2
1.91K_0402_1%
PC106

PR134 PC107 P_0.36H_ETQP4LR36WFC_24A_20%

3
2
1
1

BOOT_CPU1 1 2 1 2 2 1 +VCC_CORE
2
2

PR136
PR135

4.7_1206_5%
5
6
7
8

5
6
7
8

1
0_0603_5% 0.22U_0603_10V7K PL12

3.65K_0805_1%

10K_0402_1%
499_0402_1% PR140

PR137

PR139
C C
49

48

47

46

45

44

43

42

41

40

39

38

37
1_0402_5%

PR138
2

PQ33
3V3

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

CLK_EN#

DPRSLPVR

VR_ON
1

PQ34

680P_0603_50V8J
1 2

2
1 36 4 4 @ PR141 @ 0_0603_5%
20,25 VGATE PGOOD BOOT1

PC108
1 2
5 H_PSI# 2 35 UGATE_CPU1 VSUM PC109
PSI# UGATE1
1 2

2
45 PGD_IN 3 34 PHASE_CPU1 VCC_PRM
PGD_IN PHASE1

3
2
1

3
2
1
PR142 147K_0402_1% ISEN1
1 2 4 33 0.22U_0603_10V7K
RBIAS PGND1 IRF8113PBF_SO8 IRF8113PBF_SO8 @
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
PR143 @ 4.22K_0402_1% PH3 VR_TT# LGATE1

10U_1206_6.3V7K

10U_1206_6.3V7K
5

1
1 2 1 2 6 NTC PVCC 31
PQ35

PC110

PC111
@ 470K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2 SI7840DP_SO8
SOFT LGATE2

2
1 2
@ 0.015U_0402_16V7K PC112 8 29
0.015U_0603_25V7K PC113 OCSET ISL6262CRZ-T_QFN48 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2
PR144 13K_0402_1% 10 27 UGATE_CPU2 P_0.36H_ETQP4LR36WFC_24A_20%
COMP UGATE2 PR145 PC114
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PL13
1 2

5
6
7
8

5
6
7
8

1
1000P_0402_50V7K PC115 0_0603_5% 0.22U_0603_10V7K
DROOP

12 FB2 NC 25

1
VDIFF

VSUM

ISEN2

ISEN1

PR147 3.57K_0402_1%
VSEN

10K_0402_1%
GND

VDD
RTN

DFB

1
VIN

PR146 PR150

3.65K_0805_1%

PR148
1 2
VO

B B

PR149
1 2 PU11 PQ36 PQ37 @ 4.7_1206_5%
13

14

15

16

17

18

19

20

21

22

23

24

1 2
4 4 1_0402_5%

2
PC116 5600P_0402_25V7K

2
ISEN1 PC117 PR151 @ 0_0603_5%
ISEN2 @ 680P_0603_50V8J 1 2

2
2

PR153 61.9K_0402_1% PC118 1500P_0402_50V7K 1 2 +5VS

3
2
1

3
2
1
1

1 2 2 1 PR154 VSUM PC119

1

@ 0_0402_5% PR152 1_0603_5% 1 2

PR155 PC120
1 2 1U_0603_6.3V6M
1

@ 0_0402_5% IRF8113PBF_SO8 IRF8113PBF_SO8 0.22U_0603_10V7K

2

PC121 390P_0402_50V7K VCC_PRM

ISEN2
PR157
3.4K_0402_1% PC122 470P_0402_50V7K
1 2 1 2 1 2 +CPU_B+
1

PR1561 2 PC123 10_0603_5%

2

PR158 1.82K_0402_1% 0.01U_0402_25V7Z

PC124 0.018U_0603_50V7K
5 VCCSENSE 1 2 1 2
VSUM
1

PR159 0_0402_5%
1

PC125 PC126
2.61K_0402_1%

+VCC_CORE @0.018U_0603_50V7K 0.018U_0603_50V7K

PR161

1 2
2

PR160 20_0402_5% 1 2
PR162 0_0402_5%
10K_0603_1%_TH11-4H104FT

A 5 VSSSENSE A
2
1

PC127 180P_0402_50V8J
11K_0402_1%

PR163
PR164

1 2
2

20_0402_5%
PH4

1 2 1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

PR165 1K_0402_1% PR166 5.62K_0402_1%

PC128 0.068U_0402_10V6K 2005/06/23 2006/06/23 Title
Issued Date Deciphered Date
1

VCC_PRM 1 2 +CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PC130 0.22U_0402_10V4Z AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
PC129 2 1 2 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3011P 0.2
0.22U_0603_10V7K MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 46 of 48

5 4 3 2 1
NO DATE PAGE MODIFICATION LIST PURPOSE
-------------------------------------------------------------------------------------------------------------
8/8 P.15 Delete R589,R181,R190 No reserve those resistors
8/10 P.30 Add D35,R671 for G_beep function
8/10 P.25 Swap EC pin8 and Pin42 for G_beep function
8/11 P.30 Del R659,C613& Add D36 for G_beep function
8/16 P.7 unmount R503, R519 Intel Request
8/16 P.9 unmount R480, R478 Intel Request
8/16 P.11 unmount R514 Intel Request
8/16 P.20 Mount R249, Add R672,R673,R674 Intel Request
8/19 P.35 Add R675 For BIOS debug port
8/19 P.39 Modify R611, C557 For RUNON timing sequence
8/22 P.7 Add R676 Reserve for TS on SODIMM
8/22 P.28 Del U10,R128,R134,C162,C164,C169,C174,C175 Change G-sensor
8/23 P.28 Add C619,C620,C621,C622,C623,C624,C625,C626,C627
8/23 P.28 Add R677,R678,R679,R680,R681,R682,R683,R684,R685,R686
8/23 P.28 Del x_sensor, y_sensor, z_sensor connection to EC G-sensor circuit modification
8/23 P.28 Add Q49,Q50,U50,U51,U52,Y5 For New G-sensor solution
8/24 P.17 Change JP18.40 to +5VALW
8/24 P.29 Change U33.8 to SUSP#
8/24 P.29 Change U33.8 to SUSP#
8/25 P.16 Change D27,D28,D29 pin 3 to +2.5VS for Intel's suggestion
8/25 P.37 Change JP9 connector to 6pin To meet ME's definition
8/25 P.15 J10 change to Jump 43*79 for DFX request
8/25 P.19 CMOS_CLR1 change to Jump 43*79 for DFX request
8/30 P.39 Modify Screw holw location
8/30 P.22 To correct MSBS_SDCMD_SMWE#/SDWP#_SMCE# signals
8/30 P.39 Change R612=220K,C557=0.033uF,R611=0ohm for power on sequence
9/2 P.29 Add EC_HDPPD to U14.24 and R682 G-sensor circuit modification
9/5 P.09 Swap CRT_R & CRT_B To fix CRT issue of GM
9/8 P.20 Change LAN_Disable from GPIO15 to GPIO28
9/9 P.26 Swap RX /TX signals
9/9 P.25 Swap EC pin8 & Pin42 for follow EVT pin definition
9/9 P.29/30 To separate Line out and HP signals
9/12 P.30 D35/D36 change to Diode 4148
9/12 P.30 Add R687 ,Q51
9/12 P.29 Add R688,C628
9/12 P.24 Change JP34 connector to ACES_87213-1000
9/12 P.29 Delete R395
9/12 P.16 Change F1 to SP04301P000
9/13 P.38 Reserve SIO_SMI#/SIO_IRQ signals
9/13 P.38 Reserve JP35 for BIOS debug
9/14 P.22 Add Q52 for 5in1 LED

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3011P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 15, 2005 Sheet 47 of 48
 5 4 3 2 1

U6

NB
945GM
GM@
D D
U41 U41

LAN
82573E 82562
82573E@ 82562@

T1

TRANSFORMER
TST1284B-LF
82562@

ZZZ
C C
PCB
PCB ZKU LA-3011P REV0

U13

CARDBUS
PCI8412
PCI8412@

D20 D21 D19 D22 D23

B
Green LED B

HT-297DQ/GQ AMB/YG HT-297DQ/GQ AMB/YG HT-191UYG-DT YEL/GRN HT-191UYG-DT YEL/GRN HT-191UYG-DT YEL/GRN
LEDG@ LEDG@ LEDG@ LEDG@ LEDG@

C19 C22

CAP for LAN

0.01U 0.01U
82562@ 82562@

A A

Title
ISPD
Size Document Number Rev
B LA-2621 0.3

Date: Thursday, September 15, 2005 Sheet 48 of 48

5 4 3 2 1