EJERCICO 03:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity signal_generator_10ms is
Port ( clk_1khz : in STD_LOGIC;
reset : in STD_LOGIC;
Salida_10ms : out STD_LOGIC);
end signal_generator_10ms;

architecture Behavioral of signal_generator_10ms is

--declaracion de contador en vector de 4 bit
-- ya que se requiere contar hasta 10ms

signal Contador : STD_LOGIC_VECTOR(3 downto 0);

begin
process(clk_1khz, reset)
begin
if reset = '1' then
Contador <= (others => '0');
elsif rising_edge(clk_1khz) then
-- impementacion de flip flop tipo T en vhdl
--inicio de ff tipo T
Contador(0) <= not Contador(0);
Contador(1) <= Contador(1) xor Contador(0);
Contador(2) <= Contador(2) xor (Contador(1) and Contador(0));
Contador(3) <= Contador(3) xor (Contador(2) and Contador(1) and
Contador(0));
-- fin de ff
end if;
end process;

EJERCICO 04:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Timed_Counter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
output : out STD_LOGIC);
end Timed_Counter;

architecture Behavioral of Timed_Counter is

constant COUNT_11SEC : unsigned(30 downto 0) := to_unsigned(1100000000, 31);
constant COUNT_14SEC : unsigned(30 downto 0) := to_unsigned(1400000000, 31);
signal counter : unsigned(30 downto 0) := (others => '0');

begin
process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
output <= '0';
elsif rising_edge(clk) then
if counter < COUNT_14SEC then
 counter <= counter + 1;
else
counter <= (others => '0');
end if;

if counter >= COUNT_11SEC and counter < COUNT_14SEC then

output <= '1';
else
output <= '0';
end if;
end if;
end process;
end Behavioral;

ARCHIVO CONTRAINS

set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }];

create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports
{ clk }];

set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { output }];