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Chapter 4 Output Stages and Power Amplifier
Chapter 4 Output Stages and Power Amplifier
Class A:
Class A output stages are known for their high fidelity and low distortion characteristics. In this
configuration, the output devices operate in the active region throughout the entire signal cycle i.e. the
conduction angle is 360o. Class A amplifiers are characterized by low efficiency and generate significant
heat due to continuous current flow, even when there is no input signal. Class A amplifiers have
maximum efficiency of 25% (without transformer) and 50% (with transformer).
Class E, F, and G:
These are specialized output stage configurations used in specific applications. Class E stages are
commonly found in RF amplifiers and are designed for maximum power efficiency. Class F stages
further optimize efficiency by shaping the transistor waveforms to reduce power losses. Class G stages,
often used in audio amplifiers, utilize multiple power supply rails to improve efficiency at low output
levels.
Class A Output Stage
Class A output stage is also known as Class A Amplifier. In this type of Amplifier the output waveform
is the exact replica of input waveform. The transistor conduct in the complete cycle i.e the conduction
angle is of 360o. There are basically two configuration of Class A amplifier i.e. Series fed Class A
amplifier and Transformer coupled class A amplifier.
When IC= 0,
When VCE = 0,
Now from these values we can draw a DC load line on the output characteristic of the transistor as
shown in figure:
Input power
The DC input power to the amplifier is given as:
2
Where,
2
Output Power
The AC output power is given as
"#" "#" "#" "#"
√2 √2 2√2 2√2 8
%&' ( &(
Where, ,
√ √
%&' )*) & )*)
,
%&' )*)
"#"
+ 0.25
-.
-. /
3
Maximum efficiency:
From the characteristics curve, we can see that "#" .
From equation (iii), we get
+ 0.25 25%
"#"
4 4
-.
+ -. 25%
Hence the maximum efficiency of class A amplifier is only 25%. The low efficiency makes class A
amplifier unusual in designing audio and power amplifiers.
In the amplifier, transformer is used to couple the output to the load resistance RL. the output reistance
as seen by transformer at the collector end is RL’.
6
We know transformer behavior.
→ 89:;<= :>;?3@8>A;: 8?
5 65
65
→ BC>>=?: :>;?3@8>A;: 8?
5 6
Chapter 4 Output Stages and Power Amplifier By:Er. MB Sah
→ AF=G;?H= :>;?3@8>A;: 8?
D 5
E
D 5
6 6 6
. I J
D 5
D
E
5 65 65 65
65
E
I J K
D
6 D D
Where, K
LM
LN
= Turn ratio of the transformer
DC analysis: at DC analysis the winding resistance is ideally zero so the DC load line is a straight
vertical line as shown in figure
0
∴
Where, Q
P
E
D
Output Power
The AC output power is given as
E E
D D
I J
"#"
2√2 "#"
D
E
8 DE
"#"
8 DE
General efficiency:
The efficiency is defined as the ratio of output ac power to input dc power.
"#"
8 E
+ D
E
D
+
"#"
8
From figure we can write,
"#" -.
And
2 -. /
By substituting these values in equation (iii), we get general efficiency:
4
+
-.
8 -. /
+ 0.5
-.
-. /
32
Maximum efficiency:
From the characteristics curve, we can see that "#" .
From equation (iii), we get
4
+ 0.5 50%
"#"
8 8
-.
+ -. 50%
Hence the maximum efficiency of transformer coupled class A amplifier is only 50%.
Using Opamp
Operation
When input is zero (vI=0)
When the input is zero, the base emitter junctions of both the transistors
are reverse biased so both the transistor are in cutoff region and the
output voltage (vo) is zero.
2 2 RS 2 RS
dc value of the ac output current which may be expressed as
T RS
T D T D
2 RS
Thus, DC power supply by source is
T D
Now, the efficiency is given as
RS
2
+ T
- D RS
2 RS 4
T D
The general efficiency of class B amplifier is given by below equation.
+ T ∗ 100%
RS
4
RS V
T
For maximum efficiency,
+ T ∗ 100% T ∗ 100% ∗ 100%
RS
-.
4 4 4
+ -. 78.5%
Condition for Minimum efficiency
Power loss (dissipation) by class B amplifier
D -
2 RS RS
T D
D
2 D
G D 2
Differentiating with respect to output voltage VOP
RS
G RS T D D
For maximum power loss,
Chapter 4 Output Stages and Power Amplifier By:Er. MB Sah
G D
0
G RS
2
0
RS
T D D
2
∴ 0.6366
RS
T
Thus, when the output peak voltage is 0.6366VCC, then the efficiency of class B amplifier becomes
2 T
minimum and is given by the expression
+ T ∗ 100% ∗ 100%
RS
4 T 4
+ 50%
For the next half cycle, the transistor Q1 gets into cut off condition and the transistor Q2 gets into
conduction, to contribute the output. Hence for both the cycles, each transistor conducts alternately. The
output transformer Tr3 serves to join the two currents producing an
almost undistorted output waveform.
-
2 D
A;Z ACA 8C:FC: F8[=>
2 RS 2
T T D
2
T D
Efficiency is given by
T T
+
- D
2 D 2 4
T
+ ∗ 100% 78.5%
4
A;Z ACA =@@ H =?H\
Q.1. It is required to design a class B output stage to deliver an average power of 20W to an 8 Ω load.
The power supply is to be selected such that VCC is about 5 V greater than the peak output voltage. This
avoids transistor saturation and the associated nonlinear distortion, and allows for including short-circuit
protection circuitry. Determine the supply voltage required, the peak current drawn from each supply,
the total supply power, and the power-conversion efficiency. Also determine the maximum power that
each transistor must be able to dissipate safely.
18
The peak current drawn from each supply is
2.25_
RS
RS
D 8
Since, each supply provides a current waveform of half-sinusoids, the average current drawn from each
`
supply will be abc
. Thus the total supply power is
2 RS 2 ∗ 2.25
23 ∗ 32.9 d
T T
20
The power conversion efficiency is
+ ∗ 100% ∗ 100% 60.8%
-
32.9
The maximum power dissipated in each transistor is given by
23
6.7d
L -. S -.
T D T 8
Q.2. For class B amplifier providing a 14V peak signal to 16 Ω load and power supply of VCC= 24V,
determine input power, output power and circuit efficiency.
Solution: –
Given, RS 14
D 16Ω
24
2 RS 2 ∗ 14
We know that the input power is
24 ∗ 13.36d
T D T 16
The output power is
14
6.125d
RS
-
2 D 2 ∗ 16
6.125
The efficiency of the circuit is given by
+ ∗ 100% ∗ 100% 45.84%
-
13.36
Darlington Transistor
A Darlington transistor (or Darlington pair) is an electronics component made via the combination of
two BJTs connected in such a way that it allows a very high amount of current gain. The Darlington
transistor was invented by Sidney Darlington in 1953.
The value of VBB is selected to yield the required quiescent current IQ.
Circuit operation
When goes positive by certain amount, the voltage at the base of QN increases by the same amount,
and the output becomes positive at an almost equal value
/
2 L
The positive causes a current D to flow through RL, and thus L must increase i.e.
L S / D
The increase in L will be accompanied by a corresponding increase in L (above the quiescent value
of VBB/2). However, since the voltage between the two bases remains constant at VBB, the increase in
L will result in an equal decrease in S and hence in S .
L / S
ln / ln 2 ln
L S
i i i
f f f
L S
From the equation above, we can see that for positive output voltage, the load current is supplied by QN ,
which acts as the output emitter follower. Meanwhile, QP will be conducting a current that decreases as
increases; for large the current in QP can be ignored altogether.
For Negative input voltages the opposite occurs: the load current will be supplied by QP, which acts as
the output emitter follower, while QN conducts a current that gets smaller as becomes more negative.
The class AB amplifier operates in nearly same manner as the class B amplifier with one exception. For
small vi, both transistors conducts, and as vi increased or decreased, one of the transistor at a time takes
over the operation by providing the forward bias of ±0.5V to each diode of the transistor. since the
transition is a smooth one, crossover distortion will be almost totally eliminated.
Figure – Complementary symmetry Class AB Push Pull Amplifier using Darlington pair
The biasing diodes, however, need not be large devices, and thus the quiescent current IQ established in
QN and QP will be IQ=nIBIAS, where n is the ratio of the emitter–junction area of the output devices to the
junction area of the biasing diodes. In other words, the saturation current IS of the output transistors is n
times that of the biasing diodes.
The primary collector region has a lightly doped impurity concentration so that a large base-collector
voltage can be applied without initiating breakdown. Another N region, with a highly doping
concentration, reduces collector resistance and makes contact with the external collector terminal. The
base region is also much wider than normally encountered in small devices. A large base-collector
voltage implies a relatively large space charge width being induced in both the collector and base
regions. A relatively large base width is required to avoid punch through breakdown.
Cut-off region
A power transistor is said to be in a cut off mode if the NPN power transistor is connected in reverse
bias i.e. base-emitter and collector-base are connected in reverse bias. Hence,
IB = 0, IC = βIB = 0
This indicates that transistor is in off state and in a cut off region. But a small fraction of leakage current
flows throw the transistor from collector to emitter i.e, ICEO.
Active region
A transistor is said to be in active region only when the base-emitter region is forward bias and
collector-base region is reverse bias. Hence there will be a flow of current IB in the base of transistor and
flow of current IC through the collector to emitter of the transistor. When IB increases IC also increases.
Quasi saturation region
A transistor is said to be in the quasi saturation stage if base-emitter and collector-base are connected in
forwarding bias. The Quasi saturation region is available only in Power transistor characteristic not in
signal transistors. It is because of the lightly doped collector drift region present in Power BJT. In this
region, the power transistor take less time for transition from ON to OFF state (Saturation to cut-off).
Hard saturation region
A transistor is said to be in hard saturation if base-emitter and collector-base are connected in
forwarding bias. . In this region, the power transistor take more time for transition from ON to OFF state
(Saturation to cut-off).
1
For the parallel resonance circuit as shown in above figure, the admittance is given by,
q s / tu
r
1 1
Where, G = conductance and B = Suspectance
q / t Ivw B J
vw x
Chapter 4 Output Stages and Power Amplifier By:Er. MB Sah
1 1
We have,
wq y / t Ivw B Jz
w
vw x
The equation (i) says that at near zero and near infinity frequency, the admittance is very high. And as a
result output voltage is very low near zero.
When the frequency increases from near zero, the output voltage raises upto a certain frequency called
resonance frequency and beyond that, the output voltage falls down. At resonance frequency, the output
voltage is highest. But at a resonant frequency, the Susp
1
ectance (B) is equal to zero or the capacitive reactance is equal to inductive reactance.
vw B 0
vw x
1 1
vw 8>, @w
√xB 2T√xB
At cut-off frequency of -3db, vw we have
|s | |u |
s u
1 1
Ivw B J
vw x
1 1
Ivw B J }
vw x
At lower cutoff frequencyv 5 , we have from equation (ii)
1 1
Iv 5 B J
v 5x
1 1
At higher cutoff frequencyv , we have from equation (ii)
Iv B J /
v x
1 1 1 1
Adding equation (iii) and (iv), we get
Iv 5 B J / Iv B J
v 5x v x
1 1 1
v 5/v B I / J 0
x v 5 v
1 1 1
v 5/v I / J
xB v 5 v
1 v 5/v
v 5/v I J
xB v 5 v
1
v 5v
xB
1
∴v 5
v xB
1 1
From equation (iv) and (v), w get
Iv B J /
v x
1
v B v 5B /
1
∆v v v 5
B
1
Band width of the resonant circuit is
ud
B
Chapter 4 Output Stages and Power Amplifier By:Er. MB Sah
Quality factor (Q)
Quality factor is the measure of the selectivity or sharpness of the tuning of the resonant circuit. It can be
>=38?;?: @>=€C=?H\ vw
expressed as
• vw B
•;?G[ G:‚ 1
B
But, vw
5
, we get
√D
1 B
• B ƒ
√xB x
Synchronous tuning
Synchronous tuning is used to get sharp curve having least bandwidth (BW). Consider a case of N
identical resonant circuits. Figure shows the response of the individual stage and overall response. The
bandwidth was observed “shrinkage” of overall response.
The 3 dB bandwidth B of the overall amplifier is related to that of the individual tuned circuits, vw /•,
vw 5/L
by
ud ]2 1
•
Where,
N is the number of stages
√2 5/L 1 is bandwidth shrinkage factor
Stagger tuning
Staggered tuned amplifier is an amplifier that is used to improve the total frequency response of the
tuned amplifier. Usually, these amplifiers are designed to exhibit an overall response for maximal
flatness in the region of the center frequency. This amplifier uses tuned circuits to operate in union.
Key features
It has better overall response
The tuning of this amplifier is very easy.
It has better flat wideband characteristics.
The bandwidth is increased √2 times when compared to a single tuned amplifier.
The overall gain is increased due to the cascading of two single tuned amplifiers.
Chapter 4 Output Stages and Power Amplifier By:Er. MB Sah
Figure – Response of the stagger tuning
Q.1. Calculate the efficiency of transformer coupled push pull power amplifier for a supply voltage of
20V and output of: Vp=20V and Vp=16V.
Solution:-
T RS
We know that the efficiency of transformer coupled push pull power amplifier is given as
+ ∗ 100%
4
T20
When Vp=20V,
+ ∗ 100% 78.5%
4 ∗ 20
T16
When Vp=16V,
+ ∗ 100% 62.83%
4 ∗ 20
Q.2. A transformer coupled class A large signal amplifier has maximum and minimum values of
collector-emitter voltages of 25V and 2.5V. Determine its collector efficiency.
Solution:-
Given
-. 25
2.5
We know that the efficiency of the transformer coupled class A amplifier is given as
-. / 25 / 2.5 27.5
Q.3. A transformer coupled class A amplifier uses 25:1 transformer to drive 4Ω load. Calculate the
effective load as seen by the collector of the transistor.
Solution:- Given
Load resistance (RL) = 4Ω
Turn ratio (α) = 25:1
Effective load (RL’) = ?
We know that the effective load resistance as seen by the collector side of the transformer is given as
RL’ = α2 RL = 252 *4 = 2500 Ω = 2.5K Ω
Q.4. For a class B amplifier using a supply of VCC = 30V and driving a load of 16 Ω. Determine the
maximum input power, output power and transistor dissipation.
Solution:- Given
Load resistance (RL) = 16 Ω
Supply voltage (VCC) = 30V
We know, for class B amplifier
ab
Input power,
c P
N
ab
Output power, -
P
For maximum input and output power, VP = VCC
Therefore,
Maximum input power,
2 RS 2 2 ∗ 30 1800
35.81 d;::3
-.
T D T D T 16 50.2655
Maximum output power,
30 900
28.125 [;::3
RS
- -.
2 D 2 D 2 ∗ 16 32
Power dissipation in two transistors,
… †n‡ -. - -. 35.81 28.125 7.685 [;::3
7.685
Power dissipation in single transistor,
3.8425 [;::3
… †n‡
ˆ‡
2 2
Q.5. A silicon power transistor is operated with a heat sink (θSA=1.5 oC/W). The transistor rated at 150
w (25 oC) has θJC= 0.5 oC/W and the mounting insulation has θCS= 0.6 oC/W. what maximum
power can be dissipated if the ambient temperature is 40 oC and TJmax = 200 oC.
Solution:- we know that
lm l- n / o
lm -. l- n / -. o
lm -. l- n
-.
o
Now, we have
o o‰ / o f / of 0.5 / 0.6 / 1.5 2.6 C/W
lm -. l- n 200 40
Therefore,
61.53 [;::3
-.
o 2.6
lm -. l- n 150 25
a. The thermal resistance is given as
o 62.5 C/W
-. 2