Science Bulletin 67 (2022) 270–277

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Science Bulletin
journal homepage: www.elsevier.com/locate/scib

Article

An artificial neural network chip based on two-dimensional

semiconductor
Shunli Ma a,1, Tianxiang Wu a,1, Xinyu Chen a,1, Yin Wang a, Hongwei Tang a, Yuting Yao a, Yan Wang a,
Ziyang Zhu b, Jianan Deng b, Jing Wan b, Ye Lu b, Zhengzong Sun a, Zihan Xu c, Antoine Riaud a, Chenjian Wu d,
David Wei Zhang a, Yang Chai e, Peng Zhou a,⇑, Junyan Ren a,⇑, Wenzhong Bao a,⇑
a
State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China
b
State Key Laboratory of ASIC and System, School of Information Science and Technology, Fudan University, Shanghai 200433, China
c
Shenzhen Sixcarbon Technology, Shenzhen 518106, China
d
School of Electronic and Information Engineering, Soochow University, Suzhou 215006, China
e
Department of Applied Physics, The Hong Kong Polytechnic University, Hung Hom, Kowloon, Hong Kong, China

a r t i c l e i n f o a b s t r a c t

Article history: Recently, research on two-dimensional (2D) semiconductors has begun to translate from the fundamen-
Received 1 July 2021 tal investigation into rudimentary functional circuits. In this work, we unveil the first functional MoS2
Received in revised form 16 August 2021 artificial neural network (ANN) chip, including multiply-and-accumulate (MAC), memory and activation
Accepted 27 September 2021
function circuits. Such MoS2 ANN chip is realized through fabricating 818 field-effect transistors (FETs) on
Available online 5 October 2021
a wafer-scale and high-homogeneity MoS2 film, with a gate-last process to realize top gate structured
FETs. A 62-level simulation program with integrated circuit emphasis (SPICE) model is utilized to design
Keywords:
and optimize our analog ANN circuits. To demonstrate a practical application, a tactile digit sensing
MoS2
Two-dimensional (2D) FETs
recognition was demonstrated based on our ANN circuits. After training, the digit recognition rate
Artificial neural network (ANN) exceeds 97%. Our work not only demonstrates the protentional of 2D semiconductors in wafer-scale inte-
Multiply-and-accumulate (MAC) grated circuits, but also paves the way for its future application in AI computation.
Circuits Ó 2021 Science China Press. Published by Elsevier B.V. and Science China Press. All rights reserved.

1. Introduction
Two-dimensional (2D) semiconductors such as semiconducting
transition metal chalcogenides (TMDs) have become a promising
material family for building circuitry owing to their outstanding
electronic transport properties, sensing capabilities, and mechani-
cal compliance [1–5]. In particular, monolayer MoS2 has been
widely investigated as a channel material for field-effect transis-
tors (FETs) [6–8], mainly because of its 1.8 eV direct bandgap that
gives rise to reasonably high mobility and large on/off ratio. These
characteristics make it suitable for logic circuits [3,9–11], analog
circuits [12,13], memories [14,15], and photodetectors [16–18].
The MoS2 FETs fabricated on the insulating substrate also share
the similar structure and superiorities of the silicon-on-insulator
(SOI). Moreover, thanks to the atomic thin nature of 2D semicon-
ductors, their environment-sensitive and flexible characteristics
[19,20] make them promising materials for light [21–24], temper-
⇑ Corresponding authors.
E-mail addresses: pengzhou@fudan.edu.cn (P. Zhou), junyanren@fudan.edu.cn
(J. Ren), baowz@fudan.edu.cn (W. Bao).
1
These authors contributed equally to this work.
ature [25], gas [26–29], and pressure sensing [30–32] for flexible
electronics, such as wearable devices [33] and electronic skins
[25,34]. Meanwhile, the weak interlayer van der Waals forces
allow different 2D materials to be vertically transferred and
stacked. Therefore, it is possible to fabricate three-dimensional
(3D) monolithic integrated circuits by stacking multilayer 2D semi-
conductors with different properties and functions [35,36], which
may enable energy-efficient smart prosthesis (e.g., artificial retina,
nose, and skin).
Natural sensing-computing is provided by sensing neurons and
the neurons located next to them. Similarly, integrating prepro-
cessing directly on a sensor integrated circuit can significantly
improve the speed and efficiency of the irregular signal processing
in various types of sensors [37]. Integrating these functions into a
single package also ensures that power consumption is lower than
that in discrete components. Given the tremendous success of arti-
ficial neural networks (ANN) for image processing and pattern
recognition [38-42], ANNs are foreseen to be key models used in
individual sensors and an overall system. Compared with digital
ANN, analog ANN integrated circuits (ICs) are more suitable for
preprocessing tasks due to their lower power consumption and

https://doi.org/10.1016/j.scib.2021.10.005
2095-9273/Ó 2021 Science China Press. Published by Elsevier B.V. and Science China Press. All rights reserved.
S. Ma et al. Science Bulletin 67 (2022) 270–277

higher throughput. But unlike isolated sensor devices, the develop- [55,56]. All electrodes were patterned with an LED direct writer
ment of such sensing-computing architecture is more challenging (MicroWriter ML3) and subsequently deposited by electron beam
due to a large number of required transistors, accurate models, (E-beam) evaporation. CF4 and SF6 plasma etching were performed
and various types of circuits needed for signal amplification and to define the MoS2 channel region and via holes, respectively. The
data processing [43]. dielectric layer, 20-nm-thick HfO2, was deposited by atomic layer
The family of 2D semiconductors is potentially suitable for deposition (ALD). More experimental details are provided in the
building ANNs at the hardware level. First, semiconducting TMDs Supplementary materials (online).
grown on insulating substrates have a similar structure as silicon
on insulator (SOI), which provides low gate-induced drain leakage
3. Results and discussion
(GIDL) and substrate leakage current. Thus, for a device based on
TMDs with a relatively large bandgap like MoS2, its low leakage
3.1. Circuit architecture
current enables less energy consumption and a lower data refresh
rate for information storage devices such as in dynamic random-
An ANN model requires complex peripheral circuits. Previous
access memory (DRAM). Experimental results also suggest that
research into ANNs implemented in integrated circuits focused
MoS2 transistors show less 1/f noise than Si devices fabricated with
on devices built from memristors or flash memories that can per-
the complementary metal-oxide semiconductor (CMOS) process
form analog MAC operations [39–41,57]. However, most previous
[44–46]. Under the same signal energy, the signal-to-noise ratio
results lacked activation function or were complemented by
is sufficiently large that analog convolution calculations can be
peripheral silicon circuits, without which a neural network is
performed. Moreover, upon choosing appropriate voltage ranges,
merely a linear regression model.
a desirable correlation between the measured current and applied
Taking biological neurons as an example, neurons have multiple
voltage can be obtained for implementing analog matrix computa-
synapses which transmit sensed signals to soma. Each synapse can
tion [47]. Therefore, TMDs are ideal transistor candidates for
store and change the corresponding weight of the sensed signal,
implementing ANNs in application-specific integrated circuits
and a multiplication operation between the sensed signal and
[48], as they offer an advantageous combination of established
weight can be achieved. A soma then can realize an accumulation
sensing capabilities and outstanding transistor performance.
of multiplication results from all synapses. When the summation is
However, there are still obstacles to overcome before the use of
larger than the threshold, the soma will be activated and generate
2DLMs becomes practical. (1) Most previously demonstrated
output through an axon. A mathematical model of a biological neu-
devices are implemented using exfoliated 2DLM sheets with
ron is shown in Fig. 1a, where w1, w2


wn are synaptic weights,
micrometer size, limiting the circuit scale. Therefore, reliable
and x1, x2


xn are bio-electric signals. R is the integration opera-
wafer-scale material growth is under investigation [49,50]. (2)
tion in the soma and f indicates the activation function that gives
Fabricating wafer-scale 2D materials integrated circuits [5,13,51–
the output. The corresponding device model of one neuron is
53] is still in the early stage, especially gate-last technology with
shown in Fig. 1b. Its input signals come from various sensors,
accurate control over the threshold voltage VT. Additionally, an
and the MoS2 FETs perform a MAC operation, whose result is then
accurate device model for large-scale circuits still requires devel-
transmitted into an activation function circuit. The weight storage
opment. (3) An ANN requires a higher noise budget and linearity
and update can be enabled by MoS2 a-RAM, thus improving the
than a digital circuit, so that a more accurate device model is
speed of ANN. A complex ANN with multiple neurons is designed
needed. Analog convolutional neural network (CNN) design also
as shown in Fig. 1c. The proposed MoS2 ANN circuit consists of
requires additional circuits. A complete functional CNN requires
an input layer with 6 neurons with 10 synapses for each neuron,
various circuit modules, such as circuits for activation functions,
a fully connected layer, and an output layer with 10 neurons. In
memory, and the multiply-and-accumulate (MAC) operation [38–
each neuron, the MAC result is sent to a nonlinear activation func-
40,42,54].
tion circuit that maps the output results and normalizes them to
In this work, we develop a gate-last processing technique for
within a specified range (0 to 1). The fully connected layer connects
wafer-level MoS2 films and build a chip for general ANN process-
the input and output layers. Finally, an off-chip logical function
ing, which can be used for future smart sensing applications. The
classifier is used to label sensed targets. Based on our gate-last pro-
analog MAC can be realized on a dual-gate MoS2 FET. One MoS2
cessing technique for wafer-level MoS2 films [56], we then build a
transistor and one capacitor (1T-1C) form a simple storage module,
MoS2 chip for general ANN processing (Fig. 1d). Weight update and
which acts as an analog random-access memory (a-RAM). This chip
optimization come from off-chip control using the back propaga-
provides all fundamental functions required in AI computation:
tion (BP) algorithm [58]. Compared to previously reported ANN
convolution calculation, RAM, and activation function modules,
results based on RRAM or 2D semiconductors, our MoS2 chip inte-
which are all formed by 2D MoS2. A trained ANN is used for tactile
grates MAC, a-RAM, and activation function circuits (Fig. 1e), pre-
letter recognition with an accuracy greater than 97%. Thus, a
senting a major advance for practical circuitry applications.
2DLM-based ANN makes it possible to fabricate a sensing-
computation system beyond silicon.
3.2. Wafer-scale MoS2 film synthesis and device processing

2. Experimental Wafer-scale ANN circuits require high-quality 2DLM thin films.

The wafer-scale monolayer MoS2 film used in this work was
synthesized at atmospheric pressure through a two-temperature-
zone chemical vapor deposition (CVD) system. An appropriate
amount of sulfur powder (99.999%, Alfa Aesar) and MoO3 powder
(99.95%, Alfa Aesar) were placed in a low-temperature zone (180
℃) and high-temperature zone (650 ℃) with a distance of 30 and
10 min sulfuration time, respectively. The top-gated MoS2 FETs
and circuits were fabricated directly on the 2-inch MoS2 wafer
upon our previously developed gate-last processing technique
271
While wafer-scale 2DLM synthesis by CVD has been recently
demonstrated [10,11,59], other challenges impede practical appli-
cation, including the processing of electrical contacts and dielectric
layer deposition due to the atomic thickness and complex interface
conditions. Here, based on the high-quality continuous MoS2 film
we previously reported [55,60,61] (Fig. 2a and Fig. S1 online), a
gate-last technology is developed for MoS2 FETs (Fig. 2b) with
the manufacturing processing flow shown in Fig. S2 (online). For
the subsequent simulations, the device parameters were esti-
mated. The average mobility from 49 MoS2 TG-FETs was estimated
S. Ma et al. Science Bulletin 67 (2022) 270–277

x1 h1 O1
(a) x1
Synapse (c) Neuron-1 Neuron-1

w1 Neuron x2 h2 O2
Neuron-2 Neuron-2
Dendrite
x2 w2 Signals
from Output
x1w1 layer
Soma sensors x10 h6 On
x2w2 Neuron-6
Output Neuron-10
axon
Activation
function
Sum w1-w6 w7-w16
xnwn Off-chip
DAC for DAC for
xn wn control
weigh update weigh update
signals

(d) (e) Sensed

signals
Weight
update
(b)
Signal x1
Weight bias
Neuron Memory DAC DAC Memory Neuron
w1 Neuron
cell 1 cell 1 cell 4
Signal x2
Neuron
Weight Activation cell 2
w2 function
Neuron Memory DAC Neuron DAC Memory Neuron
cell 2 cell 3 cell 5
Signal xn
Artificial
Weight neuron
wn Neuron
Neuron Memory DAC cell 10 DAC Memory Neuron
cell 3 cell 6
Output signal

ANN output

Fig. 1. (Color online) Demonstration of the as-fabricated MoS2 ANN integrated circuit. (a) A mathematical analogy of a biological neuron. (b) An MoS2-based artificial neuron
cell including soma (MAC operation), dendrite (data input from sensor), and synapse (the a-RAM is to store the weight value). (c) Schematic diagram of the proposed ANN,
which consists of an activation function, MAC, a-RAM, and timing control circuits. h is the output of fully connected layer; O is the output of the ANN circuit. (d) A false-color
optical microscopic image of an as-fabricated ANN integrated circuit. Zoom in is a photograph of the integrated circuit in which the red square corresponds to the ANN circuit.
The scale bar is 1 mm. (e) Schematic circuit architecture of our MoS2-based ANN.

to be 51.1 cm2 V1 s1 with an average threshold voltage of
VT = 1.4 V, as shown in Fig. 2c, d. Compared with the previously
reported gate-first processing-based MoS2-FETs [9,55,62,63], our
MoS2 TG-FETs exhibit E-mode characteristics and are more com-
patible with traditional device processing, which reduces the inte-
gration difficulty of the large-scale circuits.
Moreover, implementing high-performance analog circuits
requires device modeling with higher accuracy [64–66]. For our
MoS2 FETs, we established a device model with analytic equations
and a level-62 SPICE model, whose results are consistent with the
experimental results (Fig. 2c, d, also see Supplementary materials
(online) for more details). HSPICE software can simulate and opti-
mize the analog circuits in ANNs, which reduces the excessive bur-
den of repeated tests and ape-outs. The following section of this
paper shows how MoS2 can be used to build complex digital and
analog circuits for AI computation, which is a significant step for-
ward beyond laboratory-level 2DLM devices [6,64,65].
3.3. MoS2 MAC structure for ANN computing
Here, we examine how a MAC operation is implemented in
MoS2 circuits. As shown in Fig. 2e, a single-branch structure con-
sisting of a dual-gate transistor acts as a multiplication module,
which can be used for multiplication operations between the
weight w and an input signal x on dendrite j. The input data is con-
nected to TG1 and the synapse weight is transmitted to TG2. Such a
dual-gate circuit is widely used for mixer or multiplier circuits
[67]. In our circuit, the channel under G1 works as a source-
follower FET, and the G2 drain voltage is Vd-G2 = VG1–Vth-G1, where
Vth-G1 is the threshold voltage of gate G1. G2 works in the linear
region because both VG1 and VG2 of T2 can be independently
adjusted to modify output current Id. A multiplication between
VG1 and VG2 can be performed with only one MoS2 FET, i.e.,
272
Id / wij(l) xj(l) (see Supplementary materials (online) for more
details). To better express the multiplication operation, Fig. 2f
shows a 3D plot of the measured current Id as a function of VG1
and VG2. The section cut above the gray plane corresponds to the
more linear region (relatively large VG1 and VG2 values), which is
apparently similar to the simulation results for an ideal multiplica-
tion operation between VG1 and VG2, as shown in the inset. Fig. 2g
outlines a multi-branch parallel MoS2 device and its corresponding
circuit structure. In such a structure, multiple MoS2 FET branches
are connected in parallel by connecting all the drains together,
similar to a synapse-neuron structure. Therefore, the result of an
accumulation operation corresponds to the total output current,
expressed Iout = R Id. Fig. 2h shows the total current is a linear func-
tion of branch number at different values of VG1 and VG2. The com-
plete matrix computation process is shown in Fig. 2i. G1 and G2 are
connected to an input sensor signal xj and weight signal wij, where i
is the neuron, and j corresponds to the synapse in neuron i. Thus,
the total output current from the neuron i is proportional to hi =
Rwijxj, which indicates the MAC operation is now implemented.
A convolution operation can be implemented by multiple MAC
operations depending on the size of the input matrix, and our
MoS2 chip shown in Fig. 1d connects 10 input signals for convolu-
tion operations. Compared with a digital MAC circuit, which
requires much more transistors and multiple types of blocks, our
analog MoS2 transistor network is in principle more advantageous
in terms of chip area, calculation speed and power consumption.
3.4. Peripheral circuits: a-RAM (synapse) and activation function units
In addition to performing a MAC operation, the weight update
function is also the key for training an ANN, and dynamic weight
writing and holding can be implemented by connecting the circuit
in Fig. 2e with our a-RAM circuit, whose schematic diagram and
S. Ma et al. Science Bulletin 67 (2022) 270–277

(a) (b) (c) 2.5 (d) 10 -5

Experimental Experiment
Gate-last Simulation Simulation
processing 2.0 -7
10

ID (A/ m)
ID ( A/ m)
Top gate
1.5
10-9
HfO2
Source Drain 1.0
MoS2 10-11
0.5 500 m
Sapphire
0.0 10-13
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
VTG (V) VTG (V)

(e) (f) (g) TG1-1 TG2-1

TG1-2 TG2-2
(h) 0.4
HfO2
VG1 = VG2 VD = 0.1 V
TG1-n TG2-n
ID

ab
0.3 V
Drain Source 0.3

A/ m)
0.6 V
VG1 MoS2 0.9 V
ID ( A/ m)

a b Sapphire
TG1 0.2
Isum
VG2

Itotal
I1 I2 In
TG2 0.1

0
0 1 2 3 4
Branch #

VDD R h1,1=w1,1 x1,1 +w1,2x2,1 + +w1,10x10,1

(i) Vout

w1,1 w1,2 w1,10 x1,1 x1,2 x1,10 h1,1 h1,2 h1,10

wi,1 wi,2 wi,10 w2,1 x2,2 x2,10 h2,1 h2,2 h2,10

w2,1 w2,2 w2,10

x1,j x2,j x10,j h10,1 h10,2 h10,10

w10,1 w10,2 w10,10 w10,1 x10,2 x10,10

Fig. 2. (Color online) Wafer-scale MoS2 devices and working principle of the MAC module. (a) Two 2-inch-diameter sapphire wafers. The dark yellow wafer is uniformly
covered with MoS2 grown via CVD, and the other one is a bare sapphire wafer. (b) Schematic of a MoS2 TG-FET structure. (c, d) Transfer characteristics of 49 FETs located at the
center region of a wafer in linear and logarithmic scale, respectively. The red curves show simulation results. The insert shows a photograph of the MoS2 TG-FET arrays, in
which the scale bar is 500 lm. W = 30 lm, L = 20 lm. VD = 0.5 V. (e) Schematic diagram of the multiplier unit (one branch) consisting of a MoS2 FET with dual gates TG1 and
TG2. (f) 3D plot showing measured ID data as a function of VG1 and VG2 from the multiplier unit. VD = 0.5 V. At a relatively large voltage (the region cut above the gray plane),
the result is close to the ideal multiplication correlation between VG1 and VG2, and the inset shows simulation results for a∙b as a function of a and b. (g) The upper graph
shows a MoS2 device with parallel multi-branch dual-gate FETs, and the lower graph shows the corresponding schematic. (h) Total current as a function of the number of
multiplier branches, where the result shows a summation operation. (i) The corresponding simplified MAC circuit with a corresponding schematic diagram of the MAC
computation process.

electrical connections are shown in Fig. 3a. This consists of a MoS2
FET T1 with a high on/off ratio for switching and a capacitor C,
which is able to store the weight value of dendrite j. During the
training, the control voltage VC on the transistor is at a high level,
and T1 is turned on to act as a low-impedance path. In the von Neu-
mann architecture, the computing and memory units are sepa-
rated, so that the computing unit needs to read and write the
memory at high frequency, and data transmission becomes a com-
puting bottleneck. Based on the aforementioned circuit design, it is
noticed that the a-RAM storage units and computing (MAC) mod-
ules are directly connected with each other (as shown in Fig. 3b),
therefore, a computation-in-memory structure can be imple-
mented in our proposed ANN network.
We then test its memory functions. During a write operation,
the drain voltage on T1 acts as a bit line (BL) and is raised from 0
to 1 V. Vg-T1 acts as a word line (WL) and is raised from 3 to
3 V, as shown in Fig. 3c. Measured results are plotted as shown
in the red curve, whose first positive current pulse (in red) indi-
cates the capacitor has been recharged. During the hold state, T1
is turned off to provide a high-impedance path with low current
leakage for long-term retention. During a read operation, the BL
increases from 0 to 0.5 V and the WL shifts from 3 to 3 V. The
negative measured current indicates charge remains stored after
the hold time.
273
Due to ultralow current leakage through monolayer MoS2, the
charge saved in the capacitor may persist in the neuronal layer
over many processing cycles. Consequently, Fig. 3d shows that dif-
ferent output current levels can be maintained on the order of 10 s,
which is sufficiently long for successive computation cycles in the
convolutional layer. It also confirms that the input signal Vin is suc-
cessfully stored in the capacitor, and thus it can provide a high-
resolution analog voltage control signal for VG1-T2, unlike an SRAM
structure that can only maintain binary 0 and 1 levels.
Besides the a-RAM module, activation function circuits were
also designed and fabricated on our MoS2 chip. The activation func-
tion circuit is used to process the convolutional output, which sim-
ply consists of two MoS2 FETs M1 and M2. The simulation results
based on the 62-Level SPICE model are shown in the upper graph
of Fig. 3e, where the gate of M2 is kept at a constant voltage and
M2 can be treated as a resistance RM2. RM2 changes accordingly to
different control voltages Vc. The output voltage Vout is
ðV in Þ
V out ðV in Þ ¼ RM1RðM1
V ÞþRM2 DD
V : ð1Þ
in
When the input voltage Vin is small, we have Vout  VDD. By increas-
ing Vin, RM1 approaches an appropriate range for Eq. (1) to act as an
activation function whose gradient is gm1RM2, where gm1 is the
transconductance of M1. When Vin continues increasing, Vout
S. Ma et al. Science Bulletin 67 (2022) 270–277

(a) a-RAM MAC

(c) (e)
4 80
WL 3 VDD
VDD Vc
VG M2
2 40
R BL Vin Vout
M1

Vin (V)
2

IC (nA)
Vout (V)
T1 0 0

T2
Vin
IC C -2 -40 1
0.5 V
Write Read 1.0 V
-4 -80 1.5 V 2.5 V
0 10 20 30 40 50 0
Time (ms) 2.0 V 3.0 V
(b) (d) VC 0V 1.5 V
800 T1 Vd = 0.1 V 3 0.5 V 2.0 V
T2
MAC Vin 1.0 V 2.5 V
Id 3.0 V
600

Vout (V)
Vin = 3.0 V 2
Id (nA)

400
Vin = 2.7 V 1
200
Vin = 2.3 V
a-RAM 0
0
2 4 6 8 10 -1 0 1 2 3
Time (s) Vin (V)
Fig. 3. (Color online) Peripheral circuits used to implement a complete ANN. (a) Schematic MoS2 circuit diagram resembling a neuron with one synapse, where the left a-RAM
circuit is used to store and update the weight. (b) An optical microscopic image of a multi-branch MoS2 MAC circuit with each branch connected an a-RAM. The scale bar is
150 mm. (c) Successive write and read operations of the 1T/1C unit. The retention time is longer than 10 s. (d) Measured ID value of transistor T2 controlled by the voltage
stored in the capacitor during one test cycle (10 s). Different values of Vin are used to charge the capacitance before turning off T1. (e) Simulated (upper graph) and measured
(lower graph) Vout vs. Vin for the activation function circuit with different control voltages Vc (lower graph). The inset in the upper graph shows a schematic circuit model.

approaches 0, which provides the required capability of an activa-
tion function. By tuning VC of M2, different shapes of Vout can be
obtained, and the slope of the Vout -Vin curve corresponds to the
leaning speed. Thus, we can use VC as a tuning knob to control
the ANN training process. The corresponding experimentally mea-
sured results are shown in the lower graph of Fig. 3e, which
entirely satisfies the requirement of the activation function
described above.
3.5. Braille character recognition with a MoS2 ANN classifier
Since the required synapse weight values are unknown, they
must be determined by training the network. Starting from small
random weight values, the network is fed with an input matrix I
composed of sensed signals for ANN training, whose output matrix
T is known. According to the current weights, the network com-
putes an output O that we want to be as close as possible to T.
Our proposed multilayer ANN takes inputs with 10 features and
classifies its output into 10 categories (Fig. S8 online). The synapse
weights are optimized using gradient descent starting from small
random values. Like most machine learning applications, the
weight optimization in our chip is realized off-chip (on a separate
computer) using the BP algorithm (details see Supplementary
materials online).
Finally, we demonstrate a tactile Braille classifier algorithm that
combines all the MoS2 circuits described above. The tactile sensa-
tion of skin is an important part of human perception, including
temperature, pain, vibration, and shapes by receptor neurons.
The skin receptors can also be divided into slow and fast adaptive
types, mainly depending on the location and distribution of the
receptor in the skin (Fig. 4a, also see Supplementary materials
274
online for more details). The skin perceives the shape of an object
because the generated pressure is similar to the shape of the
object, which is how blind individuals can read Braille. In the
future, the pressure sensing function can be further integrated into
our ANN-MoS2 circuits by taking advantage of the piezoelectric
properties of MoS2, which converts pressure into an electric signal
and mimics skin receptors [68–70].
In Fig. 4b, we use a 3  3 array input to represent the tactile sen-
sation of touching a Braille character. Typical current distributions
for letters ‘N’, ‘V’ and ‘Z’ with different pressure levels are demon-
strated. The value of each tactile pixel is discretized into 256 pres-
sure levels. The inputs (I1, I2


I9) into the ANN correspond to 9
voltage values in the flattened input array. Therefore, the signals
can be displayed as a voltage intensity mapping graph. In this
work, we generate pressure distribution library data by different
samples, and three different distribution sets are designed for each
letter, and each set has 50 samples for further ANN testing (Fig. S9
online). The input voltage range is from 0 to 3 V in our system,
while the bias input V10 is fixed according to the algorithm. After
optimizing the weights for 23 training epochs, the obtained weight
values for the input and output layers are shown in Fig. 4c, which
are subsequently updated by an off-chip algorithm implemented
by Matlab (see Supplementary materials (online) for more details).
The ANN is trained by 50 sets of sample images as an input. The
image classification is determined using forward propagation lay-
ers which consist of convolution, activation in the hidden layer,
and the fully connected layer. The final output layer is calculated
to predict the total error as the y-axis in Fig. 4d, and the target
matrix corresponds to vectors [0,0,1] for Z, [0, 1, 0] for N, and [1,
0, 0] for V. Based on the simulation results, ultimately yielding a
classification accuracy of 97%, as shown in Fig. 4d, e.
S. Ma et al. Science Bulletin 67 (2022) 270–277

(a) (b)
Pressure (static)

Vibration (low f )

Quiver (high f )

Applied Small pressure Large pressure

force
on skin
Current
pulse

(c) Input layer Output layer (d) (e)

103

Mean squared error (mse )

100

Recognition rate (% )
10-2 80
W (V)

W (V)

60
10-7
40

10-12 20
0
10-17
1 11 21 31 41 1 11 21 31 41
Train number Train number

Fig. 4. (Color online) A tactile sensation demonstration based on MoS2 ANN circuits. (a) Schematic showing three types of sensors in different locations on human skin
corresponding to three different vibration modes. The bottom graph shows generated current pulses with small and large pressures. (b) Current distribution for letters ‘N’, ‘V’,
and ‘Z’ with different pressure levels and classification results after successive training epochs. (c) The weights of the input and output layers which are optimized for 23
training epochs. (d) The mean squared error of the ANN network as a function of training number. (e) The recognition rate of the ANN network versus as the number of
training epochs.

4. Conclusion most of the devices. Tianxiang Wu, Xinyu Chen, Yin Wang, Hong-
wei Tang, and Jianan Deng performed electrical measurements.
To conclude, we used high-quality uniform MoS2 thin films to Yuting Yao, Yan Wang, and Ziyang Zhu performed the device sim-
produce the first analog-ANN circuit based on MoS2. These analog ulation. Zihan Xu and Zhengzong Sun prepared the 2D semicon-
circuits were designed and optimized using high-fidelity Level-62 ductors. Jing Wan, Ye Lu, Chenjian Wu, Chai Yang, and Renjun
SPICE models for MoS2 FET transistors. The chip includes 16 artificial Yan advised the circuit design and test. Antoine Riauda, Peng Zhou,
neurons organized in two layers. Each artificial neuron consists of and David Wei Zhang discussed the results. All authors contributed
MAC units acting as soma, an a-RAM memory to store the synapse to the preparation of the manuscript.
weights, and a nonlinear activation circuit. After the off-chip opti-
mization of weight values the device provides a Braille letter recog-
Appendix A. Supplementary materials
nition rate above 97%. Such illustrated proof-of-concept ANN system
integrates the essential functions required for practical ANN-
Supplementary materials to this article can be found online at
preprocessing applications, and definitely has room for further opti-
https://doi.org/10.1016/j.scib.2021.10.005.
mization since this is only an early-stage exploration. In addition,
due to the atomically thin and air-stable nature of 2DLMs, our
MoS2-based ANNs can be fabricated on flexible substrates for bio- References
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Shunli Ma received his B.S. degree in Micro-electronics
Engineering from Shanghai Jiao Tong University in 2011,
and his Ph.D. degree in Micro-electronics Engineering
from Fudan University in 2016. From 2012 to 2014, he
was a project officer at Nanyang Technological Univer-
sity. He is currently an assistant professor at the State
Key Laboratory of ASIC and System, Fudan University.
His research interest includes 2D semiconductor IC
design and mm-wave integrated-circuit design, includ-
ing mm-wave imaging sensing, mm-wave PLL and high-
speed sampler in ADC, and biomedical RF circuits for
cancer detection.
Tianxiang Wu received his B.S. degree from Anhui
University in 2014, and his M.S. degree from Southeast
University in 2017. He is currently pursuing his Ph.D.
degree in Micro-electronics Engineering at Fudan
University. His current research interest includes the
design of PLL and 2D semiconductor circuit design.
S. Ma et al.
Xinyu Chen received her B.S. degree from Xidian
University in 2018. She is currently pursuing her Ph.D.
degree in Micro-electronics Engineering at Fudan
University. Her current research interest includes
emerging devices and circuits based on 2D transition
metal dichalcogenides (TMDS), especially MoS2, and the
photoelectric performance of MoS2 photodetectors.
Peng Zhou received his B.S. (2001) and Ph.D. (2006)
degrees in Physics from Fudan University, and now he is
a full professor at Fudan University. His research focuses
on novel memory devices based on two-dimensional
layered materials.
277
Science Bulletin 67 (2022) 270–277
Junyan Ren received his B.S. degree in Physics and his
M.S. degree in Electronics Engineering from Fudan
University in 1983 and 1986, respectively. In 2000, he
joined Department of Microelectronics, Fudan Univer-
sity, where he is currently a full professor. Since 1992,
he has been a Research Member of the State Key Labo-
ratory of ASIC and System. His research interest includes
data conversion, signal processing, and analog/RF/
mixed-signal designs.
Wenzhong Bao is a full professor at School of Micro-
electronics, Fudan University. He received his Ph.D.
degree from the University of California, Riverside
(2011). He then worked as a joint postdoc at the
University of Maryland College Park and the King
Abdullah University of Science and Technology from
2012 to 2015. His current research interest includes
emerging advanced materials and their applications in
next-generation electrical, optoelectrical and energy
devices.