An In-Field Programmable Adaptive CMOS LNA for Intelligent IoT Sensor Node Applications

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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2021.3077196, IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems
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An In-Field Programmable Adaptive CMOS

LNA for Intelligent IOT Sensor Node
Applications
Maryam Shafiee, Sule Ozev
marketplace will enable IoT developers to optimize the overall

Abstract- As the Internet of Things (IOT) is growing system performance without having a deep RF design
rapidly, there is an emerging need to facilitate development experience and without having to incur the cost of taping out an
of IOT devices in the design cycle while optimized entirely new design for each product.
performance is obtained in the field of operation. This Wireless transceivers are increasingly complex and highly
paper develops reconfiguration approaches that enable integrated systems which makes them more susceptible to
post-production adaptation of circuit performance to process variations. During circuit design, a designer’s primary
enable RF IC re-use across different IOT applications. An goal is to meet circuit specifications under given process
adaptable low noise amplifier (LNA) is designed and variations. In doing so, designers spend significant effort to de-
fabricated in 130nm CMOS technology to investigate the sensitize their design with respect to process variation i.e. they
post-production reconfiguration concept. A statistical often follow a conservative design approach, pushing the device
model that relates circuit-level reconfiguration parameters operating point closer to the center of the design specification
to circuit performances is generated by characterizing a space rather than closer to the specification limits. While
limited number of samples. A deep learning algorithm is designers strive for process robustness at nominal operating
used to generate the model. This model is used to predict the conditions, such as supply voltage, noise, temperature, same
performance parameters of the device in the field. The robustness is generally difficult to maintain over a large
estimation error for LNA performance parameters are variation in operating conditions. By modifying these operating
obtained in the simulation environment as well as chip conditions during testing, we can increase sensitivity to process
measurements. parameters. There are various forms of post-production
Index Term- Adaptive IoT Sensor, Adaptable RFIC, Low Noise calibration and reconfiguration for RF devices [7-9]. The
Amplifier, Machine Learning, Deep Learning calibration is realized by built-in tuning knobs allowing for
trade-offs between RF specifications. In general, RF circuits are
I. INTRODUCTION designed to include calibration hooks in bias or passive
Internet of Things (IOT) is rapidly being integrated into our components to meet target specifications. Different calibration
daily lives in diverse applications ranging from health care to mechanisms are introduced in the literature in the form of bias
home automation, energy management to environmental current, bias voltage, and passive tank adjustments [10-13]. In
monitoring [1-4]. IOT devices have their own application- general, Analog knobs are not desirable in RFIC design due to
specific requirements which demands for multi-standard multi- complexity of additional circuitry and additive noise. Besides,
mode transceivers. Conventionally the IOT interconnected these methods typically provide limited calibration space.
objects are realized by existing commercial off-the-shelf As opposed to post-production calibration which is
components (COTS) which are designed and optimized for optimizing the device with respect to a single application, in this
certain communication standards or a specific use [5-6]. paper, we develop existing mechanisms to reconfigure the RF
However, using separate radios is power hungry, costly and the device for optimized performance with respect to multiple IOT
interconnections are not optimized with regards to an applications. Unlike conventional designs which operate
application-specific requirement. On the other hand, using power-optimally only for the nominal process corner, the
customized radio transceiver ICs for each specific application proposed adaptive RF system when subject to manufacturing
is not practical due to high overall product costs (OPC). A cost- process variations start to provide sub-optimal performance.
effective solution is a single radio transceiver adaptable to We will exploit existing calibration approaches and
localized IOT applications. Reconfigurability enables power mechanisms and enhance them to further sensitize the circuit to
optimal interconnections within IOT devices. The process/layout variations. This sensitization is expected to
reconfigurable transceiver is tweaked on the spot based on spread and shift the circuit performance distribution over
process variation, as illustrated in Fig.1. Therefore, the
operating condition will be no longer a single point in the
Manuscript received 09/10/2020; revised MM DD, YYYY. This work
was supported by National Science Foundation under grant number middle of the specification space but there are several operating
1617562. Maryam Shafiee is currently with Broadcom Ltd, Irvine CA,
conditions within the total variation range. The concept of
application-specific
USA requirements such as power, EVM,
(email: mshafiei@asu.edu) process-variation tolerant adaptive RF systems is introduced in
Sule Ozev
BER, datais rate
a professor
etc. atHaving
Arizona State
suchUniversity,
adaptable Tempe,
RF AZ,
ICsUSA
in the [14].
(email: sule.ozev@asu.edu)
0278-0070 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Prince Edward Island. Downloaded on June 08,2021 at 08:12:44 UTC from IEEE Xplore. Restrictions apply.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2021.3077196, IEEE
Number of performance. The reconfiguration and verification procedure

Samples can be statistical-based or iterative. The iterative procedure
makes a measurement with each adjustment of the tuning knobs
until the target performance is achieved [8,11,16]. This
procedure is time consuming. The statistical based method on
the other hand, develops a nonlinear prediction model to adjust
the tuning knobs. This method is fast since it is a one-time
Setup2 Setup4 Setup6 calibration procedure which requires a training set [10,17,18].
Setup1 Setup3 Setup5 Setup7
This methodology can be used for on-chip self-testing and
Performance Parameter
calibration. Statistical mapping allows for easier model
Fig.1. Sensitization over process variation using different
calibration setup generation by relying on machine learning technique [19]. In
[10], the nonlinear prediction model is developed using
successive learning process based on MARS algorithm and
Our technique proposes a programmable device which adapts
Monte-Carlo samples. A self-generated sine test signal is
to different situations depending on the application
measured for each DUT and is used as the input to the statistical
requirements. Its performance is optimized in the field with
model for prediction results. The DUT calibration knobs are
regards to required specifications e.g. distance, power
adjusted using the performance curves of the DUT. The
consumption, BER, data rate, etc. We propose to use statistical
performance curve represents the relation between performance
mapping to capture the correlations among measured
parameter and the knob value of a golden DUT. Since the knob
performance parameters and reconfiguration modes. We
values are continues, obtaining this curve for each DUT is not
employ machine learning technique to capture these non-linear
practical for in-field calibration. Hence, it only obtained for one
correlations and predict the probability distribution of a target
sample and is used for tuning the rest of samples. Therefore, it
parameter based on measurements of correlated parameters. We
does not take into account the process variation between DUTs
will show that decision-making based on the prediction
for knob value selection. In [20], a one-shot tunable LNA is
algorithm instead of iterative testing of all possible
discussed which is calibrated using regression model and
reconfiguration schemes, saves us time and facilitates fast in-
statistical mapping however, this method is used for optimal
field adaptation of the device. We have demonstrated the
operation at a nominal process corner to improve yield rather
concept by designing a custom LNA with built-in tuning knobs.
our proposed method provides local optimization employing
The tuning knobs are carefully designed to provide independent
process variation into tuning range.
adjustment of important performance parameters such as gain
None of the discussed existing approaches, address an
and linearity. Minimum number of switches are used to provide
automated fully digital reconfiguration scheme which sensitizes
the desired tuning range without a need for an external analog
the tuning range to process variation.
input.
In the following sections, the proposed performance
III. PROPOSED IN-FIELD OPTIMIZATION FLOW
prediction and optimization algorithm is discussed. The LNA
Our proposed reconfiguration approach uses transistor sizing
architecture and selection of the tuning knobs are demonstrated.
and bias control. It uses coarse tuning of performance
Simulation and chip measurement results are further discussed.
parameters which is realized by only switches and is fully
II. PRIOR WORK performed in digital. Hence it is low cost and low overhead. As
it is shown in Fig. (1), the performance distribution over process
Adaptive wireless receivers have been explored in several
variation for each switch combination has overlap with others.
published articles. Majority of these reconfigurability methods
This bring a level of uncertainty which necessitates the
use power supply, bias current, bias voltage and passive tank
verification of the performance of the DUT at potential
adjustments [8,10,11,15,16]. These techniques employ fine and
switching combinations. To decide on the optimum switch
continuous tuning using analog control signals generated by
combination, instead of lengthy testing of the performance at
simple low-speed digital to analog converters (DACs).
each potential reconfiguration state, we have used a fast
However, DACs are power hungry and require notable
statistical-based prediction procedure using artificial neural
dedicated silicon area. Besides, the DAC settling time and
network algorithm. Our approach predicts the performance
conversion rate limits the critical in-field adaptation pace.
parameters of all switch combinations of the DUT and based on
Due to process variations, the performance parameters of the
the prediction result, selects the switch combination closest to
DUT are not fixed for all parts. This necessitates an in-field
the target. Therefore, unlike previous works, the selection of the
verification of reconfiguration state with respect to the target
Neural Network
S21 at COMB0
COMB 1 {P} at COMB 1

S22 at COMB0
S11 at COMB0
{P} at COMB 0
P1dB at COMB0
NF at COMB0 COMB 3 {P} at COMB 3
IDC at COMB0
Vref at COMB0
Fig.2. (a) Proposed in-field optimization flow (b) statistical mapping process diagram
switch combination, takes into account the DUT to DUT For better understanding of the neural network algorithm a
variations. We conduct full testing of all sample DUTs for diagram is shown in Fig.2(b). Set {p} represents the demanded
training purpose to obtain parameter profiles during offline specifications to characterize the device. Set {P} at switch
phase. These profiles will help in selecting and guiding our combination zero, i.e. all switches off, is input to the neural
learning algorithm parameters. It is important to select the network. The neural network learning process predicts the set
inputs to the algorithm that are highly correlated to the target {P} for the rest of the switching combinations. This procedure
and these correlations are altered by potential process and can be one-time or iterative. Due to overlap between
circuit modifications. As it is depicted in the flow chart of performance distribution of switching combinations and
Fig.2(a), The statistical model is formed during characterization prediction error, it might be required to redo the prediction with
phase. Decision is made by statistical mapping using the two known inputs if it results in a closer to target combination
learning algorithm during online phase. Based on prediction selection. This means adding another measurement phase to the
results, the tuning knob combination(s) are selected and applied prediction procedure hence increasing reconfiguration time.
to the digital circuitry. If after measurement, desired specs are
met, the adaptation is done. Otherwise, it repeats the mapping IV. LNA ARCHITECTURE
to get a closer to target switching combination. A. LNA Design
The optimized operation is obtained by setting the correct
digital code to the calibration network. Several tunable LNAs are explored in the literature
[21,22,23]. In [21], an inductor-less reconfigurable LNA is
introduced however, their drawbacks are either poor
performance in multi-band LNAs or the selectivity issue in
wideband LNAs. [22] presents a reconfigurable multimode
VDD2
VDD1
LNA. The multimode operation is realized by incorporating a
switched multitap transformer into the input matching network
sw3
Varactor_out
of an inductively degenerated common source amplifier. In [23]
Ls2 MB5 MB6
MB2
A CMOS reconfigurable LNA is reported. By combination of
Lso
MB1
ML2
MB3 MB4
Vref out switched inductors and varactors it performs continuous
Li ML1A
ML3A ML3B ML3C
frequency tuning from 2.4 to 5.4 GHz. By transformer and
Inp
ML1B
sw2
sw4
capacitor dual feedbacks, broadband performance is achieved.
Ls1
sw1 sw5 In Table I, a performance summary of the recent published
Varactor_inp
Fig.3. LNA circuit with embedded tuning knobs
Table I. Summary of performance and comparison

Ref [21] [22] [23] [25] This
work
Tech (µm) 0.13 0.13 0.13 0.13 0.13
Freq (GHz) 1.8~2.4 3.3 3.43 2.6~4.8 2~4
NF (dB) 3.2~3.5 3.0 4.4 4.2 3~3.4
Gain (dB) 20.6~22.1 14.2 11 13.8 13~14.5
IIP3 (dBm) -16 ~-11.8 -2 -2.5 -5.8 -2**
S11 (dB) --- -18.6 <-12 <-10 <-10 (a)
Power (mW) 9.6 6.4 3.6 8 15

Area (mm2) 0.052 0.44 0.49 1.8* 0.16
*Including test pads ** Measured at 3 GHz
multi-standard CMOS LNAs is given for comparison with the
proposed LN A while all switches are off at nominal corner.
Figure (3) shows the topology of the reconfigurable wide-
band LNA presented at this work.
A current re-use technique is used to comply with the low
(b)
voltage design. It provides high gain while driving high
impedance of the second stage [24]. A DC feedback loop is used
to define the operating points and keep ML1A and ML2 in
saturation [25]. 𝐿𝑖 , 𝐿𝑠1 and 𝐿𝑠2 are tuned to obtain the optimum
noise figure and input matching. The two-stage topology helps
with the independent tuning of the performance parameters.
First stage primarily controls the noise figure while the
second stage is mainly responsible for the linearity of the LNA.
The gain control is conducted in three modes; High gain,
medium gain and low gain, each obtainable with different (c)
combinations of noise figure and linearity. Hence, gain modes
are available independent of the noise figure and linearity
configurations. The varactors are added to compensate for bond
wire inductances and provide broadband input reactive
matching for wideband operation. The LNA operation
frequency range is 2GHz-4GHz and the following results are
collected at 3GHz.
The LNA is implemented in a 130 nm CMOS technology.
The sizing of the transistors is listed in Table II. (d)
Fig.4. Distribution of a) Noise figure b) Gain c) IP1dB d)
Table II. Device sizing DC current over process variation for the default LNA
Device 𝑾⁄ (𝝁𝒎) Device 𝑾⁄ (𝝁𝒎)
𝒍 𝒍
B. Programmability Knob Selection
ML1A 80/0.12 SW2/SW3 2/0.12
The tuning knobs include switches SW1 to SW5, VDD1 and
ML1B 70/0.12 SW1/SW4 /SW5 10/0.12 VDD2 as it is shown in Fig. (3). The tuning hooks are selected
such that they cover the desired reconfiguration range. VDD1
ML2 100/0.12 MB1 1/0.12
and VDD2 are supply voltages (=1.3v) which are provided by a
ML3A 30/0.12 MB2 2.5/0.12 low-drop-out regulator since these knobs are controlled
digitally too.
ML3B 30/0.12 MB3 /MB4 3/0.12
Five switches are embedded into the design to control the
ML3C 70/0.12 MB5 /MB6 8/0.12 performance parameters. SW1 inserts ML1B into the circuit with
its gate connected to ML1A resulting in enhanced gain and
improving noise figure but aggregates input matching to some

extent. SW2 and SW3 add a parallel resistance which
consecutively changes the reference voltage of the differential
amplifier which affects the DC bias voltages of ML1A, ML2 and
ML3A. SW2 reduces the reference voltage hence reduces gain,
linearity and power consumption.
Whereas, SW3 increases the reference voltage hence increases
linearity and power consumption but aggregates noise figure.
SW4 and SW5 add transistors ML3B and ML3C in parallel with
ML3A to result in increased gain and power consumption.
NF (dB)
(a) Twelve programmable combinations are chosen to optimize
performance with respect to requirements. For instance, if
higher linearity is required, SW3 is turned on however in order
to reduce the noise figure SW1 is switched on too. The desired
performance can be achieved by setting the correct digital codes
to the reconfiguration network.
It is good to investigate the effect of adding the switches to
the design. SW1 may contribute to the NF/impedance matching
degradation of the LNA. In deep submicron process the input
capacitance of ML1 is dominated by metal overlap capacitance
(b) so that it will not be affected much by transistor switches if all
the source nodes are AC bypassed to ground (Fig.3). Hence the
input matching of LNA remains steady good in different
configurations since the change on input capacitance is little
[23].
V. SIMULATION RESULTS
A. Circuit Characterization
Using Monte-Carlo simulations, we will construct local

statistical models that relate circuit-level calibration parameters
(c)
to circuit performances.
The LNA at default state (all switches off) is characterized by
running a 200-sample Monte-Carlo run. Fig. (4) depicts the
distribution of each performance parameter.
The proposed reconfiguration scheme is used to sensitize the
LNA circuit to the process variation. Hence, a Monte-Carlo
simulation is performed to characterize the performance
parameters range for each switching combination.
The performance corners are achieved by running Monte-
Carlo simulation for 200 samples for all the switching
(d)
combinations over process variation. Fig. (5) shows the
Fig.5. Distribution of a) Noise figure b) Gain c) IP1dB d) DC histogram for each performance parameter of the
current over process variation for programmable LNA programmable LNA. It reveals the sensitization effect on
Table III. Tuning range and mean value of performance parameters widening the circuit performance parameters span over process
Performance NF IP1dB Gain Power variation. Table III shows the tuning range and the mean values
Parameters Diss. for targeted performance parameters obtained from histogram
plots. The reconfiguration feature provides a wide tuning range
Tuning ≈1.5 ≈10 dB ≈12 dB ≈23 mW for gain, obtainable at a broad linearity span, makes it suitable
Range dB for adaptation to localized application-specific requirements.
Mean 3 dB -19 dBm 14.6 dB 15 mw
Table IV. Four switch combinations for four different scenarios

Switch Combo Gain S11 S22 NF IP1dB IDC
(dB) (dB) (dB) (dB) (dBm) (mA)
Sw3 11.5 -10.0 -27.8 3.9 -14.5 17.4
Sw4-Sw5 19 -11.4 -25.6 3.2 -20.0 15
Sw1-Sw3-Sw4 16.5 -9.9 -30.7 3.0 -16.5 20.3
1.05*VDD1- 13.5 -14.4 -26.5 3.5 -19.2 13.5

Sw2
1 2 3 4
Fig. 6. Four scenarios for adaptation investigation [11]
Yet, noise figure variation is kept small providing the low combination while input parameters are assumed to be known
noise figure requirement for the LNA. at one or more combinations (e.g. at combination where all
B. Optimization in Matlab switches are off). Eventually, for a specified target performance
and based on predicted performance parameters, the optimized
A Monte-Carlo generated training set is input to the learning
operation is obtained by setting the correct digital code to the
algorithm to form the statistical model of the system in all
calibration network. Twelve switching combination are used
available states. Using artificial neural network algorithm, the
for the adaptation purpose.
performance parameters are predicted for each switch
(a) (b)
(c) (d)
Fig.7 (a) Predicted gain RMS error (b) Predicted IP1dB RMS error (c) Predicted noise figure RMS error (d) Predicted
DC current RMS error
As an example, different scenarios are investigated to show test time and characterize the DUT at two switching
the adaptation of our design to the specific requirements. Fig. combinations and predict the third combination only (case2). In
(6) shows different four scenarios where each has a particular this case, we assumed that the DUT performance at
performance parameter condition. Four different switching combination 4 and combination 6 are tested and are known;
combination provides a close match for each situation. Table IV These are applied as the inputs to the prediction algorithm to
lists the possible switch combinations which corresponds to predict the parameters at combination 5. Therefore, we save
each case 1 to 4 respectively. one-third of the conventional test time. After running our
As discussed earlier, the neural network learning algorithm is optimization algorithm, a switch combination which fits the
used in our proposed method to predict the performance desired performance the best with the optimum power
parameters of the device. The prediction RMS error is consumption, is selected. The results for both cases are
calculated and plotted in Fig. (7) for gain, noise figure and tabulated in Table V. In this table measurement error is
IP1dB. Maximum prediction RMS error for gain is 0.5 dB and neglected.
For noise figure is 0.12dB. To illustrate the optimization and In case1, the predicted gain for combination 5 is above the
adaptation procedure, we review an example. A target desired target range, hence it is removed from the choices.
performance is assumed: gain 15dB-17dB, IP1dB>-20dBm, Between combination 4 and 6, combination 4 is more power
NF<3.7dB. Three switching combinations satisfy the target efficient and can be selected. In case2 on the other hand,
requirements simultaneously as illustrated in Fig. (8). predicted gain of combination 5 lies within the desired range.
Therefore, the best switch combination is unknown. Instead of Combination 5 can be the final choice due to lower power
testing all three switch combinations, to save time, we apply the consumption. Depending on the acceptable deviation from
prediction algorithm. In this example, performance at target parameters, a margin in target performance can be
combination 4 is characterized for a part and is fed to the defined to account for the prediction error. These acceptable
algorithm as the known input feature to predict performance margins depend on overall system prerequisites. If the error is
parameters at combination 5 and combination 6. Therefore, the higher than expected margins, then the accuracy of the artificial
test time is reduced to one-third of the conventional approach neural network can be improved by increasing number of
(case1). However, there is a trade-off between the adaptation
time and the adaptation error. Alternatively, we may double the
(a) (b)
(c) (d)
Fig.8. Performance parameters of three switching combinations over process variation (a) Gain (b) Noise figure (c)P1dB (d) DC
current
Table V. Optimization result for specified target parameters

Target: Combination 4 Combination 5 Combination 6
S21: 15dB-17dB
P1dB>-20dBm
NF<3.7dB
S21(dB) NF P1dB IDC S21(dB) NF (dB) P1dB IDC S21(dB) NF (dB) P1dB IDC
(dB) (dBm) (mA) (dBm) (mA) (dBm) (mA)
Case1 Measured 16.3 3.65 -18.45 15.0 - - - - - - - -
Predicted - - - - 17.13 3.54 -18.87 15.0 15.73 3.27 -16.7 20.8
Case2 Measured 16.3 3.65 -18.45 15.0 - - - - 15.05 3.38 -15.8 21.3
Predicted - - - - 16.45 3.53 -19.0 14.1 - - - -
Actual 16.3 3.65 -18.45 15.0 16.85 3.62 -18.95 14.0 15.05 3.38 -15.8 21.3
training set, changing the activation function or weight performance parameters for each switching combination. The
initialization of the learning algorithm [26]. variations among the boards are trained to generate a hundred
Monte-Carlo samples. Using our learning algorithm in Fig.2,
VI. CHIP IMPLEMENTATION
A. Layout
The proposed adaptable LNA is designed in 130nm
technology. Overall, the LNA core occupies 0.16mm2 area and
the total area including pads is 1mm2. The complete
reconfiguration network, including the additional tuning modes
occupies less than 0.0002mm2 area. Thus, the entire
reconfiguration network imposes no more than 0.1% area -
overhead. There are four single-ended two port inductors with
a ground return path. The ground terminal is down-bonded
beneath the die to realize very low parasitic ground. Fig. (9)
depicts the layout and the microphotograph of the fabricated
adaptable LNA including the pad ring and ESD cells.
The digital circuitry to program the switches, is not

implemented in this test chip. In order to reduce the number of (a)
I/O pins, a serial to parallel 7-bit shift register (for 7 knobs)
scheme is suggested. A complete system design including
digital LDOs and digital control circuitry is left to future design.
Area overhead due to shift registers and switches in 130nm
technology is around 5400µm2 [27] which translates to less than
3.3% area overhead of the core LNA.
B. Chip Measurement Results

The fabricated chip is measured in the lab. A network
analyzer is used to measure the S-parameters. A spectrum
analyzer is used to measure IP1dB of the device. To measure
the noise figure, the Y-factor method is applied using a noise
source and the spectrum analyzer. Four PCB boards with the (b)
LNA chip and same components are measured to account for Fig. 9. (a) Proposed LNA chip layout in 0.13um
the process variation. Fig.10 shows the variations in process (b) The fabricated chip microphotograph
prediction error is 0.16dB and maximum IP1dB prediction error

14 is 0.8dB.
12
10 C. Estimated Reconfiguration Time
Gain(dB)
8 The online reconfiguration time is the summation of the

6 prediction computational time (TNN<0.5ms) using the already
4 available statistical model from the offline phase, the test time
2
(Ttest<1ms) [28], the minimum clock period (Tclk_min=1441ps)
0
including delays to send configuration bit sequence[27] and the
switches settling time (TSW<1ns). The total time for one-time
reconfiguration Treconfig is equal to TNN + Ttest + 7× Tclk_min+ 7×
Combination Number
TSW≈ 1.5ms. The duration, Treconfig, is almost doubled if a second
(a) testing step is performed as shown in Fig.2(a).
7
6
Noise Figure(dB)
VII. CONCLUSION
5
4 In this paper, we propose an automated adaptable sensor node
3 for IOT applications. The deep learning technique is used for
2 automatic adaptation. We demonstrated the concept by
1 implementing it on a wideband CMOS LNA with built-in
0 tuning knobs. The performance space over process variation is
inquired. Using the statistical model formed by the learning
algorithm over Monte-Carlo samples, the performance
Combination Number
parameters are predicted. A case study of the in-field adaptation
(b)
shows the effect of prediction error on the switching
-8 combination selection. By characterizing more combinations in
-10 the field and hence sacrificing the test time, a closer-to-target
P1dB(dBm)
-12 combination can be selected. Further, the statistical model is

-14
established for the fabricated DUT and the prediction algorithm
-16
is used to make decision on the switching knobs.
-18
-20
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An In-Field Programmable Adaptive CMOS LNA for Intelligent IoT Sensor Node Applications

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This article has been accepted for publication in a future issue of this journal, but has not been

An In-Field Programmable Adaptive CMOS

marketplace will enable IoT developers to optimize the overall

Number of performance. The reconfiguration and verification procedure

COMB 1 {P} at COMB 1

NF at COMB0 COMB 3 {P} at COMB 3

COMB 22 {P} at COMB 11

Fig.3. LNA circuit with embedded tuning knobs

Table I. Summary of performance and comparison

S11 (dB) --- -18.6 <-12 <-10 <-10 (a)

Power (mW) 9.6 6.4 3.6 8 15

improving noise figure but aggregates input matching to some

Using Monte-Carlo simulations, we will construct local

Table IV. Four switch combinations for four different scenarios

Sw4-Sw5 19 -11.4 -25.6 3.2 -20.0 15

Sw1-Sw3-Sw4 16.5 -9.9 -30.7 3.0 -16.5 20.3

1.05*VDD1- 13.5 -14.4 -26.5 3.5 -19.2 13.5

Fig. 6. Four scenarios for adaptation investigation [11]

Table V. Optimization result for specified target parameters

Case1 Measured 16.3 3.65 -18.45 15.0 - - - - - - - -

Predicted - - - - 17.13 3.54 -18.87 15.0 15.73 3.27 -16.7 20.8

Predicted - - - - 16.45 3.53 -19.0 14.1 - - - -

The digital circuitry to program the switches, is not

B. Chip Measurement Results

prediction error is 0.16dB and maximum IP1dB prediction error

8 The online reconfiguration time is the summation of the

-12 combination can be selected. Further, the statistical model is

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