Faculty of Information and Communication Technology (FICT)
Interrupt and Polling
UCCE2043 Basic Microprocessor
8088/86 Microprocessor
Interrupt
leehy@utar.edu.my
INT vs CALL Instruction.
CALL
Can jump to any location within the 1MB
address range of the 8088/86 CPU.
Used by the programmer in the sequence
of instructions in the program
Cannot be masked (disabled).
Automatically saves only CS:IP of the
next instruction on the stack.
At the end of subroutine that has been
called by the "CALL FAR" instruction, the
RETF (return FAR) is the last instruction
H Y Lee
1 2
INT
Goes to a fixed memory location in the
interrupt vector table to get the address of
the interrupt service routine.
Externally activated hardware interrupt
can come in at any time, requesting
the attention of the CPU.
Belonging to externally activated hardware
interrupts can be masked.
Saves FR (flag register) in addition to CS:IP
of the next instruction.
The last instruction in the interrupt service
routine (ISR) for "INT nn" is the instruction
IRET (interrupt return). The difference is that
RETF pops CS, IP off the stack but the IRET
pops off the FR (flag register) in addition to
CS and IP.
3 4

Still remember the “telephone” example?

When the device needs the service of the CPU, the
device informs the CPU by sending an interrupt signal.
The CPU interrupts whatever it is doing and serves the request



The advantage of interrupts is that the CPU can serve many
devices

Each receives a service based on its priority

Disadvantage of interrupts is that they require more hardware
and software

In polling, CPU monitors continuously a status condition
and when the conditions are met, it will perform the
service.

Polling is cheap and requires minimal software & no additional
hardware.

But CPU busy all the time even nothing happen
Interrupts in 8088/86

There are 256 different types of 8088/86
interrupts (00 - 0FFh)

Interrupts can be triggered by:

Software (also called Exceptions)

Execution of INT instruction

some other internal event (e.g. division error)

Hardware

Peripheral devices usually generate external interrupt
requests as asynchronous events.
 Hardware Interrupt

The following 3 pins are associate with hardware
interrupts:

INTR, (Interrupt Request)

NMI (Non-maskable Interrupt)

INTA (Interrupt Acknowledge).

INTR is an input signal into the CPU which can be
masked (ignored) and unmasked through the use of
instructions CLI and STI.

NMI, which is also an input signal into the CPU, cannot
be masked and unmasked using instructions CLI and
STI, and for this reason it is called nonmaskable interrupt.

INTR and NMI are activated externally by putting 5V on
the pins of NMI and INTR of the 80x86 microprocessor.
5 6
INTR (Input to 8088/86)

INTR is an active-high level-sensitive interrupt request
line.

Active 1 level must be maintained until tested by the 8088/86.

Logic 1 must be removed before the ISR runs to completion.

Interrupt requests are recognized if the interrupt enable
bit is 1 (IF in flag reg.)

STI is used to set the interrupt enable bit

Interrupt requests are ignored if the interrupt enable bit
is 0 (IF in flag reg.)

CLI is used to clear the interrupt enable bit

No specific location in vector table
7 8
NMI (Input to 8088/86)

The NMI (Non-maskable interrupt) is a positive-edge-
sensitive external input to the 8088/86

The NMI cannot be ignored by the 8088/86 – not
maskable - cannot be ignored by software (CLI & STI)

An NMI is at INT 02 => 02*4=08 will automatically be called

Its interrupt vector is stored at addresses 08, 09, 0A,
and 0B.

In order to be recognized as a positive edge, the NMI
line must be low for two clock cycles

The external device must hold NMI high after causing
the edge.

It is useful in small scale projects, and for emergency
operations (memory parity checks)
INTA (Output of 8088/86)

INTA is the 8088’s interrupt acknowledge pin

When the 8088 recognizes an interrupt, it
sends two logic 0 pulses via INTA pin to
external devices

1stpulse: To signal the external device to get
ready to send its type number to the 8088/86.

2nd pulse: To signals the external device to put the
type number on the data lines.
 8088/86 Interrupt Sequence Interrupt Service Routines (ISR)

When an interrupt occur, it

An Interrupt Service Routine is simply an assembly

Completes execution of the current instruction
language program that handles the device requesting

Pushes the flag register onto the stack an interrupt.

Clears the interrupt enable bit

An interrupt service routine is terminated by an IRET

Pushes the CS of the next instruction onto the stack instruction that

Pushes the IP of the next instruction onto the stack
pops the CS of the next instruction from the stack

Reads the interrupt “type” from the data bus
pops the IP of the next instruction from the stack

Does a “Jump Indirect” to the address stored at
pops the flag register from the stack
type*4, type*4 + 1 IP of interrupt service routine
type*4 + 2, type*4 + 3 CS of interrupt service routine Q: What function must the interrupt service routine perform?
e.g. INT 05 – Physical address = 00014H,
Logical address = 0000:0014 (CS:IP) A: To make the INTR line to go low!
Note: this implies that the lowest 1K (256x4) of memory is
reserved to hold the interrupt vector table.
9 10

E.g.
Intel has embedded "INT 02" into the 80x86
Multiple Interrupts
microprocessor to be used only for NMI.
Whenever the NMI pin is activated, the CPU will go to memory location 00008


to get the address (CS:IP) of the interrupt service routine (ISR) associated with
A PC processor can receive interrupt requests from
NMI. more than one source

Memory locations 00008, 00009, 0000A, and 0000B contain the 4 bytes of CS:IP
System has to resolve two things:
of the ISR belonging to NMI.

In contrast, this is not the case for the other hardware pin, INTR. There is no
Identify what device requested the interrupt
specific location in the vector table assigned to INTR.
Prioritise Interrupts when two requests happen at the same

The reason is that INTR is used to expand the number of hardware interrupts time.
and should be allowed to use any "INT nn" which has not been previously
assigned.

The 8259 programmable interrupt controller (PIC) chips can be connected to
INTR to expand the number of hardware interrupts up to 64.

In the case of the IBM PC, one Intel 8259 PIC chip is used to add a total of 8
hardware interrupts to the microprocessor.

IBM PC/AT, 80286, 80386, 80486, and Intel Pentium computers use two 8259
chips to allow up to 16 hardware interrupts.

11 12
 Interrupt priorities
Either s/w or
An interrupt service routine can itself be interrupted
h/w interrupt
only by a higher priority interrupt
Interrupt
Priorities (from highest to lowest)
Vector
Reset

Internal interrupts and exceptions
Table
Software interrupts

Non-maskable interrupt

External hardware interrupts

For external hardware interrupts,
the higher the type number, the lower the priority

From the book The 80x86 IBM PC by Muhammad Ali

13 14
Mazidi and Janice Gilispie pg. 412

Interrupt types PC/AT Interrupt Priorities

Priority Use of PC/AT Interrupt
Highest IRQ0 Timer 0

Type 0 Divide Error IRQ1 Keyboard
IRQ2 From slave 8259

Type 1 Single step IRQ8 Real time clock
IRQ9 *
IRQ10

Type 2 NMI IRQ11
IRQ12

Type 3 Breakpoint IRQ13 C0-processor
IRQ14 Hard disk controller

Type 4 Overflow IRQ15

Type 510 - 3110 Reserved (internal IRQ3 COM2 port

IRQ4 COM1 port
software and BIOS) IRQ5 LPT2
IRQ6 Floppydisk controller

Type 3210 - 25510 (20H-FFH) User Lowest IRQ7 LPT1
* IRQ9 interrupt is redirected to IRQ2 vector
available 15 16
 PC/AT Interrupt Priorities Intel H/W Interrupt

From the book The 80x86 IBM PC by Muhammad Ali From the book The 80x86 IBM PC by Muhammad Ali
17 18
Mazidi and Janice Gilispie pg. 434 Mazidi and Janice Gilispie pg. 436

Timing

The INTR pin must be externally decoded to select a vector.

Any vector is possible, but the interrupt vectors between 20H and
FFH are usually used (Intel reserves vectors between 00H and 1FH).

INTA’ is an output of the microprocessor to signal the external
decoder to place the interrupt number on data bus connections D7-
D0.

The INTR pin is set by an external device (8259A) and cleared in
the Interrupt Service Routine.

The input is automatically disabled by the microprocessor once it is
recognized and re-enabled by IRET instruction.

Timing diagram of the handshake.
E.g.

An interrupting device interrupts the microprocessor each time the
interrupt request input has a transition from 0 to 1.

74LS244 creates the interrupt type number 60H as a response to
INTA.

Assume:

CS=DS=1000H

SS=4000H

Main program offset is 200H

Count offset is 100H

Interrupt-service routine code segment is 2000H:0000H

Interrupt-service routine code offset is 1000H

Stack has an offset of 500H to the current stack segment

Sketch a circuit schematic which includes a 8088 processor, a
74LS74 Flip-flop and a & a 74LS244 Buffer.

Write a main program and a service routine to count the number of
positive interrupt transitions.

From the book Intel Microprocessor Barry. B. Brey 19 20

pg. 473
 E.g. (cont’)

Interrupts the
microprocessor each time
Active-High the interrupt request
Level-Sensitive signal has a transition
from 0 to 1.
E.g.
The corresponding
interrupt number (cont’)
generated by the
hardware in response to
INTA is 60H

From the book Intel Microprocessor Barry. B. Brey 21 From the book Intel Microprocessor Barry. B. Brey 22
pg. 474 pg. 473

E.g. (cont’) Interrupt Vector Generation

8088 /
8086

1000H

Note: Use of DIP switches

provide some flexibility

From the book Intel Microprocessor Barry. B. Brey 23 From the book Intel Microprocessor Barry. B. Brey 24
pg. 475 pg. 474
 Interrupt Vector Generation: More than 1 IRQ
Note that if more than one IRQ
goes low,
• An interrupt priority needs to be
defined
• A unique interrupt vector is
generated
Relation between Interrupt and Flag Register

Among bits D0 to D15 of the flag register, there are two bits that are
associated with the interrupt:

D9, or IF (interrupt enable flag), D8, or TF (trap or single-step flag).

IF: The interrupt flag is used to mask (ignore) any hardware interrupt
that may come in from the INTR pin.

If IF = 0, all hardware interrupt requests through INTR are ignored.

This has no effect on interrupts coming from the NMI pin or "INT nn"
instructions.

The instruction CLI (clear interrupt flag) will make IF = 0.

To allow interrupt requests through the INTR pin, this flag must be set to
one (IF = 1).

The STI (set interrupt flag) instruction can be used to set IF to 1.

The trap flag (TF) is explained in following slides when "INT 01", the
single-step interrupt, is discussed.

From the book Intel Microprocessor Barry. B. Brey 25 26

pg. 473

Predefined Functions INT00

Exception interrupts.

Invoked by the microprocessor whenever there are conditions
(exceptions) that the CPU is unable to handle.

One such situation is an attempt to divide a number by zero. Since

"INT 00" (divide error) the result of dividing a number by zero is undefined, and the CPU
has no way of handling such a result, it automatically invokes the
divide error exception interrupt.

"INT 01" (single step)
There are many more exception-handling interrupts in 80286, 80386,
80486, and Pentium CPUs

"INT 03" (breakpoint)
In the IBM PC and compatibles, the service subroutine for this
interrupt is responsible for displaying the message "DIVIDE

"INT 04" (signed number overflow). ERROR" on the screen if a program such as the following are
executed
MOV AL,92 ;AL=92 MOV AX,0FFFFH ;AX=FFFFH
SUB CL,CL ;CL=0 MOV BL,2 ;BL=2
DIV CL ;92/0=undefined result DIV BL

INT 0 is also invoked if the quotient is too large to fit into the

65535/2 =32767 larger than 255 .maximum capacity of AL
27 28
 INT 01 Control Flags - Revision

In executing a sequence of instructions, there is often a need to examine
the contents of the CPU's registers and system memory. FlagsH FlagsL

This is often done by executing the program one instruction at a time 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
and then inspecting registers and memory. X X X X OF DF IF TF SF ZF X AF X PF X CF

This is commonly referred to as single-stepping, or performing a trace.

Intel has designated INT 01 specifically for implementation of single-
stepping. CF Carry Flag high-order bit carry or borrow

To single-step, the Trap Flag (TF), D8 of the flag register, must be set to PF Parity Flag low-order 8 bits contain even number of 1’s
1.

Then after execution of each instruction, the 8086/88 automatically AF Auxiliary Carry low-order 4 bits carry or borrow of AL
jumps to physical location 00004 to fetch the 4 bytes for CS:IP of the ZF Zero Flag result is zero
interrupt service routine, whose job is, among other things, to dump the
registers onto the screen. SF Sign Flag equal to high-order bit

Resetting the Trap Flag
TF Single-step Flag if set, single-step interrupt occurs
PUSHF PUSHF control IF Interrupt-enable if set, maskable interrupts enabled
POP AX OR MOV BP,SP
AND AX,1111111011111111B AND [BP]+0,1111111011111111B
DF Direction Flag if set, auto-decrement for string instructions
PUSH AX POPF OF Overflow Flag signed result too large for destination
POPF 29 30

INT 02 (NMI) INT 03 (Breakpoint)

An active-high input. Intel has set aside INT 02
for the NMI interrupt.

Whenever the NMI pin of the 80x86 is activated
by a high (5 V) signal, the CPU jumps to
physical memory location 00008 to fetch the
CS:IP of the interrupt service routine associated
with NMI.

To allow implementation of breakpoints in
software engineering, Intel has set aside INT 03
solely for that purpose.

Whereas in single-step mode, one can inspect
the CPU and system memory after the execution
of each instruction, a breakpoint is used to
examine the CPU and memory after the
execution of a group of instructions.

In recent years, some very powerful software
debuggers have been written using INT 01 and
INT 03.

31 32
 INT 04 (Signed Number Overflow) PIC – 8259 (Programmable Interrupt Controller)

Invoked by a signed number overflow condition.

There is an instruction associated with this, INTO (Interrupt On
The 8259A PIC provides 8
Overflow).
priority-encoded interrupts to

If the instruction INTO is placed after a signed number arithmetic or
logic operation such as IMUL or ADD, the CPU will activate INT 04 if the CPU.
OF = 1.

By default IR0 is assigned

In cases where OF = 0, the INTO instruction is not executed but is
bypassed and acts as a NOP (no operation) instruction. the highest priority and IR7
E.g. MOV AL,DATA1
the lowest.
MOV BL,DATA2
D0 - D7 are connected to
ADD AL,BL
INTO system data bus to receive
commands from the CPU.
Assume DATA1 =+64 =0100 0000, DATA2 =+64 =0100 0000.
The INTO instruction will be executed and the 8086/88 will jump to physical
location 00010H, the memory location associated with INT 04.
33 34

8259 Block Diagram

Pins Layout

WR’
Connects to a write strobe signal (one of 8 for the Pentium).

RD’
Connects to the IORC signal.

INT
Connects to the INTR pin on the microprocessor.

INTA’
Connects to the INTA pin on the microprocessor.

A0
Selects different command words in the 8259A.

CS’
Chip select - enables the 8259A for programming and control.

SP’/EN’ (slave programming/enable)
Slave Program (1 for master, 0 for slave)/Enable Buffer (controls the data bus
transceivers when in buffered mode).
• IRR keeps track of which interrupt inputs are making requests.

CAS2-CAS0
Used as outputs from the master to the slaves in cascaded systems. • Priority resolver selects the highest-priority interrupt.
To use the 8259 in slave mode, the chip must be programmed and CAS0 to • The ISR indicates which interrupts are being serviced.
CAS2 are ignored.
• Individual interrupts may be disabled by data written to the
Interrupt Mask Register (IMR).
35 36
From the 8259 datasheet
 8259 Registers 8259A interrupt-handling process

IRR - Interrupt Request Register,
maintains a bit vector indicating which IRQ
hardware events are awaiting service.
Highest level interrupt is reset when the
CPU acknowledges interrupt.

ISR – In-Service Register, tracks IRQ line
currently being serviced. Updated by EOI
command.

IMR - Interrupt Mask Register

37 From the 8259 datasheet 38

8259A Programming Level sensitive and Edge triggered

8259A uses two I/O port addresses, both of which may
receive command words from the CPU.

Initialization Command Words

Defining the basic operation before the device starts working.

There are 4 initialization command words: ICW1, ICW2, ICW3
and ICW4.

Once the 8259A receives all ICWs required, it is ready to process
interrupts.

The exact way each interrupt is handled is programmed
with three Operation Command Words, OCW1, OCW2
and OCW3.

The registers IRR, ISR, IMR are readable so that the
status of the 8259A is made known to other devices
including the CPU.

Level – logic 1 is the active level of the IR inputs

The request for service must be removed before the service
routine runs to completion, else the interrupt will be
requested a second time and the service routine initiated
again.

If the input returns to logic 0 before it is acknowledged by the
MPU, the request for service will be missed.

Edge – active on the transition from the logic 0 to 1.

If the request at the IR input is removed before the MPU
acknowledges service of the interrupt, its request is kept
latched internal to the 8259 until it can be serviced.

39 40
 8259A I/O Pins Connecting 8259A to 8086/88

D0-7
IR0
INTR
Each line being 8086/ 8259
connected to PIC
an 8088 INTA*
interrupt NMI IR7
requesting I/O

From the book The 80x86 IBM PC by Muhammad Ali

41 42
Mazidi and Janice Gilispie pg. 421

ICW1
E.g

The Initialization Command Words (ICWs) are programmed
before the 8259A is able to function in the system and dictate

Find the address for ICW1 - ICW4 if chip the basic operation of the 8259A.
How can the 8259 differentiate between ICW2, ICW3, and
select is activated by A7 - Al = 0010011.

ICW4 when they are sent to the same address?
A7 A6 A5 A4 A3 A2 A1 A0
When *ICW1.D0 (the LSB of ICW1) = 1, ICW4 will be referred to.

When *ICW1.D1 = 1, the system is configured in single mode.
0 0 1 0 0 1 1 0 ICW3 would be excluded in the initialization sequence.
* Refer to slides 45 and 46
0 0 1 0 0 1 1 1
The initialization sequence must always start with ICW1,
followed by ICW2, and finally the rests, if needed.
Solution:

Writing ICW1 to 8259 clears…
The above shows
ISR and IMR
• 26H to be the port for ICW1 and
Special Masked Mode in OCW3
• 27H to be the port for ICW2, ICW3, ICW4.
IRR in OCW3

EOI in OCW2
From the book The 80x86 IBM PC by Muhammad Ali
43 44
Mazidi and Janice Gilispie pg. 422
 ICW1

Initialization flow
chart

From 8259 datasheet From the book The 80x86 IBM PC by Muhammad Ali
45 46
Mazidi and Janice Gilispie pg. 423

E.g.

What value should be written into ICW1, in order to configure the
8259 so that ICW4 is needed in the initialization sequence, the
system is going to use multiple 8259 and its inputs are to be level
sensitive? Assume that all unused bits are to be logic 0.
Since ICW4 is to be initialized, D0=1.
For cascaded mode , D1=0.
And for level sensitive inputs, D3=1.
D4=1
Bits D2,D5 to D7 are in Don’t Care states => D2=D5=D6=D7=0
ICW2

It is the function of ICW2 to assign interrupt numbers to
IR0-IR7.

The lower three bits, D0, D1, and D2, vary from 000 to
111.

Along with D3 -D7 (T3 through T7), they form the 8-bit INT type
number assigned to the corresponding IR0 through IR7.

That means that D3 - D7 can only be programmed according to the
assignment of the INT type

While the lower bits D0 to D2 being provided by the 8259, depending on
which of IR0 to IR7 is activated.

So the command word will be = 00011001

From the book The 8088 and 8086 microprocesssors,

47 48
walter A.Triebel, Avtar Singh pg. 600
 ICW2 & ICW3 NOT
ADDRESS
LINES IN µP
E.g.

What should be programmed into register ICW2
if the type numbers output on the bus by the
device are to range F016 through F716?

To set the 8255 µp so that type numbers are in the range F016 to F716…
The device code bits must be D7 D6D5D4D3 = 111102
The D2D1D0 are in don’t care states and all can be 0s
1
Command word D7 D6D5D4D3 D2D1D0 = 11110000 = F016
0

From the book The 80x86 IBM PC by Muhammad Ali From the book The 8088 and 8086 microprocesssors,
49 50
Mazidi and Janice Gilispie pg. 4224 walter A.Triebel, Avtar Singh pg. 601

ICW3 ICW3 (Cascaded Mode)

ICW3 is used only when two or more 8259s
are cascaded.

A single 8259 can be connected to 8 slave
8259s, thereby providing up to 64 hardware
interrupts.

In cascade mode, there are separate ICW3
words for the master and the slave.

For the master 8259, the ICW3 indicates which IR
has a slave connected to it.

For the slave 8259, the ICW3 indicates which IR of
the master it is connected to.
51 52

E.g.

Assume that a master PIC is to be configured so that its IR0 to
IR3 inputs are to accept inputs directly from external devices,
but IR4 through IR7 are to be supplied by the INT outputs of
slaves. What code should be used for initialization command
word ICW3?
For IR0 to IR3 to be configures to allow direct inputs from external devices,
bits D0 to D3 of ICW3 must be logic 0:
ICW4 (I)

D0 indicates the processor mode (PM), the choice of
microprocessor.

D0 equals 1 for the 8088/86 and 0 for the 8080/8085.

When D1, AEOI (automatic end of interrupt), =1 it eliminates the
need for an EOI instruction to be present before the IRET (interrupt
return) instruction in the interrupt service routine.

When D1 = 0 , the EOI must be issued using OCW2 (operation
command word) to the 8259. AEOI is preferred as this reduces the
length of the interrupt service routines.

In other words, if D1 = 0, the last three instructions of the interrupt
service routine for IR0 - IR7 must be issuing the EOI followed by IRET

The other IR inputs of the master are to be supplied by INT outputs of slaves.
Therefore their control bits must be all logic 1:
Command word = 11110000

From the book The 8088 and 8086 microprocesssors,

53 54
walter A.Triebel, Avtar Singh pg. 600

ICW4 (II)

D2 (M/S) and D3 (BUF) are for systems where data
buses are buffered with the use of bidirectional ICW4
transceivers.

The 8259 can work either in buffered (D3=1) or non-
buffered (D3=0) mode.

In buffered mode, SP’/EN’ line is configured as EN’

EN’ is a controls output that can be used to control the
direction of data transfer through the bus receiver.

Logic 0 when data transferred from the 8259 to the MPU.

In non-buffered mode, the SP’/EN’ is configured to
work as the master/slave mode select input.

SP’=1 for master mode and SP’=0 for slave mode

D4 is for SFNM (special fully nested mode).

Used only in cascaded mode and enabled (D4 =1)only for the
Master 8259;

Otherwise, it is 0
From the book The 80x86 IBM PC by Muhammad Ali
55 56
Mazidi and Janice Gilispie pg. 424
 Solution:
E.g. (a) From Figure, we get the following for each of the ICWs:
ICW1
• D0=1 ICW4 needed
• Dl =1 single
(a) Find the ICWs of the 8259 if it is used with an • D2=0 this is always zero for 80x86 CPUs
• D3=1 level triggering
8088/86 CPU, single, level triggering IRs, and; IR0 is • D4=1 required by the ICWI itself
• D5=D6=D7=0 this is always zero for 80x86 CPUs
assigned "INT50H". The 8259 is in slave buffered This gives ICW1 = 00011011= 1BH.
mode with normal EOI. ICW2
• Always equate ICW2 to the INT # assigned to IR0;
(b) Show the program to initialize the 8259 using the • ICW2 = 01010000 = 50H.
• Notice that "INT nn", assigned to IR0, can decide only bits D7 - D3 (T7 - T3) of ICW2.
port addresses in previous example in slide 43 • This means that the "INT nn" assigned to IR0 must have the lower three bits = 000;
(c) Find the addresses associated with IR0, IR1, and therefore, it can take either values of X0H or X8H, where X is a hex number.
• For example "INT 45H" cannot be assigned to IR0.
IR2 in the interrupt vector table. No ICW3 is needed since it is single and not cascaded.
• ICW4
• Note: This example is not PC-compatible and is • D0=1 8088/86
given only for exercise. • D1=0 normal (we must issue EOI before IRET instruction)
• D2 =0;D3=1 slave buffered mode
• D4=0 not nested
• D5 =D6 =D7 =0 required by the ICW4
ICW4 =00001001 =09H.
From the book The 80x86 IBM PC by Muhammad Ali
57 58
Mazidi and Janice Gilispie pg. 425

Solution: Solution Cont. - Hardware Interrupt

MOV AL,1BH ;ICW1
OUT 26H,AL ;TO PORT 26H
MOV AL,50H ;ICW2
OUT 27H,AL ;TO PORT 27H
MOV AL,09 ;ICW4
OUT 27H,AL ;TO PORT 27H

(c) If "INT 50H" is assigned to IR0, then IR1 and IR2 have "INT 51H"
and "INT 52", respectively, and so on.
The vector memory locations associated with the IRs are as follows;
Vector Location
IRQ (Pin of 8259) INT Logical Address Physical Address
IR0 50H 0000:0140H-0143 00140H-00143
IR1 51H 0000:0144H-0147 00144H-00147
IR2 52H 0000:0148H-014B 00148H-0014B

59 60
 OCW (Operation Command Word) E.g.

After ICW1, ICW2, and ICW4 have been issued in
sequence to the 8259 chip in order to initialize it, the
Find the port addresses for the OCWs
8088/86 is ready to receive hardware interrupts through of the 8259 in eg. in slide 43
the 8259's IR0 - IR7 pins.

After the process of initialization, the OCW can be sent to
mask any of IR0 - IR7, or change the priority assigned to Solution:
each IR. A7 A6 A5 A4 A3 A2 Al A0
0 0 1 0 0 1 1 0 26H Port for OCW2 and OCW3

There are three operation command words: OCW1, OCW2, 0 0 1 1 0 1 1 1 27H Port for OCW1
and OCW3.

With the help of OCWs, a programmer can dynamically
change the priority associated with each of IR0 - IR7, or There are three registers inside the 8259.
mask any of them. Examples in subsequent slides show • ISR (in-service register),
how the OCWs are sent to the 8259. • IRR (interrupt request register),
• IMR (interrupt mask register).
* Refer to slide 37
61 62

OCW1
OCW1
OCW1 is used to mask any of IR0 - IR7.

Logic 1 is for masking (disabling) and 0 is for unmasking
(enabling).

For example, 11111000 is the OCW1 to enable (unmask) IR0, IR1,
IR2, and disable/mask the rest (IR3 - IR7).

When this byte is written to the 8259 (by making A0 =1
and CS =low), it goes into the internal register called IMR
(Interrupt Mask Register).

To see which IRs are enabled and which ones are
disabled.

Read OCW1, which is the contents of IMR. For example, to read
OCW1 using the port addresses in slide 64, code "IN AL,27H".

By examining the contents of AL, one can find out which IRs are
enabled and which ones are disable

The MPU address to access OCW1 is an odd address

From the book The 80x86 IBM PC by Muhammad Ali

63 64
Mazidi and Janice Gilispie pg. 428
 E.g. OCW2 (I)

Write the code to unmask (enable) IR0 -
OCW2 command word is used to assign a specific
IR7. Use the ports in slide 62 priority to the IRs (Interrupt Requests).

Three methods for assigning priority to IR0 - IR7:
Solution:
Fully Nested Mode
To enable IR0 - IR7, use bits M0-M7 in OCW1
Assigns the highest priority to IR0 and the lowest to IR7 by
OCW 1 =0000 0000 =00H default when the 8259 is initialized.

The 8259 can be programmed to change the default mode to
MOV AL,00 ;OCW1 to unmask IR0-IR7
assign the highest priority to any IR. For example, the
OUT 27,AL ;issue OCW1 to IMR
following shows the priority sequence where OCW2 is in
Fully Nested Mode and IR6 has been assigned the highest
priority. IR7 will have the next priority, and so on.

65 66

OCW2 (II) E.G (Automatic Rotation Mode)

Three methods for assigning priority to IR0 - IR7: (cont.)

Automatic Rotation Mode

In this scheme, when an IR has been served it will take the
lowest priority and will not be served until every other request
has had a chance.

This prevents interrupt starvation, where one device
monopolizes the interrupt service.

Specific Rotation Mode

In this scheme, the 8259 can be programmed to make the
rotation follow a specific sequence rather than IR0 to 1R7,
which is the case for the automatic rotation mode.

The only difference between this mode and automatic
rotation is the sequence of rotation.

From 8259 datasheet

67 68
 OCW2 (III) OCW2 - EOI
D2 – D0 are used to assign a new priority
scheme to an IR other than the default.

Non-specific EOI - A command sent by the

Rotation
Specific Level interrupt service procedure to signal the EOI.
End of Interrupt

The 8259 automatically determines which interrupt
level was active and resets the correct bit of the In-
Service Register.

Specific EOI – A command that allows a specific
interrupt request to be reset. The exact position
is determined with bits L2-L0 of OCW2

From 82C59A Datasheet – Harris Semiconductor – Mar, 1997

69 70

Circuit for E.g.

E.g
A1

Analyze the circuit in next slide and write
an appropriate main program and a
service routine that counts as decimal
number the positive edges of the clock
signal applied to IR0, input of 8259.

Use INT type number 7210 vector.

71 72
 Solution (1)

A0 is not used – don’t care – assume 0

Two I/O addresses are FF00h (A1=0) and FF02h (A1=1)

FF00h: ICW1, FF02h: ICW2, ICW3, ICW4, OCW1

Only one 8259 and interrupt input is an edge

ICW1 = 00010011b = 13h

Interrupt type 72 is used presented to IR0

ICW2 = 01001000b = 48h

ICW3 not needed

Non-buffered and auto EOI

ICW4 = 03h

For OCWs, use only OCW1 - mask all other interrupts
but IR0

OCW1 = 11111110b = FEh
Software organization Flowcharts
73 74

From the book The 80x86 IBM PC by Muhammad Ali

75 76
Mazidi and Janice Gilispie pg. 428
 Solution (2) Solution (3)

In the interrupt vector table we need to set up ;main program
the type 72 vector where located at CLI
START: MOV AX, 0
4*72=288=120h. At address 120h we need to MOV ES, AX ; ES=0
place the offset (IP) of the service routine and at MOV AX, 1000h
MOV DS, AX ; DS=1000
address 122h the code segment (CS) value of MOV AX, 0FF0h
the service routine. MOV SS, AX
MOV SP, 100h
; Stack Segment at 0FF00

; interrupt install – set up the IP and CS for the type 72 vector

In the data area we need a location to keep a MOV AX, OFFSET SRV72 ; get offset for the service routine
decimal count – 01000H MOV [ES:120h], AX ; set up the IP
MOV AX, SEG SRV72 ; get the code segment for the service routine

Stack segment 0FF00H and ends at 0FFFFH MOV [ES:122h]. AX ; set up the CS

77 78

Solution (4)
; initialization
; service routine
MOV DX, 0FF00h
SRV72: PUSH AX
MOV AL, 13h
MOV AL, [COUNT]
OUT DX, AL
INC AL
MOV DX, 0FF02h
DAA
MOV AL, 48h
MOV [COUNT], AL
OUT DX, AL
POP AX
MOV AL, 03h
IRET
OUT DX, AL
MOV AL, 0FEh
OUT DX, AL
STI
; wait for interrupt
HERE: JMP HERE

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