Direct Memory Access (DMA)

Faculty of Information and Communication Technology (FICT)

Three methods for handling I/O.

Pooling
Processor gets involved

Interrupt
8088/86
UC

Direct memory Access (DMA)

Direct Memory Access
DMA allows data to be transferred between memory

and the I/O device without processor intervention
while the data bus is occupied.

DMA is for high-speed data transfer from/to mass
H Y Lee storage peripherals, e.g. harddisk drive, magnetic
tape, CD-ROM, and sometimes video controllers.
leehy@utar.edu.my

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DMA - Advantage DMA – Advantage

For e.g., a hard disk may boasts a transfer rate of 5 M bytes
per second, i.e. 1 byte transmission every 200 ns. To make
such data transfer via the CPU is both undesirable and
unnecessary.

The basic idea of DMA is to transfer blocks of data directly
between memory and peripherals.

“Normal”transfer of one data byte takes up to 39 clock cycles.

Solution: If the disk drive circuitry could capture the
data sent by the memory, only one bus cycle would
be necessary per data transfer.
DMA

The DMA transfer requires only 5 clock cycles
instead of 39 clocks!.

Nowadays, DMA can transfer data as fast as 60 M
byte/s. For UDMA till 133 Mbyte/s

The transfer rate is limited by the speed of memory
and peripheral devices.

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 DMA Request & Acknowledgement
8086 Pins (Refresh)
MAXIMUM MINIMUM
Two signals are used to request/acknowledge for DMA
MODE MODE
transfer in microprocessor-based system :
GND 1 40 Vcc
AD14 AD15
HOLD is an input to the µp that requests a DMA action.
AD13 A16,S3
The HOLD signal is a bus request signal which asks the µp to release control
AD12 A17,S4 of the buses after the current bus cycle.
AD11 A18,S5

HLDA is an output from the µp granting the DMA action.
AD10 A19,S6
AD9 /BHE,S7

The HLDA signal is a bus grant signal which indicates that the µp has indeed
released control of its buses by placing the buses at their high-impedance
AD8 MN,/MX
states.
AD7 /RD
AD6
8086
/RQ,/GT0 HOLD

The µp responds by suspending the execution of the program
AD5 /RQ,/GT1 HLDA
AD4 /LOCK /WR
and by placing its address, data and control bus in high-
AD3 /S2 /IO,M impedance states.
AD2 /S1 DT/R
AD1 /S0 /DEN
A DMA controller temporarily borrows the address bus, data
AD0 QS0 ALE bus, and control bus from the µp and transfers the data bytes
NMI
INTR
QS1
/TEST
/INTA
directly between an I/O port and a series of memory locations.
CLK
GND 20 21
READY
RESET

The HOLD input has a higher priority than the INTR or NMI
interrupt inputs.

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DMA Idle DMA Activated

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 DMA Controller
Memory

A DMA controller interfaces with several peripherals that may request DMA.
Data 6. Memory
The controller…
places on data

decides the priority of simultaneous DMA requests
bus

communicates with the peripheral and the CPU, and

provides memory addresses for data transfer
7.Interface latches data
The DMAC takes control of the address, data, and control buses from the
CPU
CPU.
Interface
HOLD I/O
It coordinates the interaction between the memory and I/O device.
HLDA
Similar to the PPI and PIT ICs, the DMAC is a programmable device
Control ultimately controlled by the CPU.
1. Interface is
2. HRQ =1 Bus ready to receive
DMA controller commonly used with 8088 is the 8237 programmable
request is made data, DMA device.
request is made
3. Bus grant is DMA – DREQ high
The 8237 is in fact a special-purpose microprocessor. Normally it appears as part of
returned the system controller chip-sets.
Interface
4. DACK=1 DMA
The 8237 is a 4-channel device. Each channel is dedicated to a specific peripheral
8. Bus request Address device places device and capable of addressing 64 K bytes section of memory.
dropped and address on the
9. Bus grant is
control returned to 5. DMA request is address bus
dropped by the acknowledged
CPU 9 10
CPU

Problem with using DMA What DMA needs to know about the

There is only one set of buses (one set of each bus: block to be transfer?
data bus, address bus, control bus) in a given
computer and no bus can serve two masters at the
Beginning Address of the block (address of
same time. first byte of data)

The buses can be used either by the main CPU 80x86
or the 8237 DMA.
The number of bytes (Count) it needs to
transfer.

Since the 80x86 has primary control over the buses, it
must give permission to DMA to use them.

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 8237A DMA Pin Layout & Block Diagram
Connect
to µp
13
8237 DMA Controller -2

DREQ is an input to DMAC coming from the peripheral device
(such as the hard disk controller)

DACK is an output signal from the DMAC going to the peripheral
device.

From the 8237 DMAC, there is only one HOLD and one HLDA
that are connected to HOLD and HLDA of the 80x86.

4-DREQ,4-DACK channels from four different devices can
request use of the system buses, DMA decides who gets control
based on the way its Priority Register has been programmed.

Every channel of the 8237 DMA must be initialized separately for:

the address of the data block .

the count (the size of the block) before it can be used.
From the book The 80x86 IBM PC by Muhammad 15
Ali Mazidi pg. 450
8237 DMA Controller -1

40-pin chip.

Four channels for transferring data,

Each must be used for one device. For example, one is
used for the floppy disk, one for the hard disk...

Only one device can use the DMA to transfer data at a
given time.

With every channel there are 2 associated signals,
DREQ (DMA request) and DACK (DMA acknowledge).
From the book The 80x86 IBM PC by Muhammad 14
Ali Mazidi pg. 450
Complete DMA Process -1

The peripheral device # will request the service of DMAC by
pulling DREQ# (DMA request) high.

The DMAC will put a high on its HRQ (hold request), signaling
the CPU through its HOLD pin that it needs to use the buses.

The CPU will finish the present bus cycle and respond to the
DMA request by putting high on its HLDA (hold acknowledge),
thus telling the 8237 DMAC that it can go ahead and use the
buses to perform its task.

DMAC will activate DACK# (DMA acknowledge), which tells the
peripheral device # that it will start to transfer the data.

HOLD must remain active high as long as DMA is performing its
task.
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 Complete DMA Process -2

DMA starts to transfer the data from memory to peripheral as
follows

DMA puts the address of the first byte of the block on the address
bus

Activates MEMR,

Reads the byte from memory into the data bus

Activates IOW to write it to the peripheral.

Then DMAC decrements the counter and increments the address
pointer

Repeats this process until the count reaches zero and the task is
finished.

After the DMAC has finished its job it will deactivate HRQ,
signaling the CPU that it can regain control over its buses.
DMA - Summary

DMA can only transfer information; unlike the CPU, it cannot decode
and execute instructions.

When the CPU receives a HOLD request from DMA, it finishes the
present bus cycle (but not necessarily the present instruction) before
it hands over control of the buses to the DMA.

This is in contrast to a hardware interrupt, in which the CPU finishes the
present instruction before it responds with INTA.

One could look at the DMA as a kind of CPU without the instruction
decoder/executer logic circuitry.

DMA needs data bus, address bus and control bus such as IOR,
IOW, MEMR, and MEMW in order to start the transfer

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DMA Programming

Initialization

Address of the first byte of the block of data that must be Accessing
transferred - Base Address.
DMAC’s

Number of bytes to be transferred - Word Count.
Word

After initialization, each channel can be enabled and Count
controlled with the use of a control word.
and

There are many modes of operation and these Address
various modes and options must be programmed
Registers
into the 8237's internal registers.

To access the 8237 registers, the 8237 provides:

4 address pins, A0 - A3,

CS pin. From the datasheet 8237 pg 10

From the book The 80x86 IBM PC by Muhammad 19 20

Ali Mazidi pg. 450
Accessing DMAC’s Command & Status Registers Eg.
Find the port addresses for the base address
and word count of each channel of the 8237 for
the following figure.

From the datasheet 8237 pg 9

21 From the book The 80x86 IBM PC by Muhammad 22
Ali Mazidi pg. 450

Answer Eg. (cont’)

Assume that channel 2 of the DMAC in Eg.

(slide 22) is to transfer a 2K (2048) byte block
of data from memory locations starting at
53400H. Program the memory address
register and count register of channel 2

Note: Answer can be obtained by referring to slide 20

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 Answer Answer – Special Notes

The port address for the channel 2 memory address register and
count register are 94H and 95H, respectively. (Refer to slide 23)

The initialization will look as follows:
The contents of the memory address and count registers
can be read in the same manner (low byte first, then
MOV AX, 3400H ;load lower 4 digits of start address high byte) to monitor these registers at any time.
OUT 94H, AL ;send out the low byte of the address
MOV AL, AH

From looking at the above program one might ask, since
the system address bus is 20 bits and the memory
OUT 94H, AL ;send out the high byte of the address address is 53400H, why does this program use 16-bit
MOV AX, 2048 ;load block size into AX addresses? This is a limitation of the 8237 DMA.
OUT 95H, AL ;send out the low byte of the count
The 8237, not only is the register holding the address of the block
MOV AL, AH 16 bits, but in addition there are only 16 address pins that carry
OUT 95H, AL ;send out the high byte of the count the addresses.

IBM PC solves this problem by using external 4 bits register to
hold the upper bits of address in 1M memory range.
Wake Up! Don’t you notice any wrong in the answer above ?!

Read for more from the book “The 80x86 IBM PC” by Muhammad Ali Mazidi
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QUIZ Answer

When a peripheral device wants to perform a DMA operation,
it makes a request for service at one of the DRQ inputs of the

Are signal lines /MEMR and /MEMW of the 82C37A.
82C37A used in the microprocessor interface?
In response to this DMA request, the DMA controller (82C37A)
switches its hold request (HRQ) output to logic 1.
NO

This signal is applied to the HOLD input of the 8088/8086.

In response to this input, the µP puts the bus signals into the

Summarize the 82C37A’s DMA high-impedance state and signals this fact to the DMA
request/acknowledgement handshake sequence. controller by switching the hold acknowledge (HLDA) output
to logic 1.

This output is applied to HLDA input of the 82C37A and
signals that the system bus is now available for use by the
DMA controller.

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