Bhagwan Mahavir University

Bhagwan Arihant Institute of Technology

VIP Road, Barthana – Vesu, Surat - 395007
DIGITAL ELECTRONICS
TOPIC : Universal Gate Design Using CMOS
Introduction The CMOS NAND Gate The CMOS NOR Gate

Universal gate design using CMOS (Complementary MOS) involves creating

logic gates using a combination of n-channel (NMOS) and p-channel (PMOS)
transistors. CMOS logic gates are widely used in digital systems due to their
low static power consumption and high input impedance. Some fundamental
CMOS logic gates include the NOT gate, NAND gate, and NOR gate.

CMOS Technology
• CMOS (Complementary Metal-Oxide-Semiconductor) is a type of digital
logic gate that uses both NMOS and PMOS transistors to implement logic
functions.
Table 1. The truth table for a two-input NAND circuit.
Figure 1. shows a CMOS two-input NAND gate. P-channel transistors Q1 and
Q2 are connected in parallel between +V and the output terminal. N-channel
transistors Q3 and Q4 are connected in series between the output terminal and
ground.
Table 2. The truth table for a two-input NOR circuit.
Figure 2. shows a CMOS two-input NOR gate. P-channel transistors Q1 and
Q2 are connected in series between +V and the output terminal. N-channel
transistors Q3 and Q4 are connected in parallel between the output and ground.

• The basic building blocks of CMOS logic gates are the inverter, NAND
gate, and NOR gate.

• The inverter is the simplest CMOS gate, consisting of a series connection of

a PMOS and an NMOS transistor. The NAND and NOR gates can be easily
realized using CMOS logic.

• The PDN (Pull-Down Network) of the AOI (And-Or-Invert) gate is

structurally similar to the PUN (Pull-Up Network) of the OAI (Or-And-
Invert) gate, and vice versa. This makes it possible to realize any logic
function using a combination of NAND and NOR gates. Figure 1. A CMOS two-input NAND gate.
Figure 2. A CMOS two-input NOR gate.
• The truth table is a mathematical model that demonstrates the relationship
between inputs A and B, with inputs being logic 1 and 0 respectively. • The truth table is confirmed when inputs A and B are logic 0, with Q1 and
Q2 being "on" and Q3 and Q4 being "off."
Advantages of CMOS • If Q3 and Q4 transistors are on and Q1 and Q2 are off, the output is a logic
• Low power consumption 0, confirming the lowest row in the truth table. If one input is a logic 1 and • The output is logic 1, confirming the first row. The output is logic 0 for the
• High noise immunity the other is 0 (Q3 and Q2), the output is a logic 1, validating the second and last row. The remaining input combinations have either Q1 and Q3 being
• High packing density third rows. "off" or Q2 and Q4 being "on“.
• Wide operating voltage range

References
1. Basic CMOS Logic Gates - Technical Articles (eepower.com)

1. CMOS Logic Gate – GeeksforGeeks

2. CMOS Gate Circuitry | Logic Gates | Electronics Textbook (allaboutcircuits.com)

Guided By: Prof. Rahul N Gonawala Students Name : 1) Ghadiyali Rutvika | 2) Patel Dhruvi | 3) Rakholiya Honey | 4) Vekariya Bhavyanshu