Electronic Circuit Design Lab Lab#04

Lab # 04
JFET Biasing
Objective:
In this lab, we will study the characteristics and applications of junction field-effect transistors
(JFETs). We will use two methods of biasing a JFET self-biasing and voltage divider biasing.

Apparatus:
• JFET (2N4416)
• Resistors
• DC power supply
• Oscilloscope
• Function Generator
• Capacitor
• Multimeter (DMM)
• Breadboard and wires

Self-Biasing:

JFET Self-Biasing Method

• The self-bias is commonly used biasing type of junction field effect transistor.
• During operation of JFET the gate-source junction remains reverse biased condition
always. For this state the VGS voltage should be negative for N-channel JFET and positive
for P channel JFET.
• It can get with the use of self-bias configuration shown in below figure

For n-channel the VGS is negative and for p-channel VGS is positive. In n-channel IS produces
voltage drop across RS and make source positive with ground.

Aleen Qureshi 1 UW-21-MTS-BSC-016

Electronic Circuit Design Lab Lab#04

VG = 0

IS = ID

VGS = VG – VS

VGS = 0-VS = -VS

VGS = -IDRS

VD = VDD - IDRS

VD = VD - VS

VD = VDD – IDRD – IDRS

VD = VDD – ID (RO + RS)

Voltage Divider Bias:

Voltage divider bias is a method of biasing a JFET using two resistors in series between the
positive terminal of the power supply and the ground. The resistors form a voltage divider that sets
the gate voltage. The advantage of voltage divider bias is that it has better stability and less
sensitivity to variations in temperature and device parameters. The disadvantage is that it requires
a separate power supply for the gate.

The voltage at gate source can be collected by voltage divider rule. The resistor is inserted with
the source terminal in series. The current of device flows through resistor and causes voltage drop.
VGS is negative when source voltage is zero.

VG = (R2/R1+R2) VDD

VGS = VG – VS

ID = VDD – VD/RD

VDS = VDD – VD (RD + RS)

Aleen Qureshi 2 UW-21-MTS-BSC-016

Electronic Circuit Design Lab Lab#04

Q-Point of Self Biased JFET:

RS=VGS/ID

The Q-point or quiescent point of a JFET is the operating point when we find ID at desired value.

Q-Point of Voltage Divider Biased JFET:

To plot the Q-point of a voltage divider biased JFET is operated when ID is zero and VGS is not
zero.

ID = 0

VS = 0

VGS = VG

VGS = 0

ID = VG – VGS/RS

ID = VGS/RS

TASK:
To implement For Self-Biased:

• Take all the required components.

• Patch all the components on the breadboard.
• VDD is applied through the drain source.
• Determine the required values using DMM.
• Find the values and theoretically and compare them.
• The circuit should according to the diagram.

Aleen Qureshi 3 UW-21-MTS-BSC-016

Electronic Circuit Design Lab Lab#04

To implement For Voltage Divider:

• Take all the required components.

• Patch them on the breadboard.
• Apply VDD and input signal.
• Check the output signal.
• Sketch the graph and determine Q-Point.

Observation:

Graph:

Aleen Qureshi 4 UW-21-MTS-BSC-016

Electronic Circuit Design Lab Lab#04

Conclusion:

Safety Precautions:
1. Make sure all equipment is properly grounded and follows proper electrostatic discharge
(ESD) precautions to prevent damage to sensitive electronic components.
2. Use proper tool handling techniques and ensure that all tools are in good condition before
use.
3. Follow all lab safety rules and procedures, including those related to handling hazardous
materials, operating equipment, and disposing of waste.
4. Keep the lab clean and organized, and ensure that all chemicals and equipment are properly
labeled and stored.
5. Always disconnect power from equipment before making any modifications or repairs.

Aleen Qureshi 5 UW-21-MTS-BSC-016