CS102304

rd
B.Tech.-3 Semester Examination Nov-Dec 2021
Branch: [CSE, CSE (DS), CSE (AI), CSE (AIML), CSE (IOT), CSE (BDA), CSE (GT), CSE
(IOT&CSBT)]
Course: Digital Electronics and Logic Design
Maximum Marks: 100
Time Allowed: 3 Hours Minimum Marks: 35

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Note: (i) Attempt all questions. Part (a) from each question is compulsory and carries 4 marks,attempt any two parts from part (b),
(c) and (d) carrying 8 marks each.
CO1:- Use digital electronics in the present contemporary world.
CO2:- Design various combinational digital circuits using logic gates.
CO3:- Do the analysis and design procedures for synchronous and asynchronous sequential circuits.
CO4:- Use the semiconductor memories and related technology.
CO5:- Use electronic circuits involved in the design of logic gates.

Q. No Questions Marks CO BL PI
Q.1 a) i) Convert (10.625)10 in binary
ii) Convert (736)8 in binary
iii) Obtain decimal equivalent of hexadecimal number 1.2.1
4 CO1 L4
(3A.2F)16
iv) Convert Gray code number 10110101 to binary code
number.
b) A seven bit Hamming code as received is 1110101.
Assuming that even parity has been used, check if it 8 CO1 L1 1.3.1
correct, if not find the correct code.
c) Reduce the following function using K-map and also draw
NAND circuit logic diagram. F(A,B,C,D) = Σ m (1,3,7,11,15) 8 CO1 L2 1.2.1
+ d (0,2,5).
d) Simplify the following Boolean expression using Quine
8 CO1 L2 1.4.1
McCluskey method F(A,B,C,D)= Σm (0,1,3,7,8,9,11,15)
Q.2 a) Design a 4-bit BCD to Gray code converter 4 CO2 L2 2.2.1

b) What is meant by full subtractor? Draw the logic diagram

for a full subtractor. Also construct a full subtractor using 8 CO2 L2 1.2.1
half subtractor.
c) Implement the boolean function F(A,B,C,D) =
8 CO2 L2 1.3.1
∑m(1,3,4,11,12,13,14,15) using 8:1 multiplexer.
d) Draw a circuit for adding BCD numbers and discuss its
8 CO2 L2 1.2.1
working.
Q.3 a) Explain synchronous and asynchronous counter. 4 CO3 L4 1.4.1

b) Draw a neat diagram of Master Slave J-K Flip Flop.

Explain how race around condition is avoided using 8 CO3 L2 1.2.1
Master Slave J-K Flip Flop.
c) What is a universal shift register? 8 CO3 L2 1.2.1

d) Differentiate between Meelay model and Moore model

8 CO3 L2 2.2.1
sequential circuit giving block diagram.

Q.4 a) Difference between synchronous and asynchronous

4 CO4 L2 1.3.1
sequential circuits.
b) Derive the transition table and flow table for the
Asynchronous Sequential Circuit shown in the figure. 8 CO4 L2 1.3.1
Also derive the state table for the given circuit.
 c) Find a critical race free state assignment for the reduced
flow table show in Figure.

8 CO4 L2 1.2.1

d) What is a Hazard? What are the types of hazards? Find a

circuit that has no hazard for the following function 8 CO4 L2 1.3.1
F (A,B,C,D)=∑(0,2,6,7,8,10,12).
Q.5 a) Define Propagation Delay, Noise Margin and fan out. 4 CO5 L2 1.2.1

b) Design NAND, NOR gate using CMOS logic. 8 CO5 L2 1.4.1

c) A combinational circuit is defined by the function:

F1 (A,B,C)=∑(0,1,2,4)
8 CO5 L2 2.2.1
F2 (A,B,C)=∑(0,5,6,7)
Implement the circuit with a PLA.
d) With proper diagram, discuss the operation of TTL NAND
8 CO5 L2 1.2.1
gate with Totem pole output.
CO- Course Outcomes, BL– Bloom’s Taxonomy, PI– Performance Indicator
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