Crystal Structure and Defects Microstructure of Materials

¾ Spatial arrangements of atoms play an important role in

• The goal of this lecture is to review some determining the electrical properties.
fundamental concepts from Materials ¾ Solids are classified into three broad classifications:
Science necessary to understand and to talk ¾ Amorphous: no recognizable long range order
¾ Crystalline: Entire solid is made up of atoms in an orderly array
about the properties of the materials we are
¾ Polycrystalline: Completely ordered in segments
processing.
– Microstructure
– Crystal Structure and Crystallography
– Crystal Defects

Amorphous Polycrystalline Crystalline

Microstructure of Materials Crystal Structure

¾ Crystal structures are regular 3-dimensional patterns of atoms in space
¾ The regularity with which atoms are packed in solids arises from geometrical
conditions (i.e., bond angles and lengths) which are imposed by directional
bonding and close packing
¾ Most stable arrangement will be the one that
1) Minimizes energy/volume
2) Preserves electrical neutrality
3) Satisfies directionality and discreteness of the covalent bonds
4) Minimizes ion-ion repulsion
5) Packs atoms as closely as possible consistent with (1)-(5)

Amorphous Polycrystalline Crystalline

 Description of Crystal Structure: Lattice
¾ A lattice is an infinite three dimensional array of points in
which every point has surroundings identical with that of
every other point. These are called lattice points.
¾ Example: A 2-D square space lattice:
Bravais Space Lattices
¾ The most general (“lowest symmetry”) 2-D lattice is the “oblique lattice”
in 2-D.
¾ a1 and a2 are called lattice translation vectors. Translation by integer
multiple of a1 and a2 takes one from one lattice point to another
¾ There is an infinite number of lattices because there are no restrictions on
the length or the angle (α) between the lattice translation vectors.

r ¾ But restrictions on the number of lattices are placed if relations between

Set of all points r ' defined by lengths of a1 and a2 and α are specified
r r r r r
r'= r + u a + u a + u a
1 1 2 2 3 3

where u1, u2, u3 are integers

2-D Oblique lattice a1
a1 α
a2
a2

Bravais Lattices in 2-D 14 Bravais Space Lattices in 3-D

¾ 4 restrictions that can be imposed on a1,a2 and α gives rise to
total of 5 Bravais lattices in 2-D (1 general, 4 special lattices).

http://www.chem.ox.ac.uk/icl/heyes/structure_of_solids/Lecture1/Bravais.gif
 Specifying Crystal Structure Unit Cell
¾ A motif or a basis is a specific arrangement of atoms which ¾ Moving the basis from lattice point to lattice point
belong to a lattice point. generates a crystal structure.
¾ Crystal structure can be completely described by specification ¾ A unit cell is a repeating unit of the space lattice which can
of a lattice and basis be used to reproduce the entire cell. Lattice + basis
specifies a unit cell.
Lattice + Basis = Crystal Structure ¾ Primitive unit cell is one that has only one atom per unit
cell and the lattice vectors defining the cell are said to be
a primitive lattice vectors.
a
¾ We often use primitive translation vectors and unit cells to
define the crystal structure but nonprimitive axes are also
used when they have simpler relation to the symmetry of
Lattice is square lattice
the structure.
Basis is large red atom at (0,0) and small blue atom at (½ a, ½ a)

Simple 3-D Unit Cells: Simple cubic (SC) Simple 3-D Unit Cells: Body centered cubic (BCC)

¾ 2 lattice points per cell

¾ 1 lattice points per cell
¾ Po crystal structure = SC lattice + 1 atom at lattice sites ¾ Mo, W crystal structure = BCC lattice + 1 atom at lattice sites
¾ 8 nearest neighbors at 0.87 a
¾ 6 nearest neighbors at a (a = lattice parameter)

http://cst-www.nrl.navy.mil/lattice/ http://www.chem.ox.ac.uk/icl/heyes/structure_of_solids/Lecture1/Lec1.html
BCC Primitive Unit Cell FCC Unit Cell and FCC Crystal Structure

¾ 4 lattice points per cell

¾ Cu, Au, Ag, Pt, etc.
crystal structure =
FCC lattice + 1 atom at
lattice sites
¾ 12 nearest neighbors;
close packed structure

http://cst-www.nrl.navy.mil/lattice/
http://www.webelements.com/webelements/elements/text/Pt/xtal-vr.html

FCC Primitive Unit Cell The Diamond Lattice

¾ The crystal structure of group IV semiconductors (Si and Ge) is
described by unit cell known as the diamond lattice unit cell
¾ Diamond structure is an FCC Bravais lattice with a basis that has two
identical (e.g., Si, Ge, or C) atoms at each and of the vector
(¼,¼,¼)a, where a is the lattice constant (different for Si, Ge and C).
 Diamond Structure The Diamond Lattice
¾ A less formal way of visualizing the diamond structure is to think of
it in terms of two FCC lattices interpenetrating each other.
¾ One FCC lattice is shifted with respect to the other along the body
diagonal by ¼ of the body diagonal length

The Zincblende Structure The Zincblende Structure

¾ GaAs has the Zinc blende structure
¾ An FCC Bravais lattice with a basis that has two different atoms one
at the each end of the vector (¼,¼,¼)a (e.g., Ga on one end and As on
the other end)
¾ Zincblende structure is the same as the diamond structure (two FCC
lattices interpenetrating each other with one FCC lattice shifted with
respect to the other along the body diagonal by ¼ of the body
diagonal length) but the two FCC lattices are made of different atoms
 Miller Indices Miller Indices Examples
¾ Miller indices help specify atomic planes and orientations in a crystal
¾ To obtain Miller indices of any plane of atoms do the following.
1) Set up coordinate axes along the edges of the unit cell and note
where the plane in question intercepts the axes (x,y,z).
2) Take the reciprocal of the intercepts.
3) Using appropriate multiplier convert the reciprocals obtained to
smallest set of whole numbers.
4) By convention these numbers (h,k,l) are enclosed in () to identify
a plane. If any of the numbers have a negative sign a bar is
located at the top of that index.
¾ Equivalent planes (family of planes that contain identical atomic ¾ Plane intercepts x,y,z axes at 3a1, 2a2, and 2a3 repectively
arrangements) are referenced by enclosing one of the members of the ¾ Reciprocals are 1/3, 1/2, and 1/2
group in {}. e.g., in diamond structure ¾ To get smallest integers having this ratio multiply by common
{001}=(100), (010), (001), ( 1 00), (0 1 0), (00 1 ) denominator 6. Thus this is the (233) plane

Miller Indices Examples Crystallographic Directions

¾ Miller indices enclosed within [ ] are used to designate

directions within a crystal
¾ Note also that the Miller indices also give the direction of
the normal vector of the plane they describe
¾ Miller indices enclosed within < > are used to designate
equivalent (family of) directions.
e.g., in simple cubic lattice [100] is the x-axis direction,
<100> describes all directions parallel to the x, y and z
axis.
 Crystal Defects Point Defects
¾ Vacancy: absence of an atom in a lattice point where there is
¾ Defects are imperfections which cause disruption in
suppose to be an atom. Formed when atoms are removed from
what otherwise would be a perfect lattice.
their lattice positions (typically to the surface) as a result of
¾ Defects are classified based on their dimensionality thermal fluctuations. AKA Schottky defects.
¾ Point defects (0-D) ¾ Interstitial: Atom located in a “void” (I.e., a position that is not
¾ Line defects (1-D) part of the lattice or basis) within the crystal structure.
¾ Surface Imperfections (2-D) ¾ Frenkel Defect: A vacancy-interstitial pair.
¾ Volume defects (3-D) ¾ Substitutional Impurity: Impurity atoms (an atom that does not
belong to the basis) that take up the lattice positions that are
ordinarily occupied by the atoms that make up the crystal.
¾ Interstitial Impurity: Impurity atoms that are present in the
interstitial sites.

Point Defects Point Defects

 Line Defects Line Defects
¾ Dislocations: Boundary between two regions of a surface Edge Dislocation Screw Dislocation
which are perfect themselves but are out of registry with each
other. The resulting lattice distortion is centered along a line.
¾ Burgers Vector, b: A vector by which the lattice on one side
of an internal surface containing the dislocation line is
displace relative to the lattice on the other side.
¾ There are two special cases of dislocations
¾ Edge Dislocation: b and normal vector along the
dislocation line l are perpendicular
¾ Screw Dislocation: b and normal vector along the
dislocation line l are parallel

3.1 Introduction to Device Fabrication

Chapter 3
Device Fabrication Technology Oxidation
About 1020 transistors (or 10 billion for every person in the
world) are manufactured every year. Lithography &
Etching
VLSI (Very Large Scale Integration)
ULSI (Ultra Large Scale Integration)
GSI (Giga-Scale Integration)
Ion Implantation
Variations of this versatile technology are used for flat-panel
displays, micro-electro-mechanical systems (MEMS), and
chips for DNA screening... Annealing &
Diffusion
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-1 Slide 3-2
 3.2 Oxidation of Silicon 3.2 Oxidation of Silicon
Dry Oxidation : Si + O2  SiO2

Wet Oxidation : Si +2H2O  SiO2 + 2H2

Quartz tube

Si Wafers

Flow
controller

H 2O or TCE(trichloroethylene) Resistance-heated furnace

O2 N2

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-3 Slide 3-4

3.2 Oxidation of Silicon 3.3 Lithography

EXAMPLE : Two-step Oxidation (a) Resist Coating (c) Development
Positive resist Negative resist
(a) How long does it take to grow 0.1m of dry oxide at 1000 oC ? Photoresist

(b) After step (a), how long will it take to grow an additional
0.2m of oxide at 900 oC in a wet ambient ? Si Oxide

Solution: (b) Exposure Si Si

(a) From the “1000oC dry” curve in Slide 3-3, it takes 2.5 hr to Deep Ultraviolet Light (d) Etching and Resist Strip
grow 0.1m of oxide. Optical Photomask with
Lens system opaque and
(b) Use the “900oC wet” curve only. It would have taken 0.7hr to clear patterns
grow the 0.1 m oxide and 2.4hr to grow 0.3 m oxide from Si Si
bare silicon. The answer is 2.4hr–0.7hr = 1.7hr.
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-5 Slide 3-6
 3.3 Lithography 3.3 Lithography
Photolithography Resolution Limit, R
Wafers are being loaded into a stepper in a clean room.
• R kl due to optical diffraction
• Wavelength l needs to be minimized. (248 nm, 193 nm,
157 nm?)
• k (<1) can be reduced will

• Large aperture, high quality lens

• Small exposure field, step-and-repeat using “stepper”
• Optical proximity correction
• Phase-shift mask, etc.
• Lithography is difficult and expensive. There can be 40
lithography steps in an IC process.
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-7 Slide 3-8

3.3.1 Wet Lithography Extreme UV Lithography (13nm wavelength)

Reflective “photomask”
Photo Mask Laser produced
plasma emitting
EUV
Water
Photoresist
Wafer

(a) (b)
No suitable lens material at this
conventional dry lithography wet or immersion lithography
l l
wavelength. Optics is based on mirrors
with nm flatness.

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-9 Slide 3-10
 Beyond Optical Lithography 3.4 Pattern Transfer–Etching
• Electron Beam Writing : Electron beam(s) scans and exposed Isotropic etching Anisotropic etching
photoresist photoresist
electron resist on wafer. Ready technology with relatively low
throughput.
SiO 2 SiO 2

• Electron Projection Lithography : Exposes a complex

(1) (1)
pattern using mask and electron lens similar to
photoresist photoresist
optical lithography.

• Nano-imprint : Patterns are etched into a durable material to SiO 2 SiO 2

make a “stamp.” This stamp is pressed into a liquid film over

(2) (2)
the wafer surface. Liquid is hardened with UV to create an
imprint of the fine patterns. SiO 2 SiO 2

(3)
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-11 Slide 3-12

3.4 Pattern Transfer–Etching 3.4 Pattern Transfer–Etching

Reactive-Ion Etching Systems Dry Etching (also known as Plasma Etching, or

Reactive-Ion Etching) is anisotropic.
Gas Baffle
Wafers
Gas Inlet
• Silicon and its compounds can be etched by plasmas
containing F.
• Aluminum can be etched by Cl.
• Some concerns :
- Selectivity and End-Point Detection
RF RF
Vacuum - Plasma Process-Induced Damage or Wafer Charging
Damage and Antenna Effect
Cross-section View Top View
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-13 Slide 3-14
Scanning electron microscope view of a plasma-etched 3.5 Doping
0.16 m pattern in polycrystalline silicon film. 3.5.1 Ion Implantation
Dopant ions

• The dominant doping method

• Excellent control of dose (cm-2)
• Good control of implant depth with energy (KeV to MeV)
• Repairing crystal damage and dopant activation requires
annealing, which can cause dopant diffusion and loss of
depth control.
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-15 Slide 3-16

3.5.1 Ion Implantation 3.5.1 Ion implantation

Schematic of an Ion Implanter
Phosphorous density
profile after
implantation

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-17 Slide 3-18
 3.5.1 Ion Implantation
Model of Implantation Doping Profile (Gaussian) Other Doping Methods
Ni
N ( x)   e ( x  R ) / 2 R
2 2

2  (R) • Gas-Source Doping : For example, dope Si with P

using POCl3.
Ni : dose (cm-2)
R : range or depth • Solid-Source Doping : Dopant diffuses from a doped
R : spread or sigma solid film (SiGe or oxide) into Si.

• In-Situ Doping : Dopant is introduced while a Si

film is being deposited.

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-19 Slide 3-20

3.6 Dopant Diffusion 3.6 Dopant Diffusion

Junction depth
• D increases with
SiO 2
increasing temperature.

n-type • Some applications need

diffusion layer
p-type Si very deep junctions (high
No T, long t). Others need
N ( x, t )  e  x / 4 Dt
2
very shallow junctions
  Dt (low T, short t).
N : Nd or Na (cm-3)
No : dopant atoms per cm2
t : diffusion time
D : diffusivity, Dt is the approximate distance of
dopant diffusion
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-21 Slide 3-22
 3.6 Dopant Diffusion 3.7 Thin-Film Deposition
Shallow Junction and Rapid Thermal Annealing Three Kinds of Solid
• After ion implantation, thermal annealing is required. Furnace
Crystalline Polycrystalline Amorphous
annealing takes minutes and causes too much diffusion of dopants
for some applications.

• In rapid thermal annealing (RTA), the wafer is heated to high

temperature in seconds by a bank of heat lamps.

•In flash annealing (100mS) and laser annealing (<1uS), dopant

ddiffusion is practically eliminated.

Example: Thin film of

Thin film of Si or metal.
Silicon wafer SiO2 or Si3N4.
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-23 Slide 3-24

3.7 Thin-Film Deposition 3.7.1 Sputtering

Examples of thin films in integrated circuits Schematic Illustration of Sputtering Process

• Advanced MOSFET gate dielectric

Sputtering target
• Poly-Si film for transistor gates

• Metal layers for interconnects

Ion (Ar +) Atoms sputtered out of the target
YY Y

• Dielectric between metal layers YY

Target material
deposited on wafer
YYYYY YY YYY YYYYYYYY
YYYYYYYY YYYYYY YYYY YYYYYY
YYYYYYYY YYYYYY YYYYYYYYYYYY

• Encapsulation of IC
YYYYYYYY YYYYYY YYYYYYYYYYYY YY
Y YYYYY YYYYYYY YYYYYYY
YYYY
YYYY
YY YYYYYY YYYYYYY
YY YYYY YYYYYYYY
YYYYYYYYYYYY
YYY YYYYYY
Y YY

Si Wafer

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-25 Slide 3-26
 3.7.2 Chemical Vapor Deposition (CVD) Some Chemical Reactions of CVD

Poly-Si : SiH4 (g) Si (s) + 2H2 (g)

Si3N4 : 3SiH2Cl2 (g)+4NH3 (g) Si3N4 (s)+6HCl(g)+6H2 (g)

SiO2 : SiH4 (g) + O2 (g) SiO2 (s) + 2H2 (g)

or
SiH2Cl2 (g)+2N2O (g) SiO2 (s)+2HCl (g)+2N2 (g)

Thin film is formed from gas phase components.

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-27 Slide 3-28

3.7.2 Chemical Vapor Deposition (CVD)

3.7.2 Chemical Vapor Deposition (CVD)
Pressure sensor Resistance-heated furnace
Quartz tube
Two types of CVD equipment:
Trap
To exhaust
• LPCVD (Low Pressure CVD) : Good uniformity. Si Wafers
Used for poly-Si, oxide, nitride.

• PECVD (Plasma Enhanced CVD) : Low temperature

process and high deposition rate. Used for oxide,
nitride, etc. Pump
Source
gases
Gas control
system
LPCVD Systems
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-29 Slide 3-30
 3.7.2 Chemical Vapor Deposition (CVD) 3.7.3 Epitaxy (Deposition of Single-Crystalline Film)
Epitaxy Selective Epitaxy
Cold Wall Parallel Plate SiO 2 SiO2

Si Substrate Si Substrate
Gas Injection Wafers
Ring
Pump
Heater Coil
Wafers
Pump Epi film SiO 2 Epi film SiO2
Gas
Hot Wall Parallel Plate Inlet Power leads
Si Substrate Si Substrate
Plasma Electrodes

PECVD Systems
(a) (b)
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-31 Slide 3-32

3.8 Interconnect – The Back-end Process 3.8 Interconnect – The Back-end Process
AlAl-Cu
or Cu
SEM: Multi-Level Interconnect (after removing the dielectric)
SiO2

Dopant diffusion region

Si

(a)
Encapsulation

Metal 3

Dielectric
Metal 2
via or plug
Dielectric
Metal 1

Dielectric

silicide
CoSi2
diffusion region
Si

(b)

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-33 Slide 3-34
 3.8 Interconnect – The Back-end Process 3.8 Interconnect – The Back-end Process
Copper Damascene Process
Copper Interconnect
• Al interconnect is prone to voids formation by
electromigration.
• Cu has excellent electromigration reliability dielectric dielectric

and 40% lower resistance than Al. (a) (b) •Chemical-Mechanical

Polishing (CMP)
• Because dry etching of copper is difficult (copper Cu
removes unwanted
materials.
etching products tend to be non-volatile), copper
patterns are defined by a damascene process.
Cu
•Barrier liner prevents
liner liner Cu diffusion.
dielectric dielectric

(c) (d)

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-35 Slide 3-36

3.8 Interconnect – The Back-end Process 3.9 Testing, Assembly, and Qualification
Planarization
• Wafer acceptance test
• A flat surface is highly desirable for subsequent • Die sorting
• Wafer sawing or laser cutting
lithography and etching. • Packaging
• Flip-chip solder bump technology
• CMP (Chemical-Mechanical Polishing) is used • Multi-chip modules
to planarize each layer of dielectric in the • Burn-in
• Final test
interconnect system. Also used in the front-end
• Qualification
process.

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-37 Slide 3-38
 3.10 Chapter Summary–A Device Fabrication Example 3.10 Chapter Summary–A Device Fabrication Example
Arsenic implantation
Al
(0) P-Si (4) Ion Metal (8) S iO2 S iO2
Wafer SiO2 SiO2 Implantation N+ (12) Si3 N4 Back side
etching
P Al
P-Si SiO2 SiO 2 metallization
SiO2 N+
(1)
P-Si SiO 2 SiO2 CVD (9) Si3 N4 P
Oxidation (5) N+ Al
SiO2 P Annealing & nitride SiO2 SiO2
Diffusion deposition N+ Au
UV P
wire
UV (6) Al
SiO2 SiO2
(2) N+ (10) Si3 N4 (13) Si3N 4
M ask Al Lithography
P Al Al
Sputtering and etching SiO2 SiO2 SiO2 SiO2
Positive resist N+ +
SiO2 UV
UV N
Lithography P P
P-Si (11)
M as k Photoresist Au
(3) SiO2 SiO2 (7) Res is t
Si3 N4 Plastic package
P-Si Al Al Back Side Al
SiO2 SiO2
Etching N+ milling SiO2 SiO 2 metal leads
N+
P
P Dicing, wire bonding,
Lithography and packaging

Modern Semiconductor Devices for Integrated Circuits (C. Hu) Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-39 Slide 3-40

Advantages of Si over Ge
Chapter 2 • Si has a larger bandgap (1.1 eV for Si versus 0.66 eV
for Ge)
• Si devices can operate at a higher temperature (150oC
Crystal Growth and Wafer
vs 100oC)
Preparation • Intrinsic resistivity is higher (2.3 x 105 Ω-cm vs 47 Ω-
cm)

Professor Paul K. Chu • SiO2 is more stable than GeO2 which is also water
soluble
• Si is less costly
City University of Hong Kong City University of Hong Kong

The processing characteristics and some material properties
of silicon wafers depend on its orientation.
The <111> planes have the highest density of atoms on the
surface, so crystals grow most easily on these planes and
oxidation occurs at a higher pace when compared to other
crystal planes.
Traditionally, bipolar devices are fabricated in <111>
oriented crystals whereas <100> materials are preferred for
MOS devices.
City University of Hong Kong
Dislocations are line defects.
Dislocations in a lattice are
dynamic defects. That is, they
can diffuse under applied
stress, dissociate into two or
more dislocations, or combine
with other dislocations.
Dislocations in devices are
generally undesirable, because
they act as sinks for metallic
impurities and alter diffusion
profiles.
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Defects
Any non-silicon
atoms incorporated
into the lattice at
either a substitutional
or interstitial site are
considered point
defects
Point defects are important in the kinetics of diffusion and
oxidation. Moreover, to be electrically active, dopants must
occupy substitutional sites in order to introduce an energy level in
the bandgap.
City University of Hong Kong
Defects
• Two typical area or planar defects are twins and grain
boundaries
• Twinning represents a change in the crystal orientation
across a twin plane, such that a mirror image exists across
that plane
• Grain boundaries are more disordered than twins and
separate grains of single crystals in polycrystalline silicon
• Planar defects appear during crystal growth, and crystals
having such defects are not considered usable for IC
manufacture and are discarded
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 Precipitates of impurity or dopant
atoms constitute the fourth class of Electronic Grade Silicon
defects. The solubility of dopants
varies with temperature, and so if an Electronic-grade silicon (EGS), a polycrystalline material of high
impurity is introduced at the purity, is the starting material for the preparation of single crystal
maximum concentration allowed by silicon. EGS is made from metallurgical-grade silicon (MGS) which
its solubility, a supersaturated
condition will exist upon cooling. The
in turn is made from quartzite, which is a relatively pure form of
crystal achieves an equilibrium state sand. MGS is purified by the following reaction:
by precipitating the impurity atoms in
excess of the solubility level as a Si (solid) + 3HCl (gas) → SiHCl3 (gas) + H2 (gas) + heat
second phase.
The boiling point of trichlorosilane (SiHCl3) is 32oC and can be
Precipitates are generally undesirable readily purified using fractional distillation. EGS is formed by
as they act as sites for dislocation
generation. Dislocations result from
reacting trichlorosilane with hydrogen:
the volume mismatch between the
precipitate and the lattice, inducing a 2SiHCl3 (gas) + 2H2 (gas) → 2Si (solid) + 6HCl (gas)
strain that is relieved by the
formation of dislocations.
City University of Hong Kong City University of Hong Kong

Czochralski Crystal Growth Impurity Segregation

Impurities, both intentional and unintentional, are introduced into the silicon ingot.
The Czochralski (CZ) process, which
Intentional dopants are mixed into the melt during crystal growth, while
accounts for 80% to 90% of worldwide
unintentional impurities originate from the crucible, ambient, etc.
silicon consumption, consists of dipping
a small single-crystal seed into molten
All common impurities have different solubilities in the solid and in the melt. An
silicon and slowly withdrawing the seed
equilibrium segregation coefficient ko can be defined to be the ratio of the
while rotating it simultaneously.
equilibrium concentration of the impurity in the solid to that in the liquid at the
interface, i.e. ko = Cs/Cl. Note that all the values shown in the table are below
The crucible is usually made of quartz
unity, implying that the impurities preferentially segregate to the melt and the
or graphite with a fused silica lining.
melt becomes progressively enriched with these impurities as the crystal is
After the seed is dipped into the EGS
being pulled.
melt, the crystal is pulled at a rate that
minimizes defects and yields a constant Impurity Al As B C Cu Fe O P Sb
ingot diameter.
ko 0.002 0.3 0.8 0.07 4x10-6 8x10-6 0.25 0.35 0.023

City University of Hong Kong City University of Hong Kong

 Impurity Distribution
The distribution of an impurity in the grown crystal can be
described mathematically by the normal freezing relation:
k o −1
C s = k o C o (1 − X )
X is the fraction of the melt solidified
Co is the initial melt concentration
Cs is the solid concentration
ko is the segregation coefficient
Weight = M
Consider a crystal being grown from
a melt having an initial weight Mo
with an initial dopant concentration
Co in the melt (i.e., the weight of the
Ingot Weight = dM dopant per 1 gram melt).
Dopant conc. = Cs
At a given point of growth when a
crystal of weight M has been grown,
Melt the amount of the dopant remaining
in the melt (by weight) is S.
S = dopant remaining in melt
For an incremental amount of the crystal with weight dM, the corresponding
reduction of the dopant (-dS) from the melt is Cs dM, where Cs is the dopant
concentration in the crystal (by weight): -dS = Cs dM

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The remaining weight of the melt is Mo - M, and the dopant concentration in

the liquid (by weight), Cl, is given by S
Cl =
Mo − M

Combining the two equations and substituting Cs Cl = ko Impurity concentration

dS ⎡ dM ⎤ profiles along the silicon
= −ko ⎢ ⎥
S ⎣ Mo − M ⎦ ingot (axially) for different
Given the initial weight of the dopant, Co M o , we can integrate and obtain ko with Co = 1
S dS M − dM
∫Co M o S
=k o ∫
o M − M
o
k o −1
⎡ M ⎤
Solving the equation gives C s = k o C o ⎢1 − ⎥
⎣ Mo ⎦

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 CZ-Si crystals are grown
from a silicon melt contained Oxygen in Silicon
in a fused silica (SiO2)
crucible. Fused silica reacts
with hot silicon and releases
• Oxygen forms a thermal donor in silicon
oxygen into the melt giving
CZ-Si an indigenous oxygen
• Oxygen increases the mechanical strength
concentration of about 1018
atoms/cm3. of silicon

Although the segregation coefficient of oxygen is <1, the axial

distribution of oxygen is governed by the amount of oxygen in the • Oxygen precipitates provide gettering sites
melt. Less dissolution of the crucible material occurs as the melt for unintentional impurities
volume diminishes, and less oxygen is available for incorporation.

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Internal Gettering
Thermal Donors
Under certain annealing
• Thermal donors are formed by the polymerization cycles, oxygen atoms in
the bulk of the crystal
of Si and O into complexes such as SiO4 in can be precipitated as
interstitial sites at 400oC to 500oC SiOx clusters that act as
trapping sites to
impurities.
• Careful quenching of the crystal annihilates these
donors
This process is called internal gettering and is one of the most
effective means to remove unintentional impurities from the
near surface region where devices are fabricated.

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 Float-Zone Process
The float-zone process has some
Characterization
advantages over the Czochralski
process for the growth of certain • Routine evaluation of ingots or boules
types of silicon crystals.
involves measuring the resistivity,
The molten silicon in the float-zone evaluating their crystal perfection, and
apparatus is not contained in a examining their mechanical properties, such
crucible, and is thus not subject to as size and mass
the oxygen contamination present in
CZ-Si crystals.
• Other tests include the measurement of
The float-zone process is also carbon, oxygen, and heavy metals
necessary to obtain crystals with a
high resistivity (>> 25 W-cm).
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Resistivity
Measurement Resistivity measurements are made
on the flat ends of the crystal by the
four-point probe technique.
The calculated
resistivity can be
A current, I, is passed through the correlated with
outer probes and the voltage, V, is dopant concentration
measured between the inner probes. using a dopant
concentration versus
The measured resistance (V/I) is resisitivity chart
converted to resistivity (W-cm)
using the relationship:

ρ = (V/I)2πS

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 Wafer Preparation Grinding
• Gross crystalline imperfections are detected visually and
defective crystals are cut from the boule. More subtle defects
such as dislocations can be disclosed by preferential chemical
etching

• Chemical information can be acquired employing wet

analytical techniques or more sophisticated solid-state and
surface analytical methods

• Silicon, albeit brittle, is a hard material. The most suitable

material for shaping and cutting silicon is industrial-grade
diamond. Conversion of silicon ingots into polished wafers
requires several machining, chemical, and polishing
operations
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After grinding to fix the diameter, one or

more flats are grounded along the length
of the ingot. The largest flat, called the
"major" or "primary" flat, is usually Slicing determines four wafer parameters:
relative to a specific crystal orientation.
The flat is located by x-ray diffraction
techniques. • Surface orientation (e.g., <111> or <100>)

The primary flat serves as a mechanical • Thickness (e.g., 0.5 – 0.7 mm, depending on wafer
locator in automated processing
equipment to position the wafer, and
diameter)
also serves to orient the IC device
relative to the crystal. Other smaller • Taper, which is the wafer thickness variations from one
flats are called "secondary" flats that end to another
serve to identify the orientation and
conductivity type of the wafer.
• Bow, which is the surface curvature of the wafer
The drawback of these flats is the reduction of the usable area on the wafer. measured from the center of the wafer to its edge
For some 200 mm and 300 mm diameter wafers, only a small notch is cut from
the wafer to enable lithographic alignment but no dopant type or crystal
orientation information is conveyed.
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