Toshiba Satellite P200 P205 X200 X205 (Compal ISRAA LA-3441P)

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A B C D E

1 1

Compal confidential 2

ISRAA LA-3441P Schematics Document


Mobile Merom uFCPGA with Intel
3
Crestline_PM+ICH8-M core logic 3

2006-09-21
REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 1 of 48
A B C D E
A B C D E

ISRAA Sub-board
Compal confidential
SW/B
Model : ISRAA
LS-3441P Rev01
File Name : LA-3441P CK505
Mobile Merom Thermal Sensor VGA/B for ATI
1
Santa Rosa Platform Fan Control uFCPGA-478 CPU ADM1032ARMZ Clock Generator LS-3442P Rev01 1

page 4 ICS 9LPR365


page 4,5,6
page 4 page 16 VGA/B for NVIDIA
LS-3443P Rev01
H_A#(3..35) FSB USB/B
H_D#(0..63)
667/800MHz 1.05V
LS-3444P Rev01
HDMI SII-1392 LCD Conn. CRT & TV-out
& Conn page 18 page 19 page 17 Intel Crestline MCH DDR2 667MHz 1.8V
DDR2-SO-DIMM X2 F_P/B
BANK 0, 1, 2, 3 page 14,15 LS-3401P Rev01
FCBGA 1299 Dual Channel
ATI M71M VGA/B Conn.
page 7,8,9,10,11,12
with 64/128/256 page 19 PCI-Express x 16
Int. Camera USB x 2 USB/B conn USB2.0
MB VRAM
2
USB port 9 USB x 1 page 35
conn page 35 page 35
Bluetooth Conn 2

page 35
3.3V 48MHz
New Card socket DMI X4
page 27 USB port 8 USB port 4, 5 USB port 0, 1, 2, 3 USB port 7
Port 1 USB 3.3V 480MHz
PCI-E BUS 2.5GHz

Azalia USB port 6 USB1.1


Intel ICH8-M Finger Printer

3.3V 24.576MHz/48Mhz
(port 1) SATA1.5GHz Tweeter/HP Amplifier
PCI BUS 3.3V 33 MHz mBGA-676 PATA
page 35
10/100/1000 LAN Mini-Card Mini-Card & Int-Mic
page 19,20,21,22 page 30
RTL8111B/RTL8101E Robson WLAN MDC V1.5 APA2056

3.3V ATA-100
Port 2 Port 4 Port 3 page 37
page 28 page 32 page 32 Medium Range
Amplifier
HD Audio Codec APA2068 page 30
ALC268 page 29
3
RJ45/11 CONN 3
page 28
LPC BUS Subwoofer Amplifier
3.3V 33 MHz APA3011
page 30
CardBus Controller
TI PCI8412 SATA 0 SATA HDD Connector
page 20,21 page 24

LED
SATA 1
page 36 SATA HDD Connector Audio Jack
Slot 0 1394 port 5in1 Slot ENE KB910QF page 24
page 26 page 26 page 26 page 31
RTC CKT.
page 33
page 21
PATA Slave
PATA ODD Connector
Power On/Off CKT. page 24
page 29
4 Touch Pad Int.KBD BIOS CIR
4

DC/DC Interface CKT. Connpage 32 page 36 page 34 page 32


page 36
Security Classification Compal Secret Data Compal Electronics, Inc.
2006/06/30 2007/06/30 Title
Power Circuit DC/DC Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Page 39~46 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 2 of 48
A B C D E
5 4 3 2 1

Voltage Rails Board ID / SKU ID Table for AD channel


Vcc 3.3V +/- 5%
Power Plane Description S0-S1 S3 S5 Ra/Rc/Re 100K +/- 1%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
VIN Adapter power supply (18.5V) N/A N/A N/A
B+ AC or battery power rail for power circuit N/A N/A N/A
0 0 0 V 0 V 0.100 V
D D

+CPU_CORE Core voltage for CPU ON OFF OFF


1 8.2K +/- 1% 0.216 V 0.250 V 0.289 V
+1.05Vs 1.05V power rail for Processor I/O and MCH/ICH core power ON OFF OFF
2 18K +/- 1% 0.436 V 0.503 V 0.538 V
+0.9VS 0.9V switched power rail for DDRII Vtt ON OFF OFF
3 33K +/- 1% 0.712 V 0.819 V 0.875 V
+1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF
4 56K +/- 1% 1.036 V 1.185 V 1.264 V
+1.8V 1.8V power rail for DDRII ON ON OFF
5 100K +/- 1% 1.453 V 1.650 V 1.759 V
+1.8VS 1.8V switched power rail ON OFF OFF
6 200K +/- 1% 1.935 V 2.200 V 2.341 V
+2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF
7 NC 2.500 V 3.300 V 3.300 V
+1.25Vs 1.25Vs power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
BTO Option Table
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON* BTO Item BOM Structure
+5VS 5V switched power rail ON OFF OFF 2ND HDD 2HDD@
+RTC_VCC RTC power ON ON ON BOARD ID Table 100M@
LAN 1000M@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision WLAN WLAN@
0 GM@
C NB PM@ C
1
BT BT@
2
MIC MIC@
3
CIR CIR@
External PCI Devices 4
FINGER PRINT FP@
5
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ
6 Express Card NEWCARD@
1394 D0 AD20 2 A,B,C 7 PCMCIA Card PCMCIA@
CARD BUS D4 AD20 2 A,B,C Camera Camera@
5IN1 D4 AD20 2 A,B,C
SKU ID Table Robson Robson@
1392@
SKU ID SKU
HDMI 1932@
0 10
M72M@
1 10G
KB910 I2C / SMBUS ADDRESSING 2 10H SPEAKER
DEVICE HEX ADDRESS 3
4
B
SM1 24C16 A0H 1010000Xb B
5
SM1 SMART BATTERY 16H 0001011Xb
6
SM2 ADM0132 98H 1001100Xb
CPU THERMAL MONITOR 7 USB PORT LIST
PORT DEVICE
0 RIGHT USB Port (Samll Board)
1 RIGHT USB Port (Samll Board)
2 RIGHT USB Port (Samll Board)
ICH8-M SM Bus address
3 RIGHT USB Port (Samll Board)

DEVICE HEX ADDRESS 4 LEFT USB Port


5 LEFT USB Port
DDR SO-DIMM 0 A0 10100000
6 Fingerprint
DDR SO-DIMM 1 A4 10100100
7 Blue Tooth
CLOCK GENERATOR (EXT.) D2 11010010
8 Internal Camera
9 Express Card

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 3 of 48
5 4 3 2 1
5 4 3 2 1

Thermal Sensor ADM1032ARM


+3VS

1
C1
D D
0.1U_0402_16V4Z
2 R1
1
@ 10K_0402_5%

2
C2 U1
2200P_0402_50V7K H_THERMDA 2 1
2 D+ VDD1
H_THERMDC 3 6
D- ALERT#
<7> H_A#[3..16]
JP1A 8 4
<19,33> EC_SMB_CK2 SCLK THERM#
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# <7>

ADDR GROUP 0
H_A#4 L5 E2 H_BNR# 7 5
A[4]# BNR# H_BNR# <7> <19,33> EC_SMB_DA2 SDATA GND
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# <7>
H_A#6 K5
H_A#7 A[6]# H_DEFER# ADM1032ARMZ_RM8
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21 H_DRDY#
A[8]# DRDY# H_DRDY# <7>
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# <7>
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# <7>
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# R2 2 1 @ 56_0402_5% +1.05VS
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# <21>
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# <7>
H_ADSTB#0 M1
<7> H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
<7> H_REQ#0
H_REQ#0
H_REQ#1
K3
H2
REQ[0]#
RESET#
RS[0]# F3
F4
H_RS#0
H_RS#1
H_RESET# <7>
H_RS#0 <7> FAN 1
<7> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <7>
H_REQ#2 K2 G3 H_RS#2
<7> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <7> VS
H_REQ#3 J3 G2 H_TRDY#
<7> H_REQ#3 REQ[3]# TRDY# H_TRDY# <7> +5VS
H_REQ#4 L1
<7> H_REQ#4 REQ[4]#
G6 H_HIT#
<7> H_A#[17..35] HIT# H_HIT# <7>
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# <7> C
H_A#18 U5 2 1 C757
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4

8
ADDR GROUP 1

1SS355_SOD323
H_A#20 W6 AD3 0.1U_0402_16V4Z
A[20]# BPM[1]#

3
H_A#21 U4 AD1 1 2 3
XDP/ITP SIGNALS

P
A[21]# BPM[2]# +

1
H_A#22 Y5 AC4 R616 10K_0402_5% 1 1 R763 22
S AOS3401_SOT23
H_A#23 A[22]# BPM[3]# 0 5.1K_0603_1% D40
U1 A[23]# PRDY# AC2 2 -
G

G
H_A#24 R4 AC1 R628 1 2 54.9_0402_1% +1.05VS
H_A#25 A[24]# PREQ# ITP_TCK U46A LM358DT_SO8
D
T5 AC5

4
H_A#26 A[25]# TCK ITP_TDI R629 1 Q43
T3 AA6 2 54.9_0402_1% <33> EN_DFAN1 1 2

2
H_A#27 A[26]# TDI ITP_TDO R630 1
W2 A[27]# TDO AB3 2 39_0402_1% R617 10K_0402_5% R618
H_A#28 W5 AB5 ITP_TMS R631 1 2 54.9_0402_1% 1 2
H_A#29 A[28]# TMS ITP_TRST# 5.1K_0402_5%
Y4 A[29]# TRST# AB6

1N4148_SOT23
H_A#30 U2 C20 ITP_DBRESET# 1
A[30]# DBR# ITP_DBRESET# <22>
H_A#31 V4 D41
H_A#32 A[31]# 10K_0402_5% + C758
W3 A[32]#
H_A#33 THERMAL H_PROCHOT# R764 10U_A_6.3VM
H_A#34
AA4 A[33]# H_THERMDA, H_THERMDC routing together, JP41
AB2

2
H_A#35 A[34]# Trace width / Spacing = 10 / 10 mil 2 +FAN1_VOUT
AA3 A[35]# PROCHOT# D21 1 1
H_ADSTB#1 V1 A24 H_THERMDA 2
<7> H_ADSTB#1 ADSTB[1]# THERMDA 2
B25 H_THERMDC 3
H_A20M# THERMDC 3
<21> H_A20M# A6 A20M# +3VS 1 2
ICH

H_FERR# A5 C7 H_THERMTRIP# R619 10K_0402_5% 4


<21> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,21> GND
H_IGNNE# C4 5
<21> H_IGNNE# IGNNE# GND
<33> FAN_SPEED1 1
H_STPCLK# D5 1 ACES_85205-03001
<21> H_STPCLK# STPCLK#
H_INTR C6 H CLK
<21> H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK C760
<21> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <16> 2
H_SMI# A3 A21 CLK_CPU_BCLK# @1000P_0402_50V7K
<21> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <16> 2 C759
M4 @ 1000P_0402_50V7K
RSVD[01]
N5
B
T2
V3
RSVD[02]
RSVD[03] FAN 2 B
RSVD[04]
B2
RESERVED

RSVD[05]
C3 RSVD[06]
D2 VS +5VS
RSVD[07] ITP_TRST# R7 649_0402_1%
D22 RSVD[08] 1 2
D3 RSVD[09]
F6 ITP_TCK R8 1 2 54.9_0402_1%
RSVD[10]

1SS355_SOD323
3
1 2 5

P
+

1
S
conn@ Merom Ball-out Rev 1a R620 10K_0402_5% 71 R765 2 2 AOS3401_SOT23
0 5.1K_0603_1% FAN2@ D42
FAN2@ 6 -
G

G
D
U46B LM358DT_SO8

4
1 2 Q44 FAN2@
<33> EN_DFAN2

2
R621 10K_0402_5% R622
FAN2@ 1 2
FAN2@ 5.1K_0402_5%

1N4148_SOT23
Place Caps Close to CPU Socket D43
1
+1.05VS +1.05VS 10K_0402_5% + C762
C7 1 2@ 180P_0402_50V8J H_INIT# R766 FAN2@ 10U_A_6.3VM
FAN2@ JP42

2
C8 H_A20M# 2 +FAN2_VOUT
1 2@ 180P_0402_50V8J 1 1
1

2 2
R9 R10 C9 1 2@ 180P_0402_50V8J H_INTR 3
68_0402_5% 3
+3VS 1 2
@ 56_0402_5% C10 1 2@ 180P_0402_50V8J H_NMI R623 10K_0402_5% 4 GND
FAN2@ 5
2

2 2

C11 GND
1 2@ 180P_0402_50V8J H_SMI#
<33> FAN_SPEED2 1
B

1 ACES_85205-03001
C12 1 2@ 180P_0402_50V8J H_STPCLK# FAN2@
E

A H_PROCHOT# A
3 1 OCP# OCP# <22>
C764
2
C

Q2 C13 1 2@ 180P_0402_50V8J H_IGNNE# @1000P_0402_50V7K


@ MMBT3904_SOT23 2
C14 1 2@ 180P_0402_50V8J H_FERR# C763
@1000P_0402_50V7K

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(1/3)-AGTL+
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1

+VCC_CORE +VCC_CORE
<7> H_D#[0..15] H_D#[32..47] <7>
JP1B JP1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
G22 D[3]# D[35]# V26 A12 VCC[004] VCC[071] AC9

DATA GRP 0
D H_D#4 H_D#36 D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18

DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 D[9]# D[41]# W22 B7 VCC[010] VCC[077] AD7
H_D#10 J24 Y23 H_D#42 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 D[11]# D[43]# W24 B10 VCC[012] VCC[079] AD10
H_D#12 H22 W25 H_D#44 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 D[13]# D[45]# AA23 B14 VCC[014] VCC[081] AD14
H_D#14 K22 AA24 H_D#46 B15 AD15
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
H23 D[15]# D[47]# AB25 B17 VCC[016] VCC[083] AD17
<7> H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 <7> B18 VCC[017] VCC[084] AD18
<7> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <7> B20 VCC[018] VCC[085] AE9
<7> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <7> C9 VCC[019] VCC[086] AE10
<7> H_D#[16..31] H_D#[48..63] <7> C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17 +1.05VS
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 AE21 D18 AF18

DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099]
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9 R11 0_0402_5%
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 D[29]# D[61]# AD23 E10 VCC[035] VCCP[01] G21 2 1
H_D#30 T25 AF22 H_D#62 E12 V6 2 1
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] R12 0_0402_5% C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
<7> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <7> E15 VCC[038] VCCP[04] K6 1
<7> H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 <7> E17 VCC[039] VCCP[05] M6
N24 AC20 E18 J21 + C15
<7> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <7> VCC[040] VCCP[06]
E20 K21 330U_D2E_2.5VM_R9
+GTL_REF0 COMP0 VCC[041] VCCP[07]
AD26 GTLREF COMP[0] R26 F7 VCC[042] VCCP[08] M21
R13 2
1 2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
R14 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
C16 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F14 R6
TEST5 TEST4 VCC[046] VCCP[12]
AF1 TEST5 DPRSTP# E5 H_DPRSTP# <8,21,46> F15 VCC[047] VCCP[13] T21

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
TEST6 DPSLP# H_DPSLP# <21> VCC[048] VCCP[14]

1
D24 H_DPWR# F18 V21
DPWR# H_DPWR# <7> VCC[049] VCCP[15]
B22 D6 H_PWRGOOD F20 W21
<16> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD <21> VCC[050] VCCP[16]

R15

R16

R17

R18
B23 D7 H_CPUSLP# AA7
<16> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <7> VCC[051]
<16> CPU_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# <46> AA9 VCC[052] VCCA[01] B26 +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_10V4Z

0.01U_0402_16V7K
Near pin C26

Near pin B26


layout note: Route TEST3 & TEST5 traces on conn@ Merom Ball-out Rev 1a AA12 VCC[054]
AA13 AD6 CPU_VID0 <46>
ground referenced layer to the TPs AA15
VCC[055] VID[0]
AF5 1 1
VCC[056] VID[1] CPU_VID1 <46>
AA17 VCC[057] VID[2] AE5 CPU_VID2 <46>

C17

C18
Resistor placed within AA18 VCC[058] VID[3] AF4 CPU_VID3 <46>
AA20 AE3 CPU_VID4 <46>
0.5" of CPU pin.Trace AB9
VCC[059] VID[4]
AF3
2 2
VCC[060] VID[5] CPU_VID5 <46>
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 should be at least 25 AC10 VCC[061] VID[6] AE2 CPU_VID6 <46>
AB10
mils away from any other AB12
VCC[062]
VCC[063]
toggling signal. AB14 VCC[064] VCCSENSE AF7 VCCSENSE VCCSENSE <46>
166 0 1 1 COMP[0,2] trace width is AB15 VCC[065] Length match
AB17 VCC[066]
18 mils. COMP[1,3] trace AB18 VCC[067] VSSSENSE AE7 VSSSENSE VSSSENSE <46> within 25 mils.
B width is 4 mils. conn@ Merom Ball-out Rev 1a The trace B
200 0 1 0
.
width/space/other
+VCC_CORE
R19 is 20/7/25.
100_0402_1%
1 2 VCCSENSE
+1.05VS
R20
+GTL_REF0 Impendance control 55 Ohm 100_0402_1%
1

1 2 VSSSENSE

R21
1K_0402_1%
2

+GTL_REF0
Close to CPU pin
1

within 500mils.
R22
2K_0402_1%
2

Close to CPU pin AD26


within 500mils.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(2/3)-AGTL+/PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 5 of 48
5 4 3 2 1
5 4 3 2 1

+VCC_CORE

1 1 1 1 1 1 1 1
C21 C22 C23 C24 C25 C26 C27 C28
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

+VCC_CORE
D D

JP1D 1 1 1 1 1 1 1 1
A4 P6 C29 C30 C31 C32 C33 C34 C35 C36
VSS[001] VSS[082] Place these capacitors on L8
A8 VSS[002] VSS[083] P21
A11 P24 (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[003] VSS[084] 2 2 2 2 2 2 2 2
A14 VSS[004] VSS[085] R2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
A23 VSS[007] VSS[088] R25
+VCC_CORE
AF2 VSS[008] VSS[089] T1
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26 1 1 1 1 1 1 1 1
B13 U3 C37 C38 C39 C40 C41 C42 C43 C44
VSS[012] VSS[093] Place these capacitors on L8
B16 VSS[013] VSS[094] U6
B19 U21 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[014] VSS[095] 2 2 2 2 2 2 2 2
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
+VCC_CORE
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23 1 1 1 1 1 1 1 1
C2 W26 C45 C46 C47 C48 C49 C50 C51 C52
VSS[023] VSS[104] Place these capacitors on L8
C22 VSS[024] VSS[105] Y3
C25 Y6 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[025] VSS[106] 2 2 2 2 2 2 2 2
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24 Mid Frequence Decoupling
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19 South Side Secondary North Side Secondary
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
+VCC_CORE
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
C53

C54

C55

C56

C57
F25 VSS[052] VSS[133] AC19 1 1 1 1 1 1
G4 AC21
G1
G23
VSS[053]
VSS[054]
VSS[134]
VSS[135] AC24
AD2
+ + + + + + C58
330U_D2E_2.5VM_R9
ESR <= 1.5m ohm
VSS[055] VSS[136]
G26
H3
VSS[056]
VSS[057]
VSS[137]
VSS[138]
AD5
AD8
2 2 2 2 2 2 Capacitor > 1980uF
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
B
J2
J5
VSS[061] VSS[142] AD19
AD22
330uF ESR 7m ohm X 6 PCS B
VSS[062] VSS[143]
J22 VSS[063] VSS[144] AD25 B-TEST Change to SGA19331E80
J25 VSS[064] VSS[145] AE1
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 AE23 +1.05VS
VSS[071] VSS[152]
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6 1
330U_D2E_2.5VM_R9

M22 VSS[075] VSS[156] AF8 1 1 1 1 1 1 Place these inside socket


M25 AF11 C59 + C60 C61 C62 C63 C64 C65
VSS[076] VSS[157] cavity on Bottom layer (North
N1 VSS[077] VSS[158] AF13 side Secondary)
N4 AF16 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS[078] VSS[159] 2 2 2 2 2 2 2
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25

conn@ Merom Ball-out Rev 1a


.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(3/3)-GND&Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 6 of 48
5 4 3 2 1
5 4 3 2 1

<5> H_D#[0..63] U3A H_A#[3..35] <4>


H_D#0 E2 J13 H_A#3
H_D#1 H_D#_0 H_A#_3 H_A#4
G2 H_D#_1 H_A#_4 B11
H_D#2 G7 C11 H_A#5
H_D#3 H_D#_2 H_A#_5 H_A#6
M6 H_D#_3 H_A#_6 M11
H_D#4 H7 C15 H_A#7
H_D#5 H_D#_4 H_A#_7 H_A#8
H3 H_D#_5 H_A#_8 F16
H_D#6 G4 L13 H_A#9
H_D#7 H_D#_6 H_A#_9 H_A#10
D F3 H_D#_7 H_A#_10 G17 D
H_D#8 N8 C14 H_A#11
H_D#9 H_D#_8 H_A#_11 H_A#12
H2 H_D#_9 H_A#_12 K16
H_D#10 M10 B13 H_A#13
H_D#11 H_D#_10 H_A#_13 H_A#14
N12 H_D#_11 H_A#_14 L16
H_D#12 N9 J17 H_A#15
H_D#13 H_D#_12 H_A#_15 H_A#16
H5 H_D#_13 H_A#_16 B14
H_D#14 P13 K19 H_A#17
H_D#15 H_D#_14 H_A#_17 H_A#18
K9 H_D#_15 H_A#_18 P15
H_D#16 M2 R17 H_A#19
H_D#17 H_D#_16 H_A#_19 H_A#20
W10 H_D#_17 H_A#_20 B16
H_D#18 Y8 H20 H_A#21
H_D#19 H_D#_18 H_A#_21 H_A#22
V4 H_D#_19 H_A#_22 L19
H_D#20 M3 D17 H_A#23
H_D#21 H_D#_20 H_A#_23 H_A#24
J1 H_D#_21 H_A#_24 M17
H_D#22 N5 N16 H_A#25
H_D#23 H_D#_22 H_A#_25 H_A#26
N3 H_D#_23 H_A#_26 J19
H_D#24 W6 B18 H_A#27
H_D#25 H_D#_24 H_A#_27 H_A#28
W9 H_D#_25 H_A#_28 E19
H_D#26 N2 B17 H_A#29
H_D#27 H_D#_26 H_A#_29 H_A#30
Y7 H_D#_27 H_A#_30 B15
H_D#28 Y9 E17 H_A#31
H_D#29 H_D#_28 H_A#_31 H_A#32
P4 H_D#_29 H_A#_32 C18
H_D#30 W3 A19 H_A#33
H_D#31 H_D#_30 H_A#_33 H_A#34
N1 H_D#_31 H_A#_34 B19
H_D#32 AD12 N19 H_A#35
H_D#33 H_D#_32 H_A#_35
AE3 H_D#_33
H_D#34 AD9 G12 H_ADS#
H_D#_34 H_ADS# H_ADS# <4>
H_D#35 AC9 H17 H_ADSTB#0

HOST
H_D#_35 H_ADSTB#_0 H_ADSTB#0 <4>
C H_D#36 AC7 G20 H_ADSTB#1 C
H_D#_36 H_ADSTB#_1 H_ADSTB#1 <4>
H_D#37 AC14 C8 H_BNR#
H_D#_37 H_BNR# H_BNR# <4>
H_D#38 AD11 E8 H_BPRI#
H_D#_38 H_BPRI# H_BPRI# <4>
H_D#39 AC11 F12 H_BR0#
H_D#_39 H_BREQ# H_BR0# <4>
H_D#40 AB2 D6 H_DEFER#
H_D#_40 H_DEFER# H_DEFER# <4>
H_D#41 AD7 C10 H_DBSY#
H_D#_41 H_DBSY# H_DBSY# <4>
H_D#42 AB1 AM5 CLK_MCH_BCLK
H_D#_42 HPLL_CLK CLK_MCH_BCLK <16>
H_D#43 Y3 AM7 CLK_MCH_BCLK#
H_D#_43 HPLL_CLK# CLK_MCH_BCLK# <16>
H_D#44 AC6 H8 H_DPWR#
H_D#_44 H_DPWR# H_DPWR# <5>
H_D#45 AE2 K7 H_DRDY#
H_D#_45 H_DRDY# H_DRDY# <4>
H_D#46 AC5 E4 H_HIT#
H_D#_46 H_HIT# H_HIT# <4>
H_D#47 AG3 C6 H_HITM#
H_D#_47 H_HITM# H_HITM# <4>
H_D#48 AJ9 G10 H_LOCK#
H_D#_48 H_LOCK# H_LOCK# <4>
H_D#49 AH8 B7 H_TRDY#
H_D#_49 H_TRDY# H_TRDY# <4>
H_D#50 AJ14
H_D#51 H_D#_50
AE9 H_D#_51
H_D#52 AE11
H_D#53 H_D#_52 H_DINV#0
AH12 H_D#_53 H_DINV#_0 K5 H_DINV#0 <5>
H_D#54 AJ5 L2 H_DINV#1
H_D#55 H_D#_54 H_DINV#_1 H_DINV#2 H_DINV#1 <5>
AH5 H_D#_55 H_DINV#_2 AD13 H_DINV#2 <5>
+1.05VS H_D#56 AJ6 AE13 H_DINV#3
H_D#57 H_D#_56 H_DINV#_3 H_DINV#3 <5>
AE7 H_D#_57
H_D#58 AJ7 M7 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1 H_DSTBN#0 <5>
AJ2 H_D#_59 H_DSTBN#_1 K3 H_DSTBN#1 <5>
H_D#60 AE5 AD2 H_DSTBN#2
2 H_D#_60 H_DSTBN#_2 H_DSTBN#2 <5>

2
H_D#61 AJ3 AH11 H_DSTBN#3
R23 R24 H_D#62 H_D#_61 H_DSTBN#_3 H_DSTBN#3 <5>
AH2 H_D#_62
H_D#63 AH13 L7 H_DSTBP#0
54.9_0402_1% 54.9_0402_1% H_D#_63 H_DSTBP#_0 H_DSTBP#1 H_DSTBP#0 <5>
H_DSTBP#_1 K2 H_DSTBP#1 <5>
B H_DSTBP#2 B
AC2
1

1 H_SWNG1 H_DSTBP#_2 H_DSTBP#3 H_DSTBP#2 <5>


B3 H_SWING H_DSTBP#_3 AJ10 H_DSTBP#3 <5>
H_RCOMP C2 H_RCOMP H_REQ#[0..4] <4>
M14 H_REQ#0
H_SCOMP H_REQ#_0 H_REQ#1
W1 H_SCOMP H_REQ#_1 E13
H_SCOMP# W2 A11 H_REQ#2
H_SCOMP# H_REQ#_2 H_REQ#3
H_REQ#_3 H13
H_RESET# B6 B12 H_REQ#4
<4> H_RESET# H_CPURST# H_REQ#_4
H_CPUSLP# E5
<5> H_CPUSLP# H_CPUSLP# H_RS#[0..2] <4>
Layout Note: E12 H_RS#0
H_RS#_0 H_RS#1
D7
H_RCOMP / H_VREF / H_SWNG H_AVREF B9
H_RS#_1
D8 H_RS#2
H_VREF H_DVREF H_AVREF H_RS#_2
trace width and spacing is 18/20 A9 H_DVREF
R25 0_0402_5%

CRESTLINE ES_FCBGA1299~D
GMR1@
+1.05VS +1.05VS
Change 100-->1K 200-->2K 20060825
2

R26 R27
1K_0402_5%
221_0603_1%
1

H_VREF H_RCOMP H_SWNG1


1

1
1

C66 1
A A
R28 R29 R30 C67
2K_0402_1% 0.1U_0402_16V4Z
2 24.9_0402_1% 100_0402_1% 0.1U_0402_16V4Z
2

2
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title
within 100 mils from NB Near B3 pin Crestline (1/7)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 7 of 48
5 4 3 2 1
5 4 3 2 1

U3B

P36 RSVD1 +1.8V


P37 RSVD2 SM_CK_0 AV29 DDRA_CLK0 <14>
R35 RSVD3 SM_CK_1 BB23 DDRA_CLK1 <14>
N35 RSVD4 SM_CK_3 BA25 DDRB_CLK0 <15>
AR12 RSVD5 SM_CK_4 AV23 DDRB_CLK1 <15>
AR13 R31
RSVD6 1K_0402_1%
AM12 RSVD7 SM_CK#_0 AW30 DDRA_CLK0# <14>
AN13 RSVD8 SM_CK#_1 BA23 DDRA_CLK1# <14>
J12 RSVD9 SM_CK#_3 AW25 DDRB_CLK0# <15>
AR37 AW23 SM_RCOMP_VOH
RSVD10 SM_CK#_4 DDRB_CLK1# <15>

RSVD
AM36 RSVD11
AL36 RSVD12 SM_CKE_0 BE29 DDRA_CKE0 <14> For Crestline: 20ohm
D AM37 AY32 C68 C69 D
D20
RSVD13 SM_CKE_1
BD39
DDRA_CKE1 <14> For Calero: 80.6ohm R32
RSVD14 SM_CKE_3 DDRB_CKE0 <15>
BG37 3.01K_0402_1% 2.2U_0603_6.3V6K
SM_CKE_4 DDRB_CKE1 <15>
1 Layout Note: 0.01U_0402_16V7K
C774 BG20
@ 0.1U_0402_16V4Z SM_CS#_0 DDRA_SCS0# <14> V_DDR_MCH_REF
SM_CS#_1 BK16 DDRA_SCS1# <14>
BG16 trace width and

MUXING
2 SM_CS#_2 DDRB_SCS0# <15>
H10 BE13 spacing is 20/20. SM_RCOMP_VOL
RSVD20 SM_CS#_3 DDRB_SCS1# <15>
B51 RSVD21
BJ20 RSVD22 SM_ODT_0 BH18 DDRA_ODT0 <14>
BK22 BJ15 R33 C70 C71
RSVD23 SM_ODT_1 DDRA_ODT1 <14>
BF19 BJ14 1K_0402_1%
RSVD24 SM_ODT_2 DDRB_ODT0 <15> +1.8V
BH20 BE16 2.2U_0603_6.3V6K
RSVD25 SM_ODT_3 DDRB_ODT1 <15> +1.8V
BK18 0.01U_0402_16V7K
RSVD26 SMRCOMPN R34
BJ18 RSVD27 SM_RCOMP BL15 1 2 20_0402_1%
BF23 BK14 SMRCOMPP R35 1 2 20_0402_1%

DDR
RSVD28 SM_RCOMP#

2
BG23 RSVD29
Add for using DDR2 2Gb tech. 8/28 BC23 BK31 SM_RCOMP_VOH R36
RSVD30 SM_RCOMP_VOH SM_RCOMP_VOL 1K_0402_1%
BD24 BL31
<14> DDR_A_MA14 BJ29
RSVD31
RSVD32
SM_RCOMP_VOL Strap Pin Table
<15> DDR_B_MA14 BE24 AR49

1
RSVD33 SM_VREF_0 SM_VREF
BH39 RSVD34 SM_VREF_1 AW4 011 = 667MT/s FSB
AW20 RSVD35 CFG[2:0] 010 = 800MT/s FSB

2
BK20 RSVD36
C48 C72 1 R37 0 = DMI x 2
RSVD37 CLK_DREF_96M 1K_0402_1%
D47 RSVD38 DPLL_REF_CLK B42
CLK_DREF_96M#
CLK_DREF_96M <16> CFG5 1 = DMI x 4 * (Default)
B44 RSVD39 DPLL_REF_CLK# C42 CLK_DREF_96M# <16>
C44 H48 CLK_DREF_SSC 0.1U_0402_16V4Z 0 = Lane Reversal Enable
CLK_DREF_SSC <16>

1
RSVD40 DPLL_REF_SSCLK CLK_DREF_SSC# 2
A35 RSVD41 DPLL_REF_SSCLK# H47 CLK_DREF_SSC# <16> CFG9 1 = Normal Operation * (Default)

CLK
B37 RSVD42
C B36 K44 CLK_MCH_3GPLL 00 = Reserved C
RSVD43 PEG_CLK CLK_MCH_3GPLL <16>
B34 K45 CLK_MCH_3GPLL# CFG[13:12]
C34
RSVD44 PEG_CLK# CLK_MCH_3GPLL# <16> 01 = XOR Mode Enabled
RSVD45 10 = All Z Mode Enabled
11 = Normal Operation * (Default)
AN47 DMI_ITX_MRX_N0 0 = Dynamic ODT Disabled
DMI_RXN_0 DMI_ITX_MRX_N0 <22>
DMI_ITX_MRX_N1 CFG16
DMI_RXN_1 AJ38
AN42 DMI_ITX_MRX_N2
DMI_ITX_MRX_N1 <22> 1 = Dynamic ODT Enabled * (Default)
DMI_RXN_2 DMI_ITX_MRX_N2 <22>
DMI_ITX_MRX_N3 0 = Normal Operation
DMI_RXN_3 AN46 DMI_ITX_MRX_N3 <22> *(Default)
DMI_ITX_MRX_P0
CFG19 1 = DMI Lane Reversal Enable
DMI_RXP_0 AM47 DMI_ITX_MRX_P0 <22>
MCH_CLKSEL0 P27 AJ39 DMI_ITX_MRX_P1 0 = Only PCIE or SDVO is operational.
<16> MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_ITX_MRX_P1 <22>
MCH_CLKSEL1 DMI_ITX_MRX_P2 CFG20
<16> MCH_CLKSEL1
MCH_CLKSEL2
N27
N24
CFG_1 DMI_RXP_2 AN41
AN45 DMI_ITX_MRX_P3
DMI_ITX_MRX_P2 <22> * (Default)
<16> MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_ITX_MRX_P3 <22> (PCIE/SDVO select)
C21 CFG_3 DMI_MTX_IRX_N0
1 = PCIE/SDVO are operating simu.
C23 CFG_4 DMI_TXN_0 AJ46 DMI_MTX_IRX_N0 <22>
MCH_CFG_5 DMI_MTX_IRX_N1 0 = No SDVO Device Present
F23 CFG_5 DMI_TXN_1 AJ41
DMI_MTX_IRX_N2
DMI_MTX_IRX_N1 <22> * (Default)
N23 AM40 SDVO_CTRL_DATA

DMI
CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2 <22>
MCH_CFG_7 G23 AM44 DMI_MTX_IRX_N3 1 = SDVO Device Present
CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 <22>
MCH_CFG_8 J20
MCH_CFG_9 CFG_8 DMI_MTX_IRX_P0
C20 CFG_9 DMI_TXP_0 AJ47 DMI_MTX_IRX_P0 <22>
CFG
R24 AJ42 DMI_MTX_IRX_P1
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 <22>
L23 AM39 DMI_MTX_IRX_P2
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 <22>
+1.05VS
Refer Strap MCH_CFG_12
MCH_CFG_13
J23
E23
CFG_12 DMI_TXP_3 AM43 DMI_MTX_IRX_P3
DMI_MTX_IRX_P3 <22>
CFG_13
Pin Table E20
K23
CFG_14
CFG_15
MCH_CFG_5 R38 1 2 @ 4.02K_0402_1%
MCH_CFG_16 M20 CFG_16
GRAPHICS VID

M24 CFG_17
1

L32 MCH_CFG_7 R39 1 2 @ 4.02K_0402_1%


R40 MCH_CFG_19 CFG_18
B N33 CFG_19 B
@ 56_0402_5% MCH_CFG_20 L35 E35
CFG_20 GFX_VID_0 MCH_CFG_8 R41
GFX_VID_1 A39 1 2 @ 4.02K_0402_1%
C38
2

0_0402_5% GFX_VID_2
GFX_VID_3 B39
<22> PM_BMBUSY# R42 1 2 PM_BMBUSY#_R G41 PM_BM_BUSY#
MCH_CFG_9 R43 1 2 @ 4.02K_0402_1%
R44 1 2 H_DPRSTP#_R L39 E36
<5,21,46> H_DPRSTP# PM_DPRSTP# GFX_VR_EN
0_0402_5% PM_EXTTS#0 L36
<14> PM_EXTTS#0 PM_EXT_TS#_0
<15> PM_EXTTS#1 1 2 PM_EXTTS#1_R J36 PM_EXT_TS#_1
MCH_CFG_12 R46 1 2 @ 4.02K_0402_1%
PM

R45 0_0402_5% GMCH_PWROK AW49


R47 MCH_RSTIN# AV20 PWROK +1.25VS
<18,20,22,28,32,33> PLT_RST# RSTIN#
<4,21> H_THERMTRIP# R632 100_0402_5%
1 2H_THERMTRIP#_R N20 MCH_CFG_13 R48 1 2 @ 4.02K_0402_1%
THERMTRIP#
<22,46> PM_DPRSLPVR
R49 10_0402_5%2PM_DPRSLPVR_R G36 DPRSLPVR

2
0_0402_5%
AM49 R50 MCH_CFG_16 R51 1 2 @ 4.02K_0402_1%
CL_CLK CL_CLK0 <22>
AK50 1K_0402_1%
CL_DATA CL_DATA0 <22>
BJ51 NC_1 CL_PWROK AT43 CL_PWROK <22>
BK51 AN49
ME

CL_RST#0 <22,32>

1
NC_2 CL_RST# CL_VREF
BK50 NC_3 CL_VREF AM50
BL50 NC_4 CFG[17:3] have internal pull up

2
BL49 NC_5
BL3 C73 1 R52 CFG[19:18] have internal pull down
NC_6
BL2 NC_7 392_0402_1%
NC

BK1 NC_8
PM_EXTTS#0 +3VS BJ1 H35 SDVO_SCLK <18>

1
R53 10K_0402_5% NC_9 SDVO_CTRL_CLK 2 +3VS
E1 K36
MISC

NC_10 SDVO_CTRL_DATA SDVO_SDAT <18>


PM_EXTTS#1_R A5 G39 CLKREQB#
NC_11 CLK_REQ# CLKREQB# <16>
R54 10K_0402_5% C51 G40 MCH_ICH_SYNC# <22>
CLKREQB# NC_12 ICH_SYNC# 0.1U_0402_16V4Z MCH_CFG_19 R56
B50 NC_13 1 2
R55 10K_0402_5% A50 @ 4.02K_0402_1%
NC_14 MCH_TEST_1 R57 0_0402_5%
A49 NC_15 TEST_1 A37
A MCH_TEST_2 R58 20K_0402_5% MCH_CFG_20 R59 A
BK2 NC_16 TEST_2 R32 Closed to AM50 pin 1 2
@ 4.02K_0402_1%

CRESTLINE ES_FCBGA1299~D
GMR1@
R60 @ 0_0402_5%
GMCH_PWROK 1 2 VGATE
VGATE <22,33,46>
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title
R61 0_0402_5%
1 2 SYS_PWROK
SYS_PWROK <22,33> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (2/7)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 8 of 48
5 4 3 2 1
5 4 3 2 1

DDRB_SDQ[0..63]
<15> DDRB_SDQ[0..63]
DDRA_SDQ[0..63]
<14> DDRA_SDQ[0..63]
DDRB_SDM[0..7]
<15> DDRB_SDM[0..7]
DDRA_SDM[0..7]
<14> DDRA_SDM[0..7]
DDRB_SMA[0..13]
<15> DDRB_SMA[0..13]
D DDRA_SMA[0..13] D
<14> DDRA_SMA[0..13]

U3D U3E
DDRA_SDQ0 AR43 BB19 DDRB_SDQ0 AP49 AY17
SA_DQ_0 SA_BS_0 DDRA_SBS0# <14> SB_DQ_0 SB_BS_0 DDRB_SBS0# <15>
DDRA_SDQ1 AW44 BK19 DDRB_SDQ1 AR51 BG18
SA_DQ_1 SA_BS_1 DDRA_SBS1# <14> SB_DQ_1 SB_BS_1 DDRB_SBS1# <15>
DDRA_SDQ2 BA45 BF29 DDRB_SDQ2 AW50 BG36
SA_DQ_2 SA_BS_2 DDRA_SBS2# <14> SB_DQ_2 SB_BS_2 DDRB_SBS2# <15>
DDRA_SDQ3 AY46 DDRB_SDQ3 AW51
DDRA_SDQ4 SA_DQ_3 DDRB_SDQ4 SB_DQ_3
AR41 SA_DQ_4 AN51 SB_DQ_4
DDRA_SDQ5 AR45 AT45 DDRA_SDM0 DDRB_SDQ5 AN50 AR50 DDRB_SDM0
DDRA_SDQ6 SA_DQ_5 SA_DM_0 DDRA_SDM1 DDRB_SDQ6 SB_DQ_5 SB_DM_0 DDRB_SDM1
AT42 SA_DQ_6 SA_DM_1 BD44 AV50 SB_DQ_6 SB_DM_1 BD49
DDRA_SDQ7 AW47 BD42 DDRA_SDM2 DDRB_SDQ7 AV49 BK45 DDRB_SDM2
DDRA_SDQ8 SA_DQ_7 SA_DM_2 DDRA_SDM3 DDRB_SDQ8 SB_DQ_7 SB_DM_2 DDRB_SDM3
BB45 SA_DQ_8 SA_DM_3 AW38 BA50 SB_DQ_8 SB_DM_3 BL39
DDRA_SDQ9 BF48 AW13 DDRA_SDM4 DDRB_SDQ9 BB50 BH12 DDRB_SDM4
DDRA_SDQ10 SA_DQ_9 SA_DM_4 DDRA_SDM5 DDRB_SDQ10 SB_DQ_9 SB_DM_4 DDRB_SDM5
BG47 SA_DQ_10 SA_DM_5 BG8 BA49 SB_DQ_10 SB_DM_5 BJ7
DDRA_SDQ11 BJ45 AY5 DDRA_SDM6 DDRB_SDQ11 BE50 BF3 DDRB_SDM6
DDRA_SDQ12 SA_DQ_11 SA_DM_6 DDRA_SDM7 DDRB_SDQ12 SB_DQ_11 SB_DM_6 DDRB_SDM7
BB47 SA_DQ_12 SA_DM_7 AN6 BA51 SB_DQ_12 SB_DM_7 AW2
DDRA_SDQ13 BG50 DDRB_SDQ13 AY49
DDRA_SDQ14 SA_DQ_13 DDRB_SDQ14 SB_DQ_13
BH49 SA_DQ_14 BF50 SB_DQ_14
DDRA_SDQ15 BE45 AT46 DDRA_SDQS0 DDRB_SDQ15 BF49 AT50 DDRB_SDQS0
SA_DQ_15 SA_DQS_0 DDRA_SDQS0 <14> SB_DQ_15 SB_DQS_0 DDRB_SDQS0 <15>

B
DDRA_SDQ16 DDRA_SDQS1 DDRB_SDQ16 DDRB_SDQS1

A
AW43 SA_DQ_16 SA_DQS_1 BE48 DDRA_SDQS1 <14> BJ50 SB_DQ_16 SB_DQS_1 BD50 DDRB_SDQS1 <15>
DDRA_SDQ17 BE44 BB43 DDRA_SDQS2 DDRB_SDQ17 BJ44 BK46 DDRB_SDQS2
SA_DQ_17 SA_DQS_2 DDRA_SDQS2 <14> SB_DQ_17 SB_DQS_2 DDRB_SDQS2 <15>
DDRA_SDQ18 BG42 BC37 DDRA_SDQS3 DDRB_SDQ18 BJ43 BK39 DDRB_SDQS3
SA_DQ_18 SA_DQS_3 DDRA_SDQS3 <14> SB_DQ_18 SB_DQS_3 DDRB_SDQS3 <15>
C DDRA_SDQ19 BE40 BB16 DDRA_SDQS4 DDRB_SDQ19 BL43 BJ12 DDRB_SDQS4 C
SA_DQ_19 SA_DQS_4 DDRA_SDQS4 <14> SB_DQ_19 SB_DQS_4 DDRB_SDQS4 <15>
DDRA_SDQ20 BF44 BH6 DDRA_SDQS5 DDRB_SDQ20 BK47 BL7 DDRB_SDQS5

MEMORY
SA_DQ_20
MEMORY SA_DQS_5 DDRA_SDQS5 <14> SB_DQ_20 SB_DQS_5 DDRB_SDQS5 <15>
DDRA_SDQ21 BH45 BB2 DDRA_SDQS6 DDRB_SDQ21 BK49 BE2 DDRB_SDQS6
SA_DQ_21 SA_DQS_6 DDRA_SDQS6 <14> SB_DQ_21 SB_DQS_6 DDRB_SDQS6 <15>
DDRA_SDQ22 BG40 AP3 DDRA_SDQS7 DDRB_SDQ22 BK43 AV2 DDRB_SDQS7
SA_DQ_22 SA_DQS_7 DDRA_SDQS7 <14> SB_DQ_22 SB_DQS_7 DDRB_SDQS7 <15>
DDRA_SDQ23 BF40 DDRB_SDQ23 BK42
DDRA_SDQ24 SA_DQ_23 DDRB_SDQ24 SB_DQ_23
AR40 SA_DQ_24 BJ41 SB_DQ_24
DDRA_SDQ25 AW40 AT47 DDRA_SDQS0# DDRB_SDQ25 BL41 AU50 DDRB_SDQS0#
SA_DQ_25 SA_DQS#_0 DDRA_SDQS0# <14> SB_DQ_25 SB_DQS#_0 DDRB_SDQS0# <15>
DDRA_SDQ26 AT39 BD47 DDRA_SDQS1# DDRB_SDQ26 BJ37 BC50 DDRB_SDQS1#
SA_DQ_26 SA_DQS#_1 DDRA_SDQS1# <14> SB_DQ_26 SB_DQS#_1 DDRB_SDQS1# <15>
DDRA_SDQ27 AW36 BC41 DDRA_SDQS2# DDRB_SDQ27 BJ36 BL45 DDRB_SDQS2#
SA_DQ_27 SA_DQS#_2 DDRA_SDQS2# <14> SB_DQ_27 SB_DQS#_2 DDRB_SDQS2# <15>
DDRA_SDQ28 AW41 BA37 DDRA_SDQS3# DDRB_SDQ28 BK41 BK38 DDRB_SDQS3#
SA_DQ_28 SA_DQS#_3 DDRA_SDQS3# <14> SB_DQ_28 SB_DQS#_3 DDRB_SDQS3# <15>
DDRA_SDQ29 AY41 BA16 DDRA_SDQS4# DDRB_SDQ29 BJ40 BK12 DDRB_SDQS4#
SA_DQ_29 SA_DQS#_4 DDRA_SDQS4# <14> SB_DQ_29 SB_DQS#_4 DDRB_SDQS4# <15>
DDRA_SDQ30 AV38 BH7 DDRA_SDQS5# DDRB_SDQ30 BL35 BK7 DDRB_SDQS5#

SYSTEM
SYSTEM

SA_DQ_30 SA_DQS#_5 DDRA_SDQS5# <14> SB_DQ_30 SB_DQS#_5 DDRB_SDQS5# <15>


DDRA_SDQ31 AT38 BC1 DDRA_SDQS6# DDRB_SDQ31 BK37 BF2 DDRB_SDQS6#
SA_DQ_31 SA_DQS#_6 DDRA_SDQS6# <14> SB_DQ_31 SB_DQS#_6 DDRB_SDQS6# <15>
DDRA_SDQ32 AV13 AP2 DDRA_SDQS7# DDRB_SDQ32 BK13 AV3 DDRB_SDQS7#
SA_DQ_32 SA_DQS#_7 DDRA_SDQS7# <14> SB_DQ_32 SB_DQS#_7 DDRB_SDQS7# <15>
DDRA_SDQ33 AT13 DDRB_SDQ33 BE11
DDRA_SDQ34 SA_DQ_33 DDRB_SDQ34 SB_DQ_33
AW11 SA_DQ_34 BK11 SB_DQ_34
DDRA_SDQ35 AV11 BJ19 DDRA_SMA0 DDRB_SDQ35 BC11 BC18 DDRB_SMA0
DDRA_SDQ36 SA_DQ_35 SA_MA_0 DDRA_SMA1 DDRB_SDQ36 SB_DQ_35 SB_MA_0 DDRB_SMA1
AU15 SA_DQ_36 SA_MA_1 BD20 BC13 SB_DQ_36 SB_MA_1 BG28
DDRA_SDQ37 AT11 BK27 DDRA_SMA2 DDRB_SDQ37 BE12 BG25 DDRB_SMA2
DDRA_SDQ38 SA_DQ_37 SA_MA_2 DDRA_SMA3 DDRB_SDQ38 SB_DQ_37 SB_MA_2 DDRB_SMA3
BA13 SA_DQ_38 SA_MA_3 BH28 BC12 SB_DQ_38 SB_MA_3 AW17
DDRA_SDQ39 BA11 BL24 DDRA_SMA4 DDRB_SDQ39 BG12 BF25 DDRB_SMA4
DDRA_SDQ40 SA_DQ_39 SA_MA_4 DDRA_SMA5 DDRB_SDQ40 SB_DQ_39 SB_MA_4 DDRB_SMA5

DDR
DDR

BE10 SA_DQ_40 SA_MA_5 BK28 BJ10 SB_DQ_40 SB_MA_5 BE25


DDRA_SDQ41 BD10 BJ27 DDRA_SMA6 DDRB_SDQ41 BL9 BA29 DDRB_SMA6
DDRA_SDQ42 SA_DQ_41 SA_MA_6 DDRA_SMA7 DDRB_SDQ42 SB_DQ_41 SB_MA_6 DDRB_SMA7
BD8 SA_DQ_42 SA_MA_7 BJ25 BK5 SB_DQ_42 SB_MA_7 BC28
DDRA_SDQ43 AY9 BL28 DDRA_SMA8 DDRB_SDQ43 BL5 AY28 DDRB_SMA8
DDRA_SDQ44 SA_DQ_43 SA_MA_8 DDRA_SMA9 DDRB_SDQ44 SB_DQ_43 SB_MA_8 DDRB_SMA9
BG10 SA_DQ_44 SA_MA_9 BA28 BK9 SB_DQ_44 SB_MA_9 BD37
DDRA_SDQ45 AW9 BC19 DDRA_SMA10 DDRB_SDQ45 BK10 BG17 DDRB_SMA10
DDRA_SDQ46 SA_DQ_45 SA_MA_10 DDRA_SMA11 DDRB_SDQ46 SB_DQ_45 SB_MA_10 DDRB_SMA11
BD7 SA_DQ_46 SA_MA_11 BE28 BJ8 SB_DQ_46 SB_MA_11 BE37
DDRA_SDQ47 BB9 BG30 DDRA_SMA12 DDRB_SDQ47 BJ6 BA39 DDRB_SMA12
B DDRA_SDQ48 SA_DQ_47 SA_MA_12 DDRA_SMA13 DDRB_SDQ48 SB_DQ_47 SB_MA_12 DDRB_SMA13 B
BB5 SA_DQ_48 SA_MA_13 BJ16 BF4 SB_DQ_48 SB_MA_13 BG13
DDRA_SDQ49 AY7 DDRB_SDQ49 BH5
DDRA_SDQ50 SA_DQ_49 DDRB_SDQ50 SB_DQ_49
AT5 SA_DQ_50 BG1 SB_DQ_50
DDRA_SDQ51 AT7 DDRB_SDQ51 BC2
DDRA_SDQ52 SA_DQ_51 DDRB_SDQ52 SB_DQ_51
AY6 SA_DQ_52 SA_CAS# BL17 DDRA_SCAS# <14> BK3 SB_DQ_52 SB_CAS# BE17 DDRB_SCAS# <15>
DDRA_SDQ53 BB7 BE18 DDRB_SDQ53 BE4 AV16
SA_DQ_53 SA_RAS# DDRA_SRAS# <14> SB_DQ_53 SB_RAS# DDRB_SRAS# <15>
DDRA_SDQ54 AR5 BA19 DDRB_SDQ54 BD3 BC17
SA_DQ_54 SA_WE# DDRA_SWE# <14> SB_DQ_54 SB_WE# DDRB_SWE# <15>
DDRA_SDQ55 AR8 DDRB_SDQ55 BJ2
DDRA_SDQ56 SA_DQ_55 DDRB_SDQ56 SB_DQ_55
AR9 SA_DQ_56 BA3 SB_DQ_56
DDRA_SDQ57 AN3 DDRB_SDQ57 BB3
DDRA_SDQ58 SA_DQ_57 SA_RCVEN# DDRB_SDQ58 SB_DQ_57 SB_RCVEN#
AM8 SA_DQ_58 SA_RCVEN# AY20 PAD T4 AR1 SB_DQ_58 SB_RCVEN# AY18 PAD T5
DDRA_SDQ59 AN10 DDRB_SDQ59 AT3
DDRA_SDQ60 SA_DQ_59 DDRB_SDQ60 SB_DQ_59
AT9 SA_DQ_60 AY2 SB_DQ_60
DDRA_SDQ61 AN9 DDRB_SDQ61 AY3
DDRA_SDQ62 SA_DQ_61 DDRB_SDQ62 SB_DQ_61
AM9 SA_DQ_62 AU2 SB_DQ_62
DDRA_SDQ63 AN11 DDRB_SDQ63 AT2
SA_DQ_63 SB_DQ_63
CRESTLINE ES_FCBGA1299~D CRESTLINE ES_FCBGA1299~D
GMR1@ GMR1@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (3/7)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 9 of 48
5 4 3 2 1
5 4 3 2 1

U3C
1 2 +1.05VS
R633 0_0402_5%
R62
GM@ 0_0402_5% J40
LBKLT_EN L_BKLT_CTRL PEG_COMP
<33> GMCH_ENBKL 2 1 H39 L_BKLT_EN PEG_COMPI N43 1 2 1 2 +1.25VS
LCTLA_CLK E39 M43 10mils R63 24.9_0402_1% R634 @ 0_0402_5%
LCTLB_DATA L_CTRL_CLK PEG_COMPO
E40 L_CTRL_DATA
<19> GMCH_LCD_CLK GMCH_LCD_CLK C37
GMCH_LCD_DATA L_DDC_CLK PCIE_GTX_C_MRX_N0
D <19> GMCH_LCD_DATA D35 L_DDC_DATA PEG_RX#_0 J51 D
1 2GMCH_ENVDD_R K40 L51 PCIE_GTX_C_MRX_N1 PCIE_MTX_C_GRX_N[0..15]
<19> GMCH_ENVDD L_VDD_EN PEG_RX#_1 PCIE_MTX_C_GRX_N[0..15] <19>
R64 0_0402_5% N47 PCIE_GTX_C_MRX_N2
LVDS_IBG PEG_RX#_2 PCIE_GTX_C_MRX_N3 PCIE_MTX_C_GRX_P[0..15]
L41 LVDS_IBG PEG_RX#_3 T45 PCIE_MTX_C_GRX_P[0..15] <19>
L43 T50 PCIE_GTX_C_MRX_N4
LVDS_VBG PEG_RX#_4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N[0..15]
N41 LVDS_VREFH PEG_RX#_5 U40 PCIE_GTX_C_MRX_N[0..15] <19>
N40 Y44 PCIE_GTX_C_MRX_N6
LVDS_VREFL PEG_RX#_6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P[0..15]
PEG_RX#_7 Y40 PCIE_GTX_C_MRX_P[0..15] <19>
GMCH_TXCLK- D46 AB51 PCIE_GTX_C_MRX_N8
<19> GMCH_TXCLK- LVDSA_CLK# PEG_RX#_8
GMCH_TXCLK+ C45 W49 PCIE_GTX_C_MRX_N9
<19> GMCH_TXCLK+ LVDSA_CLK PEG_RX#_9
GMCH_TZCLK- D44 AD44 PCIE_GTX_C_MRX_N10
<19> GMCH_TZCLK- LVDSB_CLK# PEG_RX#_10

LVDS
GMCH_TZCLK+ E42 AD40 PCIE_GTX_C_MRX_N11
<19> GMCH_TZCLK+ LVDSB_CLK PEG_RX#_11
AG46 PCIE_GTX_C_MRX_N12
GMCH_TXOUT0- PEG_RX#_12 PCIE_GTX_C_MRX_N13
<19> GMCH_TXOUT0- G51 LVDSA_DATA#_0 PEG_RX#_13 AH49
GMCH_TXOUT1- E51 AG45 PCIE_GTX_C_MRX_N14
<19> GMCH_TXOUT1- LVDSA_DATA#_1 PEG_RX#_14
GMCH_TXOUT2- F49 AG41 PCIE_GTX_C_MRX_N15
<19> GMCH_TXOUT2- LVDSA_DATA#_2 PEG_RX#_15

GRAPHICS
J50 PCIE_GTX_C_MRX_P0
GMCH_TXOUT0+ PEG_RX_0 PCIE_GTX_C_MRX_P1
<19> GMCH_TXOUT0+ G50 LVDSA_DATA_0 PEG_RX_1 L50
GMCH_TXOUT1+ E50 M47 PCIE_GTX_C_MRX_P2
<19> GMCH_TXOUT1+ LVDSA_DATA_1 PEG_RX_2
GMCH_TXOUT2+ F48 U44 PCIE_GTX_C_MRX_P3
<19> GMCH_TXOUT2+ LVDSA_DATA_2 PEG_RX_3
T49 PCIE_GTX_C_MRX_P4
PEG_RX_4 PCIE_GTX_C_MRX_P5
PEG_RX_5 T41
GMCH_TZOUT0- G44 W45 PCIE_GTX_C_MRX_P6
<19> GMCH_TZOUT0- LVDSB_DATA#_0 PEG_RX_6
GMCH_TZOUT1- B47 W41 PCIE_GTX_C_MRX_P7
<19> GMCH_TZOUT1- LVDSB_DATA#_1 PEG_RX_7
GMCH_TZOUT2- B45 AB50 PCIE_GTX_C_MRX_P8
<19> GMCH_TZOUT2- LVDSB_DATA#_2 PEG_RX_8
Y48 PCIE_GTX_C_MRX_P9
PEG_RX_9 PCIE_GTX_C_MRX_P10
PEG_RX_10 AC45
GMCH_TZOUT0+ E44 AC41 PCIE_GTX_C_MRX_P11
<19> GMCH_TZOUT0+

PCI-EXPRESS
C GMCH_TZOUT1+ LVDSB_DATA_0 PEG_RX_11 PCIE_GTX_C_MRX_P12 C
<19> GMCH_TZOUT1+ A47 LVDSB_DATA_1 PEG_RX_12 AH47
GMCH_TZOUT2+ A45 AG49 PCIE_GTX_C_MRX_P13
<19> GMCH_TZOUT2+ LVDSB_DATA_2 PEG_RX_13
AH45 PCIE_GTX_C_MRX_P14
PEG_RX_14 PCIE_GTX_C_MRX_P15
PEG_RX_15 AG42

N45 PCIE_MTX_GRX_N0 C74 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0


PEG_TX#_0 PCIE_MTX_GRX_N1 C75
PEG_TX#_1 U39 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N1
GMCH_TV_COMPS E27 U47 PCIE_MTX_GRX_N2 C76 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2
GMCH_TV_LUMA TVA_DAC PEG_TX#_2 PCIE_MTX_GRX_N3 C77
<17> GMCH_TV_LUMA G27 TVB_DAC PEG_TX#_3 N51 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N3
GMCH_TV_CRMA K27 R50 PCIE_MTX_GRX_N4 C78 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4
<17> GMCH_TV_CRMA TVC_DAC PEG_TX#_4
T42 PCIE_MTX_GRX_N5 C79 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N5
PEG_TX#_5

TV
F27 Y43 PCIE_MTX_GRX_N6 C80 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6
TVA_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C81
J27 TVB_RTN PEG_TX#_7 W46 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N7
L27 W38 PCIE_MTX_GRX_N8 C82 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8
TVC_RTN PEG_TX#_8 PCIE_MTX_GRX_N9 C83
PEG_TX#_9 AD39 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N9
TV_DCONSEL_0 M35 AC46 PCIE_MTX_GRX_N10 C84 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10
TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C85
P33 TV_DCONSEL_1 PEG_TX#_11 AC49 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N11
AC42 PCIE_MTX_GRX_N12 C86 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C87
PEG_TX#_13 AH39 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N13
AE49 PCIE_MTX_GRX_N14 C88 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N14
PEG_TX#_14 PCIE_MTX_GRX_N15 C89
PEG_TX#_15 AH44 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N15

H32 M45 PCIE_MTX_GRX_P0 C90 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0


<17> GMCH_CRT_B CRT_BLUE PEG_TX_0
2 1 G32 T38 PCIE_MTX_GRX_P1 C91 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P1
R65 150_0402_1% CRT_BLUE# PEG_TX_1 PCIE_MTX_GRX_P2 C92
<17> GMCH_CRT_G K29 CRT_GREEN PEG_TX_2 T46 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2
2 1 J29 N50 PCIE_MTX_GRX_P3 C93 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P3
CRT_GREEN# PEG_TX_3
VGA

R66 150_0402_1% F29 R51 PCIE_MTX_GRX_P4 C94 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4


<17> GMCH_CRT_R CRT_RED PEG_TX_4
2 1 E29 U43 PCIE_MTX_GRX_P5 C95 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P5
R67 150_0402_1% CRT_RED# PEG_TX_5 PCIE_MTX_GRX_P6 C96
PEG_TX_6 W42 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6
B PCIE_MTX_GRX_P7 C97 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P7 B
PEG_TX_7 Y47 1 2
GMCH_CRT_CLK K33 Y39 PCIE_MTX_GRX_P8 C98 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8
<17> GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8
GMCH_CRT_DATA G35 AC38 PCIE_MTX_GRX_P9 C99 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P9
<17> GMCH_CRT_DATA CRT_DDC_DATA PEG_TX_9
F33 AD47 PCIE_MTX_GRX_P10 C100 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10
<17> GMCH_CRT_VSYNC CRT_HSYNC PEG_TX_10
E33 AC50 PCIE_MTX_GRX_P11 C101 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P11
<17> GMCH_CRT_HSYNC CRT_VSYNC PEG_TX_11
AD43 PCIE_MTX_GRX_P12 C102 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P12
PEG_TX_12
1 2CRT_IREF C32 CRT_TVO_IREF PEG_TX_13 AG39 PCIE_MTX_GRX_P13 C103 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P13
R68 1.3K_0402_5% AE50 PCIE_MTX_GRX_P14 C104 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14
PEG_TX_14 PCIE_MTX_GRX_P15 C105 1
PEG_TX_15 AH43 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P15

+3VS
CRESTLINE ES_FCBGA1299~D
R635 GMR1@
R69 1 GM@ 2 2.2K_0402_5% GMCH_LCD_CLK 1 PM@ 2 0_0402_5%
R636
R70 1 GM@ 2 2.2K_0402_5% GMCH_LCD_DATA 1 PM@ 2 0_0402_5% PCIE_GTX_C_MRX_N1 C106 1 2 1392@ 0.1U_0402_16V4Z SDVO_INT# <18>
R637 PCIE_GTX_C_MRX_P1 C107 1 2 1392@ 0.1U_0402_16V4Z SDVO_INT <18>
R71 1 GM@ 2 10K_0402_5% LCTLB_DATA 1 PM@ 2 0_0402_5%
R638
R72 1 GM@ 2 10K_0402_5% LCTLA_CLK 1 PM@ 2 0_0402_5% PCIE_MTX_GRX_N0 C108 1 2 1392@ 0.1U_0402_16V4Z SDVOB_R# <18>
R639 PCIE_MTX_GRX_P0 C109 1 2 1392@ 0.1U_0402_16V4Z SDVOB_R <18>
R73 1 GM@ 2 2.2K_0402_5% GMCH_CRT_CLK 1 PM@ 2 0_0402_5%
R640 PCIE_MTX_GRX_N1 C110 1 2 1392@ 0.1U_0402_16V4Z SDVOB_G# <18>
R74 1 GM@ 2 2.2K_0402_5% GMCH_CRT_DATA 1 PM@ 2 0_0402_5% PCIE_MTX_GRX_P1 C111 1 2 1392@ 0.1U_0402_16V4Z SDVOB_G <18>
R641
R75 GM@ 2.2K_0402_5% TV_DCONSEL_0 1 PM@ 2 0_0402_5% PCIE_MTX_GRX_N2 C112 1 2 1392@ 0.1U_0402_16V4Z SDVOB_B# <18>
R642 PCIE_MTX_GRX_P2 C113 1 2 1392@ 0.1U_0402_16V4Z SDVOB_B <18>
R76 GM@ 2.2K_0402_5% TV_DCONSEL_1 1 PM@ 2 0_0402_5%
PCIE_MTX_GRX_N3 C114 1 2 1392@ 0.1U_0402_16V4Z
A SDVOB_CLK# <18> A
PCIE_MTX_GRX_P3 C115 1 2 1392@ 0.1U_0402_16V4Z SDVOB_CLK <18>
R77 1 2 100K_0402_5% LBKLT_EN

R78 1 2 2.37K_0402_1% LVDS_IBG

R79 1 2 75_0402_1% GMCH_TV_COMPS


Security Classification Compal Secret Data Compal Electronics, Inc.
R80 1 2 150_0402_1% GMCH_TV_LUMA 2006/06/30 2007/06/30 Title
Issued Date Deciphered Date
R81 1 2 150_0402_1% GMCH_TV_CRMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline(4/7)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 10 of 48
5 4 3 2 1
5 4 3 2 1

U3G

+1.05VS AT35 VCC_1 U3F


AT34 VCC_2 VCC_AXG_NCTF_1 T17 +1.05VS
AH28 VCC_3 VCC_AXG_NCTF_2 T18 +1.05VS AB33 VCC_NCTF_1
AC32 VCC_4 VCC_AXG_NCTF_3 T19 AB36 VCC_NCTF_2
AC31 VCC_5 VCC_AXG_NCTF_4 T21 AB37 VCC_NCTF_3
AK32 VCC_6 VCC_AXG_NCTF_5 T22 AC33 VCC_NCTF_4 VSS_NCTF_1 T27
AJ31 VCC_7 VCC_AXG_NCTF_6 T23 AC35 VCC_NCTF_5 VSS_NCTF_2 T37
AJ28 T25 AC36 U24

VCC CORE
VCC_8 VCC_AXG_NCTF_7 VCC_NCTF_6 VSS_NCTF_3
AH32 VCC_9 VCC_AXG_NCTF_8 U15 AD35 VCC_NCTF_7 VSS_NCTF_4 U28
AH31 VCC_10 VCC_AXG_NCTF_9 U16 AD36 VCC_NCTF_8 VSS_NCTF_5 V31
AH29 VCC_11 VCC_AXG_NCTF_10 U17 AF33 VCC_NCTF_9 VSS_NCTF_6 V35
D AF32 VCC_12 VCC_AXG_NCTF_11 U19 AF36 VCC_NCTF_10 VSS_NCTF_7 AA19 D
VCC_AXG_NCTF_12 U20 AH33 VCC_NCTF_11 VSS_NCTF_8 AB17
VCC_AXG_NCTF_13 U21 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35
VCC_AXG_NCTF_14 U23 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19
+GMCH_VCC_13 R30 U26 AH37 AD37
R82 0_0603_5% VCC_13 VCC_AXG_NCTF_15 VCC_NCTF_14 VSS_NCTF_11
VCC_AXG_NCTF_16 V16 AJ33 VCC_NCTF_15 VSS_NCTF_12 AF17
VCC_AXG_NCTF_17 V17 AJ35 VCC_NCTF_16 VSS_NCTF_13 AF35
VCC_AXG_NCTF_18 V19 AK33 VCC_NCTF_17 VSS_NCTF_14 AK17
VCC_AXG_NCTF_19 V20 AK35 VCC_NCTF_18 VSS_NCTF_15 AM17
V21 AK36 AM24
POWER VCC_AXG_NCTF_20
VCC_AXG_NCTF_21 V23 AK37
VCC_NCTF_19
VCC_NCTF_20
VSS_NCTF_16
VSS_NCTF_17 AP26
VCC_AXG_NCTF_22 V24
+1.05VS VCC: 1300mA AD33 VCC_NCTF_21 VSS_NCTF_18 AP28
Y15 AJ36 AR15
AU32
VCC_AXG_NCTF_23
Y16 (220UF*1, 22UF*1, 0.22UF*1, 0.1UF*1) AM35
VCC_NCTF_22 VSS_NCTF_19
AR19
+1.8V VCC_SM_1 VCC_AXG_NCTF_24 VCC_NCTF_23 VSS_NCTF_20
AU33 VCC_SM_2 VCC_AXG_NCTF_25 Y17 AL33 VCC_NCTF_24 VSS_NCTF_21 AR28
AU35 VCC_SM_3 VCC_AXG_NCTF_26 Y19 1 AL35 VCC_NCTF_25
AV33 VCC_SM_4 VCC_AXG_NCTF_27 Y20 1 1 AA33 VCC_NCTF_26
AW33 Y21 C116 + C117 C118 C119 C120 AA35
VCC_SM_5 VCC_AXG_NCTF_28 VCC_NCTF_27
AW35 VCC_SM_6 VCC_AXG_NCTF_29 Y23 AA36 VCC_NCTF_28
AY35 Y24 220U_D2_2VMR15 0.22U_0603_16V7K 0.1U_0402_16V4Z AP35
VCC_SM_7 VCC_AXG_NCTF_30 2 2 2 VCC_NCTF_29
BA32 VCC_SM_8 VCC_AXG_NCTF_31 Y26 AP36 VCC_NCTF_30 VSS_SCB1 A3
BA33 Y28 22U_0805_6.3V6M 0.22U_0603_16V7K AR35 B2
VCC_SM_9 VCC_AXG_NCTF_32 VCC_NCTF_31 VSS_SCB2
BA35 VCC_SM_10 VCC_AXG_NCTF_33 Y29 AR36 VCC_NCTF_32 VSS_SCB3 C1
BB33 VCC_SM_11 VCC_AXG_NCTF_34 AA16 Y32 VCC_NCTF_33 VSS_SCB4 BL1
BC32 AA17 Y33 BL51
VCC GFX NCTF
VCC_SM_12 VCC_AXG_NCTF_35 VCC_NCTF_34 VSS_SCB5
BC33 VCC_SM_13 VCC_AXG_NCTF_36 AB16 Y35 VCC_NCTF_35 VSS_SCB6 A51
BC35 VCC_SM_14 VCC_AXG_NCTF_37 AB19
+1.8V VCC_SM: 2400mA Y36 VCC_NCTF_36
BD32 AC16 Y37
BD35
VCC_SM_15 VCC_AXG_NCTF_38
AC17 (330UF*1, 22UF*2, 0.1UF*1) T30
VCC_NCTF_37
C
VCC_SM_16 VCC_AXG_NCTF_39 VCC_NCTF_38 C
BE32 AC19 T34
POWER
VCC SM

VCC_SM_17 VCC_AXG_NCTF_40 VCC_NCTF_39


BE33 VCC_SM_18 VCC_AXG_NCTF_41 AD15 1 T35 VCC_NCTF_40
BE35 AD16 C121 1 1 1 U29
VCC_SM_19 VCC_AXG_NCTF_42 + C122 C123 C124 VCC_NCTF_41
BF33 VCC_SM_20 VCC_AXG_NCTF_43 AD17 U31 VCC_NCTF_42
BF34 VCC_SM_21 VCC_AXG_NCTF_44 AF16 U32 VCC_NCTF_43
BG32 AF19 330U_D2E_2.5VM 22U_0805_6.3V6M U33
VCC_SM_22 VCC_AXG_NCTF_45 2 2 2 2 VCC_NCTF_44
BG33 VCC_SM_23 VCC_AXG_NCTF_46 AH15 U35 VCC_NCTF_45
BG35 AH16 22U_0805_6.3V6M 0.1U_0402_16V4Z U36
VCC_SM_24 VCC_AXG_NCTF_47 VCC_NCTF_46
BH32 VCC_SM_25 VCC_AXG_NCTF_48 AH17 V32 VCC_NCTF_47
BH34 VCC_SM_26 VCC_AXG_NCTF_49 AH19 V33 VCC_NCTF_48
BH35 VCC_SM_27 VCC_AXG_NCTF_50 AJ16 V36 VCC_NCTF_49
BJ32 VCC_SM_28 VCC_AXG_NCTF_51 AJ17 V37 VCC_NCTF_50
BJ33 VCC_SM_29 VCC_AXG_NCTF_52 AJ19
+1.05VS VCC_AXG: 7700mA
BJ34 AK16
BK32
VCC_SM_30 VCC_AXG_NCTF_53
AK19 (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)
VCC_SM_31 VCC_AXG_NCTF_54
BK33 VCC_SM_32 VCC_AXG_NCTF_55 AL16 VCC_AXM_1 AT33 +1.05VM_AXM
BK34 VCC_SM_33 VCC_AXG_NCTF_56 AL17 1 1 VCC_AXM_2 AT31
BK35 AL19 C125 C126 C127 1 C128 1 C129 C130 C131 1 C132 1 AK29
VCC_SM_34 VCC_AXG_NCTF_57 + + VCC_AXM_3
BL33 VCC_SM_35 VCC_AXG_NCTF_58 AL20 +1.05VM_AXM AL24 VCC_AXM_NCTF_1 VCC_AXM_4 AK24
AU30 VCC_SM_36 VCC_AXG_NCTF_59 AL21 AL26 VCC_AXM_NCTF_2 VCC_AXM_6 AK23
AL23 330U_D2E_2.5VM 22U_0805_6.3V6M 1U_0603_10V4Z 0.1U_0402_16V4Z AL28 AJ26
VCC_AXG_NCTF_60 2 2 2 2 2 2 VCC_AXM_NCTF_3 VCC_AXM_5
VCC_AXG_NCTF_61 AM15 AM26 VCC_AXM_NCTF_4 VCC_AXM_7 AJ23
AM16 330U_D2E_2.5VM 10U_0805_10V4Z 0.47U_0603_16V4Z 0.1U_0402_16V4Z AM28
VCC_AXG_NCTF_62 VCC_AXM_NCTF_5
VCC_AXG_NCTF_63 AM19 AM29 VCC_AXM_NCTF_6
VCC_AXG_NCTF_64 AM20 AM31 VCC_AXM_NCTF_7
+1.05VS R20 VCC_AXG_1 VCC_AXG_NCTF_65 AM21 AM32 VCC_AXM_NCTF_8
T14 VCC_AXG_2 VCC_AXG_NCTF_66 AM23 AM33 VCC_AXM_NCTF_9
W13 VCC_AXG_3 VCC_AXG_NCTF_67 AP15 AP29 VCC_AXM_NCTF_10
B
W14 VCC_AXG_4 VCC_AXG_NCTF_68 AP16
+1.05VM_AXM VCC_AXM: 540mA AP31 VCC_AXM_NCTF_11 B
Y12 AP17 AP32
AA20
VCC_AXG_5 VCC_AXG_NCTF_69
AP19 (22UF*2, 0.22UF*2, 0.1UF*2) AP33
VCC_AXM_NCTF_12
VCC_AXG_6 VCC_AXG_NCTF_70 VCC_AXM_NCTF_13
AA23 VCC_AXG_7 VCC_AXG_NCTF_71 AP20 +1.05VS AL29 VCC_AXM_NCTF_14
AA26 AP21 R83 0_0805_5% AL31
VCC_AXG_8 VCC_AXG_NCTF_72 VCC_AXM_NCTF_15
AA28 VCC_AXG_9 VCC_AXG_NCTF_73 AP23 1 1 1 1 AL32 VCC_AXM_NCTF_16
AB21 AP24 C133 C134 C135 C136 C137 C138 AR31
VCC_AXG_10 VCC_AXG_NCTF_74 VCC_AXM_NCTF_17
AB24 VCC_AXG_11 VCC_AXG_NCTF_75 AR20 AR32 VCC_AXM_NCTF_18
AB29 AR21 22U_0805_6.3V6M 0.22U_0603_16V7K 0.1U_0402_16V4Z AR33
VCC_AXG_12 VCC_AXG_NCTF_76 2 2 2 2 VCC_AXM_NCTF_19
AC20 VCC_AXG_13 VCC_AXG_NCTF_77 AR23
AC21 AR24 0.22U_0603_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC_AXG_14 VCC_AXG_NCTF_78
AC23 VCC_AXG_15 VCC_AXG_NCTF_79 AR26
AC24 V26 CRESTLINE ES_FCBGA1299~D
VCC GFX

VCC_AXG_16 VCC_AXG_NCTF_80
AC26 VCC_AXG_17 VCC_AXG_NCTF_81 V28 GMR1@
AC28 VCC_AXG_18 VCC_AXG_NCTF_82 V29
AC29 VCC_AXG_19 VCC_AXG_NCTF_83 Y31
AD20 VCC_AXG_20
AD23 VCC_AXG_21
AD24 VCC_AXG_22
AD28 VCC_AXG_23
AF21 AW45 VCCSM_LF1
VCC SM LF

VCC_AXG_24 VCC_SM_LF1 VCCSM_LF2


AF26 VCC_AXG_25 VCC_SM_LF2 BC39
AA31 BE39 VCCSM_LF3
VCC_AXG_26 VCC_SM_LF3 VCCSM_LF4
AH20 VCC_AXG_27 VCC_SM_LF4 BD17
AH21 BD4 VCCSM_LF5
VCC_AXG_28 VCC_SM_LF5 VCCSM_LF6
AH23 VCC_AXG_29 VCC_SM_LF6 AW8
AH24 AT6 VCCSM_LF7
VCC_AXG_30 VCC_SM_LF7
AH26 VCC_AXG_31 1 1
AD31 C139 C140 C141 C142 C143 C144 C145
VCC_AXG_32
A AJ20 VCC_AXG_33 A
AN14 0.1U_0402_16V4Z 0.22U_0603_16V7K 0.47U_0603_16V4Z 1U_0603_10V4Z
VCC_AXG_34 2 2
0.1U_0402_16V4Z 0.22U_0603_16V7K 1U_0603_10V4Z

CRESTLINE ES_FCBGA1299~D
GMR1@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (5/7)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Thursday, September 21, 2006 Sheet 11 of 48
5 4 3 2 1
5 4 3 2 1

+1.25VS_DPLLA
GM@ VCC_SYNC: 10mA (0.1UF*1)
+1.25VS L1 1 2 1 +3VS
MBK1608121YZF_0603 1 1
VCCA_DPLLA: 80mA C147 + C148 C146

(470UF*1, 0.1UF*1) 470U_D2_2.5VMR12 VCCA_CRT_DAC: 80mA+3VS_CRTDAC 0.1U_0402_16V4Z


GM@ 2 GM@ 2 GM@ 2 U3H
0.1U_0402_16V4Z (0.1UF*1, 0.022UF*1) +1.05VS VTT: 850mA
+3VS L2 1 2 J32 (220UF*1, 4.7UF*21, 2.2UF*1, 0.47UF*1)
VCCSYNC

2
MBK1608121YZF_0603 1 U13
+1.25VS_DPLLB GM@ C149 C150 R646 VTT_1
A33 VCCA_CRT_DAC_1 VTT_2 U12 1
D GM@ 0_0402_5% B33 U11 D
L3 1 0.1U_0402_16V4Z PM@ VCCA_CRT_DAC_2 VTT_3 C151 + C152 C153 C154 C155
2 1 VTT_4 U9
MBK1608121YZF_0603 1 VCCA_DAC_BG: 5mA GM@ 2 0.022U_0402_16V7K U8

CRT
1
+3VS_DACBG VTT_5
VCCA_DPLLB: 80mA C156 + C157
(0.1UF*1, 0.022UF*1)
GM@
VTT_6 U7 220U_D2_2VMR15
2
4.7U_0805_10V4Z 0.47U_0603_16V4Z
A30 U5
(470UF*1, 0.1UF*1) 470U_D2_2.5VMR12 +3VS L4 1 2
VCCA_DAC_BG VTT_7
U3 4.7U_0805_10V4Z 2.2U_0805_10V6K
GM@ 2 GM@2 MBK1608121YZF_0603 VTT_8
1 B32 VSSA_DAC_BG VTT_9 U2

2
0.1U_0402_16V4Z C158 C159
+1.25VM_AXDVCC_AXD: 200mA
VTT_10 U1
R645 T13

VTT
0.1U_0402_16V4Z 0_0402_5%
VTT_11
T11 (22UF*1, 1UF*1)
+1.25VS_DPLLA +1.25VS_DPLLB 2 0.022U_0402_16V7K VTT_12
+1.25VS_DPLLA
PM@ B49 VCCA_DPLLA VTT_13 T10 +1.25VS
VCCA_LVDS: 10mA T9 R84 0_0603_5%

1
VTT_14
+1.25VS_DPLLB H49 T7 1
(0.1UF*1) VCCA_DPLLB VTT_15

2
T6 C160 C161

PLL
+1.25VS_HPLL +1.8V_TX_LVDS VTT_16
R647 R648 1 +1.25VS_HPLL AL2 T5
0_0402_5% 0_0402_5% C162 VCCA_HPLL VTT_17 22U_0805_6.3V6M
VTT_18 T3
L5 1 PM@ PM@ GM@ +1.25VS_MPLL 2
+1.25VS 2 AM2 VCCA_MPLL VTT_19 T2
MBK1608121YZF_0603 1 1 1000P_0402_50V7K
2 1 R3 1U_0603_10V4Z

1
VTT_20

2
C163 C164 2 R649 0_0402_5%
VCCA_HPLL: 50mA +3VS
R650 VTT_21 R2
+1.25VS_AXF VCC_AXF: 350mA
1 A41 R1

LVDS
(22UF*1, 0.1UF*1) 22U_0805_6.3V6M C165 0_0402_5% VCCA_LVDS VTT_22
2 2 PM@ B41 (10UF*1, 1UF*1)
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCCA_PEG_BG: 5mA VSSA_LVDS
AT23 +1.25VS

1
2 VCC_AXD_1 R85 0_0603_5%
AU28
(0.1UF*1) K50
VCC_AXD_2
AU24 1
+1.25VS_MPLL VCCA_PEG_BG VCC_AXD_3 C166 C167
K49 AT29

AXD
L6 1 VSSA_PEG_BG VCC_AXD_4
2 +1.25VS_A_PEGPLL AT25

PEG
+1.25VS VCC_AXD_5
L7 1 2 MBK1608121YZF_0603 1 AT30 10U_0805_10V4Z
MBK1608121YZF_0603 C169 VCC_AXD_6 2
1 2 1 U51 VCCA_PEG_PLL
C
VCCA_MPLL: 150mA C170 C168 R86 1_0603_5% VCCA_PEG_PLL: 100mA AR29 1U_0603_10V4Z C
R87 10U_0805_10V4Z 0.1U_0402_16V4Z VCC_AXD_NCTF
(10UF*1, 0.1UF*1) 0.5_0603_1%
2 (0.1UF*1) +1.25VS VCC_DMI: 100mA (0.1UF*1)
2 +1.25VM_A_SM
0.1U_0402_16V4Z
VCCA_SM POWER VCC_AXF_1 B23 1
C171
B21

AXF
1 +1.25VS 1 (22UF*21, 4.7UF*1, 1UF*1) AW18
VCC_AXF_2
A21
R88 0_0603_5% VCCA_SM_1 VCC_AXF_3 0.1U_0402_16V4Z
1 AV19 VCCA_SM_2
C172 C173 + C174 C175 C176 2 +1.8V_SM_CK
AU19 VCCA_SM_3 VCC_SM_CK: 200mA (22UF*1, 0.1UF*1)
10U_0805_10V4Z AU18 VCCA_SM_4 VCC_DMI AJ50
2 150U_D_6.3VM 4.7U_0805_10V4Z AU17 1 2

SM
2 2 VCCA_SM_5 +1.8V
AT22 L8
22U_0805_6.3V6M 1U_0603_10V4Z VCCA_SM_7 MBK1608121YZF_0603
AT21 VCCA_SM_8 VCC_SM_CK_1 BK24 1 1
AT19 BK23 C177 C178

CLK
+1.25VM_A_SM_CK VCCA_SM_9 VCC_SM_CK_2
VCCA_SM_CK AT18 VCCA_SM_10 VCC_SM_CK_3 BJ24
22U_0805_6.3V6M R89
1
C179
2
AT17 BJ23
+1.25VS
(22UF*1, 1UF*2, 0.1UF*1) AR17
VCCA_SM_11 VCC_SM_CK_4 2 2 1_0603_5% 10U_0805_10V4Z
R90 0_0603_5% 1 VCCA_SM_NCTF_1 +1.8V_TX_LVDS 0.1U_0402_16V4Z
1 AR16 VCCA_SM_NCTF_2
C180 C181 C182 C183
A43 GM@
22U_0805_6.3V6M 1U_0603_10V4Z VCC_TX_LVDS
BC29 VCCA_SM_CK_1 1 2 +1.8V
2 2 L9
BB29 VCCA_SM_CK_2 1
1U_0603_10V4Z 0.1U_0402_16V4Z VCC_HV: 100mA 1 MBK1608121YZF_0603

2
+3VS_A_TVDAC C184 + C185
GM@ VCC_HV_1 C40
GM@ GM@
+1.8V_TX_LVDS: 100mA (220UF*1, 1000PF*1)
L10 1
VCCA_TV_DAC: 40mA (0.1UF*1, 0.022UF*1 for each DAC) VCC_HV_2 B40 +3VS_HV
R651 220U_D2_2VMR15
+3VS 2 2 C25 VCCA_TVA_DAC_1
MBK1608121YZF_0603 0_0402_5% 2 2
1 1 1 1 B25 VCCA_TVA_DAC_2
C186 C187 C188 C189 C190 C191 C192 R652 C27 PM@ 1000P_0402_50V7K

1
GM@ GM@ GM@ GM@ GM@ GM@ GM@ 0_0402_5% VCCA_TVB_DAC_1 +1.25VS_PEG
B27 AD51 +1.25VS_PEG: 1200mA (220UF*1, 10UF*1)

TV
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z PM@ VCCA_TVB_DAC_2 VCC_PEG_1
B28 W50

PEG
B 2
10U_0805_10V4Z 2 2 2 VCCA_TVC_DAC_1 VCC_PEG_2 B
A28 W51 1 2 +1.25VS
1

0.022U_0402_16V7K 0.022U_0402_16V7K 0.022U_0402_16V7K VCCA_TVC_DAC_2 VCC_PEG_3 L11


VCC_PEG_4 V49 1
V50 1 @ MBK1608121YZF_0603
R91 PM@0_0603_5% VCC_PEG_5 C193 + C194 1 2 +1.05VS
+1.5VS +1.5VS_CRT M32 L12
+1.5VS

TV/CRT
R92 GM@0_0603_5% VCCD_CRT 220U_D2_2VMR15 MBK1608121YZF_0603
L29 VCCD_TVDAC 2 2
AH50

DMI
VCC_RXR_DMI_1 10U_0805_10V4Z
VCCD_TVDAC: 60mA C195
1
C196
+1.5VS_QDAC N28 VCCD_QDAC VCC_RXR_DMI_2 AH51
+1.25VS_HPLL
(0.1UF*1, 0.022UF*1) 1 VCCA_HPLL: 250mA
0.1U_0402_16V4Z C197 AN2
2 0.022U_0402_16V7K (0.1UF*1) VCCD_HPLL
0.1U_0402_16V4Z +1.25VS_A_PEGPLL U48 A7 VTTLF_CAP1

VTTLF
2 VCCD_PEG_PLL VTTLF1 VTTLF_CAP2
1 VTTLF2 F2
C198 AH1 VTTLF_CAP3
+1.5VS_QDAC +1.5VS_QDAC VTTLF3
GM@ VCCA_PEG_PLL: 100mA 0.1U_0402_16V4Z J41
LVDS

L15 1 2 VCCD_LVDS_1 +3VS_HV +1.05VS_D


+1.5VS 2 H42
(0.1UF*1) VCCD_LVDS_2
2

MBK1608121YZF_0603 1 D44
C201 C202 R653 GM@ 0_0402_5% 10_0402_5% CH751H-40_SC76
GM@
VCCD_QDAC: 5mA 0.1U_0402_16V4Z GM@ 0_0402_5% +1.8V 2 1 C203 C204 C205 1 R656 2 1 R657 2 1 2 +1.05VS
2

PM@ 1 1 R654 0_0402_5% CRESTLINE ES_FCBGA1299~D


(0.1UF*1, 0.022UF*1) 2

0.1U_0402_16V4Z
C775
0.022U_0402_16V7K C206 C207 0.47U_0603_16V4Z 0.47U_0603_16V4Z
1

GMR1@ +3VS
VCCD_LVDS: 150mA GM@ GM@ R655 1 +3VS
10U_0805_10V4Z 0.1U_0402_16V4Z 0_0402_5% 0.47U_0603_16V4Z
(10UF*1, 0.1UF*1) 2 2 PM@ 1
1

C208
2
0.1U_0402_16V4Z
A 2 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (6/7)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 12 of 48
5 4 3 2 1
5 4 3 2 1

U3I U3J

A13 VSS_1 VSS_100 AW24 C46 VSS_199 VSS_287 W11


A15 VSS_2 VSS_101 AW29 C50 VSS_200 VSS_288 W39
A17 VSS_3 VSS_102 AW32 C7 VSS_201 VSS_289 W43
A24 VSS_4 VSS_103 AW5 D13 VSS_202 VSS_290 W47
AA21 VSS_5 VSS_104 AW7 D24 VSS_203 VSS_291 W5
AA24 VSS_6 VSS_105 AY10 D3 VSS_204 VSS_292 W7
AA29 VSS_7 VSS_106 AY24 D32 VSS_205 VSS_293 Y13
AB20 VSS_8 VSS_107 AY37 D39 VSS_206 VSS_294 Y2
AB23 VSS_9 VSS_108 AY42 D45 VSS_207 VSS_295 Y41
AB26 VSS_10 VSS_109 AY43 D49 VSS_208 VSS_296 Y45
D AB28 VSS_11 VSS_110 AY45 E10 VSS_209 VSS_297 Y49 D
AB31 VSS_12 VSS_111 AY47 E16 VSS_210 VSS_298 Y5
AC10 VSS_13 VSS_112 AY50 E24 VSS_211 VSS_299 Y50
AC13 VSS_14 VSS_113 B10 E28 VSS_212 VSS_300 Y11
AC3 VSS_15 VSS_114 B20 E32 VSS_213 VSS_301 P29
AC39 VSS_16 VSS_115 B24 E47 VSS_214 VSS_302 T29
AC43 VSS_17 VSS_116 B29 F19 VSS_215 VSS_303 T31
AC47 VSS_18 VSS_117 B30 F36 VSS_216 VSS_304 T33
AD1 VSS_19 VSS_118 B35 F4 VSS_217 VSS_305 R28
AD21 VSS_20 VSS_119 B38 F40 VSS_218
AD26 VSS_21 VSS_120 B43 F50 VSS_219
AD29 VSS_22 VSS_121 B46 G1 VSS_220
AD3 VSS_23 VSS_122 B5 G13 VSS_221 VSS_306 AA32
AD41 VSS_24 VSS_123 B8 G16 VSS_222 VSS_307 AB32
AD45 VSS_25 VSS_124 BA1 G19 VSS_223 VSS_308 AD32
AD49 VSS_26 VSS_125 BA17 G24 VSS_224 VSS_309 AF28
AD5 VSS_27 VSS_126 BA18 G28 VSS_225 VSS_310 AF29
AD50 VSS_28 VSS_127 BA2 G29 VSS_226 VSS_311 AT27
AD8 VSS_29 VSS_128 BA24 G33 VSS_227 VSS_312 AV25
AE10 VSS_30 VSS_129 BB12 G42 VSS_228 VSS_313 H50
AE14 VSS_31 VSS_130 BB25 G45 VSS_229
AE6 VSS_32 VSS_131 BB40 G48 VSS_230
AF20
AF23
VSS_33
VSS_34
VSS VSS_132
VSS_133
BB44
BB49
G8
H24
VSS_231
VSS_232
AF24
AF31
VSS_35
VSS_36
VSS_134
VSS_135
BB8
BC16
H28
H4
VSS_233
VSS_234
VSS
AG2 VSS_37 VSS_136 BC24 H45 VSS_235
AG38 VSS_38 VSS_137 BC25 J11 VSS_236
AG43 VSS_39 VSS_138 BC36 J16 VSS_237
C AG47 BC40 J2 C
VSS_40 VSS_139 VSS_238
AG50 VSS_41 VSS_140 BC51 J24 VSS_239
AH3 VSS_42 VSS_141 BD13 J28 VSS_240
AH40 VSS_43 VSS_142 BD2 J33 VSS_241
AH41 VSS_44 VSS_143 BD28 J35 VSS_242
AH7 VSS_45 VSS_144 BD45 J39 VSS_243
AH9 VSS_46 VSS_145 BD48
AJ11 VSS_47 VSS_146 BD5 K12 VSS_245
AJ13 VSS_48 VSS_147 BE1 K47 VSS_246
AJ21 VSS_49 VSS_148 BE19 K8 VSS_247
AJ24 VSS_50 VSS_149 BE23 L1 VSS_248
AJ29 VSS_51 VSS_150 BE30 L17 VSS_249
AJ32 VSS_52 VSS_151 BE42 L20 VSS_250
AJ43 VSS_53 VSS_152 BE51 L24 VSS_251
AJ45 VSS_54 VSS_153 BE8 L28 VSS_252
AJ49 VSS_55 VSS_154 BF12 L3 VSS_253
AK20 VSS_56 VSS_155 BF16 L33 VSS_254
AK21 VSS_57 VSS_156 BF36 L49 VSS_255
AK26 VSS_58 VSS_157 BG19 M28 VSS_256
AK28 VSS_59 VSS_158 BG2 M42 VSS_257
AK31 VSS_60 VSS_159 BG24 M46 VSS_258
AK51 VSS_61 VSS_160 BG29 M49 VSS_259
AL1 VSS_62 VSS_161 BG39 M5 VSS_260
AM11 VSS_63 VSS_162 BG48 M50 VSS_261
AM13 VSS_64 VSS_163 BG5 M9 VSS_262
AM3 VSS_65 VSS_164 BG51 N11 VSS_263
AM4 VSS_66 VSS_165 BH17 N14 VSS_264
AM41 VSS_67 VSS_166 BH30 N17 VSS_265
AM45 VSS_68 VSS_167 BH44 N29 VSS_266
B B
AN1 VSS_69 VSS_168 BH46 N32 VSS_267
AN38 VSS_70 VSS_169 BH8 N36 VSS_268
AN39 VSS_71 VSS_170 BJ11 N39 VSS_269
AN43 VSS_72 VSS_171 BJ13 N44 VSS_270
AN5 VSS_73 VSS_172 BJ38 N49 VSS_271
AN7 VSS_74 VSS_173 BJ4 N7 VSS_272
AP4 VSS_75 VSS_174 BJ42 P19 VSS_273
AP48 VSS_76 VSS_175 BJ46 P2 VSS_274
AP50 VSS_77 VSS_176 BK15 P23 VSS_275
AR11 VSS_78 VSS_177 BK17 P3 VSS_276
AR2 VSS_79 VSS_178 BK25 P50 VSS_277
AR39 VSS_80 VSS_179 BK29 R49 VSS_278
AR44 VSS_81 VSS_180 BK36 T39 VSS_279
AR47 VSS_82 VSS_181 BK40 T43 VSS_280
AR7 VSS_83 VSS_182 BK44 T47 VSS_281
AT10 VSS_84 VSS_183 BK6 U41 VSS_282
AT14 VSS_85 VSS_184 BK8 U45 VSS_283
AT41 VSS_86 VSS_185 BL11 U50 VSS_284
AT49 VSS_87 VSS_186 BL13 V2 VSS_285
AU1 VSS_88 VSS_187 BL19 V3 VSS_286
AU23 VSS_89 VSS_188 BL22
AU29 VSS_90 VSS_189 BL37
AU3 VSS_91 VSS_190 BL47 CRESTLINE ES_FCBGA1299~D
AU36 VSS_92 VSS_191 C12 GMR1@
AU49 VSS_93 VSS_192 C16
AU51 VSS_94 VSS_193 C19
AV39 VSS_95 VSS_194 C28
AV48 VSS_96 VSS_195 C29
A AW1 VSS_97 VSS_196 C33 A
AW12 VSS_98 VSS_197 C36
AW16 VSS_99 VSS_198 C41

CRESTLINE ES_FCBGA1299~D
GMR1@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (7/7)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Thursday, September 21, 2006 Sheet 13 of 48
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V

JP3 +1.8V
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ6
VSS DQ4

1
DDRA_SDQ5 5 6 DDRA_SDQ4
DDRA_SDQ0 DQ0 DQ5 R93
7 DQ1 VSS 8
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 1K_0402_1%
<9> DDRA_SDQS0# 11 DQS0# VSS 12
DDRA_SDQS0 13 14 DDRA_SDQ2 20mils

2
<9> DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ1
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ7 17 18
DQ2 VSS

1
DDRA_SDQ3 19 20 DDRA_SDQ9 1 1
DQ3 DQ12 DDRA_SDQ8 C209 C210 R94
21 VSS DQ13 22
DDRA_SDQ13 23 24
D DDRA_SDQ12 DQ8 VSS DDRA_SDM1 0.1U_0402_16V4Z 2.2U_0805_10V6K 1K_0402_1% D
25 DQ9 DM1 26
2 2
27 28

2
DDRA_SDQS1# VSS VSS
<9> DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0 <8>
DDRA_SDQS1 31 32
<9> DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# <8>
33 VSS VSS 34
DDRA_SDQ14 35 36 DDRA_SDQ11
DDRA_SDQ15 DQ10 DQ14 DDRA_SDQ10
37 DQ11 DQ15 38
39 VSS VSS 40
DDRA_SMA[0..13]
<9> DDRA_SMA[0..13]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDQ[0..63]
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 <9> DDRA_SDQ[0..63]
45 DQ17 DQ21 46
47 48 0_0402_5% DDRA_SDM[0..7]
VSS VSS <9> DDRA_SDM[0..7]
DDRA_SDQS2# 49 50 R95 1 2
<9> DDRA_SDQS2# DQS2# NC PM_EXTTS#0 <8> +1.8V
DDRA_SDQS2 51 52 DDRA_SDM2
<9> DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRA_SDQ18 55 56 DDRA_SDQ23
DDRA_SDQ22 DQ18 DQ22 DDRA_SDQ19
57 DQ19 DQ23 58
59 VSS VSS 60 1 1 1 1 1
DDRA_SDQ24 61 62 DDRA_SDQ28 C211 C212 C213 C214 C215
DDRA_SDQ25 DQ24 DQ28 DDRA_SDQ29
63 DQ25 DQ29 64
65 66 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
DDRA_SDM3 VSS VSS DDRA_SDQS3# 2 2 2 2 2
67 DM3 DQS3# 68 DDRA_SDQS3# <9>
69 70 DDRA_SDQS3 +0.9VS
NC DQS3 DDRA_SDQS3 <9>
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ31
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ30
75 DQ27 DQ31 76
77 78 DDR_A_MA14 1 2 +1.8V
DDRA_CKE0 VSS VSS DDRA_CKE1 R728 56_0402_1%
<8> DDRA_CKE0 79 CKE0 NC/CKE1 80 DDRA_CKE1 <8>
81 VDD VDD 82
83 84 DDRA_CKE0 1 4
C DDRA_SBS2# NC NC/A15 DDR_A_MA14 DDRA_SBS2# C
<9> DDRA_SBS2# 85 BA2 NC/A14 86 DDR_A_MA14 <8> Add for using DDR2 2 3 1 1 1 1
87 88 RP1 56_0404_4P2R_5% C216 C217 C218 C219
DDRA_SMA12 89
VDD VDD
90 DDRA_SMA11 2Gb tech. 8/28
DDRA_SMA9 A12 A11 DDRA_SMA7 DDRA_SMA12 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
91 A9 A7 92 1 4
DDRA_SMA8 DDRA_SMA6 DDRA_SMA9 2 2 2 2
93 A8 A6 94 2 3
95 96 RP2 56_0404_4P2R_5%
DDRA_SMA5 VDD VDD DDRA_SMA4
97 A5 A4 98
DDRA_SMA3 99 100 DDRA_SMA2 DDRA_SMA8 1 4
DDRA_SMA1 A3 A2 DDRA_SMA0 DDRA_SMA5
101 A1 A0 102 2 3
103 104 RP3 56_0404_4P2R_5%
DDRA_SMA10 VDD VDD DDRA_SBS1#
105 A10/AP BA1 106 DDRA_SBS1# <9>
DDRA_SBS0# 107 108 DDRA_SRAS# DDRA_SMA3 1 4
<9> DDRA_SBS0# BA0 RAS# DDRA_SRAS# <9> +0.9VS
DDRA_SWE# 109 110 DDRA_SCS0# DDRA_SMA1 2 3
<9> DDRA_SWE# WE# S0# DDRA_SCS0# <8>
111 112 RP4 56_0404_4P2R_5%
DDRA_SCAS# VDD VDD DDRA_ODT0
<9> DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 <8>
DDRA_SCS1# 115 116 DDRA_SMA13 DDRA_SMA10 1 4
<8> DDRA_SCS1# NC/S1# NC/A13
117 118 DDRA_SBS0# 2 3 1 1 1 1 1
DDRA_ODT1 VDD VDD RP5 56_0404_4P2R_5% C220 C221 C222 C223 C224
<8> DDRA_ODT1 119 NC/ODT1 NC 120
121 VSS VSS 122
DDRA_SDQ37 123 124 DDRA_SDQ32 DDRA_SWE# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ36 DQ32 DQ36 DDRA_SDQ33 DDRA_SCAS# 2 2 2 2 2
125 DQ33 DQ37 126 2 3
127 128 RP6 56_0404_4P2R_5%
DDRA_SDQS4# VSS VSS DDRA_SDM4
<9> DDRA_SDQS4# 129 DQS4# DM4 130
DDRA_SDQS4 131 132 DDRA_SCS1# 1 4
<9> DDRA_SDQS4 DQS4 VSS DDRA_SDQ34 DDRA_ODT1
133 VSS DQ38 134 2 3
DDRA_SDQ35 135 136 DDRA_SDQ39 RP7 56_0404_4P2R_5% +0.9VS
DDRA_SDQ38 DQ34 DQ39
137 DQ35 VSS 138
139 140 DDRA_SDQ45
DDRA_SDQ40 VSS DQ44 DDRA_SDQ44
141 DQ40 DQ45 142
DDRA_SDQ41 143 144 DDRA_SMA11 1 4 1 1 1 1 1
DQ41 VSS DDRA_SDQS5# DDRA_CKE1 C225 C226 C227 C228 C229
145 VSS DQS5# 146 DDRA_SDQS5# <9> 2 3
DDRA_SDM5 147 148 DDRA_SDQS5 RP8 56_0404_4P2R_5%
B DM5 DQS5 DDRA_SDQS5 <9> 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
149 VSS VSS 150
DDRA_SDQ42 DDRA_SDQ47 DDRA_SMA6 2 2 2 2 2
151 DQ42 DQ46 152 1 4
DDRA_SDQ46 153 154 DDRA_SDQ43 DDRA_SMA7 2 3
DQ43 DQ47 RP9 56_0404_4P2R_5%
155 VSS VSS 156
DDRA_SDQ49 157 158 DDRA_SDQ52
DDRA_SDQ48 DQ48 DQ52 DDRA_SDQ53 DDRA_SMA2
159 DQ49 DQ53 160 1 4
161 162 DDRA_SMA4 2 3 +0.9VS
VSS VSS RP10 56_0404_4P2R_5%
163 NC,TEST CK1 164 DDRA_CLK1 <8>
165 VSS CK1# 166 DDRA_CLK1# <8>
DDRA_SDQS6# 167 168 DDRA_SBS1# 1 4
<9> DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6 DDRA_SMA0
<9> DDRA_SDQS6 169 DQS6 DM6 170 2 3 1 1 1
171 172 RP11 56_0404_4P2R_5% C230 C231 C232
DDRA_SDQ54 VSS VSS DDRA_SDQ51
173 DQ50 DQ54 174
DDRA_SDQ50 175 176 DDRA_SDQ55 DDRA_SCS0# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DQ51 DQ55 DDRA_SRAS# 2 2 2
177 VSS VSS 178 2 3
DDRA_SDQ60 179 180 DDRA_SDQ57 RP12 56_0404_4P2R_5%
DDRA_SDQ61 DQ56 DQ60 DDRA_SDQ56
181 DQ57 DQ61 182
183 184 DDRA_SMA13 1 4
DDRA_SDM7 VSS VSS DDRA_SDQS7# DDRA_ODT0
185 DM7 DQS7# 186 DDRA_SDQS7# <9> 2 3
187 188 DDRA_SDQS7 RP13 56_0404_4P2R_5%
DDRA_SDQ59 VSS DQS7 DDRA_SDQS7 <9>
189 DQ58 VSS 190
DDRA_SDQ58 191 192 DDRA_SDQ62
DQ59 DQ62 DDRA_SDQ63
193 VSS DQ63 194
D_CK_SDATA 195 196
5,16,22,27,32> ICH_SMBDATA SDA VSS
D_CK_SCLK 197 198 R96 1 2 10K_0402_5%
5,16,22,27,32> ICH_SMBCLK SCL SAO
+3VS 199 200 R97 1 2 10K_0402_5%
VDDSPD SA1

P-TWO_A5692B-A0G16-P

A
DIMM0 STD H:9.2mm (BOT) A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 14 of 48
5 4 3 2 1
A B C D E

+1.8V +1.8V

JP4
1 2 +DIMM_VREF +1.8V
+DIMM_VREF VREF VSS
3 4 DDRB_SDQ5
DDRB_SDQ0 VSS DQ4 DDRB_SDQ4
5 DQ0 DQ5 6
DDRB_SDQ1 7 8 1 1
DQ1 VSS DDRB_SDM0
9 VSS DM0 10 1 1
DDRB_SDQS0# 11 12 C235 C236 C233+ C234 +
<9> DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6
<9> DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7 2.2U_0805_10V6K @ 150U_D2_6.3VM
DDRB_SDQ2 VSS DQ7 2 2
0.1U_0402_16V4Z 2 2
330U_D2E_2.5VM_R9
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ9 23 24
1 DDRB_SDQ10 DQ8 VSS DDRB_SDM1 1
25 DQ9 DM1 26
27 VSS VSS 28
DDRB_SDQS1# 29 30
<9> DDRB_SDQS1# DQS1# CK0 DDRB_CLK0 <8>
DDRB_SDQS1 31 32
<9> DDRB_SDQS1 DQS1 CK0# DDRB_CLK0# <8>
33 VSS VSS 34
DDRB_SDQ8 35 36 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDRB_SDQ17 43 44 DDRB_SDQ21 DDRB_SMA[0..13]
DQ16 DQ20 <9> DDRB_SMA[0..13]
DDRB_SDQ20 45 46 DDRB_SDQ16
DQ17 DQ21 0_0402_5% DDRB_SDQ[0..63]
47 VSS VSS 48 <9> DDRB_SDQ[0..63]
DDRB_SDQS2# 49 50 R98 1 2
<9> DDRB_SDQS2# DQS2# NC PM_EXTTS#1 <8> DDRB_SDM[0..7]
DDRB_SDQS2 51 52 DDRB_SDM2 <9> DDRB_SDM[0..7]
<9> DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22 +1.8V
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ29
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ28
63 DQ25 DQ29 64 1 1 1 1 1
65 66 C241 C242 C243 C244 C245
DDRB_SDM3 VSS VSS DDRB_SDQS3#
67 DM3 DQS3# 68 DDRB_SDQS3# <9>
69 70 DDRB_SDQS3 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
NC DQS3 DDRB_SDQS3 <9> 2 2
2.2U_0805_10V6K 2 2
2.2U_0805_10V6K 2
71 VSS VSS 72
DDRB_SDQ26 73 74 DDRB_SDQ30 +0.9VS
DDRB_SDQ31 DQ26 DQ30 DDRB_SDQ27
75 DQ27 DQ31 76
77 VSS VSS 78
DDRB_CKE0 79 80 DDRB_CKE1
<8> DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 <8> +1.8V
81 82 DDR_B_MA14 1 2
VDD VDD R729 56_0402_1%
83 NC NC/A15 84
2 DDRB_SBS2# DDR_B_MA14 2
<9> DDRB_SBS2# 85 BA2 NC/A14 86 DDR_B_MA14 <8> Add for using DDR2
87 88 DDRB_CKE0 1 4
DDRB_SMA12 89
VDD VDD
90 DDRB_SMA11 2Gb tech. 8/28 DDRB_SBS2# 2 3
A12 A11 1 1 1 1
DDRB_SMA9 91 92 DDRB_SMA7 RP14 56_0404_4P2R_5% C246 C247 C248 C249
DDRB_SMA8 A9 A7 DDRB_SMA6
93 A8 A6 94
95 96 DDRB_SMA12 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SMA9 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
97 A5 A4 98 2 3
DDRB_SMA3 99 100 DDRB_SMA2 RP15 56_0404_4P2R_5%
DDRB_SMA1 A3 A2 DDRB_SMA0
101 A1 A0 102
103 104 DDRB_SMA8 1 4
DDRB_SMA10 VDD VDD DDRB_SBS1# DDRB_SMA5
105 A10/AP BA1 106 DDRB_SBS1# <9> 2 3
DDRB_SBS0# 107 108 DDRB_SRAS# RP16 56_0404_4P2R_5%
<9> DDRB_SBS0# BA0 RAS# DDRB_SRAS# <9>
DDRB_SWE# 109 110 DDRB_SCS0#
<9> DDRB_SWE# WE# S0# DDRB_SCS0# <8>
111 112 DDRB_SMA3 1 4
DDRB_SCAS# VDD VDD DDRB_ODT0 DDRB_SMA1 +0.9VS
<9> DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 <8> 2 3
DDRB_SCS1# 115 116 DDRB_SMA13 RP17 56_0404_4P2R_5%
<8> DDRB_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120 DDRB_SMA10 1 4
<8> DDRB_ODT1 NC/ODT1 NC
121 122 DDRB_SBS0# 2 3 1 1 1 1 1
DDRB_SDQ32 VSS VSS DDRB_SDQ33 RP18 56_0404_4P2R_5% C250 C251 C252 C253 C254
123 DQ32 DQ36 124
DDRB_SDQ36 125 126 DDRB_SDQ37
DQ33 DQ37 DDRB_SWE# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
127 VSS VSS 128 1 4
DDRB_SDQS4# DDRB_SDM4 DDRB_SCAS# 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
<9> DDRB_SDQS4# 129 DQS4# DM4 130 2 3
DDRB_SDQS4 131 132 RP19 56_0404_4P2R_5%
<9> DDRB_SDQS4 DQS4 VSS DDRB_SDQ35
133 VSS DQ38 134
DDRB_SDQ38 135 136 DDRB_SDQ34 DDRB_SCS1# 1 4
DDRB_SDQ39 DQ34 DQ39 DDRB_ODT1
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ40 RP20 56_0404_4P2R_5% +0.9VS
DDRB_SDQ45 VSS DQ44 DDRB_SDQ41
141 DQ40 DQ45 142
DDRB_SDQ44 143 144
DQ41 VSS DDRB_SDQS5# DDRB_SMA11
145 VSS DQS5# 146 DDRB_SDQS5# <9> 1 4
DDRB_SDM5 147 148 DDRB_SDQS5 DDRB_CKE1 2 3 1 1 1 1 1
3 DM5 DQS5 DDRB_SDQS5 <9> RP21 56_0404_4P2R_5% C255 C256 C257 C258 C259 3
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ43
DDRB_SDQ47 DQ42 DQ46 DDRB_SDQ46 DDRB_SMA6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
153 DQ43 DQ47 154 1 4
DDRB_SMA7 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
155 VSS VSS 156 2 3
DDRB_SDQ49 157 158 DDRB_SDQ52 RP22 56_0404_4P2R_5%
DDRB_SDQ48 DQ48 DQ52 DDRB_SDQ53
159 DQ49 DQ53 160
161 162 DDRB_SMA2 1 4
VSS VSS DDRB_SMA4 +0.9VS
163 NC,TEST CK1 164 DDRB_CLK1 <8> 2 3
165 166 RP23 56_0404_4P2R_5%
VSS CK1# DDRB_CLK1# <8>
DDRB_SDQS6# 167 168
<9> DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SBS1#
<9> DDRB_SDQS6 169 DQS6 DM6 170 1 4
171 172 DDRB_SMA0 2 3 1 1 1
DDRB_SDQ55 VSS VSS DDRB_SDQ54 RP24 56_0404_4P2R_5% C260 C261 C262
173 DQ50 DQ54 174
DDRB_SDQ50 175 176 DDRB_SDQ51
DQ51 DQ55 DDRB_SCS0# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
177 VSS VSS 178 1 4
DDRB_SDQ60 DDRB_SDQ61 DDRB_SRAS# 2 2
0.1U_0402_16V4Z 2
179 DQ56 DQ60 180 2 3
DDRB_SDQ56 181 182 DDRB_SDQ57 RP25 56_0404_4P2R_5%
DQ57 DQ61
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7# DDRB_SMA13 1 4
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# <9> DDRB_ODT0
187 VSS DQS7 188 DDRB_SDQS7 <9> 2 3
DDRB_SDQ59 189 190 RP26 56_0404_4P2R_5%
DDRB_SDQ58 DQ58 VSS DDRB_SDQ62
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
D_CK_SDATA VSS DQ63
6,22,27,32> ICH_SMBDATA 195 SDA VSS 196
D_CK_SCLK 197 198 1 2
6,22,27,32> ICH_SMBCLK SCL SAO
+3VS 199 200 R99 1 2 10K_0402_5% +3VS
VDDSPD SA1 R100 10K_0402_5%

PTI_A5652D-A0G16-P

4
DIMM1 STD H:5.2mm (BOT) 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 15 of 48
A B C D E
5 4 3 2 1

C263 1 CLK_48M_ICH
FSLC FSLB FSLA CPU SRC PCI 2
@ 5P_0402_50V8C
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz C264 2 1 CLK_14M_ICH
@ 4.7P_0402_50V8C
+3VS +3VS_CK505 C265 2 1 CLK_PCI_ICH
0 1 0 200 100 33.3 C269 C271 C273 @ 4.7P_0402_50V8C
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C267 2 1 CLK_PCI_EC
R101 0_1206_5% 1 1 1 1 1 1 1 @ 4.7P_0402_50V8C
0 1 1 166 100 33.3 C274 C275 2 1 CLK_PCI_PCM
0.1U_0402_16V4Z @ 4.7P_0402_50V8C
C276 1 CLK_PCI_SIO
FSB Frequency Selet: 2 2 2 2 2 2 2
2
@ 4.7P_0402_50V8C
C268 C270 C272 C829 2 1 CLK_48M_CB
CPU Driven Stuff R108 R130 R149 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z @ 4.7P_0402_50V8C
D D

*(Default) No Stuff R103 R110 R122 R152 +1.25VS +1.25VS_CK505 Place close to U4

Stuff R103 R110 R149 R152 R102


0_1206_5% C278 C280 C282
667MHz 2 1 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
No Stuff R108 R122 R130 1 1 1 1 1 1 1

Stuff R149 R152 2 2 2 2 2 2 2


800MHz
C277 C279 C281 C777
No Stuff R103 R108 R110 R122 R130 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3VS_CK505 U4

2 VDDPCI NC 48
9 VDD48
16 VDDPLL3
61 VDDREF
+1.05VS +3VS 64
SCLK ICH_SMBCLK <14,15,22,27,32>
39 VDDSRC SDATA 63 ICH_SMBDATA <14,15,22,27,32>
55 VDDCPU
2

PCI_STOP# 38 PM_STP_PCI# <22>


@ R103 37 PM_STP_CPU# <22>
56_0402_5% PCI_CLK0 CPU_STOP#
2 1 +1.25VS_CK505 12 VDD96_IO
R104 CLK_Rd R665 10K_0402_5% 20
2.2K_0402_5% PCI_CLK1 VDDPLL3_IO
2 1 26
1

FSA 2 R666 10K_0402_5% VDDSRC_IO R_CPU_BCLK 0_0402_5% R106


1 1 2 MCH_CLKSEL0 <8> CPU0 54 1 2 CLK_CPU_BCLK <4>
36 53 R_CPU_BCLK# 0_0402_5% 1 2 R107
VDDSRC_IO CPU0# CLK_CPU_BCLK# <4>
1 2 R105 49
C <5> CPU_BSEL0 VDDCPU_IO C
R108 1K_0402_5%
0_0402_5%
1

CLK_Ra 51 R_MCH_BCLK 0_0402_5% 1 2 R109


CPU1_F CLK_MCH_BCLK <7>
R110 50 R_MCH_BCLK# 0_0402_5% 1 2 R111
CPU1#_F CLK_MCH_BCLK# <7>
@ 1K_0402_5%
47 R_PCIE_NAND 0_0402_5% 1 2 R112
CLK_PCIE_CARD <27>
2

SRC8/CPU2_ITP R_PCIE_NAND#0_0402_5% R113


SRC8#/CPU2_ITP# 46 1 2 CLK_PCIE_CARD# <27>
R114 2 1 475_0402_1% PCI_CLK0 1
<22> CLKSATAREQ# PCI0/CR#_A
R115 2 1 475_0402_1% PCI_CLK1 3 34 R_CLK_PCIE_LAN 0_0402_5%1 2 R116
<8> CLKREQB# PCI1/CR#_B SRC10 CLK_PCIE_LAN <28>
35 R_CLK_PCIE_LAN#0_0402_5%1 2 R117
+1.05VS SRC10# CLK_PCIE_LAN# <28>
CLK_PCI_SIO R118 1 2 33_0402_5% PCI2_TME 4
<37> CLK_PCI_SIO PCI2/TME
CLK_PCI_EC R120 1 2 33_0402_5% PCI_CLK3 5
<33> CLK_PCI_EC PCI3
2

33 R_PCIE_VGA 0_0402_5%1 PM@ 2 R157 PCIE_VGA


SRC11/CR#_H CLK_PCIE_VGA <19>
R122 CLK_PCI_PCM R123 1 2 33_0402_5% 27_SEL 6 32 R_PCIE_VGA# 0_0402_5%1 PM@ 2 R158 PCIE_VGA#
<25> CLK_PCI_PCM PCI4/27_Select SRC11#/CR#_G CLK_PCIE_VGA# <19>
@ 1K_0402_5% CLK_PCI_ICH R125 1 2 33_0402_5% ITP_EN 7
<20> CLK_PCI_ICH PCI_F5/ITP_EN 0_0402_5%
1

FSB 1 2 30 R_CLK_PCIE_CARD 1 2 R128


MCH_CLKSEL1 <8> SRC9 CLK_PCIE_NAND <32>
31 R_CLK_PCIE_CARD# 1 2 R129
SRC9# CLK_PCIE_NAND# <32>
1 2 R127 CLK_XTAL_IN 60 0_0402_5%
<5> CPU_BSEL1 X1
R130 1K_0402_5% R131 1 2 10K_0402_5% +3VS
0_0402_5% CLK_XTAL_OUT 59 X2
1

CLK_Rb 44 R_CLKREQ#_F 475_0402_1%2 1 R132


SRC7/CR#_F EXP_CLKREQ# <27>
@ R133 43 R_CLKREQ#_E 475_0402_1%2 1 R134 For WLAN REQ
SRC7#/CR#_E WLAN_CLKREQ# <32>
0_0402_5% Change to 0 ohm 8/28 R135 1 2 10K_0402_5% +3VS
CLK_Re
2

0_0402_5%
B R_CLK_PCIE_MCARD R136 B
SRC6 41 1 2 CLK_PCIE_MCARD <32>
CLK_48M_ICH R137 1 2 15_0402_1% FSA 10 40 R_CLK_PCIE_MCARD# 1 2 R138
<22> CLK_48M_ICH USB_48MHZ/FSLA SRC6# CLK_PCIE_MCARD# <32>
CLK_48M_CB R139 1 2 15_0402_1% 0_0402_5%
+1.05VS <25> CLK_48M_CB
FSB 57 FSLB/TEST_MODE R_MCH_3GPLL 0_0402_5%1 R140
SRC4 27 2 CLK_MCH_3GPLL <8>
2

28 R_MCH_3GPLL# 0_0402_5%1 2 R141


SRC4# CLK_MCH_3GPLL# <8>
R142 <22> CLK_14M_ICH CLK_14M_ICH R143 1 2 15_0402_1% FSC 62
CLK_14M_SIO R756 1 REF0/FSLC/TEST_SEL
<37> CLK_14M_SIO 2 15_0402_1%
R146 @ 1K_0402_5%
10K_0402_5% 24 R_PCIE_ICH 0_0402_5%1 2 R145
CLK_PCIE_ICH <22>
1

FSC SRC3/CR#_C R_PCIE_ICH# 0_0402_5%1 R148


2 1 1 2 MCH_CLKSEL2 <8> +1.25VS_CK505 45 VDDSRC_IO SRC3#/CR#_D 25 2 CLK_PCIE_ICH# <22>
1 2 R147
<5> CPU_BSEL2
R149 1K_0402_5% For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
0_0402_5% 21 R_PCIE_SATA 0_0402_5%1 2 R150
SRC2/SATA CLK_PCIE_SATA <21>
1

CLK_Rc For SRC5_EN, 0 = Enable DOT96 & SRC1 42 22 R_PCIE_SATA# 0_0402_5%1 2 R151
GNDSRC SRC2#/SATA# CLK_PCIE_SATA# <21>
@ R152
1 = Enable SRC0 & 27MHz 8 GNDPCI
0_0402_5% CK_PWRGD
CLK_Rf For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed 11 17 CLK_PCIE0 0_0402_5%1 2 R153 1
CLK_DREF_SSC <8>
2

GND48 SRC1/SE1/27MHz_NonSS

2
18 CLK_PCIE0# 0_0402_5%1 2 R154
SRC1#/SE2/27MHz_SS CLK_DREF_SSC# <8>
1 = Overclocking of CPU and SRC NOT allowed 15 R162 C283
GND @ 1K_0402_5% @ 0.1U_0402_16V4Z
2
19 GND
13 R_CLK_DOT 0_0402_5%1 GM@ 2 R155 CLK_DOT CLK_DREF_96M <8>

1
+3VS +3VS +3VS SRC0/DOT96 R_CLK_DOT#
52 GNDCPU SRC0#/DOT96# 14 0_0402_5%1 GM@ 2 R156 CLK_DOT# CLK_DREF_96M# <8>
14.31818MHZ_20P_1BX14318BE1A

23 GNDSRC
2

CLK_XTAL_OUT
R159 R160 R161 29
CLK_XTAL_IN @10K_0402_5% @ 10K_0402_5% 10K_0402_5% GNDSRC CK_PWRGD
CK_PWRGD/PD# 56
A
58 CK_PWRGD <22> A
GNDREF
1

ICS9LPRS365AGLFT_TSSOP64
ITP_EN 27_SEL PCI2_TME
Y1
2

2 1
R163 R164 R165
10K_0402_5% 10K_0402_5% @10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title
CLOCK GENERATOR
1

22P_0402_50V8J C284 C285


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
22P_0402_50V8J AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 1 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ISRAA LA-3441P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 16 of 48
5 4 3 2 1
A B C D E

Near to JP5
CRT CONNECTOR +5VS
D3
+R_CRT_VCC
F1
+CRT_VCC

1
D4 D5 D6 2 1 1 2

+3VS
CH491D_SC59 1
1A_6VDC_MINISMDC110 C286
CRT Conn.
DAN217_SC59 DAN217_SC59 DAN217_SC59 0.1U_0402_16V4Z

3
2
@ @ @
JP5
6
L16 11
1 2 CRT_R 1 2 CRT_R_L 1
1 <19> VGA_CRT_R 1
R166 PM@ 0_0402_5% FCM2012C-800_0805 7
<10> GMCH_CRT_R 1 2 12
R167 GM@ 0_0402_5% CRT_G_L 2
8
L17 13
1 2 CRT_G 1 2 CRT_B_L 3
<19> VGA_CRT_G
R168 PM@ 0_0402_5% FCM2012C-800_0805 9
<10> GMCH_CRT_G 1 2 14
R169 GM@ 0_0402_5% 4
L18 1 10
1 2 CRT_B 1 2 15
<19> VGA_CRT_B C287
R170 PM@ 0_0402_5% FCM2012C-800_0805 5

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K
<10> GMCH_CRT_B 1 2
2

150_0402_1%

150_0402_1%

150_0402_1%
R171 GM@ 0_0402_5% 1 1 1 TYCO_1470801-1

1
C288 C289 C290 1 1 1
R172 R173 R174 C291 C292 C293 DSUB_12_DATA
220P_0402_50V7K
2 2 2 @ @ @ DSUB_15_CLK
2 2 2

68P_0402_50V8K

68P_0402_50V8K
1 1
C294 C295
+CRT_VCC
2 2
1 2 2 1
C296 0.1U_0402_16V4Z R175 10K_0402_5%

5
1
P
OE#
1 2 CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC
<19> VGA_CRT_HSYNC A Y
R176 PM@ 0_0402_5% L19 10_0402_5%

G
1 2 U5
<10> GMCH_CRT_HSYNC
R177 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5 D_CRT_VSYNC 1 2 VSYNC
2
3 L20 10_0402_5% 2
+CRT_VCC

10P_0402_50V8J

10P_0402_50V8J
1 1
1 2 C298 C299
C297 0.1U_0402_16V4Z

5
1
2 2

P
OE#
1 2 CRT_VSYNC 2 4
<19> VGA_CRT_VSYNC A Y
R178 PM@ 0_0402_5%

G
1 2 U6 +CRT_VCC
<10> GMCH_CRT_VSYNC +3VS
R179 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

1
GM@
<10> GMCH_CRT_DATA 1 2
0_0402_5% R180 R181 R182

2
G
4.7K_0402_5% 4.7K_0402_5%
PM@

2
1 2 3 1 DSUB_12_DATA
<19> VGA_DDC_DATA
0_0402_5% R183

D
2
G
Q3
PM@ 2N7002_SOT23
1 2 3 1 DSUB_15_CLK
<19> VGA_DDC_CLK
0_0402_5% R184

D
GM@ Q4
1 2 2N7002_SOT23
<10> GMCH_CRT_CLK
0_0402_5% R185

3 3

D7 D8
@ DAN217_SC59 @ DAN217_SC59
1

1
2

+3VS
1 2 C300
1 2 @ 22P_0402_50V8J
<19> VGA_TV_LUMA
R186 PM@ 0_0402_5%
1 2 TV_LUMA L21 1 2
<10> GMCH_TV_LUMA
R187 GM@ 0_0402_5% FBM-11-160808-121T_0603

1 2 TV_CRMA L22 1 2
<19> VGA_TV_CRMA
R188 PM@ 0_0402_5% FBM-11-160808-121T_0603
1 2 JP6
<10> GMCH_TV_CRMA
1

R189 GM@ 0_0402_5% 1 2 C301 TV_CRMA_L 4 4


1

1 1 @ 22P_0402_50V8J TV_LUMA_L 3 6
R191 R190 3
2 5
150_0402_1% 150_0402_1% C302
100P_0402_50V8J
C303
100P_0402_50V8J
1
C304
1
C305
1
2
1
2
TV-OUT Conn.
2

2 2 ALLTO_C10877-104A1-L_4P R192 1. Y ground


2

2 2
0_0805_5% 2. C ground
100P_0402_50V8J 100P_0402_50V8J 3. Y (luminance+sync)
4 4. C (crominance) 4
1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title
CRT & TVout Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 17 of 48
A B C D E
5 4 3 2 1

+1.8VS

L62 L63

VCC_PWR

VCC_PWR
AVCC18V

AVCC33V

HDAVCC
VCC_PWR C783 C784 C785 C786 C787 C788 C789 C790 C791 1 2 2 1 C779 C780 C781 C782 AVCC18V

SPVCC
PVCC1
PVCC2

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
CHB1608U301_0603 CHB1608U301_0603

OVCC

SVCC
1 1 1 1
1 1 1 1 1 1 1 1 1

2 2 2 2

38
43
48

21
27
32

17
31

33
37

64

50
56

62
2
9
U47 2 2 2 2 2 2 2 2 2

AVCC1.8
AVCC1.8
AVCC3.3

PVCC1
PVCC2
VCC
VCC
VCC
VCC
VCC

OTPVCC
HDAVCC

OVCC

SVCC
SVCC

SPVCC
300_0402_1% 0.1U_0402_16V7K DVI_TXD2+
<10> SDVO_INT 46 SDI+ TX2+ 29 1 R675 2 1 2
47 28 C794 DVI_TXD2-
<10> SDVO_INT# SDI- TX2- 300_0402_1% 0.1U_0402_16V7K DVI_TXD1+ L64 L65

Serial Input Interface


D R720 1 GM@ 2 0_0402_1% HDMI_R 51 26 1 R676 2 1 2 PVCC1 C797 C798 C799 1 2 2 1 C800 C801 C802 C803 SVCC D
<10> SDVOB_R SDR+ Red TX1+

1000P_0402_50V7K
1000P_0402_50V7K
1U_0805_16V7K

100P_0402_50V8J
10U_0805_10V4Z
0.1U_0402_16V7K

0.1U_0402_16V7K
R721 1 GM@ 2 0_0402_1% HDMI_R# 52 25 C795 DVI_TXD1- CHB1608U301_0603 CHB1608U301_0603
<10> SDVOB_R# SDR- TX1- 300_0402_1% 0.1U_0402_16V7K DVI_TXD0+ 1 1 1 1 1 1 1
R722 1 GM@ 2 0_0402_1% HDMI_G 54 HDMI/DVI 23 1 R677 2 1 2
<10> SDVOB_G SDG+ Green
R723 1 GM@ 2 0_0402_1% HDMI_G# 55 Interface TX0+ 22 C796 DVI_TXD0-
<10> SDVOB_G# SDG- TX0- 300_0402_1% 0.1U_0402_16V7K DVI_TXC+
R724 1 GM@ 2 2 2 2 2 2 2
<10> SDVOB_B 2 0_0402_1% HDMI_B 57 SDB+ Blue TXC+ 20 1 R678 2 1 2
R725 1 GM@ 2 0_0402_1% HDMI_B# 58 19 C804 DVI_TXC-
<10> SDVOB_B# SDB- TXC-
R726 1 GM@ 2 0_0402_1% HDMI_CLK 60 42 HTPLG
<10> SDVOB_CLK
<10> SDVOB_CLK#
R727 1 GM@ 2 0_0402_1% HDMI_CLK# 61
SDC+ Clock
SDC-
SiI1392 Tx HTPLG L72
16 R679 1 2 820_0402_5% AVCC18V PVCC2 C826 C827 C828 1 2
64-Pin QFN EXT_SWING

1000P_0402_50V7K

1U_0805_16V7K
0.1U_0402_16V7K
1 2 49 CHB1608U301_0603
EXT_RES ICH_BITCLK_HDMI_AUDIO <21>
1392@ R680 1K_0402_5% 39 ICH_BITCLK_HDMI_AUDIO 1 1 1
HDABCLK +3VS
HDMI_RST# 1 35
RESET# HDARST# ICH_RST_HDMI_AUDIO# <21>
SDVO_SDAT 6
<8> SDVO_SDAT SDSDA 2 2 2
SDVO_SCLK 7 I2C from 36 ICH_AC_SDIN2 <21>
<8> SDVO_SCLK SDSCL HDASDI

2
SDVO
<19> DVI_SDATA R681 1 21932@ 0_0402_5% DVI_DAT 12 I2C to 40 ICH_SYNC_HDMI_AUDIO <21> R683
R684 1 SDADDC HDASYNC
<19> DVI_SCLK 21932@ 0_0402_5% DVI_CLK 11 DDC/
SCLDDC HDCP
R682 2.2K_0402_5%
34 ICH_SDOUT_HDMI_AUDIO <21> 2.2K_0402_5%1932@
R685 1 SPDIF/HDASDO
2 1932@ 0_0402_5% 14 SCLROM I2C to
1932@

1
R686 1 2 1932@ 0_0402_5% 13 4 LSCL
SDAROM Config. LSCL TPI_CLK <19>
PROM
1 2 8 3 LSDA R732 1 2 TPI_DAT <19>
1392@ R687 1K_0402_5% A1 LSDA 1932@ 0_0402_5% +3VS

SPGND
44 TEST LINT# 15 DVI_HPD <19>

2
SGND
SGND

AGND
AGND
AGND
GND
GND
GND
GND
GND
R688
0_0402_5% L66 L67
SII1392CNU_QFN64_9X9 1392@ AVCC33V C805 C806 C807 C808 2 1 2 1 C809 C810 OVCC
65
5
10
41
45

53
59

18
24
30

63

1000P_0402_50V7K

1000P_0402_50V7K

1U_0805_16V7K
10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V7K
CHB1608U301_0603 CHB1608U301_0603

1
1 1 1 1 1 1

+3VALW
2 2 2 2 2 2
C C
5

U48
1
P

<19> SW_RST# B
4 HDMI_RST#
Y L68
2 A
G

For EMI 2 1 C811 C812 C813 SPVCC

1000P_0402_50V7K
1U_0805_16V7K

0.1U_0402_16V7K
TC7SH08FU_SSOP5 CHB1608U301_0603
3

1 1 1
ICH_BITCLK_HDMI_AUDIO 2 R737 1 C830 1 2
@ 10_0402_5% @ 10P_0402_50V8J
2 2 2

<8,20,22,28,32,33> PLT_RST# 1 R673 2 1392@ 0_0402_5%

<19,20> PLTRST_VGA# 1 R674 2 @ 0_0402_5%

Need close R748 ~ R755 HD_IOPWR


VGA_DVI_TXD0- 1 R748 2 1932@ 0_0402_5% R_HDMI_B# C814 1 2 0.1U_0402_16V7K 1932@ HDMI_B# VGA_DVI_TXD0- R712 1 M72@ 2 0_0402_1% DVI_TXD0-
<19> VGA_DVI_TXD0-
VGA_DVI_TXD0+ 1 R749 2 1932@ 0_0402_5% R_HDMI_B C815 1 2 0.1U_0402_16V7K 1932@ HDMI_B VGA_DVI_TXD0+ R713 1 M72@ 2 0_0402_1% DVI_TXD0+
<19> VGA_DVI_TXD0+
VGA_DVI_TXD1- 1 R750 2 1932@ 0_0402_5% R_HDMI_G# C816 1 2 0.1U_0402_16V7K 1932@ HDMI_G# VGA_DVI_TXD1- R714 1 M72@ 2 0_0402_1% DVI_TXD1- Keep 30mil spacing to other signals L69
<19> VGA_DVI_TXD1-
VGA_DVI_TXD1+ 1 R751 2 1932@ 0_0402_5% R_HDMI_G C817 1 2 0.1U_0402_16V7K 1932@ HDMI_G VGA_DVI_TXD1+ R715 1 M72@ 2 0_0402_1% DVI_TXD1+ HDAVCC 1 2 +3VS
<19> VGA_DVI_TXD1+
1392@ CHB1608U301_0603

0.1U_0402_16V7K
VGA_DVI_TXD2- 1 R752 2 1932@ 0_0402_5% R_HDMI_R# C819 1 2 0.1U_0402_16V7K 1932@ HDMI_R# VGA_DVI_TXD2- R716 1 M72@ 2 0_0402_1% DVI_TXD2- SDVO_SDAT R697 1 2 5.6K_0402_5% 1 2 +2.5VS 1
<19> VGA_DVI_TXD2-
VGA_DVI_TXD2+ 1 R753 2 1932@ 0_0402_5% R_HDMI_R C820 1 2 0.1U_0402_16V7K 1932@ HDMI_R VGA_DVI_TXD2+ R717 1 M72@ 2 0_0402_1% DVI_TXD2+ R698 0_0402_5% C818
<19> VGA_DVI_TXD2+
1932@
VGA_DVI_TXC+ 1 R754 2 1932@ 0_0402_5% R_HDMI_CLK C821 1 2 0.1U_0402_16V7K 1932@ HDMI_CLK VGA_DVI_TXC+ R718 1 M72@ 2 0_0402_1% DVI_TXC+ SDVO_SCLK R699 1 2 5.6K_0402_5% 1 2 +3VS
<19> VGA_DVI_TXC+ 2
VGA_DVI_TXC- 1 R755 2 1932@ 0_0402_5% R_HDMI_CLK# C822 1 2 0.1U_0402_16V7K 1932@ HDMI_CLK# VGA_DVI_TXC- R719 1 M72@ 2 0_0402_1% DVI_TXC- R700 0_0402_5%
<19> VGA_DVI_TXC-
B B

+3VS +5VS

HDMI ESD Protection HDMI Connector


1

R703 R704

1
2.2K_0402_5% 2.2K_0402_5% 1
+3VS R711 C825
R705 U9 15K_0402_5% 0.1U_0402_16V7K
2

2.2K_0402_5% 1 38
5V_SUPPLY 5V_OUT 2
2 37 2 1

2
LV_SUPPLY ESD_BYP C823 0.1U_0402_16V7K

1
16 23 HDMI_CEC 1 R707 2 1.8K_0402_5% JP7
DVI_CLK CE_REMOTE_IN CE_REMOTE_OUT HDMI_SCL HDMI_DET
17 DDC_CLK_IN DDC_CLK_OUT 22 19 HP_DET
DVI_DAT 18 21 HDMI_SDA R710 HDMI_5V_OUT 18
HTPLG DDC_DAT_IN DDC_DAT_OUT HDMI_DET @ 27K_0402_5% +5V
19 HOTPLG_DET_IN HOTPLG_DET_OUT 20 1 2 17 DDC/CEC_GND
R708 1.8K_0402_5% HDMI_SDA 16

2
DVI_TXD2- HDMI_D2- HDMI_SCL SDA
13 TMDS_CK+ TMDS_CK+ 26 15 SCL
1

DVI_TXD2+ 15 24 HDMI_D2+ 14
TMDS_CK- TMDS_CK- F2 HDMI_CEC Reserved
13
1

DVI_TXD1- HDMI_D1- @ 1A_6VDC_MINISMDC110 HDMI_CK- CEC


10 TMDS_D0+ TMDS_D0+ 29 12 CK- GND 20
DVI_TXD1+ 12 27 HDMI_D1+ 11 21
TMDS_D0- TMDS_D0- CK_shield GND

2
J2
2

HDMI_CK+ 10 22
1

DVI_TXD0- HDMI_D0- R736 HDMI_D0- CK+ GND


7 32 9 23
2

DVI_TXD0+ TMDS_D1+ TMDS_D1+ HDMI_D0+ D0- GND


9 TMDS_D1- TMDS_D1- 30 0_0402_5% 8 D0_shield
@ HDMI_5V_OUT HDMI_D0+ 7
DVI_TXC- HDMI_CK- JUMP_43X79 1 HDMI_D1- D0+
4 35 6

1
DVI_TXC+ TMDS_D2+ TMDS_D2+ HDMI_CK+ D1-
A 6 TMDS_D2- TMDS_D2- 33 5 D1_shield A
C824 HDMI_D1+ 4
HDMI_D2- D1+
5 TMDS_GND 0.1U_0402_16V7K 3 D2-
2
8 TMDS_GND 2 D2_shield
11 HDMI_D2+ 1
TMDS_GND D2+
14 TMDS_GND
25 TYCO_1939864-1_19P
TMDS_GND
28 TMDS_GND
31 TMDS_GND
34 TMDS_GND
3 GND
Security Classification Compal Secret Data Compal Electronics, Inc.
36 GND Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

CM2020-00TR_TSSOP38
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SiI1392/1932 & HDMI Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 18 of 48
5 4 3 2 1
5 4 3 2 1

+3VS
LCD POWER CIRCUIT

1
R217 VGA BOARD Conn.
D9 4.7K_0402_5%

2
VGA_ENVDD R218 1 2PM@ 0_0402_5% BKOFF# 1 2 DISPOFF# JP8
<33> BKOFF#
B+ 1 2 +1.8VS
GMCH_ENVDD R219 1 2GM@ 0_0402_5%
<10> GMCH_ENVDD 3 4
RB751V_SOD323
5 6
7 8
+3VALW 9 10
D U10 PCIE_MTX_C_GRX_N[0..15] D
<10> PCIE_MTX_C_GRX_N[0..15] 11 12

5
1
SN74AHCT1G125GW_SOT353-5
PCIE_MTX_C_GRX_P[0..15] 13 14

P
OE#
+LCDVDD <10> PCIE_MTX_C_GRX_P[0..15] 15 16
2 A Y 4 17 18
1 PCEI_GTX_C_MRX_N[0..15]
<10> PCIE_GTX_C_MRX_N[0..15] <18> TPI_CLK 19 20

G
+2.5VS 21 22
1

2
C324 PCEI_GTX_C_MRX_P[0..15]
<10> PCIE_GTX_C_MRX_P[0..15]

3
0.01U_0402_16V7K 23 24
2 +3VS 25 26
R220 +1.5VS 27 28
300_0402_5% TPI_DAT <18>
R221 29 30 R222 1 2 PM@ 0_0402_5% EC_SMB_CK2 <4,33>
1 2

1
100_0402_5% Q6 31 32 R223 1
33 34 2 PM@ 0_0402_5% EC_SMB_DA2 <4,33>

3
D S
G 35 36 +3VS
Q5 2 2 AO3413_SOT23
2N7002_SOT23 G 37 38
39 40
S 1
D
+5VALW
3

1
41 42
2

+LCDVDD
PCEI_GTX_C_MRX_P15 43 44 PCIE_MTX_C_GRX_P15
R224 C325 PCEI_GTX_C_MRX_N15 45 46 PCIE_MTX_C_GRX_N15
2 47 48
100K_0402_5% 0.047U_0402_16V7K PCEI_GTX_C_MRX_P14 49 50 PCIE_MTX_C_GRX_P14
1 1
1

C326 C327 PCEI_GTX_C_MRX_N14 51 52 PCIE_MTX_C_GRX_N14


53 54
4.7U_0805_10V4Z 0.1U_0402_16V4Z PCEI_GTX_C_MRX_P13 55 56 PCIE_MTX_C_GRX_P13
2 2 PCEI_GTX_C_MRX_N13 57 58 PCIE_MTX_C_GRX_N13
59 60
PCEI_GTX_C_MRX_P12 61 62 PCIE_MTX_C_GRX_P12
LCD/PANEL BD. Conn. PCEI_GTX_C_MRX_N12 63
65
64
66
PCIE_MTX_C_GRX_N12

PCEI_GTX_C_MRX_P11 67 68 PCIE_MTX_C_GRX_P11
PCEI_GTX_C_MRX_N11 69 70 PCIE_MTX_C_GRX_N11
71 72
C +INV +INV PCEI_GTX_C_MRX_P10 73 74 PCIE_MTX_C_GRX_P10 C
JP9 PCEI_GTX_C_MRX_N10 75 76 PCIE_MTX_C_GRX_N10
JP46 77 78
1 1 2 2 79 80
3 4 B+ 1 PCEI_GTX_C_MRX_P9 PCIE_MTX_C_GRX_P9
3 4 1 PCEI_GTX_C_MRX_N9 81 82 PCIE_MTX_C_GRX_N9
5 5 6 6 2 2 83 84
VGA_TZOUT0- 7 8 VGA_TXCLK+ 3
VGA_TZOUT0+ 7 8 VGA_TXCLK- 3 PCEI_GTX_C_MRX_P8 85 86 PCIE_MTX_C_GRX_P8
9 9 10 10 4 4 87 88
11 12 5 PCEI_GTX_C_MRX_N8 PCIE_MTX_C_GRX_N8
VGA_TZOUT1- 11 12 VGA_TXOUT2- G5 89 90
13 13 14 14 6 G6 91 92
VGA_TZOUT1+ 15 16 VGA_TXOUT2+ PCEI_GTX_C_MRX_P7 PCIE_MTX_C_GRX_P7
15 16 @ ACES_85205-04001 PCEI_GTX_C_MRX_N7 93 94 PCIE_MTX_C_GRX_N7
17 17 18 18 95 96
VGA_TZOUT2- 19 20 VGA_TXOUT1-
VGA_TZOUT2+ 19 20 VGA_TXOUT1+ PCEI_GTX_C_MRX_P6 97 98 PCIE_MTX_C_GRX_P6
21 21 22 22 99 100
23 24 PCEI_GTX_C_MRX_N6 PCIE_MTX_C_GRX_N6
VGA_TZCLK+ 23 24 VGA_TXOUT0- 101 102
25 26
VGA_TZCLK- 27
25
27
26
28 28 VGA_TXOUT0+ B+ for NVIDIA VGA BOARD USE PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_N5
103
105
104
106
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
29 29 30 30 107 108
VGA_LCD_DATA 31 32 VGA_LCD_CLK +3VS
31 32 PCEI_GTX_C_MRX_P4 109 110 PCIE_MTX_C_GRX_P4
33 33 34 34 111 112
DISPOFF# 35 36 DAC_BRIG PCEI_GTX_C_MRX_N4 PCIE_MTX_C_GRX_N4
35 36 DAC_BRIG <33> 113 114
L60 37 38 INVT_PWM
37 38 INVT_PWM <33> 115 116
+LCDVDD 1 2 39 40 PCEI_GTX_C_MRX_P3 PCIE_MTX_C_GRX_P3
39 40 PCEI_GTX_C_MRX_N3 117 118 PCIE_MTX_C_GRX_N3
41 GND GND 42 119 120
KC FBM-L11-201209-221LMAT_0805 1
L70 ACES_88242-4001~N C765 PCEI_GTX_C_MRX_P2 121 122 PCIE_MTX_C_GRX_P2
PCEI_GTX_C_MRX_N2 123 124 PCIE_MTX_C_GRX_N2
1 2 1 125 126
KC FBM-L11-201209-221LMAT_0805C766 0.1U_0402_16V4Z
2 PCEI_GTX_C_MRX_P1 127 128 PCIE_MTX_C_GRX_P1
22U_0805_6.3V6M PCEI_GTX_C_MRX_N1 129 130 PCIE_MTX_C_GRX_N1
2 131 132
PCEI_GTX_C_MRX_P0 133 134 PCIE_MTX_C_GRX_P0
PCEI_GTX_C_MRX_N0 135 136 PCIE_MTX_C_GRX_N0
B 137 138 B
139 140 CLK_PCIE_VGA
<18> DVI_HPD 141 142 CLK_PCIE_VGA <16>
CLK_PCIE_VGA#
<18> DVI_SCLK 143 144 CLK_PCIE_VGA# <16>
B+ +INV <18> DVI_SDATA 145 146
1 2@ C767 68P_0402_50V8K DAC_BRIG
147 148 ICH_SYNC_AUDIO <21,29>
L61 KC FBM-L11-201209-221LMAT_0805 ICH_SDOUT_AUDIO <21,29>
<18> VGA_DVI_TXC- 149 150
1 2@ C768 68P_0402_50V8K INVT_PWM 1 2 R626 1 222_0402_5%
<18> VGA_DVI_TXC+ 151 152 ICH_BITCLK_AUDIO <21,29>
L71 KC FBM-L11-201209-221LMAT_0805 R627 1 233_0402_5% ICH_AC_SDIN3 <21>
DISPOFF# 153 154
1 2@ C769 68P_0402_50V8K 1 2 1 1 <18> VGA_DVI_TXD0- 155 156 ICH_RST_AUDIO# <21,29>
@C771
@ C771 @ C772 VGA_LCD_DATA
<18> VGA_DVI_TXD0+ 157 158
1 2@ C770 68P_0402_50V8K VGA_LCD_CLK
159 160
VGA_LCD_CLK
0.1U_0402_16V4Z 68P_0402_50V8K
2 2 <18> VGA_DVI_TXD1- 161 162
1 2@ C773 68P_0402_50V8K VGA_LCD_DATA
<18> VGA_DVI_TXD1+ 163 164
VGA_TXCLK-
VGA_TXCLK+
165 166
<18> VGA_DVI_TXD2- 167 168 VGA_TXOUT0-
<18> VGA_DVI_TXD2+ 169 170 VGA_TXOUT0+
VGA_TV_LUMA 171 172 VGA_TXOUT1-
<17> VGA_TV_LUMA 173 174
0_0402_5% GM@ VGA_TV_CRMA VGA_TXOUT1+
<17> VGA_TV_CRMA 175 176
VGA_LCD_CLK 2 1 R245 GMCH_LCD_CLK VGA_ENVDD VGA_TXOUT2-
GMCH_LCD_CLK <10> 177 178
VGA_LCD_DATA 2 1 R246 GMCH_LCD_DATA VGA_ENBKL VGA_TXOUT2+
GMCH_LCD_DATA <10> <33> VGA_ENBKL 179 180
0_0402_5% GM@
<27,33,34,38,43,44,45> SUSP# 181 182 VGA_TZOUT0-
<18,20> PLTRST_VGA# 183 184
VGA_TZOUT0- R247 1 2 GM@ 0_0402_5% VGA_CRT_VSYNC VGA_TZOUT0+
GMCH_TZOUT0- <10> <17> VGA_CRT_VSYNC 185 186
VGA_TXOUT0- R248 1 2 GM@ 0_0402_5% VGA_TZOUT0+ R249 1 2 GM@ 0_0402_5% VGA_CRT_HSYNC VGA_TZOUT1-
GMCH_TXOUT0- <10> GMCH_TZOUT0+ <10> <17> VGA_CRT_HSYNC 187 188
VGA_TXOUT0+ R250 1 2 GM@ 0_0402_5% VGA_DDC_CLK VGA_TZOUT1+
GMCH_TXOUT0+ <10> <17> VGA_DDC_CLK 189 190
VGA_TZOUT1- R251 1 2 GM@ 0_0402_5% VGA_DDC_DATA VGA_TZOUT2-
GMCH_TZOUT1- <10> <17> VGA_DDC_DATA 191 192
VGA_TXOUT1- R252 1 2 GM@ 0_0402_5% VGA_TZOUT1+ R253 1 2 GM@ 0_0402_5% VGA_TZOUT2+
GMCH_TXOUT1- <10> GMCH_TZOUT1+ <10> <18> SW_RST# 193 194
VGA_TXOUT1+ R254 1 2 GM@ 0_0402_5% VGA_CRT_R
GMCH_TXOUT1+ <10> <17> VGA_CRT_R 195 196
VGA_TZOUT2- R255 1 2 GM@ 0_0402_5% VGA_CRT_G VGA_TZCLK-
GMCH_TZOUT2- <10> <17> VGA_CRT_G 197 198
VGA_TXOUT2- R256 1 2 GM@ 0_0402_5% VGA_TZOUT2+ R257 1 2 GM@ 0_0402_5% VGA_CRT_B VGA_TZCLK+
GMCH_TXOUT2- <10> GMCH_TZOUT2+ <10> <17> VGA_CRT_B 199 200
VGA_TXOUT2+ R258 1 2 GM@ 0_0402_5%
A GMCH_TXOUT2+ <10> A
VGA_TZCLK- R259 1 2 GM@ 0_0402_5% ACES_88386-1K71
GMCH_TZCLK- <10>
VGA_TXCLK- R260 1 2 GM@ 0_0402_5% VGA_TZCLK+ R261 1 2 GM@ 0_0402_5%
GMCH_TXCLK- <10> GMCH_TZCLK+ <10>
VGA_TXCLK+ R262 1 2 GM@ 0_0402_5% GMCH_TXCLK+ <10>

ALL R CLOSE TO LVDS CONNECTOR Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 19 of 48
5 4 3 2 1
5 4 3 2 1

+3VS

R263 1 2 8.2K_0402_5% PCI_DEVSEL#

D R264 1 2 8.2K_0402_5% PCI_STOP# D

R265 1 U11B
2 8.2K_0402_5% PCI_TRDY# <25> PCI_AD[0..31]
PCI_AD0 D20 A4 PCI_REQ#0
R266 1 AD0 REQ0#
2 8.2K_0402_5% PCI_FRAME# PCI_AD1 E19 AD1 GNT0# D7 PCI_GNT#0
PCI_AD2 PCI_REQ#1
R267 1 2 8.2K_0402_5% PCI_PLOCK# PCI_AD3
D19
A20
AD2 PCI REQ1#/GPIO50 E18
C18
PCI_AD4 AD3 GNT1#/GPIO51 PCI_REQ#2
D17 AD4 REQ2#/GPIO52 B19 PCI_REQ#2 <25>
R268 1 2 8.2K_0402_5% PCI_IRDY# PCI_AD5 A21 F18 PCI_GNT#2
AD5 GNT2#/GPIO53 PCI_GNT#2 <25>
PCI_AD6 A19 A11 PCI_REQ#3
R269 1 AD6 REQ3#/GPIO54
2 8.2K_0402_5% PCI_SERR# PCI_AD7 C19 AD7 GNT3#/GPIO55 C10
PCI_AD8 A18
R270 1 AD8
2 8.2K_0402_5% PCI_PERR# PCI_AD9 B16 AD9 C/BE0# C17 PCI_CBE#0
PCI_CBE#0 <25>
PCI_AD10 A12 E15 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1 <25>
PCI_AD11 E16 F16 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2 <25>
PCI_AD12 A14 E17 PCI_CBE#3
AD12 C/BE3# PCI_CBE#3 <25>
PCI_AD13 G16
PCI_AD14 AD13 PCI_IRDY#
A15 AD14 IRDY# C8 PCI_IRDY# <25>
PCI_AD15 B6 D9 PCI_PAR
AD15 PAR PCI_PAR <25>
PCI_AD16 C11 G6 PCI_RST#
AD16 PCIRST# PCI_RST# <25,27,33,37>
PCI_AD17 A9 D16 PCI_DEVSEL#
AD17 DEVSEL# PCI_DEVSEL# <25>
PCI_AD18 D11 A7 PCI_PERR#
AD18 PERR# PCI_PERR# <25>
PCI_AD19 B12 B7 PCI_PLOCK#
PCI_AD20 AD19 PLOCK# PCI_SERR#
C12 AD20 SERR# F10 PCI_SERR# <25>
PCI_AD21 D10 C16 PCI_STOP#
AD21 STOP# PCI_STOP# <25>
PCI_AD22 C7 C9 PCI_TRDY#
AD22 TRDY# PCI_TRDY# <25>
PCI_AD23 F13 A17 PCI_FRAME#
+3VS AD23 FRAME# PCI_FRAME# <25>
PCI_AD24 E11
PCI_AD25 AD24 PCI_PLTRST#
E13 AD25 PLTRST# AG24
C PCI_AD26 E12 B10 CLK_PCI_ICH C
AD26 PCICLK CLK_PCI_ICH <16>
R271 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD27 D8 G7
PCI_AD28 AD27 PME#
A6 AD28
R272 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD29 E8 1 2 +3VALW
PCI_AD30 AD29 R273 8.2K_0402_5%
D6 AD30
R274 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD31 A3 AD31
R275 1 2 8.2K_0402_5% PCI_PIRQD#

R276 1 2 8.2K_0402_5% PCI_PIRQE# PCI_PIRQA# F9


Interrupt I/F F8 PCI_PIRQE#
<25> PCI_PIRQA# PIRQA# PIRQE#/GPIO2 PCI_PIRQE# <25>
PCI_PIRQB# B5 G11 PCI_PIRQF#
<25> PCI_PIRQB# PIRQB# PIRQF#/GPIO3 PCI_PIRQF# <25>
R277 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQC# C5 F12 PCI_PIRQG#
<25> PCI_PIRQC# PIRQC# PIRQG#/GPIO4 PCI_PIRQG# <25>
PCI_PIRQD# A10 B3 PCI_PIRQH#
R278 1 PIRQD# PIRQH#/GPIO5
2 8.2K_0402_5% PCI_PIRQG#
ICH8M_BGA676~D
R279 1 2 8.2K_0402_5% PCI_PIRQH# <BOM Structure>

R280 1 2 8.2K_0402_5% PCI_REQ#0

R281 1 2 8.2K_0402_5% PCI_REQ#1

R282 1 2 8.2K_0402_5% PCI_REQ#2 +3VALW

R283 1 2 8.2K_0402_5% PCI_REQ#3


Boot BIOS Strap
5

U12
PCI_PLTRST# 1
P

B
Y 4 PLT_RST# <8,18,22,28,32,33>
2 A PCI_GNT0# SPI_CS#0 Boot BIOS Location
G

B @ TC7SH08FU_SSOP5 B
3

1
R284
100K_0402_5% 0 1 SPI
R285 2 1 0_0402_5%
2
1 0 PCI
Place closely pin A9
+3VALW 1 1 LPC *
CLK_PCI_ICH
2

U13
1 PCI_GNT#0
P

B <22> SPI_CS1#_R
R286 4
Y PLTRST_VGA# <18,19>
10_0402_5% 2 A
G

1
@
1

TC7SH08FU_SSOP5 R287 R288


3

1 @ 1K_0402_5% @ 1K_0402_5%
C330 R289
10P_0402_50V8K 100K_0402_5%

2
@ R290 2 1 @ 0_0402_5%
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 20 of 48
5 4 3 2 1
5 4 3 2 1

+RTCVCC

+1.05VS

2
R291

1
1M_0402_5%
R292
1

SM_INTRUDER# @ 56_0402_5%

2
U11A
D
+RTCVCC ENABLE INTERNAL ICH_RTCX1 AG25 E5 LPC_AD0 D
1.05V RTCX1 FWH0/LAD0 LPC_AD0 <33,37>
ICH_RTCX2 AF24 F5 LPC_AD1 H_DPSLP#
SUSPEND RTCX2 FWH1/LAD1 LPC_AD1 <33,37>
G8 LPC_AD2
REGULARTOR FWH2/LAD2 LPC_AD2 <33,37>
+RTCVCC 1 2 ICH_RTCRST# AF23 F6 LPC_AD3 20060814 ADD
RTCRST# FWH3/LAD3 LPC_AD3 <33,37>
2

R293
R294 20K_0402_5% SM_INTRUDER# AD22 C4 LPC_FRAME#

RTC

LPC
INTRUDER# FWH4/LFRAME# LPC_FRAME# <33,37>
332K_0402_1% J1
ICH_INTVRMEN AF25 G9
LAN100_SLP INTVRMEN LDRQ0# LPC_DRQ#1
1 2 AD21 E6 LPC_DRQ#1 <37>
1

1 2 LAN100_SLP LDRQ1#/GPIO23
2 1 R295 10K_0402_5% +3VS
ICH_INTVRMEN @ B24 AF13 EC_GA20
JUMP_43X79 GLAN_CLK A20GATE EC_GA20 <33>
close to RAM door AG26 H_A20M#
A20M# H_A20M# <4>
C331 D22
1U_0603_10V4Z LAN_RSTSYNC DPRSTP# R296 1 0_0402_5%
DPRSTP# AF26 2 H_DPRSTP# <5,8,46>
+3VS +RTCVCC 1 2 C21 AE26 H_DPSLP#
LAN_RXD0 DPSLP# H_DPSLP# <5>
B21 R297 2 1 56_0402_5% +1.05VS
LAN_RXD1

LAN / GLAN
C22 AD24 H_FERR#
LAN_RXD2 FERR# H_FERR# <4>
1

R298 R658 D21 AG29 H_PWRGOOD


LAN_TXD_0 CPUPWRGD/GPIO49 H_PWRGOOD <5>
332K_0402_1% E20 LAN_TXD_1
10K_0402_5% C20 AF27 H_IGNNE#
LAN_TXD_2 IGNNE# H_IGNNE# <4>
2

AH21 AE24 H_INIT#

CPU
GLAN_DOCK#/GPIO13 INIT# H_INIT# <4> +1.05VS
AC20 H_INTR
INTR H_INTR <4>
PHDD_LED# LAN100_SLP D25 AH14 EC_KBRST#
GLAN_COMPI RCIN# EC_KBRST# <33>
C25 GLAN_COMPO 2 1 R299 +3VS

1
1 2 ICH_AC_BITCLK AD23 H_NMI 10K_0402_5%
<37> ICH_BITCLK_MDC NMI H_NMI <4>
R300 33_0402_5% AJ16 AG28 H_SMI# R301
HDA_BIT_CLK SMI# H_SMI# <4>
<37> ICH_SYNC_MDC 1 2 ICH_AC_SYNC_R AJ15
C R302 33_0402_5% HDA_SYNC H_STPCLK# within 2" 56_0402_5% C
For Audio code use STPCLK# AA24 H_STPCLK# <4>
<37> ICH_RST_MDC# 1 2 ICH_AC_RST_R# AE14

2
ICH_AC_BITCLK R303 33_0402_5% HDA_RST# THRMTRIP_ICH# R305 1
<19,29> ICH_BITCLK_AUDIO 1 2 THRMTRIP# AE27 2 24.9_0402_1% H_THERMTRIP# <4,8>
R304 33_0402_5% <29> ICH_AC_SDIN0 R306 2 1 0_0402_5% AJ17
ICH_AC_SYNC_R R308 HDA_SDIN0
<19,29> ICH_SYNC_AUDIO 1 2 <37> ICH_AC_SDIN1 2 1 0_0402_5% AH17 HDA_SDIN1 TP8 AA23 placed within 2"
R307 33_0402_5% R309 2 1 0_0402_5% AH15

IHDA
<18> ICH_AC_SDIN2 HDA_SDIN2 IDE_DD[0..15] <24> from ICH8M
1 2 ICH_AC_RST_R# <19> ICH_AC_SDIN3 R311 2 1 0_0402_5% AD13 V1 IDE_DD0
<19,29> ICH_RST_AUDIO# HDA_SDIN3 DD0
R310 33_0402_5% U2 IDE_DD1
ICH_AC_SDOUT_R ICH_AC_SDOUT_R AE13 DD1 IDE_DD2
<19,29> ICH_SDOUT_AUDIO 1 2 <37> ICH_SDOUT_MDC 1 2 HDA_SDOUT DD2 V3
R312 33_0402_5% R313 39_0402_5% T1 IDE_DD3
<37> MDC_RST#
<24> ODD_RST#
AE10
AG14
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
DD3
DD4
DD5
V4
T5
IDE_DD4
IDE_DD5
- BATT1 + +RTCBATT

For HDMI Audio use AB2 IDE_DD6 2 1 +RTCBATT


PHDD_LED# DD6 IDE_DD7
<33> PHDD_LED# AF10 SATALED# DD7 T6
<18> ICH_BITCLK_HDMI_AUDIO 1 1392@ 2 ICH_AC_BITCLK Main HDD DD8 T3 IDE_DD8
R314 33_0402_5% <24> SATA_RXN0_C SATA_RXN0_C AF6 R2 IDE_DD9
SATA0RXN DD9
<18> ICH_SYNC_HDMI_AUDIO 1 1392@ 2 ICH_AC_SYNC_R <24> SATA_RXP0_C SATA_RXP0_C AF5 SATA0RXP DD10 T4 IDE_DD10 45@ RTCBATT

1
R315 33_0402_5% SATA_TXN0_C AH5 V6 IDE_DD11
<24> SATA_TXN0_C SATA0TXN DD11
<18> ICH_RST_HDMI_AUDIO# 1 1392@ 2 ICH_AC_RST_R# <24> SATA_TXP0_C
SATA_TXP0_C AH6 SATA0TXP DD12 V5 IDE_DD12 D10
R316 33_0402_5% U1 IDE_DD13
DD13
<18> ICH_SDOUT_HDMI_AUDIO 1 1392@ 2 ICH_AC_SDOUT_R SATA_RXN1 AG3 V2 IDE_DD14 BAS40-04_SOT23

IDE
R317 33_0402_5% SATA_RXP1 SATA1RXN DD14 IDE_DD15 +RTCVCC
AG4 SATA1RXP DD15 U6
AJ4 IDE_DA[0..2] <24>

2
SATA1TXN IDE_DA0
AJ3 SATA1TXP DA0 AA4
Second HDD IDE_DA1

SATA
DA1 AA1
<24> SATA_RXN2_C SATA_RXN2_C AF2 AB3 IDE_DA2
SATA2RXN DA2 +CHGRTC
<24> SATA_RXP2_C SATA_RXP2_C AF1 1
SATA_TXN2_C SATA2RXP IDE_DCS1#
<24> SATA_TXN2_C AE4 SATA2TXN DCS1# Y6 IDE_DCS1# <24>
SATA_TXP2_C AE3 Y5 IDE_DCS3# IDE_DCS3# <24> C332
B <24> SATA_TXP2_C SATA2TXP DCS3# 0.1U_0402_16V4Z B
CLK_PCIE_SATA# IDE_DIOR# 2
<16> CLK_PCIE_SATA# AB7 SATA_CLKN DIOR# W4 IDE_DIOR# <24>
CLK_PCIE_SATA AC6 W3 IDE_DIOW#
<16> CLK_PCIE_SATA SATA_CLKP DIOW# IDE_DIOW# <24>
Y2 IDE_DDACK#
DDACK# IDE_DDACK# <24>
AG1 Y3 IDE_IRQ
SATARBIAS# IDEIRQ IDE_IRQ <24>
ICH_RTCX1 R318 1 2 24.9_0402_1% SATARBIAS AG2 Y1 IDE_DIORDY
SATARBIAS IORDY IDE_DIORDY <24>
10mils W5 IDE_DDREQ

1
R319
2 ICH_RTCX2
DDREQ
ICH8M_BGA676~D
IDE_DDREQ <24>
RTC Battery
<BOM Structure>
Layout Note:
10M_0402_5%
1. Under BATT1 battery Body, no Trace no Via
2. BATT1 + - PIN keep out 80mil from other component ,trace and via
Y2 R320 1 2 4.7K_0402_5% IDE_DIORDY
+3VS
1

+3VS
1 1
32.768KHZ_12.5P_1TJS125BJ2A251
OUT
IN

<22> ICH_TP3
C333 C334 R321 1 2 8.2K_0402_5% IDE_IRQ
10P_0402_50V8J 10P_0402_50V8J
2 2 MAINPWON <39,40,42>
R322 R323
1K_0402_5% 1K_0402_5%
NC

NC

@ @ R324

1
@ 330_0402_5% C
2

ICH_AC_SDOUT_R 1 2 SATA_RXN1 +1.05VS 1 2 2 Q7


R325 0_0402_5% B
1 2 SATA_RXP1 E @ 2SC2411K_SOT23

3
R326 0_0402_5%

H_THERMTRIP#
A A

XOR Chain Entrance Strap


SATA_RXn/p need tie to ground when SATA port no used
ICH_TP3 HDA_SDOUT Description
0 0 RSVD Security Classification Compal Secret Data Compal Electronics, Inc.
0 1 Enter XOR Chain Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

1 0 Normal Operation THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8-M(2/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 1 Set PCIE port config bit 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 21 of 48
5 4 3 2 1
5 4 3 2 1

+3VS
+3VALW R345 10K_0402_5%
10K_0402_5%
Place closely pin B2 Place closely pin AC1
1 2
R327 1 2 CLKSATAREQ# PM_RSMRST#
PM_RSMRST# <33>
CLK_48M_ICH CLK_14M_ICH

1
10K_0402_5%
R328 1 2 SIRQ R329 R330

1
2.2K_0402_5% 2.2K_0402_5%
8.2K_0402_5% +3VS R331 R332
R333 1 PM_CLKRUN# U11C 10_0402_5% 10_0402_5%
2

2
<14,15,16,27,32> ICH_SMBCLK ICH_SMBCLK AJ26 AJ12 1 2 @ @
10K_0402_5% ICH_SMBDATA SMBCLK SATA0GP/GPIO21 R334 8.2K_0402_5%
AD19 AJ10

SATA
GPIO
SMB
<14,15,16,27,32> ICH_SMBDATA

2
R336 1 MCH_ICH_SYNC# LINKALERT# SMBDATA SATA1GP/GPIO19
2 AG21 LINKALERT# SATA2GP/GPIO36 AF11
ICH_SMLINK0 AC17 AG11 1 1
R624 1 EC_THERM# ICH_SMLINK1 SMLINK0 SATA3GP/GPIO37 C335 C336
D
2 20060821 ADD AE19 SMLINK1 D
@ 8.2K_0402_5% AG9 CLK_14M_ICH 10P_0402_50V8K 10P_0402_50V8K
CLK14 CLK_14M_ICH <16>
10K_0402_5% 20060814 ADD RI# CLK_48M_ICH @ @
R659 1 2 PM_STP_PCI#
AF17 RI# clocks CLK48 G5 CLK_48M_ICH <16> 2 2
LPC_PD# F4 D3 SUS_CLK
<33> LPC_PD# SUS_STAT#/LPCPD# SUSCLK
10K_0402_5% ITP_DBRESET# AD15
<4> ITP_DBRESET# SYS_RESET#
R660 1 2 PM_STP_CPU# AG23 PM_SLP_S3#
SLP_S3# PM_SLP_S3# <33>
PM_BMBUSY# AG12 AF21 SLP_S4#

SYS / GPIO
10K_0402_5% <8> PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# SLP_S5#
SLP_S5# AD18
R738 1 2 BT_DET# EC_LID_OUT# AG22 R340
<33> EC_LID_OUT# SMBALERT#/GPIO11
10K_0402_5% AH27 1 2 10K_0402_5%
R767 1 R_ACIN PM_STP_PCI# S4_STATE#/GPIO26 +3VALW
2 <16> PM_STP_PCI# AE20 STP_PCI#/GPIO15
PM_STP_CPU# AG18 AE23 SYS_PWROK 20060814 Change
<16> PM_STP_CPU# STP_CPU#/GPIO25 PWROK SYS_PWROK <8,33>
C337 2 1

Power MGT
+3VALW PM_CLKRUN# AH11 AJ14 PM_DPRSLPVR
CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR <8,46>
10K_0402_5% 0.1U_0402_16V4Z

14
<27,32,33> ICH_PCIE_WAKE#
R337 1 2 RI# SB_WAKE# AE17 AE21 PM_BATLOW# U14A
<27,32,33> EC_SWI# WAKE# BATLOW#
SIRQ AF12 SLP_S4# 1

P
<25,33,37> SIRQ SERIRQ A
10K_0402_5% EC_THERM# AC13 C2 PBTN_OUT# 3
<33> EC_THERM# THRM# PWRBTN# PBTN_OUT# <33> O PM_SLP_S5# <33>
R338 1 2 ICH_SMLINK0 SLP_S5# 2 B

G
2 1 VRMPWRGD AJ20 AH20
<8,33,46> VGATE VRMPWRGD LAN_RST# PLT_RST# <8,18,20,28,32,33>
10K_0402_5% R343 0_0402_5%

7
R339 1 2 ICH_SMLINK1 PAD AJ22 AG27 EC_RSMRST# 1 2 R667 PM_RSMRST# SN74LVC08APW_TSSOP14
T6 TP7 RSMRST# 100_0402_5%
10K_0402_5% OCP# AJ8 E1 CK_PWRGD
<4> OCP# TACH1/GPIO1 CK_PWRGD CK_PWRGD <16>
R341 1 2 LINKALERT# 1 2 R_ACIN AJ9
<33,36,39> ACIN D56 CH751H-40_SC76 TACH2/GPIO6 CL_PWROK
AH9 TACH3/GPIO7 CLPWROK E3 CL_PWROK <8>
10K_0402_5% EC_SMI# AE16 +3VS
<33> EC_SMI# GPIO8
R342 1 2 ITP_DBRESET# EC_SCI# AC19 AJ25
<33> EC_SCI# GPIO12 SLP_M#
AG8 TACH0/GPIO17
1K_0402_5% AH12 F23

GPIO
Controller Link
GPIO18 CL_CLK0 CL_CLK0 <8>
R344 1 2 SB_WAKE# 2HDD_DET# AE11 AE18 R349
GPIO20 CL_CLK1 CL_CLK1 <32>
BT_DET# AG10 3.24K_0402_1%
C 8.2K_0402_5% <35> BT_DET# SCLOCK/GPIO22 C
<34> SB_INT_FLASH_SEL# AH25 QRT_STATE0/GPIO27 CL_DATA0 F22 CL_DATA0 <8>
R346 2 1 PM_BATLOW# AD16 AF19
QRT_STATE1/GPIO28 CL_DATA1 CL_DATA1 <32>
CLKSATAREQ# AG13 CL_VREF0_ICH
<16> CLKSATAREQ# SATACLKREQ#/GPIO35
10K_0402_5% <26> PCM_DISABLE# AF9 D24 CL_VREF0_ICH
R351 1 OCP# 1K_0402_5% SLOAD/GPIO38 CL_VREF0 CL_VREF1_ICH
2 AJ11 SDATAOUT0/GPIO39 CL_VREF1 AH23 1
+3VS R661 1 2 AD10 C338 R352
100K_0402_5% 1K_0402_5% SDATAOUT1/GPIO48 453_0402_1%
CL_RST# AJ23 CL_RST#0 <8,32>
R353 1 2 2HDD_DET# R3541 2 SB_SPKR AD9 0.1U_0402_16V4Z
<29> SB_SPKR SPKR 2
2HDD@ AJ27 EC_FLASH#

MISC
MEM_LED/GPIO24 EC_FLASH# <34>
MCH_ICH_SYNC# AJ13 AJ24
<8> MCH_ICH_SYNC# MCH_SYNC# ME_EC_ALERT/GPIO10
10K_0402_5% AF22
R355 1 EC_LID_OUT# ICH_TP3 EC_ME_ALERT/GPIO14 CL_PWROK SYS_PWROK
2 20060814 ADD <21> ICH_TP3 AJ21 TP3 WOL_EN/GPIO9 AG19 1 2
R768 0_0402_5%
ICH8M_BGA676~D +3VALW

U11D <BOM Structure>


100K_0402_5%
R356 1 2 PM_DPRSLPVR PCIE_PTX_C_IRX_N1 P27 V27 DMI_MTX_IRX_N0
<27> PCIE_PTX_C_IRX_N1 PERN1 DMI0RXN DMI_MTX_IRX_N0 <8>
PCIE_PTX_C_IRX_P1 P26 V26 DMI_MTX_IRX_P0 R358
<27> PCIE_PTX_C_IRX_P1 PERP1 DMI0RXP DMI_MTX_IRX_P0 <8>
@ 10K_0402_5% NEW Card C339 2 1NEWCARD@ 0.1U_0402_16V4Z PCIE_ITX_PRX_N1 N29 U29 DMI_ITX_MRX_N0 3.24K_0402_1%

Direct Media Interface


<27> PCIE_ITX_C_PRX_N1 PETN1 DMI0TXN DMI_ITX_MRX_N0 <8>
R357 1 2 SUS_CLK <27> PCIE_ITX_C_PRX_P1 C340 2 1NEWCARD@ 0.1U_0402_16V4Z PCIE_ITX_PRX_P1 N28 U28 DMI_ITX_MRX_P0
PETP1 DMI0TXP DMI_ITX_MRX_P0 <8>
PCIE_PTX_C_IRX_N2 M27 Y27 DMI_MTX_IRX_N1 CL_VREF1_ICH
<28> PCIE_PTX_C_IRX_N2 PERN2 DMI1RXN DMI_MTX_IRX_N1 <8>
@ 100K_0402_5% PCIE_PTX_C_IRX_P2 M26 Y26 DMI_MTX_IRX_P1
<28> PCIE_PTX_C_IRX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1 <8>
R335 1 2 VRMPWRGD LAN <28> PCIE_ITX_C_PRX_N2 C341 2 1 0.1U_0402_16V4Z PCIE_ITX_PRX_N2 L29 W29 DMI_ITX_MRX_N1 1
PETN2 DMI1TXN DMI_ITX_MRX_N1 <8>
<28> PCIE_ITX_C_PRX_P2 C342 2 1 0.1U_0402_16V4Z PCIE_ITX_PRX_P2 L28 W28 DMI_ITX_MRX_P1 C343 R359
PETP2 DMI1TXP DMI_ITX_MRX_P1 <8>

PCI - Express
20060821 ADD 453_0402_1%
PCIE_PTX_C_IRX_N3 K27 AB26 DMI_MTX_IRX_N2 0.1U_0402_16V4Z
<32> PCIE_PTX_C_IRX_N3 PERN3 DMI2RXN DMI_MTX_IRX_N2 <8> 2
PCIE_PTX_C_IRX_P3 K26 AB25 DMI_MTX_IRX_P2
<32> PCIE_PTX_C_IRX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2 <8>
WLAN <32> PCIE_ITX_C_PRX_N3 C344 2 1 WLAN@ 0.1U_0402_16V4Z PCIE_ITX_PRX_N3 J29 AA29 DMI_ITX_MRX_N2
PETN3 DMI2TXN DMI_ITX_MRX_N2 <8>
FOR 2ND HDD DETECTION 1: SINGLE HDD <32> PCIE_ITX_C_PRX_P3 C345 2 1 WLAN@ 0.1U_0402_16V4Z PCIE_ITX_PRX_P3 J28 AA28 DMI_ITX_MRX_P2
PETP3 DMI2TXP DMI_ITX_MRX_P2 <8>
0: DUAL HDD <32> PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_N4 H27 AD27 DMI_MTX_IRX_N3
DMI_MTX_IRX_N3 <8>
B PCIE_PTX_C_IRX_P4 PERN4 DMI3RXN DMI_MTX_IRX_P3 B
<32> PCIE_PTX_C_IRX_P4 H26 PERP4 DMI3RXP AD26 DMI_MTX_IRX_P3 <8>
Robson <32> PCIE_ITX_C_PRX_N4 C346 2 1ROBSON@ 0.1U_0402_16V4ZPCIE_ITX_PRX_N4 G29 PETN4 DMI3TXN AC29 DMI_ITX_MRX_N3
DMI_ITX_MRX_N3 <8>
<32> PCIE_ITX_C_PRX_P4 C347 2 1ROBSON@ 0.1U_0402_16V4Z PCIE_ITX_PRX_P4 G28 AC28 DMI_ITX_MRX_P3
PETP4 DMI3TXP DMI_ITX_MRX_P3 <8>
F27 T26 CLK_PCIE_ICH# +3VS
PERN5 DMI_CLKN CLK_PCIE_ICH# <16>
F26 T25 CLK_PCIE_ICH
PERP5 DMI_CLKP CLK_PCIE_ICH <16>
E29 PETN5

2
E28 Y23 R360 24.9_0402_1% Within 500 mils
+3VALW PETP5 DMI_ZCOMP DMI_IRCOMP R361
DMI_IRCOMP Y24 1 2 +1.5VS
D27 330_0402_5%
PERN6/GLAN_RXN USB20_N0
D26 PERP6/GLAN_RXP USBP0N G3 USB20_N0 <35>
C29 G2 USB20_P0
USB20_P0 <35>

1
PETN6/GLAN_TXN USBP0P USB20_N1
C28 PETP6/GLAN_TXP USBP1N H5 USB20_N1 <35> 1 2 CK_PWRGD
H4 USB20_P1 R362 0_0402_5%
USBP1P USB20_P1 <35>

1
10K_0402_5% R363 D
<37> SPI_CLK 1 2 SPI@ 15_0402_5%SPI_CLK_R C23 SPI_CLK USBP2N H2 USB20_N2
USB20_N2 <35> USB/B
R347 1 2 SPI_MOSI R364 1 2 SPI@ 15_0402_5%SPI_CS#_R B23 H1 USB20_P2 2 1 2 VRMPWRGD
<37> SPI_CS# SPI_CS0# USBP2P USB20_P2 <35> <46> CLK_ENABLE#
E22 J3 USB20_N3 G R365 @ 0_0402_5%
10K_0402_5% <20> SPI_CS1#_R SPI_CS1# SPI USBP3N
J2 USB20_P3
USB20_N3 <35>
Q8 S
USB20_P3 <35>

3
SPI_MISO USBP3P
R348 1 2 <37> SPI_SI
R366 1 2 SPI@ 15_0402_5% SPI_MOSI D23 SPI_MOSI USBP4N K5 USB20_N4
USB20_N4 <35>
RHU002N06_SOT323 1
R367 2 1 SPI@ 0_0402_5% SPI_MISO F21 K4 USB20_P4
<37> SPI_SO_R SPI_MISO USBP4P USB20_P4 <35>
10K_0402_5% K2 USB20_N5 MB USB C350
USBP5N USB20_N5 <35>
R350 1 2 SPI_CS#_R USB_OC#0 AJ19 K1 USB20_P5 @ 0.1U_0402_16V4Z
OC0# USBP5P USB20_P5 <35> 2
Add in 08/11. USB_OC#1 AG16 L3 USB20_N6
OC1#/GPIO40 USBP6N USB20_N6 <35>
USB_OC#2 USB20_P6 F_P(1.1) Add for find
USB_OC#3
AG15
AE15
OC2#/GPIO41 USB USBP6P L2
M5 USB20_N7
USB20_P6 <35>
USB_OC#4 AF15
OC3#/GPIO42 USBP7N
M4 USB20_P7
USB20_N7 <35>
BT tune
OC4#/GPIO43 USBP7P USB20_P7 <35>
1 2 USB_OC#0 USB_OC#5 AG17 OC5#/GPIO29 USBP8N M2 USB20_N8
USB20_N8 <35>
timing.(glich
R662 10K_0402_5% USB_OC#6 AD12 M1 USB20_P8 Int .Camera issue 7/28)
OC6#/GPIO30 USBP8P USB20_P8 <35>
RP31 USB_OC#7 AJ18 N3 USB20_N9
<27> EXP_CPPE# OC7#/GPIO31 USBP9N USB20_N9 <27>
5 4 USB_OC#1 USB_OC#8 AD14 N2 USB20_P9 NEW CARD
+3VALW OC8# USBP9P USB20_P9 <27>
6 3 USB_OC#2 USB_OC#9 AH18 R368 22.6_0402_1%
USB_OC#3 OC9# USBRBIAS USBRBIAS
7 2 USBRBIAS# F2 1 2
A USB_OC#4 A
8 1 USBRBIAS F3

10K_1206_8P4R_5% ICH8M_BGA676~D
Within 500 mils
<BOM Structure>

RP32
5 4 USB_OC#6
6 3 USB_OC#7
7 2 USB_OC#5
Security Classification Compal Secret Data Compal Electronics, Inc.
8 1 USB_OC#8 Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

10K_1206_8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8-M(3/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 2 USB_OC#9 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
R369 10K_0402_5% MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 22 of 48
5 4 3 2 1
5 4 3 2 1

+5VS +3VS U11F U11E


W = 20 mil
+RTCVCC AD25 VCCRTC VCC1_05[01] A13 +1.05VS A23 VSS[001] VSS[099] K7
1 VCC1_05[02] B13 A5 VSS[002] VSS[100] L1

2
C351 C352 +ICH_V5REF A16 C13 1 1 (47UF*1, 0.047UF*1, 0.022UF*1) AA2 L13
R370 D11 V5REF[1] VCC1_05[03] C353 C354 VSS[003] VSS[101]
T7 V5REF[2] VCC1_05[04] C14 AA7 VSS[004] VSS[102] L15
0.1U_0402_16V4Z D14 A25 L26
100_0402_5% CH751H-40_SC76 2 +ICH_V5REF_SUS VCC1_05[05] 0.1U_0402_16V4Z VSS[005] VSS[103]
G4 V5REF_SUS VCC1_05[06] E14 AB1 VSS[006] VSS[104] L27
1U_0603_10V4Z 2 2
<BOM Structure> F14 AB24 L4
1

1
+ICH_V5REF VCC1_05[07] 0.1U_0402_16V4Z VSS[007] VSS[105]
AA25 VCC1_5_B[01] VCC1_05[08] G14 AC11 VSS[008] VSS[106] L5
2 20 mils AA26 VCC1_5_B[02] VCC1_05[09] L11 AC14 VSS[009] VSS[107] M12
C355 AA27 L12 AC25 M13
VCC1_5_B[03] VCC1_05[10] VSS[010] VSS[108]
AB27 VCC1_5_B[04] VCC1_05[11] L14 AC26 VSS[011] VSS[109] M14
0.1U_0402_16V4Z AB28 L16 AC27 M15
D 1 VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH +1.5VS_DMIPLL_R VSS[012] VSS[110] D
AB29 VCC1_5_B[06] VCC1_05[13] L17 AD17 VSS[013] VSS[111] M16
D28 L18 AD20 M17

CORE
VCC1_5_B[07] VCC1_05[14] L31 1 R371 1_0603_5% VSS[014] VSS[112]
D29 VCC1_5_B[08] VCC1_05[15] M11 2 +1.5VS AD28 VSS[015] VSS[113] M23
+5VALW +3VALW MBK1608121YZF_0603
E25 VCC1_5_B[09] VCC1_05[16] M18 AD29 VSS[016] VSS[114] M28
E26 VCC1_5_B[10] VCC1_05[17] P11 1 (10UF*1, 0.01UF*1) AD3 VSS[017] VSS[115] M29
E27 P18 C357 AD4 M3
VCC1_5_B[11] VCC1_05[18] VSS[018] VSS[116]
2

F24 T11 C356 AD6 N1


R372 D12 VCC1_5_B[12] VCC1_05[19] VSS[019] VSS[117]
F25 VCC1_5_B[13] VCC1_05[20] T18 10U_0805_10V4Z AE1 VSS[020] VSS[118] N11
2
G24 VCC1_5_B[14] VCC1_05[21] U11 AE12 VSS[021] VSS[119] N12
10_0402_5% CH751H-40_SC76 H23 U18 0.01U_0402_16V7K AE2 N13
VCC1_5_B[15] VCC1_05[22] VSS[022] VSS[120]
H24 V11 AE22 N14
1

+ICH_V5REF_SUS VCC1_5_B[16] VCC1_05[23] VSS[023] VSS[121]


J23 VCC1_5_B[17] VCC1_05[24] V12 AD1 VSS[024] VSS[122] N15
2 20 mils J24 VCC1_5_B[18] VCC1_05[25] V14 +1.25VS AE25 VSS[025] VSS[123] N16

VCCA3GP
C358 K24 V16 AE5 N17
VCC1_5_B[19] VCC1_05[26] VSS[026] VSS[124]
0.1U_0402_16V4Z
K25 VCC1_5_B[20] VCC1_05[27] V17
C359
1 (22UF*1, 0.1UF*1) AE6 VSS[027] VSS[125] N18
L23 VCC1_5_B[21] VCC1_05[28] V18 AE9 VSS[028] VSS[126] N26
1
L24 VCC1_5_B[22] AF14 VSS[029] VSS[127] N27
+1.5VS_PCIE_ICH L25 R29 22U_0805_6.3V6M AF16 N4
VCC1_5_B[23] VCCDMIPLL 2 VSS[030] VSS[128]
(220UF*1, 22UF*2, 2.2UF*1) M24 VCC1_5_B[24] AF18 VSS[031] VSS[129] N5
+1.5VS L32 2 1 M25 AE28 AF3 N6
KC FBM-L11-201209-221LMAT_0805 VCC1_5_B[25] VCC_DMI[1] VSS[032] VSS[130]
1 N23 VCC1_5_B[26] VCC_DMI[2] AE29 AF4 VSS[033] VSS[131] P12
1 1 N24 VCC1_5_B[27] +1.05VS AG5 VSS[034] VSS[132] P13
+ C361 C362 C363 N25 AC23 AG6 P14
C360 VCC1_5_B[28] V_CPU_IO[1] VSS[035] VSS[133]
SGA00000Y80 2nd P24 VCC1_5_B[29] V_CPU_IO[2] AC24 1 1 AH10 VSS[036] VSS[134] P15
22U_0805_6.3V6M P25 C364 C365 C366 (4.7UF*1, 0.1UF*2) AH13 P16
220U_D2_4VM 2 2 2 VCC1_5_B[30] VSS[037] VSS[135]
R24 VCC1_5_B[31] VCC3_3[01] AF29 AH16 VSS[038] VSS[136] P17
22U_0805_6.3V6M 2.2U_0603_6.3V6K R25 4.7U_0805_10V4Z 0.1U_0402_16V4Z AH19 P23
VCC1_5_B[32] 2 2 VSS[039] VSS[137]
R26 VCC1_5_B[33] VCC3_3[02] AD2 AH2 VSS[040] VSS[138] P28
R27 0.1U_0402_16V4Z AF28 P29
VCC1_5_B[34] VSS[041] VSS[139]
T23 VCC1_5_B[35] VCC3_3[03] AC8 AH22 VSS[042] VSS[140] R11

VCCP_CORE
C +1.5VS_SATAPLL_R +1.5VS_SATAPLL_ICH C
T24 VCC1_5_B[36] VCC3_3[04] AD8 close to AD2 AH24 VSS[043] VSS[141] R12
T27 VCC1_5_B[37] VCC3_3[05] AE8 AH26 VSS[044] VSS[142] R13
+1.5VS L33 1 2 T28 AF8 +3VS AH3 R14
R373 MBK1608121YZF_0603 VCC1_5_B[38] VCC3_3[06] VSS[045] VSS[143]
T29 VCC1_5_B[39] AH4 VSS[046] VSS[144] R15
1_0603_5% 1 U24 AA3 1 1 1 AH8 R16
C368 VCC1_5_B[40] VCC3_3[07] C369 C370 C371 VSS[047] VSS[145]
U25 VCC1_5_B[41] VCC3_3[08] U7 AJ5 VSS[048] VSS[146] R17
C367 V23 V7 B11 R18

IDE
VCC1_5_B[42] VCC3_3[09] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[049] VSS[147]
10U_0805_10V4Z V24 VCC1_5_B[43] VCC3_3[10] W1 B14 VSS[050] VSS[148] R28
2 2 2 2
(10UF*1, 1UF*1) V25 VCC1_5_B[44] VCC3_3[11] W6 B17 VSS[051] VSS[149] R4
1U_0603_10V4Z W25 W7 0.1U_0402_16V4Z B2 T12
VCC1_5_B[45] VCC3_3[12] VSS[052] VSS[150]
Y25 VCC1_5_B[46] VCC3_3[13] Y7 B20 VSS[053] VSS[151] T13
close to AF29 close to AA3 B22 VSS[054] VSS[152] T14
AJ6 VCCSATAPLL VCC3_3[14] A8 B8 VSS[055] VSS[153] T15
VCC3_3[15] B15 +3VS C24 VSS[056] VSS[154] T16
+1.5VS AE7 VCC1_5_A[01] VCC3_3[16] B18 C26 VSS[057] VSS[155] T17
AF7 B4 +VCC_HDA_ICH C27 T2
VCC1_5_A[02] VCC3_3[17] 1 1 1 VSS[058] VSS[156]
ARX

AG7 B9 C372 C373 C374 C6 U12


C375 C376 VCC1_5_A[03] VCC3_3[18] R374 0_0603_5% VSS[059] VSS[157]
AH7 C15 D12 U13
PCI
VCC1_5_A[04] VCC3_3[19] +3VS VSS[060] VSS[158]
AJ7 D13 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 D15 U14
1U_0603_10V4Z VCC1_5_A[05] VCC3_3[20] 2 2 2 C377 VSS[061] VSS[159]
VCC3_3[21] D5 D18 VSS[062] VSS[160] U15
AC1 E10 0.1U_0402_16V4Z D2 U16
1U_0603_10V4Z VCC1_5_A[06] VCC3_3[22] 0.1U_0402_16V4Z VSS[063] VSS[161]
close to AE7 AC2 VCC1_5_A[07] VCC3_3[23] E7
2
D4 VSS[064] VSS[162] U17
ATX

AC3 VCC1_5_A[08] VCC3_3[24] F11 E21 VSS[065] VSS[163] U23


AC4 VCC1_5_A[09] E24 VSS[066] VSS[164] U26
AC5 AC12 +VCCSUS_HDA_ICH E4 U27
VCC1_5_A[10] VCCHDA VSS[067] VSS[165]
close to AC1 E9 VSS[068] VSS[166] U3
AC10 AD11 R376 0_0603_5% +3VALW F15 U5
VCC1_5_A[11] VCCSUSHDA VSS[069] VSS[167]
AC9 VCC1_5_A[12] 1 E23 VSS[070] VSS[168] V13
J6 TP_VCCSUS1_05_ICH_1 PAD C378 F28 V15
VCCSUS1_05[1] T7 VSS[071] VSS[169]
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 TP_VCCSUS1_05_ICH_2 PAD T8 F29 VSS[072] VSS[170] V28
B AA6 0.1U_0402_16V4Z F7 V29 B
VCC1_5_A[14] 2 VSS[073] VSS[171]
VCCSUS1_5[1] AC16 TP_VCCSUS1_5_ICH_1 PAD T9 G1 VSS[074] VSS[172] W2
G12 VCC1_5_A[15] E2 VSS[075] VSS[173] W26
+1.5VS G17 J7 TP_VCCSUS1_5_ICH_2 PAD G10 W27
VCC1_5_A[16] VCCSUS1_5[2] T10 VSS[076] VSS[174]
H7 VCC1_5_A[17] G13 VSS[077] VSS[175] Y28
1 1 VCCSUS3_3[01] C3 +3VALW G19 VSS[078] VSS[176] Y29
C379 C380 AC7 G23 Y4
VCC1_5_A[18] VSS[079] VSS[177]
AD7 VCC1_5_A[19] VCCSUS3_3[02] AC18 1 1 G25 VSS[080] VSS[178] AB4
0.1U_0402_16V4Z AC21 C381 C382 C383 G26 AB23
VCCPSUS

2 2 VCCSUS3_3[03] VSS[081] VSS[179]


D1 VCCUSBPLL VCCSUS3_3[04] AC22 G27 VSS[082] VSS[180] AB5
0.1U_0402_16V4Z AG20 4.7U_0805_10V4Z 0.1U_0402_16V4Z (0.1UF*1, 0.022UF*2) H25 AB6
VCCSUS3_3[05] 2 2 VSS[083] VSS[181]
USB CORE

F1 VCC1_5_A[20] VCCSUS3_3[06] AH28 H28 VSS[084] VSS[182] AD5


L6 0.1U_0402_16V4Z H29 U4
VCC1_5_A[21] VSS[085] VSS[183]
close to F1 L7 VCC1_5_A[22] VCCSUS3_3[07] P6 H3 VSS[086] VSS[184] W24
close to D1 M6 VCC1_5_A[23] VCCSUS3_3[08] P7 H6 VSS[087]
M7 VCC1_5_A[24] VCCSUS3_3[09] C1 close to P6 close to AC18 J1 VSS[088] VSS_NCTF[01] A1
+3VS VCCSUS3_3[10] N7 J25 VSS[089] VSS_NCTF[02] A2
1 W23 P1 J26 A28
VCCPUSB

C384 VCC1_5_A[25] VCCSUS3_3[11] VSS[090] VSS_NCTF[03]


VCCSUS3_3[12] P2 J27 VSS[091] VSS_NCTF[04] A29
PAD TP_VCCLAN1_05_ICH_1 F17 P3 J4 AH1
T11 VCCLAN1_05[1] VCCSUS3_3[13] VSS[092] VSS_NCTF[05]
PAD TP_VCCLAN1_05_ICH_2 G18 P4 J5 AH29
2 T12 VCCLAN1_05[2] VCCSUS3_3[14] VSS[093] VSS_NCTF[06]
VCCSUS3_3[15] P5 K23 VSS[094] VSS_NCTF[07] AJ1
0.1U_0402_16V4Z F19 R1 K28 AJ2
VCCLAN3_3[1] VCCSUS3_3[16] VSS[095] VSS_NCTF[08]
G20 VCCLAN3_3[2] VCCSUS3_3[17] R3 K29 VSS[096] VSS_NCTF[09] AJ28
VCCSUS3_3[18] R5 1 K3 VSS[097] VSS_NCTF[10] AJ29
+1.5VS +VCC_GLANPLL_R 1 2 +VCC_GLANPLL_ICH A24 R6 C385 C386 K6 B1
VCCGLANPLL VCCSUS3_3[19] VSS[098] VSS_NCTF[11]
GLAN POWER

R378 MBK1608121YZF_0603 1 (0.1UF*1) B29


VSS_NCTF[12]
1_0603_5% L34 C388 A26 VCCGLAN1_5[1] VCCCL1_05 G22 TP_VCCCL1_05_ICH PAD T13
@ 1U_0603_10V4Z
C387 2 ICH8M_BGA676~D
A27 VCCGLAN1_5[2]
(10UF*1, 1UF*1) 10U_0805_10V4Z B26 A22 +VCCCL1_5_INT_ICH @ 0.1U_0402_16V4Z <BOM Structure>
A 2 VCCGLAN1_5[3] VCCCL1_5 A
B27 VCCGLAN1_5[4]
2.2U_0603_6.3V6K B28 F20 +3VS
VCCGLAN1_5[5] VCCCL3_3[1]
VCCCL3_3[2] G21
B25 VCCGLAN3_3
+1.5VS_PCIE_ICH
ICH8M_BGA676~D
C389 <BOM Structure>
(220UF*1, 1UF*1) 4.7U_0805_10V4Z
+3VS Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8-M(4/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 23 of 48
5 4 3 2 1
A B C D E

+3VS +5VS Place component's closely SATA CONN. +3VS +5VS Place component's closely SATA CONN.

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C390 C391 C392 C393 C394 C395 C396 C397 C398 C399 C400 C401 C402 C403 C404 C405
2HDD@ 2HDD@
@ 10U_0805_10V4Z @ 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z @ 10U_0805_10V4Z @ 0.1U_0402_16V4Z 10U_0805_10V4Z 2HDD@ 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2HDD@ 2 2 2
@ 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1

SATA HDD-1 Conn.(5.2mm) SATA HDD-2 Conn.(11.8mm)


JP10 2HDD@
JP11
SATA_TXP2_C 2 1 1
SATA_TXP0_C <21> SATA_TXP2_C 3900P_0402_50V7K C406 2HDD@ SATA_TXP2 GND
<21> SATA_TXP0_C 2 1 1 GND 2 A+
3900P_0402_50V7K C407 SATA_TXP0 2 SATA_TXN2_C 2 1 SATA_TXN2 3
SATA_TXN0_C SATA_TXN0 A+ <21> SATA_TXN2_C 3900P_0402_50V7K C408 2HDD@ A-
<21> SATA_TXN0_C 2 1 3 A- 4 GND
3900P_0402_50V7K C409 4 <21> SATA_RXN2_C SATA_RXN2_C 2 1 SATA_RXN2 5
SATA_RXN0_C SATA_RXN0 GND 3900P_0402_50V7K C410 2HDD@ SATA_RXP2 B-
<21> SATA_RXN0_C 2 1 5 B- 6 B+
3900P_0402_50V7K C411 SATA_RXP0 6 <21> SATA_RXP2_C SATA_RXP2_C 2 1 7
SATA_RXP0_C B+ 3900P_0402_50V7K C412 2HDD@ GND
<21> SATA_RXP0_C 2 1 7 GND
3900P_0402_50V7K C413

+3VS 8 V33 +3VS 8 VCC3.3


9 V33 9 VCC3.3
10 V33 10 VCC3.3
11 GND 11 GND
12 GND 12 GND
13 GND 13 GND
+5VS 14 V5 +5VS 14 VCC5
15 V5 15 VCC5
16 V5 16 VCC5
17 GND 17 GND
2 2
18 Reserved 18 RESERVED
19 GND 19 GND
20 V12 20 VCC12
21 V12 GND 24 21 VCC12 GND 24
22 V12 GND 23 22 VCC12 GND 23

SUYIN_060802-TK103_22P SUYIN_060802-TK102_22P

Placea caps. near ODD CONN.


+5VS

1 1 1 1
IDE_DD[0..15] C414 C415 C416 C417
<21> IDE_DD[0..15]
IDE_DA[0..2] 10U_0805_10V4Z 0.1U_0402_16V4Z
<21> IDE_DA[0..2] 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z
Place component's closely ODD CONN.

3 3

ODD CONN
JP12
1 2
3 4 1 2
5 6 IDE_DD8 R379 @ 0_0603_5%
<21> ODD_RST#
IDE_DD7 7 8 IDE_DD9
IDE_DD6 9 10 IDE_DD10
IDE_DD5 11 12 IDE_DD11
IDE_DD4 13 14 IDE_DD12
IDE_DD3 15 16 IDE_DD13
IDE_DD2 17 18 IDE_DD14
IDE_DD1 19 20 IDE_DD15
IDE_DD0 21 22 PD_DREQ
IDE_DDREQ <21>
23 24 PD_IOR#
IDE_DIOR# <21>
IDE_DIOW# 25 26
<21> IDE_DIOW#
IDE_DIORDY 27 28 IDE_DDACK#
<21> IDE_DIORDY IDE_DDACK# <21>
PD_IRQ 29 30
<21> IDE_IRQ
IDE_DA1 31 32 IDE_PDIAG# R380
1 2 +5VS
IDE_DA0 33 34 IDE_DA2 100K_0402_5%
<21> IDE_DCS1# IDE_DCS#1 35 36 IDE_DCS#3 IDE_DCS3# <21>
2 1 100K_0402_5% 37 38 W=80mils
+5VS +5VS
R381 +5VS 39 40 +5VS
+5VS 41 42 +5VS
43 44 2 1
45 46
4 SEC_CSEL C418 0.1U_0402_16V4Z 4
2 1 47 48
R382 470_0402_5% 49 50
53 54

OCTEK_CDR-50JD1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA & ODD Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 24 of 48
A B C D E
5 4 3 2 1

+5VS
+3VS
PCI8412:6IN1 + 1394 + CardBus CHB1608U301_0603

1
0.01U_0402_16V7K 1 2
R383
1 1 1 1 1 L35 120_0402_5%
C419 C420 C421 C422 C423 7412@
+3VS +AVDD_7412

2 2
+3VS 10U_0805_10V4Z 0.1U_0402_16V4Z
CHB1608U301_0603 2 2 2 2 2 D13
0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 0.01U_0402_16V7K
C424 0.01U_0402_16V7K 0.1U_0402_16V4Z 7412@
1 L36 1 1 1 1 1 1 2 VSSPLL 6 IN 1 LED HT-191NB_BLUE_0603
C425 C426 C427 C428 C429 0.1U_0402_16V4Z
+3VS

1 1
D C447 C448 0.1U_0402_16V4Z 10U_0805_10V4Z D
1 2 D
2 2 2 2 2 2 C430 1U_0603_10V4Z Q9
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 5IN1_LED 2
0.01U_0402_16V7K 1 1 1 1 2 G

2
7412@ S

3
C431 C432 C433 C434 C435 R384 2N7002_SOT23

U15

U19
P13
P14

P15

K19

W8
1U_0603_10V4Z 10K_0402_5%

K1

P1
U15B 2 2 2 2 1 7412@
0.1U_0402_16V4Z 0.01U_0402_16V7K

VCCP
VCCP
AVDD_33
AVDD_33
AVDD_33

VDDPLL_33
VDDPLL_15

VR_PORT
VR_PORT

1
PCI_AD[0..31] M1 PCI_AD31
<20> PCI_AD[0..31] AD31
M2 PCI_AD30
PCI_CBE#[0..3] AD30 PCI_AD29
<20> PCI_CBE#[0..3] AD29 M3
M6 PCI_AD28 +VCC_5IN1
MC_PWRON# AD28 PCI_AD27
C8 MC_PWR_CTRL_0 AD27 M5
SM_RB F8 N1 PCI_AD26 1 2
MC_PWR_CTRL_1/SM_R/B# AD26 PCI_AD25 R745 0_0402_5%
AD25 N2
33_0402_5% R388 N3 PCI_AD24 7412@
MSCLK_SDCLK AD24 PCI_AD23 MSBS_SDCMD_SMWE# L76
2 1 AD23 P3 1 2
1 7412@ SD_CD# E9 R1 PCI_AD22 R385 100K_0402_5% XTPA0+ 4 3 XTPA0+_C
MS_CD# SD_CD# AD22 PCI_AD21 7412@ 4 3
A8 MS_CD# AD21 R2
C778 B8 P5 PCI_AD20 SMRE 1 2
@ 0.01U_0402_16V7K SM_CD# AD20 PCI_AD19 R386 100K_0402_5% XTPA0- XTPA0-_C
AD19 R3 1 1 2 2
2 PCI_AD18 7412@
AD18 T1
T2 PCI_AD17 SDWP#_SMCE# 1 2 @ WCM2012F2S-900T04_0805 JP13
MSCLK_SDCLK_SMELWP# AD17 PCI_AD16 R387 100K_0402_5%
A7 MS_CLK/SD_CLK/SM_EL_WP# AD16 W4 4 4
MSBS_SDCMD_SMWE# E8 W7 PCI_AD15 7412@ 1 R744 2 3 6
7412@ R390 MSD3_SDD3_SMD3 MS_BS/SD_CMD/SM_WE# AD15 PCI_AD14 SM_RB 3 6
B6 MS_DATA3/SD_DAT3/SM_D3 AD14 R8 1 2 1 2 0_0402_5% 2 2 5 5
SMELWP# 2 1 MSD2_SDD2_SMD2 A6 U8 PCI_AD13 R389 22K_0402_5% R746 0_0402_5% 1
33_0402_5% MSD1_SDD1_SMD1 MS_DATA2/SD_DAT2/SM_D2 AD13 PCI_AD12 1
1 C7 MS_DATA1/SD_DAT1/SM_D1 AD12 V8
MSD0_SDD0_SMD0 B7 W9 PCI_AD11 L77 FOX_UV31413-4R1-TR
C831 MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD11 PCI_AD10 XTPB0+ XTPB0+_C
AD10 V9 1 1 2 2
@ 0.01U_0402_16V7K U9 PCI_AD9
C 2 AD9 PCI_AD8 C
AD8 R9
V10 PCI_AD7 XTPB0- 4 3 XTPB0-_C
SMRE AD7 PCI_AD6 CLK_PCI_PCM 4 3
A4 SD_CLK/SM_RE# AD6 U10
SDCMD_SMALE PCI_AD5 @ WCM2012F2S-900T04_0805
place near Chip 8412 C5 SD_CMD/SM_ALE AD5 R10

1
SDD0_SMD4 C6 W11 PCI_AD4
CLK_48M_CB SDD1_SMD5 SD_DAT0/SM_D4 AD4 PCI_AD3 R391
A5 SD_DAT1/SM_D5 AD3 V11 1 2
SDD2_SMD6 B5 U11 PCI_AD2 R747 0_0402_5%
SD_DAT2/SM_D6 AD2
1

SDD3_SMD7 E6 P11 PCI_AD1 @ 10_0402_5%


R392 SDWP#_SMCE# SD_DAT3/SM_D7 AD1 PCI_AD0
E7 R11

2
SD_WP/SM_CE# AD0
1
@ 10_0402_5% G5 C436
SC_PWR_CTRL PCI_CBE#3
P2
2

SMCLE C/BE3# PCI_CBE#2 @ 15P_0402_50V8J


B4 U5
1
C437 XD_CD# A3
SM_CLE C/BE2#
V7 PCI_CBE#1 2 +3VS 6 In 1 Card Power Switch
@ 10P_0402_50V8K
XD_CD#/SM_PHYS_WP#
PCI7412 C/BE1#
C/BE0# W10 PCI_CBE#0
+VCC_5IN1
2
PAR U7 PCI_PAR <20>

2
R394 1 2 1K_0402_5% P12 R6 PCI_FRAME# <20>
TEST0 FRAME# R393 U16
<16> CLK_48M_CB F1 CLK_48 TRDY# W5 PCI_TRDY# <20>
+3VS R395 1 2 4.7K_0402_5% P17 V5 PCI_IRDY# <20> 10K_0402_5% 1 8
PHY_TEST_MA IRDY# 7412@ GND OUT 4.7U_0805_10V4Z
STOP# V6 PCI_STOP# <20> 2 IN OUT 7
1U_0603_10V4Z

2 U6 PCI_DEVSEL# <20> 3 6

1
DEVSEL# IN OUT
1

1
56.2_0603_1%

56.2_0603_1%
C441

R397

R398

IDSEL N5 2 R396 1 PCI_AD20 MC_PWRON# 4 EN# FLG 5 1 1


R399 6.34K_0402_1% R7 100_0402_5% 7412@
PERR# PCI_PERR# <20>
1 2 T18 W6 G528_SO8 C438 C440
1 R0 SERR# PCI_SERR# <20>
T19 L3 7412@ 0.1U_0402_16V4Z C439 7412@ 7412@
R1 REQ# PCI_REQ#2 <20> 2 2
XTPBIAS0 R13 L2 PCI_GNT#2 <20>
2

XTPA0+ TPBIAS0 GNT#


V14
XTPA0-
XTPB0+
W14
TPA0P
TPA0N PCLK L1 CLK_PCI_PCM
PCI_RST#
CLK_PCI_PCM <16> 6 in 1 CardReader Conn. 1U_0603_10V4Z
V13 TPB0P PRST# K3 PCI_RST# <20,27,33,37>
XTPB0- W13 K5 JP14
TPB0N GRST#
220P_0402_50V7K 56.2_0603_1%

5.1K_0603_1% 56.2_0603_1%

1 2 W17 TPBIAS1 RI_OUT#/PME# L5 +VCC_5IN1 41 XD-VCC SD-VCC 15 +VCC_5IN1


1

1
R400

R401

B C442 1U_0603_10V4Z R402 B


V16 TPA1P MS-VCC 9
1K_0402_5% W16 J5 1 2 +3VS MSD0_SDD0_SMD0 33
R403 TPA1N SUSPEND# 43K_0402_5% MSD1_SDD1_SMD1 XD-D0 MSCLK_SDCLK
1 2 V15 TPB1P 34 XD-D1 4 IN 1 CONN SD_CLK 16
R404 1 2 W15 H3 MSD2_SDD2_SMD2 35 19 MSD0_SDD0_SMD0
TPB1N SPKROUT PCM_SPK <29> XD-D2 SD-DAT0
1K_0402_5% CPS R12 R405 1 2 43K_0402_5% MSD3_SDD3_SMD3 36 20 MSD1_SDD1_SMD1
2

CPS PIRQA R406 0_0402_5% SDD0_SMD4 XD-D3 SD-DAT1 MSD2_SDD2_SMD2


MFUNC0 G1 2 1 PCI_PIRQA# <20> 37 XD-D4 SD-DAT2 11
X_OUT R18 H5 PIRQB R407 2 1 0_0402_5% SDD1_SMD5 38 12 MSD3_SDD3_SMD3
XO MFUNC1 PCI_PIRQB# <20> XD-D5 SD-DAT3
1
C443

1 X_IN R19 H2 PIRQC R408 2 1 0_0402_5% SDD2_SMD6 39 13 MSBS_SDCMD_SMWE#


XI MFUNC2 PCI_PIRQC# <20> XD-D6 SD-CMD
R409

H1 SDD3_SMD7 40 21 SD_CD#
+3VS MFUNC3 SIRQ <22,33,37> XD-D7 SD-CD-SW
J1 DEVICE_ID 22
MFUNC4 5IN1_LED MSBS_SDCMD_SMWE# SD-CD-COM SDWP#_SMCE#
MFUNC5 J2 30 XD-WE SD-WP-SW 43
2 SMELWP#
J3 2 1 +3VS 31 44
2

R412 1 MFUNC6 XD-WP SD-WP-COM


2 CPS R411 10K_0402_5% SDCMD_SMALE 29 XD-ALE
4.7K_0402_5% G2 1 2 XD_CD# 23 8 MSCLK_SDCLK
SCL XD-CD MS-SCLK
SDA G3 1 R413 2 300_0402_5% SM_RB 25 XD-R/B MS-DATA0 4 MSD0_SDD0_SMD0
+5VS
VSSPLL

R414 300_0402_5% SMRE 26 3 MSD1_SDD1_SMD1


XD-RE MS-DATA1
AGND
AGND
AGND

K2 SDWP#_SMCE# 27 5 MSD2_SDD2_SMD2
VR_EN# XD-CE MS-DATA2

2
SMCLE 28 7 MSD3_SDD3_SMD3
R668 XD-CLE MS-DATA3 MS_CD#
MS-INS 6
2

8412@ PCI7412ZHK_PBGA257 1 10K_0402_5% 32 2 MSBS_SDCMD_SMWE#


R14
U13
U14

R17

C445 XD-GND MS-BS


CLOSE TO CHIP R415 0.1U_0402_16V4Z
24 XD-GND SD-GND 14
17

1
VSSPLL 1K_0402_5% SD-GND
42 1

GND
GND
N.C.
N.C.
18P_0402_50V8J C444 X_OUT 2 DEVICE_ID N.C. MS-GND
18 10
1

N.C. MS-GND
2

2
TAITW_R007-530-L3 7412@

45
46
47
48
X1 R669
24.576MHz_16P_3XG-24576-43E1 @ 10K_0402_5%
Pull High for 8412
1

+VCC_5IN1
Pull Down for 8402 Bottom Side, Normal Insertion
1

18P_0402_50V8J C446 X_IN


For EMI
1

A A
R416 PIRQA R417 2 @ 1 0_0402_5% PCI_PIRQE# <20>
PIRQB R418 2 @ 1 0_0402_5% MSCLK_SDCLK 2 R739 1 C832 1 2
PCI_PIRQF# <20>
470_0805_5% PIRQC R419 2 @ 1 0_0402_5% @ 10_0402_5% @ 10P_0402_50V8J
PCI_PIRQG# <20>
7412@
1 2

D
Q10 2 MC_PWRON#
G
2N7002_SOT23
Security Classification Compal Secret Data Compal Electronics, Inc.
S Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title
3

7412@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCI8412/PCI/1394 CONN/CARD SLOT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 25 of 48
5 4 3 2 1
5 4 3 2 1

CardBus Power Switch

U17 +S1_VCC 1 2 PCMCIA@


13 40mil C449 0.1U_0402_16V4Z
VCC PCMCIA@
VCC 12
9 11 C450 0.1U_0402_16V4Z
12V VCC
1 2 PCMCIA@
+S1_VCC +3VS C451 10U_0805_10V4Z
+S1_VPP 1 2 PCMCIA@
D 0.1U_0402_16V4Z C452 0.01U_0402_16V7K D
20mil
PCMCIA@ +5VS 10 1 2 PCMCIA@
C454 VPP C453 1U_0603_10V4Z
0.1U_0402_16V4Z 5
0.1U_0402_16V4Z C455 C456 C457 C458 5V
6 5V
4.7U_0805_10V4Z C459
PCMCIA@ 1 VCCD0#
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCCD0 VCCD1#
VCCD1 2
15 VPPD0
PCMCIA@ +3VS VPPD0 VPPD1
14

A15

P10
F12
F14
VPPD1

L14
J19

J14
C460

P6
P8
F6
F9

L6
J6
U15A 0.1U_0402_16V4Z 3 3.3V
4 8

VCCB
VCCB

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
3.3V OC

SHDN
S1_D10 C10 4.7U_0805_10V4Z C461

GND
S1_D9 CAD31/D10 PCMCIA@
A10 CAD30/D9

2
S1_D1 F11 B9 VPPD1
S1_D8 CAD29/D1 DATA/VD2/VPPD1 VCCD0# R421 TPS2211AIDBR_SSOP16
E11 A9

16
S1_D0 CAD28/D8 CLOCK/VD1/VCCD0# VPPD0 10K_0402_5% PCMCIA@
C11 CAD27/D0 LATCH/VD3/VPPD0 C9
S1_A0 B13 PCMCIA@
S1_A1 CAD26/A0
C13

1
S1_A2 CAD25/A1 R422 0_0402_5%
A14 CAD24/A2
S1_A3 B14 2 1
CAD23/A3 PCM_DISABLE# <22>
S1_A4 B15 PCMCIA@
S1_A5 CAD22/A4
E14 CAD21/A5
S1_A6 A16
S1_A25 CAD20/A6 ***
D19 CAD19/A25
S1_A7 E17 B10 S1_D2 JP15
S1_A24 CAD18/A7 RSVD/D2 VCCD1#
F15 CAD17/A24 RSVD/VD0/VCCD1# C4 GND 1
S1_A17 H19 D1 35
CAD16/A17 RSVD GND

2
S1_IOWR# J17 E1 2 S1_D3
S1_A9 CAD15/IOWR# RSVD +3VS R423 DATA3 S1_CD1#
J15 CAD14/A9 RSVD E2 CD1# 36
S1_IORD# J18 E3 43K_0402_5% 3 S1_D4
C S1_A11 CAD13/IORD# RSVD DATA4 S1_D11 C
K15 CAD12/A11 RSVD F2 DATA11 37
S1_OE# K17 F3 4 S1_D5

1
S1_CE2# CAD11/OE# RSVD R424 0_0402_5% DATA5 S1_D12
K18 CAD10/CE2# RSVD F5 DATA12 38
S1_A10 L15 G6 2 1 5 S1_D6
S1_D15 CAD9/A10 RSVD DATA6
L18 CAD8/D15 RSVD H17 S1_A18 DATA13 39 S1_D13
S1_D7 L19 M19 S1_D14 6 S1_D7
S1_D13 CAD7/D7 RSVD DATA7 S1_D14
M17 CAD6/D13 DATA14 40
S1_D6 M18 7 S1_CE1#
S1_D12 CAD5/D6 CE1# S1_D15
N19 CAD4/D12 NC A2 DATA15 41
S1_D5 M15 A17 8 S1_A10
S1_D11 CAD3/D5 NC ADD10 S1_CE2#
N17 CAD2/D11 NC A18 CE2# 42
S1_D4 N18 B1 9 S1_OE#
S1_D3 P19
CAD1/D4 NC
B2
Near to PCMCIA slot. OE#
43 S1_VS1
CAD0/D3 NC VS1# S1_A11
NC B3 ADD11 10
B17 44 S1_IORD#
S1_REG#
S1_A12
E13
E18
CC/BE3#/REG# PCI 7412 NC
NC B18
B19
+S1_VCC IORD#
ADD9 11
45
S1_A9
S1_IOWR#
S1_A8 CC/BE2#/A12 NC IOWR# S1_A8
H18 CC/BE1#/A8 NC C1 ADD8 12
S1_CE1# L17 C2 1 1 46 S1_A17
CC/BE0#/CE1# NC C462 C463 ADD17 S1_A13
NC C3 ADD13 13
S1_A13 H14 C16 47 S1_A18
S1_A23 CPAR/A13 NC 10U_0805_10V4Z 0.1U_0402_16V4Z ADD18 S1_A14
E19 CFRAME#/A23 NC C17 ADD14 14
S1_A22 2 2 S1_A19
G15 CTRDY#/A22 NC C18 ADD19 48
S1_A15 F17 C19 15 S1_WE#
S1_A20 CIRDY#/A15 NC PCMCIA@ PCMCIA@ WE# S1_A20
G18 CSTOP#/A20 NC D2 ADD20 49
S1_A21 F19 D3 16 S1_RDY#
S1_A19 CDEVSEL#/A21 NC READY S1_A21
H15 CBLOCK#/A19 NC D17 ADD21 50
S1_A14 G19 D18 17 +S1_VCC
CPERR#/A14 NC VCC +S1_VCC
S1_WAIT# C12 E5 51
S1_INPACK# CSERR#/WAIT# NC +S1_VPP VCC
C14 CREQ#/INPACK# NC N14 VPP 18
S1_WE# G17 P18 52 +S1_VPP
S1_BVD1 CGNT#/WE# NC VPP S1_A16_C +S1_VPP
A12 CSTSCHG/BVD1(STSCHG#/RI#) NC T3 ADD16 19
B R425 S1_WP S1_A22 B
A11 CCLKRUN#/WP(IOIS16#) NC T17 1 1 ADD22 53
S1_A16_C 1 2 S1_A16 F18 U1 C464 C465 20 S1_A15
33_0402_5% S1_RDY# CCLK/A16 NC ADD15 S1_A23
E12 CINT#/READY(IREQ#) NC U2 ADD23 54
U3 10U_0805_10V4Z 0.1U_0402_16V4Z 21 S1_A12
S1_RST NC 2 2 ADD12 S1_A24
C15 CRST#/RESET NC U4 ADD24 55
U12 22 S1_A7
S1_BVD2 NC PCMCIA@ PCMCIA@ ADD7 S1_A25
B12 CAUDIO/BVD2(SPKR#) NC U16 ADD25 56
U17 69 23 S1_A6
S1_CD1# NC GND ADD6 S1_VS2
N15 CCD1#/CD1# NC U18 70 GND VS2# 57
S1_CD2# B11 V1 71 24 S1_A5
S1_VS1 CCD2#/CD2# NC GND ADD5 S1_RST
A13 CVS1/VS1# NC V2 72 GND RESET 58
S1_VS2 B16 V3 73 25 S1_A4
CVS2/VS2# NC GND ADD4 S1_WAIT#
NC V4 74 GND WAIT# 59
V12 75 26 S1_A3
NC GND ADD3 S1_INPACK#
E10 A_USB_EN# NC V17 76 GND INPACK# 60
2 1 S1_CD1# V18 77 27 S1_A2
C466 100P_0402_50V8J NC GND ADD2 S1_REG#
NC V19 78 GND REG# 61
W2 79 28 S1_A1
NC GND ADD1 S1_BVD2
NC W3 80 GND BVD2 62
W12 81 29 S1_A0
S1_CD2# NC GND ADD0 S1_BVD1
2 1 W18 82 63
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

C467 100P_0402_50V8J NC GND BVD1 S1_D0


83 GND DATA0 30
84 64 S1_D8
PCI7412ZHK_PBGA257 GND DATA8 S1_D1
31
F7
F10
F13
G14
H6
K6
K14
M14
N6
P7
P9

8412@ DATA1 S1_D9


DATA9 65
32 S1_D2
DATA2 S1_D10
85 GND DATA10 66
86 33 S1_WP
GND WP S1_CD2#
87 GND CD2# 67
88 GND GND 34
GND 68
A SANTA_130606-1_LT A
PCMCIA@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCI7412/CB/CB SLOT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 26 of 48
5 4 3 2 1
A B C D E

New Card Power Switch

1 1

JP16
U18
60mils 1 GND
+3VS 5 3.3Vin1 3.3Vout1 7 +3VS_CARD <22> USB20_N9 2 USB_D-
6 3.3Vin2 3.3Vout2 8 <22> USB20_P9 3 USB_D+
CP_USB# 4 CPUSB#
5 RSV
40mil 6 RSV
+3VALW 21 3.3Vaux_in Aux_out 20 +3VALW_CARD <14,15,16,22,32> ICH_SMBCLK 7 SMB_CLK
<14,15,16,22,32> ICH_SMBDATA 8 SMB_DATA
40mil +1.5VS_CARD 9 +1.5V
+1.5VS 18 1.5Vin1 1.5Vout1 16 +1.5VS_CARD 10 +1.5V
19 1.5Vin2 1.5Vout2 17 <22,32,33> ICH_PCIE_WAKE# 11 WAKE#
+3VALW_CARD 12 +3.3VAUX
NEWCARD@ PERST1# 13
R426 2 PERST#
+3VALW 1 100K_0402_5% CP_USB# 14 CPUSB# +3VS_CARD 14 +3.3V
R427 1 2 100K_0402_5% EXP_CPPE# 15 23 15
NEWCARD@ CPPE# OC# CLKREQ# +3.3V
<19,33,34,38,43,44,45> SUSP# 4 STBY# 16 CLKREQ#
3 22 RCLKEN <22> EXP_CPPE# EXP_CPPE# 17
<29,33,36,38,43> SYSON SHDN# RCLKEN CPPE#
PCI_RST# 2 9 PERST1# 18
<20,25,33,37> PCI_RST# SYSRST# PERST# <16> CLK_PCIE_CARD# REFCLK-
2 19 2
<16> CLK_PCIE_CARD REFCLK+
20
GND

NC1
NC2
NC3
NC4
NC5

GND
<22> PCIE_PTX_C_IRX_N1 21 PERn0
<22> PCIE_PTX_C_IRX_P1 22 PERp0
NEWCARD@ TPS2231PWPR_PWP24 23 29
11

1
10
12
13
24

GND GND
<22> PCIE_ITX_C_PRX_N1 24 PETn0 GND 30
<22> PCIE_ITX_C_PRX_P1 25 PETp0 GND 31
26 GND GND 32

27 GND
28 GND
+3VS +3VS
TYCO_1759056-1
NEWCARD@
1

+3VS 1
R428
10K_0402_5% C480
1

NEWCARD@ 0.1U_0402_16V4Z
R429 2 NEWCARD@
2

NEWCARD@ 10K_0402_5% U19


CLKREQ# 2
P

I0
4 EXP_CLKREQ# <16>
2

O +3VS +3VALW +1.5VS


1 I1
G
1

D TC7SH32FU_SSOP5
3

RCLKEN 2 Q11 NEWCARD@ 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M


G 2N7002_SOT23 NEWCARD@ NEWCARD@ NEWCARD@
S NEWCARD@
3

3 3
1 2 1 1 1 1 1 1
R430 @ 0_0402_5% C468 C469 C470 C471 C472 C473

0.1U_0402_16V4Z
NEWCARD@ 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z
NEWCARD@ NEWCARD@

+3VALW_CARD +3VS_CARD +1.5VS_CARD


Imax = 0.275A Imax = 1.35A Imax = 0.75A

1 1 1 1 1 1
C474 C475 C476 C477 C478 C479

NEWCARD@ 10U_0805_6.3V6M NEWCARD@ 10U_0805_6.3V6M NEWCARD@ 10U_0805_6.3V6M


2 2 2 2 2 2
NEWCARD@ 0.1U_0402_16V4Z
NEWCARD@ 0.1U_0402_16V4Z NEWCARD@ 0.1U_0402_16V4Z

4 4

Compal Electronics, Inc.


Title
New Card Socket
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ISRAA LA-3441P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, September 22, 2006 Sheet 27 of 48
A B C D E
5 4 3 2 1

1 2 +3VALW
R431 +3VALW
3.6K_0402_5%
Place Close to Chip U20
U21
C481 1 2 0.1U_0402_16V4Z PCIE_PTX_IRX_P2 29 45 4 5 2
<22> PCIE_PTX_C_IRX_P2 HSOP EEDO DO GND
47 3 6 C483 2 2 2 2 2
C482 1 EDDI/AUX DI NC
<22> PCIE_PTX_C_IRX_N2 2 0.1U_0402_16V4Z PCIE_PTX_IRX_N2 30 HSON EESK 48 2 SK NC 7 C484 C485 C486 C487 C488
EECS 44 1 CS VCC 8 +3VALW
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<22> PCIE_ITX_C_PRX_P2 23 HSIP AT93C46-10SI-2.7_SO8 1 1 1 1 1
<22> PCIE_ITX_C_PRX_N2 24 HSIN
LED3 54
D D
LED2 55
26 56 LAN_LINK#
<16> CLK_PCIE_LAN REFCLK_P LED1
57 LAN_ACTIVITY#
LED0
<16> CLK_PCIE_LAN# 27 REFCLK_N +LAN_VDD18
20 3 LAN_MDI0+
<8,18,20,22,32,33> PLT_RST# PERSTB MDIP0
4 LAN_MDI0- L37
MDIN0 LAN_MDI1+ AVDD18
MDIP1 6
LAN_CTRL18 LAN_MDI1- 0_0603_5%
2K for 8101E(100M) 1000M@
1 VCTRL18 MDIN1 7
2 2 2 2 2 2
2.49K for 8111B(1000M) 1
R664
2
2.49K_0402_1%
LAN_CTRL15 63 VCTRL15 MDIP2 9 LAN_MDI2+
LAN_MDI2-
C489 C490 C491 C492 C493 C494
MDIN2 10
1 2 64 12 LAN_MDI3+ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R432 2K_0402_1% RSET MDIP3 LAN_MDI3- 1 1 1 1 1 1
MDIN3 13
100M@
<33> EC_PME# 1 2 19 LANWAKEB
R433 0_0402_5% 15 +LAN_VDD15
VDD15
VDD15 21
+3VS R434 1 2 1K_0402_1% 36 32
ISOLATEB VDD15
VDD15 33
38 +LAN_VDD15
LAN_X1 VDD15
60 CKXTAL1 VDD15 41
R435 43
LAN_X2 VDD15
61 CKXTAL2 VDD15 49
15K_0402_5% 52
VDD15
VDD15 58 2 2 2 2 2 2
62 C495 C496 C497 C498 C499 C500
GVDD
1 2 16 +3VALW 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C501 VDD33 +3VALW 1 1 1 1 1 1
65 EXPOSE_PAD VDD33 37
C502 53 L38
1U_0603_10V4Z VDD33 AVDD33
0.1U_0402_16V4Z 25 EGND VDD33 46 1 2
C 2 1 BLM18AG601SN1D_0603 C
1 2
31 2 AVDD33 C503 C504
EGND AVDD33 +3VALW +3VALW
59 10U_0805_10V4Z 0.1U_0402_16V4Z
AVDD33 2 1
Y3
LAN_X1 LAN_X2 17 NC AVDD18
18 NC AVDD18 5

1
25MHZ_20P_6X25000017
1
35
34
NC AVDD18 8
11
Mount for 8111B & 8100E
C505 C506 NC AVDD18
39 NC AVDD18 14

3
40 NC
27P_0402_50V8J 27P_0402_50V8J 42
2 2 NC LAN_CTRL18 Q12 LAN_CTRL15 Q13
50 NC EVDD18 22 +LAN_VDD18 1 1
51 40mil MMJT9435T1G_SOT223 40mil MMJT9435T1G_SOT223
NC 1000M@ 1000M@
EVDD18 28

2
4

2
4
RTL8111B_QFN64 1000M@
L39 100M@ 40mil L40 100M@ 40mil
Mount for 8101E 1 2 1 2
+LAN_VDD18 +LAN_VDD15
1 BLM18AG601SN1D_0603 1 2 1 BLM18AG601SN1D_0603 1 2
C507 C508 C509 C511 C512
Place Close to Chip 22U_0805_6.3V6M C510
100M@ 100M@ 22U_0805_6.3V6M 0.1U_0402_16V4Z 22U_0805_6.3V6M 22U_0805_6.3V6M 0.1U_0402_16V4Z
+LAN_VDD18 100M@ R4362 2 2 1 100M@ 2 2 1
1 49.9_0402_1% LAN_MDI0-
C513 2 1 R4372 1 49.9_0402_1% LAN_MDI0+

0.01U_0402_16V7K 100M@ Mount for 8101E Mount for 8101E


100M@
1

100M@ R4382 1 49.9_0402_1% LAN_MDI1-


100M@ 100M@ C514 2 1 R4412 1 49.9_0402_1% LAN_MDI1+
B R439 R440 B
0_0402_5% 0_0402_5% 0.01U_0402_16V7K 100M@ LAN Conn.
Place Close to Chip
2

JP2
+3VALW 12 Amber LED+
U22 LAN_ACTIVITY# 2 1 300_0402_5% 11
R442 Amber LED-
1 SHLD2 16
1 24 RJ45_MIDI3- 8
LAN_MDI3- TCT1 MCT1 RJ45_MIDI3- 68P_0402_50V8K C515 PR4-
2 TD1+ MX1+ 23 SHLD1 15
LAN_MDI3+ 3 22 RJ45_MIDI3+ RJ45_MIDI3+ 7
TD1- MX1- 2 PR4+
4 21 RJ45_MIDI1- 6
LAN_MDI2- TCT2 MCT2 RJ45_MIDI2- PR2-
5 TD2+ MX2+ 20
LAN_MDI2+ 6 19 RJ45_MIDI2+ RJ45_MIDI2- 5
TD2- MX2- PR3-
7 18 RJ45_MIDI2+ 4
LAN_MDI1- TCT3 MCT3 RJ45_MIDI1- PR3+
8 TD3+ MX3+ 17
LAN_MDI1+ 9 16 RJ45_MIDI1+ RJ45_MIDI1+ 3
TD3- MX3- PR2+
10 15 2 RJ45_MIDI0- 2
LAN_MDI0- TCT4 MCT4 RJ45_MIDI0- PR1-
11 TD4+ MX4+ 14 SHLD2 14
LAN_MDI0+ 12 13 RJ45_MIDI0+ 68P_0402_50V8K C516 RJ45_MIDI0+ 1
TD4- MX4- PR1+
SHLD1 13
LAN_LINK# 1
2 1 10 Green LED-
1

1 1 R443 300_0402_5%
0.5u_GST5009 R444 R445 9
C517 C518 1000M@ +3VALW Green LED+
0.01U_0402_16V7K 0.01U_0402_16V7K 75_0402_1% 75_0402_1% C519 TYCO_3-440470-4
1

2 2 RJ45_GND LANGND
1 1 1 2
2

R446 R447 1 1
A C520 C521 1000P_1206_2KV7K C522 C523 A
0.01U_0402_16V7K 0.01U_0402_16V7K 75_0402_1% 75_0402_1%
2 2 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2

RJ45_GND 2 2

Place these components


colsed to LAN chip
Security Classification Compal Secret Data Compal Electronics, Inc.
Title
GST5009 for GIGA LAN Issued Date 2006/06/30 Deciphered Date 2007/06/30
RTL8111B/8101E 10/100/1000 LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TST1284 for 10/100 LAN AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
Custom ISRAA LA-3441P
Rev
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 28 of 48
5 4 3 2 1
5 4 3 2 1

+VDDA
HD Audio Codec

1
+AVDD_AC97 +3VS_DVDD
L42 R448
L41 1 2 0.1U_0402_16V4Z 680P_0402_50V7K 40mil 20mil 0.1U_0402_16V4Z 10U_0805_10V4Z 680P_0402_50V7K 1 2 10K_0402_5%
+VDDA +3VS
FBM-L11-160808-800LMT_0603 1 1 1 1 FBM-L11-160808-800LMT_0603
C525 C526 C527 C528 1 1 1 1

2
C524 C529 C530 C531 C532 C533 C534
10U_0805_10V4Z 1 2
2 2 2 2 C535 1U_0402_6.3V4Z

1
0.1U_0402_16V4Z 100P_0402_50V8J 2 2 2 2
R449
0.1U_0402_16V4Z 680P_0402_50V7K 100P_0402_50V8J 10K_0402_5%
D
Int MIC Conn. EC Beep D

25

38
R450

9
20060825 change to connector U23 C536 1 2 1 2
<33> BEEP#

2
1 1 1U_0402_6.3V4Z 560_0402_5% C537

AVDD1

AVDD2

DVDD_IO
DVDD
+MIC2_VREFO 1 2 C539 C540 1 2 MONO_IN
R451 4.7K_0402_5% 1 2 MIC2_L
JP43 MIC@ C538 100P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 1U_0402_6.3V4Z
PCI Beep

1
INT_MIC AMP_SPK_L 2 2 C
1 1 2 14 NC LINE_OUT_L 35 AMP_SPK_L <30> R453 1 2
2 1 C541 1U_0402_6.3V4Z C543 1 2 1 2 1 2 2 Q14
2 <22> SB_SPKR B R452
C542 MIC@ 1 2 MIC2_R 15 36 AMP_SPK_R 1U_0402_6.3V4Z 560_0402_5% 2SC2411K_SC59 2.4K_0402_5%
NC LINE_OUT_R AMP_SPK_R <30> E
ACES_85204-0200 220P_0402_50V7K C544 1U_0402_6.3V4Z R454

3
MIC@ 1 2 16 39 AMP_HP_L 1K_0402_5%
MIC2_L HP_OUT_L AMP_HP_L <30>
C545 100P_0402_50V8J
1 2 100P_0402_50V8J 17 MIC2_R HP_OUT_R 41 AMP_HP_R
AMP_HP_R <30>
CardBus Beep R455
3

C546 C547 1 2 1 2
<25> PCM_SPK BEEP_MIX <30>
SM05_SOT23

LINE1_L
1 2 1U_0402_6.3V4Z LINE1_C_L 23 45 1U_0402_6.3V4Z 560_0402_5%
<31> LINE1_L LINE1_L NC

1
@ C548 2 D14
LINE1_R
1 2 1U_0402_6.3V4Z LINE1_C_R 24 46
<31> LINE1_R C549 LINE1_R DMIC_CLK C550 R456
1 2 100P_0402_50V8J 18 43 0.01U_0402_16V7K 10K_0402_5% RB751V_SOD323
1

D51 C551 CD_L NC 1

2
1 2 20 CD_R NC 44
C552 100P_0402_50V8J

1
D
1 2 100P_0402_50V8J 19 CD_GND 1 2 ICH_BITCLK_AUDIO <19,21>
C553 6 R457 22_0402_5% 2
BIT_CLK <33> NSE_DPR
MIC1_L 1 2 1U_0402_6.3V4Z MIC1_C_L 21 2 R458 1 C555 1 2 G
<31> MIC1_L C554 MIC1_L @ 10_0402_5% @ 10P_0402_50V8J Q15 S

3
MIC1_R 1 2 1U_0402_6.3V4Z MIC1_C_R 22 8 1 2 ICH_AC_SDIN0 <21> 2N7002_SOT23
<31> MIC1_R C556 MIC1_R SDATA_IN R459 33_0402_5%
C 1 2 100P_0402_50V8J MONO_IN 12 PCBEEP MONO_OUT 37 AMP_SUB <30>
C

1
C557 R460 C
1 2 100P_0402_50V8J LINE1_VREFO 29 +S1_VCC 2 Q16
C558 11 B MMBT3904_SOT23
<19,21> ICH_RST_AUDIO# RESET# E
31 SPDIF_SENSE <31> 2.2K_0402_5%

3
GPIO1
<19,21> ICH_SYNC_AUDIO 10 SYNC
5
MIC1_VREFO_L 28 10mil +MIC1_VREFO_L
<19,21> ICH_SDOUT_AUDIO SDATA_OUT
SPK_SEL HIGH: HARMAN 2
MIC1_VREFO_R 32 10mil +MIC1_VREFO_R
<33> SPK_SEL_CODEC GPIO0
LOW: NO-BRAND SENSE_A
3
13
GPIO3 MIC2_VREFO 30 10mil +MIC2_VREFO
SENSE_B 34
SENSE A
27 ACZ_VREF 10mil 10U_0805_10V4Z
SENSE B VREF
1 1
EAPD 47 40 ACZ_JDREF 20K_0402_1% C559
<30,33> EAPD EAPD JDREF C560
Regulator for CODEC

1
SPDIF 48 33 1
<31> SPDIF SPDIFO NC 2 2
C561
4 26 R461
DVSS1 AVSS1 100P_0402_50V8J 100P_0402_50V8J
7 DVSS2 AVSS2 42
2
SENSE FOR Ext. Mic.

2
ALC268-GR_LQFP48
+5VALW +VDDA
Adjustable Output
R462
DGND AGND Change R13 from 5.1K to 20K_0402_1%
U24 4.75V
<31> MIC_SENSE 1 2 SENSE_A 4 5
20K_0402_1% VIN OUT
2
8 SHDN# BYP 1 2
C562
B 1U_0402_6.3V4Z C563 B
2 NC NC 7
1
1U_0402_6.3V4Z
1
3 GND NC 6
For EMI C564
G982-475P81U_MSOP8
SENSE FOR Int. Mic. <27,33,36,38,43> SYSON 2
R463
1
0_0402_5%
0.1U_0402_16V4Z
C8331 R7402 EAPD
2
10P_0402_50V8J @
1
10_0402_5% @ Sense Pin Impedance Codec Signals
R464
1 2 SENSE_B 39.2K PORT-A (PIN 39, 41)
20K_0402_1%
MIC@ 2 1 C8341 R7412 SPDIF
10P_0402_50V8J @ 10_0402_5% @ 20K PORT-B (PIN 21, 22)
SENSE A
10K PORT-C (PIN 23, 24)

5.1K PORT-D (PIN 35, 36)


Moat Bridge
1 2
39.2K PORT-E (PIN 14, 15) R465 0_0805_5%
SENSE FOR HP 1 2
R466 0_0805_5%

R468
20K PORT-F (PIN 16, 17) 1
R467
2
0_0805_5%
SENSE_A
SENSE B
<31> HP_SENSE 2 1 1 2
39.2K_0402_1% 10K PORT-G (PIN 43, 44) R469 0_0805_5%
A A

5.1K PORT-H (PIN 45, 46)


SENSE FOR LINE

R470
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
SENSE_A
Issued Date 2006/06/30 Deciphered Date 2007/06/30 <Title>
<31> LINE_SENSE 1 2
10K_0402_1%
HD Audio Codec ALC861D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 29 of 48
5 4 3 2 1
5 4 3 2 1

APA2056 Tweeter/HP Amplifier APA2068 Medium Range Amplifier


AMP_SPK_R R759 1 2 @ 0_0402_5% AMP_R
AMP_SPK_L R760 1 2 @ 0_0402_5% AMP_L

+5VSA +5VSA
W=40mil

680P_0402_50V7K

10U_0805_10V4Z
10U_0805_10V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
1 2 1
C567 C568 C569 C570 1 1
D
+5VSA 0.1U_0402_16V7K D
C565 C566
fo=1/(2*3.14*R*C)=106Hz 2 1 2

1
R473 2 2 U25
R=1.5K / C= 1uF
100K_0402_5% 10 1 EC_EAPD
R472 1K_0402_5% VDD MUTE R471 1

11

19

20
10
15 VDD SHUTDOWN# 2 2 +5VSA

1
1 2 U26 100K_0402_5%
R474 1K_0402_5% 9

CVDD

HVDD

PVDD
PVDD

VDD
M_SPK_L- <31>

2
VOLUME VOLUME LOUT-
1 2 7 VOLUME
ROUT- 16 M_SPK_R- <31>

1
<29> AMP_SPK_R 1 2 AMP_R 1 2 AMPR 1 R475 2 8
C571 0.68U_0402_6.3V6K C572 0.1U_0402_16V4Z 0_0402_5% INR_A R478 VOLMAX
3 INR_A ROUT+ 22 H_SPK_R+ <31> LOUT+ 11 M_SPK_L+ <31>
<29> AMP_SPK_L 1 2 AMP_L 1 2 AMPL 1 R476 2 INL_A 5 21 10K_0402_5% 100K_0402_5% 1 R477 2 13
INL_A ROUT- H_SPK_R- <31> SE/BTL#
C573 0.68U_0402_6.3V6K C574 0.1U_0402_16V4Z 0_0402_5% 14
ROUT+ M_SPK_R+ <31>
R479 1 2 100K_0402_5% AMP_EN#27 8 LIN- 6
H_SPK_L+ <31>

2
/AMP EN LOUT+ RIN- LIN-
LOUT- 9 H_SPK_L- <31> 3 RIN-
+5VS R480 1 2 100K_0402_5% HP_EN 24 5
HP EN GND
HP_R 17 HP_R <31> 4 BYPASS GND 12
AMP_R_HPIN 1 R481 2 INR_H 4 18
<29> AMP_HP_R INR_H HP_L HP_L <31>
C575 2.2U_0603_6.3V6K 39K_0402_5% INL_H 6 1 1 APA2068KAI-TRL_SOP16
AMP_L_HPIN INL_H
<29> AMP_HP_L 1 R482 2
EC_EAPD# C578 2.2U_0603_6.3V6K 39K_0402_5% 26 0.1U_0402_16V7K C576 C577
/SD CVSS 2.2U_0805_10V6K
CVSS 15
AMP_BEEP 2 2
1 2 2 R483 1 28 BEEP
C579 0.47U_0402_6.3V6K 0_0402_5% 16
AMP_CP+ VSS
12 CP+
AMP_CP-

1U_0402_6.3V4Z
1 2 14 CP- GND 2 1
C580 1U_0402_6.3V4Z 23 C582 Pin2 /SD should be tied to 5V always and mute pin controled by EC_EAPD
AMP_BIAS PGND
2 1 25 BIAS PGND 7
C C581 2.2U_0805_16V4Z 13 C
CGND 2
2 1
C585 0.1U_0402_16V4Z
C583
APA2056_TSSOP28 R484 1K_0402_1% 0.47U_0402_6.3V6K
<29> AMP_SPK_L 1 2 1 2 1 2 LIN-
+5VSA C584
R761 1 2@ 0_0402_5% AMP_EN# 1U_0402_6.3V4Z
<33> EC_AMP_EN#

2
+VDDA
2
1

R762 1 2@ 0_0402_5% HP_EN R485


<33> EC_HP_EN
5.11K_0402_1% C586
100K_0402_5%

2
33N_0603_16V7K
R488 1

1
R491 20K_0402_5%
2

2 1 EC_EAPD# R486
@ 0_0402_5% C589
C587

1
BEEP_IN 1 2 2 1 AMP_BEEP R487 1K_0402_1% 0.47U_0402_6.3V6K
1

D R490 10K_0402_5% RIN-


<29> AMP_SPK_R 1 2 1 2 1 2

2
EC_EAPD 2 Q45 C 1U_0402_6.3V4Z C588
<33> EC_EAPD
G 2N7002_SOT23 2 Q17 1U_0402_6.3V4Z
<29> BEEP_MIX

2
S B 2.4K_0402_5% 2
3

E R492 R489
1 <29,33> EAPD 3 5.11K_0402_1% C590

1
MMBT3904_SOT23 33N_0603_16V7K
C591 1

1
0.1U_0402_16V4Z
2
@

B
Volume Control APA3011 Subwoofer Amplifier B

+3VS
+5VSA
+3VS
1

R493
100K_0402_5% 10U_0805_10V4Z
1

C592 1 1
5

SW1 R494 R495 1 2


+3VS
2

10K_0402_5% 10K_0402_5% +3VS C593 C594


DIP

0.1U_0402_16V4Z 1 0.1U_0402_16V7K
0.1U_0402_16V4Z 2 2
P
2

2 1 2 2 4 C595
A R496 10K_0402_5% A Y
G

NC7SZ14M5X_SOT23-5 2
1 U27 U28 INTSPK_SUB+ U29
3

COM C596 EC_EAPD#


1 CD1# VCC 14 6 VDD SHUTDOWN# 1
2 13 30K_0402_1% 2.2N_0603_100V7K
D1 CD2# INTSPK_SUB+
B 3 1 2 3 CP1 D2 12 1 2 1 2 3 IN+ Vo+ 5 INTSPK_SUB+ <31>
R497 10K_0402_5% 4 11 C601 C597 R498
SD1# CP2
1 R500
0.1U_0402_16V4Z

1 1 5 Q1 SD2# 10 <29> AMP_SUB 1 2 2 4 IN- Vo- 8 INTSPK_SUB- <31>


DIP

0.01U_0402_16V7K

0.01U_0402_16V7K

C598 C599 6 09 1 R499 10K_0402_5% 43K_0402_5%


SW_XRE094_3P Q1# Q2 2.2U_0603_6.3V6K
7 GND Q2# 08 1 2 2 BYPASS GND 7
C600
GND 9
4

2 2 74LCX74MTC_TSSOP14 0.022U_0402_16V7K
2 APA3011XA-TRL_MSOP8
C602
A 2.2U_0603_6.3V6K A
ENCODER_DIR <33>
ENCODER_PULSE <33>

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2006/06/30 Deciphered Date 2007/06/30 <Title>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP/Volume Control
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 30 of 48
5 4 3 2 1
5 4 3 2 1

+MIC1_VREFO_L +MIC1_VREFO_R
MICROPHONE
IN JACK
10mil 10mil

1
Tweeter Conn. R501 R502
JP18
4.7K_0402_5% 4.7K_0402_5% 5 10

2
9
<29> MIC_SENSE 4 8
7
D L43 1 2 HLMA-160808-39NKT HSPK_R+ MIC1_R 1 2 L44 MIC1_R_1 3 D
<30> H_SPK_R+ <29> MIC1_R
L45 1 2 HLMA-160808-39NKT HSPK_R- KC FBM-L11-160808-121LMT 0603 6
<30> H_SPK_R-
MIC1_L 1 2 L46 MIC1_L_1 2
<29> MIC1_L
KC FBM-L11-160808-121LMT 0603 1

2
220P_0402_50V7K

220P_0402_50V7K
JP44 1 1

SM05_SOT23
HSPK_R+ 1 SINGA_2SJ-S351-012
HSPK_R- 1 C603 C604 @
2 2
MSPK_R+ 3 Normal OPEN
L47 1 HLMA-160808-39NKT HSPK_L+ MSPK_R- 3 2 2
<30> H_SPK_L+ 2 4 4
L48 1 2 HLMA-160808-39NKT HSPK_L- 5
<30> H_SPK_L-

1
G5 D16
6 G6
ACES_85205-04001

HEADPHONE
OUT JACK
Medium SPK Conn. 5
JP21
10
9
<29> HP_SENSE 4 8
7
JP45 HP_R L49 1 2 HPR 3
<30> HP_R
HSPK_L+ 1 KC FBM-L11-160808-121LMT 0603 6
L50 1 HLMA-160808-39NKT MSPK_R+ HSPK_L- 1 HP_L L51 1 HPL
<30> M_SPK_R+ 2 2 2 <30> HP_L 2 2
L52 1 2 HLMA-160808-39NKT MSPK_R- MSPK_L+ 3 KC FBM-L11-160808-121LMT 0603 1
<30> M_SPK_R- 3

10P_0402_50V8J

10P_0402_50V8J
C MSPK_L- 4 1 1 C
4

2
5 R503 R504 SINGA_2SJ-S351-012
G5 0_0402_5% 0_0402_5% D19
6 G6 Normal OPEN
@ @ C605 C606 @
ACES_85205-04001 2 2

2
SM05_SOT23
L53 1 2 HLMA-160808-39NKT MSPK_L+
<30> M_SPK_L+

1
L54 1 2 HLMA-160808-39NKT MSPK_L-
<30> M_SPK_L-

LINE IN JACK
JP24
5 10
9
<29> LINE_SENSE 4 8
7
LINE1_R 1 2 L55 LINE1_R_1 3
<29> LINE1_R
KC FBM-L11-160808-121LMT 0603 6
Sub-woofer Conn. <29> LINE1_L
LINE1_L 1 2 L56
KC FBM-L11-160808-121LMT 0603
LINE1_L_1 2
1

2
220P_0402_50V7K

220P_0402_50V7K
1 1

SM05_SOT23
SINGA_2SJ-S351-012
C607 C608 @ Normal OPEN
2 2

1
B SM05_SOT23 D22 D21 B

2
1
3
@ JP25
L57 1 2 HLMA-160808-39NKT SPK_SUB+
<30> INTSPK_SUB+ 1
L58 1 2 HLMA-160808-39NKT SPK_SUB-
<30> INTSPK_SUB- 2
ACES_85204-0200 S/PDIF OUT JACK
<29> SPDIF_SENSE
JP26
+5VS 2
4
6
1

3
S
G
2 SPDIF_PLUG# +5VS 2 1 SPDIF_PLUG# 5
R505 100K_0402_5%
Q18 7
AO3413_SOT23 10
D <29> SPDIF
9

1
3
+5VSPDIF 1
+5VSPDIF 20mil C609
8
100P_0402_50V8J ACES_20234-0101
2
A A
Normal OPEN

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2006/06/30 Deciphered Date 2007/06/30 <Title>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Jack/MIC/SPDIF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 31 of 48
5 4 3 2 1
A B C D E

+3VS +3VS +1.5VS

+3VS +1.5VS +3VALW

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
0.1U_0402_16V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z
1 1 1 1 1 1 1 1

C610

C611

C612

C613

C614

C615

C616

C617
1 1 1 1 1 1 1
C618 C619 C620 C621 C622 C623 C624
1 2 2 2 2 2 2 2 2 1
0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2

WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@

ROBSON@ ROBSON@ ROBSON@ ROBSON@


ROBSON@ ROBSON@ ROBSON@ ROBSON@

Mini-Express Card for WLAN +1.5VS +3VS NAND mini Card(Robson support)
<22,27,33> ICH_PCIE_WAKE# R625 1 2 @ 0_0402_5% ***
JP27
PCIE_WAKE# 1 1 2 Add in 4/27. +3VS +1.5VS
<33> PCIE_WAKE# 2
WLAN_BT_DATA 3 3 4
<35> WLAN_BT_DATA 4
WLAN_BT_CLK 5 5 6 JP28
<35> WLAN_BT_CLK 6
<16> WLAN_CLKREQ# MINI_CLKREQ# 7 7 8 1 2
8 1 2
9 9 10 10 3 3 4 4
CLK_PCIE_MCARD# 11 11 12 5 6
<16> CLK_PCIE_MCARD# 12 5 6
CLK_PCIE_MCARD 13 13 14 ROB_CLKREQF# 7 8
<16> CLK_PCIE_MCARD 14 7 8
15 15 16 16 9 9 10 10
17 17 18 18 <16> CLK_PCIE_NAND# 11 11 12 12
19 19 20 XMIT_OFF# <16> CLK_PCIE_NAND 13 14
2 20 PLT_RST# 13 14 2
21 21 22 22 PLT_RST# <8,18,20,22,28,33> 15 15 16 16
<22> PCIE_ITX_C_PRX_N3 23 23 24 24 +3VALW 17 17 18 18
<22> PCIE_ITX_C_PRX_P3 25 25 26 26 19 19 20 20
27 27 28 21 22 PLT_RST#
28 ICH_SMBCLK 21 22
29 29 30 30 ICH_SMBCLK <14,15,16,22,27> <22> PCIE_ITX_C_PRX_N4 23 23 24 24
PCIE_TXN3 31 31 32 ICH_SMBDATA <22> PCIE_ITX_C_PRX_P4 25 26
<22> PCIE_PTX_C_IRX_N3 32 ICH_SMBDATA <14,15,16,22,27> 25 26
PCIE_TXP3 33 33 34 27 28
<22> PCIE_PTX_C_IRX_P3 34 27 28
35 35 36 36 29 29 30 30
37 37 38 38 <22> PCIE_PTX_C_IRX_N4 31 31 32 32
39 39 40 40 <22> PCIE_PTX_C_IRX_P4 33 33 34 34
41 41 42 42 35 35 36 36
43 43 44 44 37 37 38 38
R506 1 2 @ 0_0402_5% 45 45 46 39 40
<22> CL_CLK1 46 39 40
R507 1 2 @ 0_0402_5% 47 47 48 41 42 R757 @ 0_0402_5%
<22> CL_DATA1 48 41 42 ROB_LED <33>
R508 1 2 @ 0_0402_5% 49 49 50 43 44
<8,22> CL_RST#0 50 43 44
51 51 52 52 45 45 46 46
47 47 48 48
53 GND1 GND2 54 49 49 50 50
51 51 52 52

FOX_AS0B226-S40N-7F~D 53 54
WLAN@ GND1 GND2

FOX_AS0B226-S40N-7F
1 2 PCIE_WAKE# ROBSON@
<22,27,33> EC_SWI#
R509 0_0402_5%

+3VALW TP Button
3 C625 3
1 2 0.1U_0402_16V4Z
SW3 SW4
TIP
5

U30 SW_L 1 3 SW_R 1 3


WL_OFF# 1
CIR
P

<33> WL_OFF# B
Y 4 2 4 2 4
KILL_SW# 2
<33,35> KILL_SW# A
G

SMT1-05_4P SMT1-05_4P

6
5

6
5
TC7SH08FU_SSOP5 D23
3

1 2 XMIT_OFF#
RB751V_SOD323

C662 1
4.7U_0805_10V4Z CIR@ U38
3 GND
100_0805_5% CIR@ R562 2
2 1 2 SW_R 1 2 @
Kill SWITCH +5VALW VCC
TP CONN. SW_L
C655 33P_0402_50V8J
<33> CIR_IN 2 1 1 Vout 1 2 @
C656 33P_0402_50V8J
+3VALW 0_0402_5% R563 4 JP35
CIR@ GND TP_DATA
+5VS 1 1 G1 13 1 2 @
IRM-V538/TR1_3P 2 C657 33P_0402_50V8J
+3VALW CIR@ TP_DATA 2 TP_CLK
<33> TP_DATA 3 3 1 2 @
<33> TP_CLK TP_CLK 4 C658 33P_0402_50V8J
4
3

D24 5
DAN217_SC59 5
6 6
2

WLAN@ SW_R 7 7
8 8
R511 9
100K_0402_5% 9
10
1

4 10 4
11
1

SW_L 11
12 12 G2 14
KILL_SW#
KILL_SW# <33,35>
E&T_6701-Q12N-00R
3

Compal Electronics, Inc.


3

Security Classification Compal Secret Data


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title
1BS003-1211L_3P SW2
WLAN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/CIR/TP Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 32 of 48
A B C D E
5 4 3 2 1

+3VALW
KBA[0..19] +3VALW
KBA[0..19] <34> For EC Tools

2
ADB[0..7] JP31
ADB[0..7] <34>
R512 1
KSI[0..7] 1 +5VALW
R513 Change to 0 ohm 0_0402_5% 2 E51_RXD
KSI[0..7] <36> 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 3 E51_TXD
KSO[0..17] 3
1 1 C629 1 1 2 2 0_0603_5%
KSO[0..17] <36> 4

1
C628 4
1
C630 C631 C632 C633 @ ACES_85205-0400
L59 1000P_0402_50V7K 1000P_0402_50V7K C634 1 1
ECAGND 2 2 2 2 1 1 C635 C636
1 2
2

ECAGND
FBM-L11-160808-800LMT_0603 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 2
1U_0603_10V4Z RSMRST circuit
D D
R670

123
136
157
166

161

159
0_0402_5%

16
34
45

95

96
U31 1 2
LPC_AD0 15

VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCA

AGND

VCCBAT

BATGND
<21,37> LPC_AD0 LAD0
C637 LPC_AD1 14 49 KSO0 Q46
<21,37> LPC_AD1 LAD1 GPOK0/KSO0 KSO0 <36>
@ 22P_0402_50V8J LPC_AD2 KSO1 EC_RSMRST#

C
<21,37> LPC_AD2 13 LAD2 GPOK1/KSO1 50 3 1 PM_RSMRST# <22>
R514 2 1 @ 33_0402_5% LPC_AD3 KSO2 D47B

E
2 1 <21,37> LPC_AD3 10 LAD3 GPOK2/KSO2 51
KSO3 @ BAV99DW-7_SOT363 @ MMBT3906_SOT23
<21,37> LPC_FRAME#
LRST#
9 LFRAME# LPC Interface GPOK3/KSO3 52
KSO4

B
165 53

1 2
LRST#/GPIO2C GPOK4/KSO4

ENE-KB910-B4
18 56 KSO5
<16> CLK_PCI_EC LCLK GPOK5/KSO5

2
7 57 KSO6
<22,25,37> SIRQ SERIRQ GPOK6/KSO6
25 58 KSO7 R671 D47A
R515 1 CLKRUN#/GPIO0C * GPOK7/KSO7 KSO8
<22> LPC_PD# 2 0_0402_5% 24 LPCPD#/GPIO0B * GPOK8/KSO8 59 @ 2.2K_0402_5% @ BAV99DW-7_SOT363
20060814 ADD 60 KSO9
PM@ FRD# GPOK9/KSO9 KSO10
<34> FRD# 150 61

1
R516 1 0_0402_5% FWR# RD# GPOK10/KSO10 KSO11

Internal Keyboard
<19> VGA_ENBKL 2 <34> FWR# 151 64 R672

6
FSEL# WR# GPOK11/KSO11 KSO12
<34> FSEL# 173 MEMCS# GPOK12/KSO12 65 1 2
GM@ SELIO# 152 66 KSO13
R517 1 0_0402_5% ENBKL ADB0 IOCS# GPOK13/KSO13 KSO14 @ 2.2K_0402_5%
<10> GMCH_ENBKL 2 138 D0 GPOK14/KSO14 67
ADB1 139 68 KSO15
ADB2 D1 GPOK15/KSO15 KSO16
140 D2 GPOK16/KSO16 153
R518 1 2 0_0402_5% LRST# ADB3 141 154 KSO17
<20,25,27,37> PCI_RST# D3 GPOK17/KSO17
ADB4 144
R520 1 ADB5 D4 KSI0
<8,18,20,22,28,32> PLT_RST# 2 @ 0_0402_5% 145 D5 GPIK0/KSI0 71

X-BUS Interface
ADB6 146 72 KSI1
D6 GPIK1/KSI1 EC_PLAYBTN# <36>
ADB7 147 73 KSI2 +3VALW
D7 GPIK2/KSI2 EC_STOPBTN# <36>
KBA0 124 74 KSI3
A0 GPIK3/KSI3 EC_FRDBTN# <36>

2
KBA1 125 77 KSI4
+3VALW KBA2 A1/XIOP_TP GPIK4/KSI4 KSI5
126 A2 GPIK5/KSI5 78 EC_REVBTN# <36>
KBA3 127 79 KSI6 R521
C IE_BTN# KBA4 A3 GPIK6/KSI6 KSI7 10K_0402_5% C
1 2 128 A4/DMRP_TP GPIK7/KSI7 80
R523 10K_0402_5% +3VALW KBA5 131

1
KBA6 A5/EMWB_TP INVT_PWM +3VALW
132 A6 GPOW0/PWM0 32 INVT_PWM <19>
2 1 KBA1 KBA7 133 33 BEEP#
A7 GPOW1/PWM1 BEEP# <29>
1K_0402_5% R526 KBA8 143 36 PWR_SUSP_LED EC_PME#
A8 FAN2PWM/GPOW2/PWM2 PWR_SUSP_LED <36>

2
+3VALW 2 1 KBA4 KBA9 142 37 ACOFF
A9 GPOW3/PWM3 ACOFF <41>
RP33 1K_0402_5% R529 KBA10 135 Pulse Width GPOW4/PWM4 38 USB_EN# R524
A10 USB_EN# <35> 10K_0402_5%
1 8 MODE# 2 1 KBA5 KBA11 134 39 EC_ON
A11 GPOW5/PWM5 EC_ON <36>
2 7 FRD# 1K_0402_5% R531 KBA12 130 40 EC_LID_OUT#
A12 GPOW6/PWM6 EC_LID_OUT# <22>
3 6 SELIO# KBA13 129 43 Sattlate_LED#
Sattlate_LED# <36>

1
FSEL# KBA14 A13 FAN1PWM/GPOW7/PWM7 D26
4 5 121 A14
KBA15 120 2 ON/OFFBTN#
A15 GPWU0 ON/OFFBTN# <36>
10K_0804_8P4R_5% KBA16 113 26 2 1
+5VALW A16 GPWU1 ACIN <22,36,39>
+5VS KBA17 112 29 KILL_SW#
A17 GPWU2 KILL_SW# <32,35>
RP34 RP35 KBA18 104 30 PM_SLP_S3#
A18 GPWU3 PM_SLP_S3# <22> RB751V_SOD323
1 8 EC_SMB_CK1 1 8 KB_CLK KBA19 103 Wake Up Pin 44 PM_SLP_S5#
A19 GPWU4 PM_SLP_S5# <22>
2 7 EC_SMB_DA1 2 7 KB_DATA 108 76
A20/GPIO23 GPWU5 CIR_IN <32>
3 6 EC_SMB_CK2 3 6 PS_CLK +3VALW R525 2 1100K_0402_5% 105 172 EC_PME# EC_PME# <28>
EC_SMB_DA2 PS_DATA E51CS#/GPIO20/ISPEN TIN1/GPWU6
4 5 4 5 TIN2/FANFB2/GPWU7 176 FAN_SPEED2 <4>
KB_CLK 110 2 1 ECAGND
4.7K_0804_8P4R_5% 4.7K_0804_8P4R_5% KB_DATA PSCLK1 BATT_TEMPA C639 0.01U_0402_16V7K
111 PSDAT1 GPIAD0/AD0 81 BATT_TEMPA <40>
PS_CLK 114 82 BUTTON_ID
PSCLK2 GPIAD1/AD1 BUTTON_ID <36>
PS_DATA BATT_OVP
TP_CLK
115 PSDAT2PS2 Interface GPIAD2/AD2 83 BATT_OVP <41>
<32> TP_CLK 116 PSCLK3 GPIAD3/AD3 84 ROB_LED <32>
TP_DATA 117 Analog To Digital 87
<32> TP_DATA PSDAT3 GPIAD4/AD4 ALI/MH# <40,41>
88 SKU_ID
+5VS EC_SMB_CK1 GPIAD5/AD5 AD_BID0
<34,40> EC_SMB_CK1 163 SCL1 GPIAD6/AD6 89
EC_SMB_DA1 164 90 1 2
<34,40> EC_SMB_DA1 SDA1 GPIAD7/AD7 100K_0402_5% ADP_I <41>
2 1 TP_CLK EC_SMB_CK2 169 SMBus R527
<4,19> EC_SMB_CK2 SCL2
4.7K_0402_5% R528 EC_SMB_DA2 170 99 DAC_BRIG 1 2
<4,19> EC_SMB_DA2 SDA2 GPODA0/DA0 DAC_BRIG <19>
2 1 TP_DATA GPODA1/DA1 100 BT_PWR
BT_PWR <35>
C640 0.22U_0402_10V4Z
B 4.7K_0402_5% R530 IE_BTN# 8 101 IREF B
<36> IE_BTN# GPIO04 GPODA2/DA2 IREF <41>
EC_SCI# 20 102 EN_DFAN1#
<22> EC_SCI# GPIO07 GPODA3/DA3 EN_DFAN1 <4>
BT_RST# 21 Digital To Analog 1 SYS_PWROK
<35> BT_RST# GPIO08 GPODA4/DA4 SYS_PWROK <8,22>
EC_AMP_EN# 22 42 EN_DFAN2#
<30> EC_AMP_EN# GPIO09 GPODA5/DA5 EN_DFAN2 <4>
ENBKL 27 47 EC_EAPD
ENBKL GPIO0D GPODA6/DA6 EC_EAPD <30>
BKOFF# 28 174 CRY1 1 R533 2CRY2
<19> BKOFF# GPIO0E GPODA7/DA7
FSTCHG 48 @ 20M_0603_5%
<41> FSTCHG GPIO10
EC_SMI# 62 85 POWER_LED#
<22> EC_SMI# GPIO13 * GPIO18/XIO8CS# POWER_LED# <36>
ENCODER_DIR 63 86 WL_BT_LED#
<30> ENCODER_DIR GPIO14 * GPIO19/XIO9CS# WL_BT_LED# <36>
1 2 ENBKL 69 91 HDD_LED#
<32> WL_OFF# GPIO15 * GPIO1A/XIOACS# HDD_LED# <36>
R534 100K_0402_5% 70 GPIO 92 BATT_CHG_LOW_LED#
<22,27,32> EC_SWI# GPIO16 * GPIO1B/XIOBCS# BATT_CHG_LOW_LED# <36>
1 2 SYSON 2 0_0402_5%
1 75 Expanded I/O * GPIO1C/XIOCCS# 93 BATT_FULL_LED#
<32> PCIE_WAKE# GPIO17 BATT_FULL_LED# <36>
R535 100K_0402_5% R537 EAPD 109 94
<29,30> EAPD GPIO24 * GPIO1D/XIODCS# VGATE <8,22,46>
1 2 SUSP# LID_SW# 118 97
<36> LID_SW# GPIO25 * GPIO1E/XIOECS# NSE_DPR <29>
R538 100K_0402_5% MODE# 119 98 CB_PWR_OK 2 1 +S1_VCC 1 1
<36> MODE# GPIO26 * GPIO1F/XIOFCS#
SYSON 148 R540 10K_0402_5% C641 C642
<27,29,36,38,43> SYSON GPIO27

4
SUSP# 149 171 R_FAN_SPEED1 R541 1 2 0_0402_5%
<19,27,34,38,43,44,45> SUSP# GPIO28 GPIO2E/TOUT1/FANFB1 FAN_SPEED1 <4>

10P_0402_50V8J

10P_0402_50V8J
VR_ON 155 12 ENCODER_PULSE R543 1 2 4.7K_0402_5% X2

OUT
IN
<46> VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3 2 2
EC_HP_EN 156 FANTEST_TP/GPIO05/FAN3PWM 11 R544 1 2 4.7K_0402_5%
<30> EC_HP_EN GPIO2A
BT_DETACH 162
<35> BT_DETACH GPIO2B SPK_SEL_CODEC <29>
PBTN_OUT# 168 175 EC_THERM#
<22> PBTN_OUT# GPIO2D TOUT2/GPIO2F EC_THERM# <22>
Timer Pin

NC

NC
55 3 EC_RSMRST#
C643 0.1U_0402_16V4Z CAPS_LED# FnLock#/GPIO12 * E51IT0/GPIO00
<36> CAPS_LED# 54 4

3
NUM_LED# CapLock#/GPIO011 * E51IT1/GPIO01 E51_RXD
Analog Board ID definition, 2 1 <36> NUM_LED# 23 NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK 106 E51_RXD <37>
41 107 E51_TXD
Please see page 3. <21> PHDD_LED# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT E51_TXD <37>
+3VALW 2 1 19 ECRST# MISC
R545 47K_0402_5% 5 158 CRY2
<21> EC_GA20 GA20/GPIO02 XCLKI
6 160 CRY1 32.768KHZ_12.5P_1TJS125BJ2A251
<21> EC_KBRST# KBRST#/GPIO03 XCLKO
31
GND
GND
GND
GND
GND
GND

ECSCI#
SKU_ID 0: +3VALW
A A
1:10 KB910Q B4_LQFP176 ENCODER_PULSE
ENCODER_PULSE <30>
17
35
46
122
137
167

2:10G SKU_ID 2 1
R546 100K_0402_5%
3:10H 1 2
R547 GM@ 0_0402_5%
BUTTON_ID ID0:0 BUTTON
BUTTON_ID 2 1
ID2:2 BUTTON R548 100K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
ID4:6 BUTTON Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

AD_BID0: Board ID AD_BID0 2 1


ENE-KB910
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R549 100K_0402_5% Size Document Number Rev
Ra AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
1
R550
2
0_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ISRAA LA-3441P
* Rb MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 33 of 48
5 4 3 2 1
+3VALW

R551

14
100K_0402_5%
R552
1 INT_FLASH_EN# 1 2

P
INT_FSEL# A
1 2 3 O
2 FSEL#
B FSEL# <33>

G
22_0402_5%

7
U32A
SN74LVC32APWLE_TSSOP14 +3VALW
+3VALW

14

14
R556
1 2 9 12

P
A A
8 O 11 O
@ 0_0402_5% 10 13
B B

G
Reserve R4, if U1B is single gate.

7
U32C U32D
SN74LVC32APWLE_TSSOP14 SN74LVC32APWLE_TSSOP14

+3VALW +3VALW
C646
1

1 2 R558
100K_0402_5%
SUSP# <19,27,33,38,43,44,45>
0.1U_0402_16V4Z

2
G
14

4 1 3
P

A EC_FLASH# <22>
FWE# 6
D

S
O
B 5
G

Q21
U32B 2N7002_SOT23 Module ID
7

SN74LVC32APWLE_TSSOP14 Indication for polarity of reset


Reset input High Active --> Low ,
FWR# <33>
Reset input Low Active --> Open

KBA[0..19]
<33> KBA[0..19]
ADB[0..7]
<33> ADB[0..7]

1MB Flash ROM


U33
+3VALW 1MB ROM Socket
KBA0 21 31
KBA1 A0 VCC0 JP33
20 A1 VCC1 30 1
KBA2 19 C651 KBA16 KBA17 +5VALW
KBA3 A2 KBA15 1 2
18 A3 3 4
KBA4 17 25 ADB0 0.1U_0402_16V4Z KBA14 +5VALW
A4 D0 5 6

1
KBA5 ADB1 2 KBA13 KBA19 C652
16 A5 D1 26 7 8
KBA6 15 27 ADB2 KBA12 KBA10 1 2 0.1U_0402_16V4Z R559
KBA7 A6 D2 ADB3 KBA11 9 10 ADB7
14 A7 D3 28 11 12
KBA8 8 32 ADB4 KBA9 ADB6 100K_0402_5%
KBA9 A8 D4 ADB5 KBA8 13 14 ADB5 U34
7 33

2
KBA10 A9 D5 ADB6 FWE# 15 16 ADB4
36 A10 D6 34 17 18 8 VCC A0 1
KBA11 6 35 ADB7 RESET# +3VALW 7 2
KBA12 A11 D7 INT_FLASH_EN# 19 20 WP A1
5 A12 21 22 <33,40> EC_SMB_CK1 6 SCL A2 3
KBA13 4 INT_FLASH_SEL 5 4
A13 <22> SB_INT_FLASH_SEL# 23 24 <33,40> EC_SMB_DA1 SDA GND
KBA14 3 10 RESET# 1 2 +3VALW KBA18 ADB3
KBA15 A14 RP# R560 100K_0402_5% KBA7 25 26 ADB2 AT24C16AN-10SI-2.7_SO8
2 A15 NC 11 27 28
KBA16 1 12 KBA6 ADB1
KBA17 A16 READY/BUSY# KBA5 29 30 ADB0
40 A17 NC0 29 31 32

1
KBA18 13 38 KBA4 FRD#
KBA19 A18 NC1 KBA3 33 34 R561
37 A19 35 36
KBA2 FSEL#
INT_FSEL# KBA1 37 38 KBA0 100K_0402_5%
22 CE# 39 40
FRD# 24 23
<33> FRD#

2
FWE# OE# GND0 @ SUYIN_80065AR-040G2T
9 WE# GND1 39

SST39VF080-70_TSOP40

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title
BIOS I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 34 of 48
5 4 3 2 1

BlueTooth Interface USB Board Right side 2x2 Port

+5VS +3VS
+5VALW 1.4A
U35
+USB_VCCC
+USB_VCCD +USB_VCCC
1 GND OUT 8
2 7 JP34
IN OUT

2
3 IN OUT 6 1 1
D R553 C644 USB_EN# 4 5 2 D
0.1U_0402_16V4Z EN# FLG 2
1M_0402_5% 1 1 3 3
BT@ BT@ C653 G528_SO8 C654 4 4

3
S
1 R555 5
G
4.7U_0805_10V4Z 4.7U_0805_10V4Z 5
1 2 2 6 6
BT@ 100K_0402_5% Q19 2 2
7
2
D BT@AO3413_SOT23 Close to JP34 8
7

1
8
<22> USB20_N1 9 9
C645 1000P_0402_50V7K <22> USB20_P3 10
BT@ 10
+BT_VCC <22> USB20_P1 11 11
1

D 1
<22> USB20_N3 12 12
<33> BT_PWR 2 13 13
G 2N7002_SOT23 14
Q20 14
S <22> USB20_N0 15
3

BT@ 15
<22> USB20_P2 16 16
17
+5VALW 1.4A
U36
+USB_VCCD
<22>
<22>
USB20_P0
USB20_N2 18
17
18
19 19
1 GND OUT 8 20 20
2 IN OUT 7
3 6 Aces_88242-2001_20P
USB_EN# IN OUT
4 EN# FLG 5
1 1
C659 G528_SO8 C660

4.7U_0805_10V4Z 4.7U_0805_10V4Z
2 2
Change at 8/30 Close to JP34
C C
JP32
1 1
+3VALW 2
<22> USB20_P7 2
<22> USB20_N7 3 3
SN74LVC08APW_TSSOP14
14

<32> WLAN_BT_CLK 4 4
U14B <22> BT_DET# 1 2 5
R730 0_0402_5% BT_RESET# 6 5
<32,33> KILL_SW# 4
P

<33> BT_RST# 5
A

B
O 6 1
R554
2 BT_RESET#
@0_0402_5%
<32> WLAN_BT_DATA 7
8
6
7
8
USB Conn Left side 1x2 Port
G

<33> BT_DETACH 1 2 9 9
R731 0_0402_5% 10
7

10 +5VALW +USB_VCCA
+BT_VCC
ACES_87213-1000 U37
(MAX=200mA)
1 BT@ 1 8
C649 C650 GND OUT
1 2 2 IN OUT 7
R557 BT@0_0402_5% BT@ BT@ Bluetooth Connector 3 6
10U_0805_10V4Z 0.1U_0402_16V4Z IN OUT
1 4 EN# FLG 5
2 C661
G528_SO8
4.7U_0805_10V4Z
2
check it !

USB_EN#
<33> USB_EN#
Int. Camera Conn
B B

R510
W=20mils
+5VS 1 2 +CAM_VDD
1
0_0805_5% +USB_VCCA +USB_VCCA
W=40mils W=40mils
Camera@ C627 Finger printer Conn
0.1U_0402_16V4Z
JP30 2
Camera@ 1 1
1 1 1 1 1 1
2 USB20_N8_R +3VS C663 + C665 C666 C667 C668 + C664
2 USB20_P8_R 150U_UD_6.3VM_R18M 150U_UD_6.3VM_R18M
3 3
4 0.1U_0402_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z
4 2 2 2 2 2 2
5 5 1
6 C626
GND1 JP36
GND2 7
0.1U_0402_16V4Z 1 5
ACES_88266-05001 2 JP29 VCC VCC
<22> USB20_N4 2 D0- D1- 6 USB20_N5 <22>
Camera@ 3 7
1 <22> USB20_P4 D0+ D1+ USB20_P5 <22>
FP@ 4 8
2 VSS VSS
3

2
C669
1 1 C670 1 C671 1 C672
<22> USB20_N6 3

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K
D27 10 9 D28
<22> USB20_P6 4 G2 G1
@ SM05_SOT23 12 11 @ SM05_SOT23
5 @ @ G4 G3 @ @
2

ACES_85201-0505 2 2 SUYIN_060830-TK101_8P 2 2
1 2 D25 FP@
1

1
R742 0_0402_5% @ SM05_SOT23
A A
L75
USB20_N8_R 1 2 USB20_N8 <22>
1

1 2

USB20_P8_R 4 3
4 3 USB20_P8 <22>
@ WCM2012F2S-900T04_0805 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title
1
R743
2
0_0402_5% USB/BT/F_P/Int. Ca Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 35 of 48
5 4 3 2 1
5 4 3 2 1

+3VALW
Lid SW +3VALW
ON/OFF BUTTON

2
+3VALW
+5VALW +5VALW R564
for debug only

1
R565 SYSON SYSON 100K_0402_5%
47K SYSON <27,29,33,38,43> 47K BTN TOP

3
U39 47K_0402_5% Q24 D29

1
2

2
A3212EEH_MLP6 2N7002_SOT23 Q26

G
2 ON/OFFBTN# <33>
2N7002_SOT23 1 3 1 3 ON/OFF 1

2
5 1 LID_SW# 10K 2 1 3 10K 2 1 3 3 51_ON#
VDD OUTPUT LID_SW# <33> PWR_SUSP_LED <33> POWER_LED# <33> 51_ON# <39>
2 4 2 4

S
DAN202U_SC70
D55

10P_0402_50V8J
0.1U_0402_16V4Z

1 4 2 1 SW5 SW6

6
5

6
5
C673 NC NC C674 Q23 Q25
2
GND

1
D DTA114YKA_SOT23 DTA114YKA_SOT23 SMT1-05_4P SMT1-05_4P D
1 1

1
3 R574 1 2 120_0402_5% PWR_LED_0# D30
2 2 R573 1 PWR_SUSPLED1#
2 300_0402_5% C675 RLZ20A_LL34
3

@ SM05_SOT23 Q22 0.01U_0402_25V7K

1
D 2

2
<33> EC_ON 2
G

2
S 2N7002_SOT23

3
R566
10K_0402_5%

AC IN LED HDD LED BATT CHARGE/FULL LED POWER/SUSPEND LED Satellite logo LED

1
+5VALW +5VS +5VALW

Q47
DTA114YKA_SOT23
WL&BT LED

PWR_LED_0#

PWR_SUSPLED1#
1

1
R570
120_0402_5% R567 R568 R569 1 3 +5VALW +5VALW

47K
120_0402_5% 120_0402_5% 300_0402_5%

10K
2

1
R758

1
200_0402_5%
2

HT-191UD_AMBER_0603 R571
Q48
2

2
C D34 C
300_0402_5%

1
D31 D32 D33 D35 D36 D 2N7002_SOT23-3
HT-191NB_BLUE_0603 WLAN@
HT-191NB_BLUE_0603 2 SYSON SYSON <27,29,33,38,43>

2
HT-191NB_BLUE_0603 G
HT-191NB_BLUE_0603 HT-191UD_AMBER_0603 S
1

3
1

2
2
D37

BATT_FULL_LED#

BATT_CHG_LOW_LED#
D45 HT-191UD_AMBER_0603
12-21-BHC-ZL1M2RY-2C_BLUE WLAN@
Sattlate_LED# <33>

1
1
VF=2.8V
1

D
2 Q27
<22,33,39> ACIN
G 2N7002_SOT23 <33> HDD_LED#
S <33> BATT_FULL_LED# BATT_CHG_LOW_LED# <33>
3

<33> WL_BT_LED#

KSI[0..7]
B KSI[0..7] <33> B
KEYBOARD CONN. KSO[0..17]
KSO[0..17] <33>
2 IE_BTN# <33>
JP37 2 IEBTN# 1
MODE# <33>
1 2 +3VS MODEBTN# 1 3 51_ON#
34 KSO16 R576 300_0402_5% 51_ON#
33 3
NUM_LED# 1 2 D39
32 KSO17 C676 100P_0402_50V8J D38 DAN202U_SC70
31
30 2 1 KSO14 CAPS_LED# 1 2 DAN202U_SC70
100P_0402_50V8J C677 C678 100P_0402_50V8J
29 KSO2
28 2 1 KSO11 KSO15 1 2
KSO1 100P_0402_50V8J C679 C680 100P_0402_50V8J KSO17 C681 1 2@ 220P_0402_50V7K
27 KSO0
26 2 1 KSO9 KSO10 1 2
KSO4 100P_0402_50V8J C682 C683 100P_0402_50V8J ON/OFF C684 1 2@ 220P_0402_50V7K
25 KSO3 2 1 KSI7 KSO8 1 2
SW/LED Connector
24 KSO5 100P_0402_50V8J C685 C686 100P_0402_50V8J PWR_LED_0# C687 1
23 2@ 220P_0402_50V7K
KSO14 2 1 KSO7 KSO13 1 2
22 KSO6 100P_0402_50V8J C688 C689 100P_0402_50V8J
21 KSO7
20 2 1 KSI4 KSO3 1 2 JP38
KSO13 100P_0402_50V8J C691 C692 100P_0402_50V8J 1 ON/OFF IEBTN# C693 1 2@ 220P_0402_50V7K
19 KSO8 1
18 2 1 KSI5 KSO12 1 2 2 2 IEBTN#
KSO9 100P_0402_50V8J C694 C695 100P_0402_50V8J 3 KSO0 MODEBTN# C696 1 2@ 220P_0402_50V7K
17 KSO10 3 KSO0 <33>
16 2 1 KSO5 KSI6 1 2 4 4 MODEBTN#
KSO11 100P_0402_50V8J C697 C698 100P_0402_50V8J 5 KSI1 EC_REVBTN# C699 1 2@ 220P_0402_50V7K
15 KSO12 5 EC_PLAYBTN# <33>
14 2 1 KSI0 KSO6 1 2 6 6 KSI2
EC_STOPBTN# <33>
KSO15 100P_0402_50V8J C700 C701 100P_0402_50V8J 7 KSI3 EC_FRDBTN# C702 1 2@ 220P_0402_50V7K
13 KSI0 7 EC_FRDBTN# <33>
12 2 1 KSO1 KSI3 1 2 8 8 KSI5
EC_REVBTN# <33>
KSI5 100P_0402_50V8J C703 C704 100P_0402_50V8J 9 BUTTON_ID EC_PLAYBTN# C705 1 2@ 220P_0402_50V7K
11 KSI4 9 BUTTON_ID <33>
10 2 1 KSI2 KSO0 1 2 10 10
KSI3 100P_0402_50V8J C706 C707 100P_0402_50V8J 11 EC_STOPBTN# C708 1 2@ 220P_0402_50V7K
9 KSI7 GND
8 2 1 KSO4 KSI1 1 2 GND 12
A KSI2 100P_0402_50V8J C709 C710 100P_0402_50V8J BUTTON_ID C711 1 A
7 2@ 220P_0402_50V7K
KSI1 2 1 KSO16 KSO2 1 2 ACES_85201-1005N
6 KSI6 100P_0402_50V8J C712 C713 100P_0402_50V8J
5
4 2 1 +3VS
For EMI Request
CAPS_LED# R577 300_0402_5%
3
2
CAPS_LED# <33> For EMI Request
NUM_LED#
1 NUM_LED# <33>
ACES_88170-3400 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LID/KB/LED/SW-B Conn
Size Document Number Rev
20070718 change new KB define AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ISRAA LA-3441P
Date: Friday, September 22, 2006 Sheet 36 of 48
5 4 3 2 1
A B C D E

New LPC Debug Pad ---- MB side R578


MDC Conn.
@ 0_0402_5% JP39
1 2 E51_TXD E51_TXD <33>
R579 +3VALW D_PAD1 1 2
1 GND1 RES0 1
@ 0_0402_5% ICH_SDOUT_MDC 3 4 20mil
<21> ICH_SDOUT_MDC IAC_SDATA_OUT RES1
<33> E51_RXD E51_RXD 1 2 6 5 1 2 LPC_DRQ#1 LPC_DRQ#1 <21> 5 6
GND2 3.3V +3VALW
R580 <21> ICH_SYNC_MDC ICH_SYNC_MDC 7 8
0_0402_5% R581 1 IAC_SYNC GND3
<21> ICH_AC_SDIN1 2 33_0402_5% 9 IAC_SDATA_IN GND4 10
<22,25,33> SIRQ SIRQ 1 2 7 4 PCI_RST# PCI_RST# <20,25,27,33> MDC_RESET# 11 12 ICH_BITCLK_MDC
IAC_RESET# IAC_BITCLK ICH_BITCLK_MDC <21>
R582
R583 C714
0_0402_5%
<21,33> LPC_AD3 LPC_AD3 8 3 LPC_AD2 LPC_AD2 <21,33> 2 1 1 2

GND
GND
GND
GND
GND
GND
@ 10_0402_5% @ 10P_0402_50V8K
<21,33> LPC_AD1 LPC_AD1 9 2 LPC_AD0 LPC_AD0 <21,33> ACES_88018-124G

13
14
15
16
17
18
<21,33> LPC_FRAME# LPC_FRAME# 10 1 CLK_PCI_SIO2 CLK_PCI_SIO2 Connector for MDC Rev1.5
R584 C715
@ 1 2 1 2
DEBUG_PAD
+3VALW
Under DDR ME Assigment Area 10_0402_5% 10P_0402_50V8J

1 1 1
Keep Resistor near Debug Pad and in the same side C716 C717 C718

+3VALW 1000P_0402_50V7K @ 4.7U_0805_10V4Z


Reverse side DIMM ---- Pin 1 keep away DIMM 2 2 2
0.1U_0402_16V4Z

14
U14C
2 2
9

P
<21> MDC_RST# A
8 MDC_RESET#
ICH_RST_MDC# O
<21> ICH_RST_MDC# 10 B

G
SN74LVC08APW_TSSOP14

7
R585 @ 0_0402_5%

LPC_AD[0..3] +3VS
LPC Debug Port <21,33> LPC_AD[0..3]
SPI BIOS ROM 20mils
1
+5VS +3VS C721 U40
CLK_PCI_SIO 8 4
3 SPI@ 0.1U_0402_16V4Z VCC VSS 3
2

2 SPI_WP# 3 W
JP40 R586
1 @ 22_0402_5% 20mils 1 2 SPI_HOLD#_0 7
1 +3VS HOLD
2 R587 SPI@ 3.3K_0402_5%
2 SPI_CS#
3 <22> SPI_CS# 1
1

3 S
4 4 1
5 C722 @ 10P_0402_50V8K SPI_CLK R588 1 2 SPI@ 47_0402_5% SPI_CLK_0 6
5 <22> SPI_CLK C
6 CLK_14M_SIO
6 CLK_14M_SIO <16>
7 LPC_AD0 SPI_SI R589 1 2 SPI@ 47_0402_5% SPI_SI_0 5 2 SPI_SO_L0 1 2 SPI_SO_R SPI_SO_R <22>
7 LPC_AD0 <21,33> 2 <22> SPI_SI D Q
8 LPC_AD1 R590 SPI@ 15_0402_5%
8 LPC_AD1 <21,33>
9 LPC_AD2 SPI@ SST25LF080A_SO8-200mil
9 LPC_AD2 <21,33>
10 LPC_AD3
10 LPC_AD3 <21,33>
11 LPC_FRAME#
11 LPC_FRAME# <21,33>
12 LPC_DRQ#1
12 PCI_RST# LPC_DRQ#1 <21> 20mils SPI_WP# R592
13 13 PCI_RST# <20,25,27,33> +3VS 1 2 1 2 SPI@ 0_0402_5%
14 1 2 R591 @ 3.3K_0402_5%
14 R593 @ 0_0402_5% CLK_PCI_SIO
15 15 CLK_PCI_SIO <16>
16 SIRQ
16 SIRQ <22,25,33>
17 17
18 18
19 Add in 08/11.
19
20 20 close to RAM Door
@ ACES_85201-2005

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title
MDC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 37 of 48
A B C D E
A B C D E

+5VALW TO +5VS 20060802 ADD for AMP use


FD1 FD2 FD3 FD4 FD5 FD6
+5VALW TO +5VSA (For Amp)
+5VALW +5VS @ @ @ @ @ @
+5VALW +5VSA

1
U42
8 1 U43
D S
7 D S 2 8 D S 1

2
6 3 1 1 7 2 FD7 FD8 FD9 FD10 FD11 FD12 FD13 FD14 FD15 FD16
D S D S

2
1 1 5 4 C738 C739 R600 6 3 1 1 1 1 1 1 1 1 1 1 1 1
C742 C743 D G 470_0603_5% D S C740 C741 R601 @ @ @ @ @ @ @ @ @ @
1 1 5 D G 4
AO4422_SO8 10U_0805_10V4Z C744 C745 470_0603_5%
10U_0805_10V4Z 2 2
1U_0603_10V4Z AO4422_SO8 10U_0805_10V4Z
AOS 4422

1
2 2
10U_0805_10V4Z 10U_0805_10V4Z 2 2
1U_0603_10V4Z
AOS 4422

1
1 2 2
10U_0805_10V4Z 1

1
D

1
D
2 SUSP
G 2 SUSP
+VSB 2 1 5VS_GATE S Q30 G

3
R604 2N7002_SOT23 +VSB 2 1 5VS_GATE S Q31 H1 H2 H3 H4 H5 H6

3
200K_0402_5% 1 R605 2N7002_SOT23 H_S394D118 H_S394D118 H_S394D118 H_S394D118 H_S394D118 H_S394D118
1

D C746 200K_0402_5% 1

1
SUSP D C747 @ @ @ @ @ @
2
Q32G 0.1U_0603_25V7K SUSP 2

1
2N7002_SOT23 S 2 Q33G 0.1U_0603_25V7K
3

2N7002_SOT23 S 2

3
H7 H8 H9 H10 H11 H12 H13
H_C315D118 H_C315D118 H_C315D118 H_C315D118 H_C315D118 H_C315D118 H_C315D118

@ @ @ @ @ @ @

1
+3VALW TO +3VS
+3VALW +3VS +5VALW
H14 H15 H16 H17 H18 H19 H20
U44 H_C315D118 H_C315D118 H_C315D157 H_C315D157 H_C315D157 H_C276D126 H_C276D126

2
8 D S 1
7 2 R599 @ @ @ @ @ @ @
D S
2

6 3 1 1 100K_0402_5%

1
D S C748 C749 R607
1 1 5 D G 4
C750 C751 470_0603_5%

1
AO4422_SO8 10U_0805_10V4Z
10U_0805_10V4Z 2 2
1U_0603_10V4Z SYSON#
AOS 4422 SYSON#
1 1

2 2
10U_0805_10V4Z H21 H22 H23 H24 H25 H26 H27

1
2 D D H_C276D126 H_C276D126 H_C236D87 H_C236D87 H_C236D87 H_C236D87 H_C236D87 2
2 SUSP <27,29,33,36,43> SYSON
SYSON 2 Q29
G G 2N7002_SOT23 @ @ @ @ @ @ @
S Q35 S
3

1
1
5VS_GATE 2N7002_SOT23
R603
100K_0402_5%

H28 H29 H30 H31 H32 H33 H34

2
H_C236D87 H_C197D126 H_C197D126 H_C197D118 H_C197D118 H_C197D118 H_C197D118
+1.8V to +1.8VS @ @ @ @ @ @ @

1
+1.8V +1.8VS

U45 +5VALW
8 1 H35 H36 H37 H38 H39 H40
D S H_R197X102D118X24 H_R197X102D118X24 H_C197D87 H_C197D87 H_C197D87 H_C197D87
7 D S 2 1 1
2

2
6 3 C752 C753
D S R609 R606 @ @ @ @ @ @
1 1 5 D G 4
C754 C755 10U_0805_10V4Z 470_0603_5% 100K_0402_5%

1
SI4856ADY_SO8 2 2
1U_0603_10V4Z
10U_0805_10V4Z SI4856/AO4430
1

1
2 2
10U_0805_10V4Z SUSP
<45> SUSP
1

1
SUSP D
2
G 2 Q34 M1 M2 M3 M4 M5 M6 M7
<19,27,33,34,43,44,45> SUSP#
+VSB 2 1 1.8VS_GATE S Q36 G 2N7002_SOT23 H_C79D79N H_C79D79N H_C79D79N H_C79D79N H_C79D79N H_C79D79N H_C150D150N
3

R610 2N7002_SOT23 S

3
1

510K_0402_5% 1 @ @ @ @ @ @ @
C756 R608

1
1

3 D 100K_0402_5% 3
SUSP 2 0.1U_0603_25V7K
G 2
2

Q37 S M8 M9 M10 M11


3

2N7002_SOT23 H_C339D339N H_O236X118D236X118N H_O256X150D256X150N H_O256X150D256X150N

@ @ @ @

1
+1.5VS +2.5VS +1.05VS +0.9VS +1.8V
2

R611 R612 R613 R614 R615


For EMI
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
@ @
+1.8V C835 1 2 @ 0.01U_0402_25V7J B+
1

+1.8V C836 1 2 @ 0.01U_0402_25V7J B+


1

D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON# +1.8V C837 1 2 @ 0.01U_0402_25V7J +3VS
G G G G G
S Q38 S Q39 S Q40 S Q41 S Q42 +1.8V C838 1 2 @ 0.01U_0402_25V7J +1.05VS
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23


@ @ +1.8V C839 1 2 @ 0.01U_0402_25V7J +1.05VS

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/06/30 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC I/F & Screw
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ISRAA LA-3441P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 38 of 48
A B C D E
A B C D

VS
PR1
VIN VIN 1M_0402_1%
PL1 1 2
PF1 C8B BPH 853025_2P
DC301000F00

1
DC_IN_S1 1 2 DC_IN_S2 1 2

1
VS PR2
PJP1 15A_65V_451015MRL PR3 5.6K_0402_5% PR4
1 84.5K_0402_1% 10K_0402_1%
+
1 2

2
ACIN <22,33,36>

1
2 PR5

2
+

8
PC1 PC2 PC3 PC4 22K_0402_1% PU1A
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1 2 3

P
2

2
- + PACIN
1
O 1 PACIN <41> 1

- 4 2 -

G
1

1
@ SINGA_2DW-0005-B03 PR6 LM393DG_SO8

4
PC5 20K_0402_1% PC6 PR7
0.1U_0402_16V7K PD1 10K_0402_1%

2
RLZ4.3B_LL34

2
0.068U_0402_10V6K 2
PR8
1 RTCVREF Vin Detector
10K_0402_1%
VIN 3.3V
High 18.384 17.901 17.430

2
PD2
RLS4148_LLDS2
Low 17.728 17.257 16.976

1
PD3
BATT+ 2 1

1
RLS4148_LLDS2 PR9 PR10
68_1206_5% 68_1206_5%
1 2
PR12 PR11

2
200_0603_5% PQ1 1K_1206_5%
CHGRTCP 1 2 N1 3 TP0610K-T1-E3_SOT23-3
1 VS
PD4
1

2 1 N3 1 2
VIN B+
1

1
2
PC8 PR13 2

PR14 PC7 0.1U_0603_25V7K RLS4148_LLDS2 1K_1206_5%


100K_0402_1% 0.22U_1206_25V7K
2

2
2

<36> 51_ON# 1 2 1 2
PR15 PR16
22K_0402_1% 1K_1206_5%

RTCVREF
1

PR18 PR19
PR17 100K_0402_1% 2.2M_0402_5%

1
200_0603_5% 1 2 2 1
PR21 PR22 PU2 VL PR20
560_0603_5% 560_0603_5% 3.3V 499K_0402_1%
2

1 2 1 2 3 2 N2
+CHGRTC OUT IN

2
1

8
PD6 PU1B
1

GND G920AT24U_SOT89-3 PD5 2 5

P
PC9 PC10 RLZ16B_LL34 <21,40,42> MAINPWON 1 7
+
10U_0805_10V4Z 1 1U_0805_25V4Z O
3 6 2 1 VL
<41> ACON
2

1
G
2

1
RB715F_SOT323-3 LM393DG_SO8 PR23 PR24

4
1

1
34K_0402_1% 499K_0402_1% PC11

1
PC12 PR26 1000P_0402_50V7K

2
1000P_0402_50V7K PC13 PR25 191K_0402_1%

2
1000P_0402_50V7K 66.5K_0402_1%

2
3 3

PJ1
2 2 1 1
PJ2 PR27

1
@ JUMP_43X118 D 47K_0402_1%
+3VALWP 2 2 1 1 +3VALW
2PQ2 2 1 PACIN
@ JUMP_43X118 PJ3 G RHU002N06_SOT323-3
(8A,320mils ,Via NO.= 16) +1.8VP 2 1 +1.8V
Precharge detector S

3
2 1
PJ4 @ JUMP_43X118
15.97V/14.84V FOR

1
+5VALWP 2 2 1 1 +5VALW (20A,800mils ,Via NO.= 40) ADAPTOR PQ3
@ JUMP_43X118 PJ5 DTC115EUA_SC70-3
(8A,320mils ,Via NO.= 16) +1.25VSP 2 1 +1.25VS
2 1
PJ6 2 +5VALWP
@ JUMP_43X118
+VSBP 2 2 1 1 +VSB
(4.0A,160mils ,Via NO.=8)
@ JUMP_43X39

3
(120mA,40mils ,Via NO.= 2) PJ7
+0.9VSP 2 2 1 1 +0.9VS
@ JUMP_43X79
PJ8 (2A,80mils ,Via NO.= 4)
+1.05VSP 2 2 1 1 +1.05VS
@ JUMP_43X118 PJ9
+1.5VSP 2 1 +1.5VS
PJ10 2 1
2 1 @ JUMP_43X118
4 2 1 4

@ JUMP_43X118 (6.0A,240mils ,Via NO.=12)

(14A,560mils ,Via NO.= 28)


PJ12
+2.5VSP 2 2 1 1 +2.5VS Security Classification Compal Secret Data Compal Electronics, Inc.
@ JUMP_43X39 Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title

(0.35A,40mils ,Via NO.=2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 39 of 48
A B C D
A B C D

PH1 under CPU botten side :


CPU thermal protection at 84 degree C
Recovery at 45 degree C

VL VS VL

PL2

2
VMB C8B BPH 853025_2P
PF2 PR28

1
1 1

BATT_S1 1 2 1 2 47K_0402_1%
BATT+
PJP2 PH1 PC14
MAINPWON <21,39,42>
1 PR29 15A_65V_451015MRL PL14 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR31

1
1 1K_0402_1% C8B BPH 853025_2P 47K_0402_1%
2 2

1
3 1 2 1 2 +3VALWP 1 2 1 2

2
3 PR30 PR32 PQ4
4 4

8
5 47K_0402_1% 13.7K_0402_1% PU3A DTC115EUA_SC70-3
5 PD7
6 1 2 3

P
6 +

1
7 7 O 1 2 1 2
8 PR33 PC15 PC16 TM_REF1 2
8 -

G
9 1K_0402_1% 1000P_0402_50V7K 0.01U_0402_25V7K 1SS355_SOD323-2

2
9 LM393DG_SO8
13 10

4
G4 G1
12 11

3
G3 G2
2

0.22U_0805_16V7K
SUYIN_200275MR009G180ZR PR35

22K_0402_1%
PR34 100_0402_1%

1
PC17
100_0402_1%

1000P_0402_50V7K
PR36
ALI/MH# <33,41>
1

2 1 VL

PC18
PR38 PR37

2
6.49K_0402_1% 100K_0402_1%

2
2 1 +3VALWP

1
PR39
100K_0402_1%
1

2
PR40
1K_0402_1%
2 2
2

PH2 near main Battery CONN :


BATT_TEMPA <33>
BAT. thermal protection at 79 degree C
EC_SMB_DA1 <33,34> Recovery at 45 degree C
EC_SMB_CK1 <33,34>

VL VL

2
PR41
PH2 47K_0402_1%
100K_0603_1%_TH11-4H104FT PR42
47K_0402_1%

1
1 2

PR43

8
10.7K_0402_1% PU3B
1 2 5 PD8

P
+
O 7 2 1
PQ5 TM_REF1 6 -

G
3 3

B+ 3 1 +VSBP
TP0610K-T1-E3_SOT23-3 1SS355_SOD323-2

1
LM393DG_SO8

4
0.22U_1206_25V7K

0.1U_0603_25V7K

PC19 PR44
1

100K_0402_1%

0.22U_0805_16V7K 22K_0402_1%

2
1

1
PR45

PC20

PC21

2
2

PR46
2

22K_0402_1%
VL 1 2
@
100K_0402_1%
2
PR47

PR48
1

0_0402_5% D
1 2 2 PQ6
<42> POK
G RHU002N06_SOT323-3
0.1U_0402_16V7K

S
3
1

PC22
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 40 of 48
A B C D
A B C D

PQ19 @ AO4407_SO8 P2 PQ20 75W, Iadapter=0~3.947A, Current sense=0.02ohm, PR66=10.7K, CP=3.71A


@ AO4407_SO8 90W, Iadapter=0~4.737A, Current Sense=0.015ohm, PR66=19.6K, CP=4.459A 1 8 @PQ40
@ PQ40
8 1 1 8 2 7 AO4407_SO8
7 2 2 7
P3
120W, Iadapter=0~6.315A, Current Sense=0.010ohm, PR66=19.6K, CP=5.936A 3 6
6 3 3 6 5
5 5
1 4

4
4

4
PQ9 PJ13 PQ7
VIN 2 3
AO4407_SO8 B+ 2 1 AO4407_SO8
2 1 B++
8 1 1 8 PR49 1 8
7 2 2 7 0.02_2512_1% @ JUMP_43X118 CSIP 2 7

1
6 3 3 6 3 6
5 5 PC144 CSIN 5
5600P_0402_25V7K
PD14

1
1 1

PC24 PC25

4
PQ8 2 1 PC23
VIN
AO4407_SO8 PR51

2
1
4.7U_1206_25V6K 4.7U_1206_25V6K 47K_0402_1%

2
6251VDD 1SS355_SOD323-2 4.7U_1206_25V6K 1 2 VIN
PR50 PC142
1

3
0.1U_0603_25V7K

2
PR52 PQ11 200K_0402_1%

2
1
47K_0402_1% DTA144EUA_SC70-3 2 PR53 1 PU4 PR54
<33> FSTCHG PC28
2 0_0402_5% 10K_0402_1% PD15

PC26
1 24 2 1 BATT+ 1 2
2

2
6251VDD 1 VDD DCIN ACOFF <33>
2

1
1
PC27 1SS355_SOD323-2
0.1U_0603_25V7K

1
PR55 2 23
ACSET ACPRN
1

10K_0402_1% PQ12 2.2U_0603_6.3V6K 1 PR182 2 VIN


1

2
PQ13 DTC115EUA_SC70-3

1
DTC115EUA_SC70-3 3 22 CSON
EN CSON 200K_0402_1%

2
0.1U_0603_25V7K 2 PC30 PC29 PQ14
<33,40> ALI/MH#
2 @ 680P_0402_50V7K 1U_0603_16V6K DTC115EUA_SC70-3
CSON1 2 4 21 1 2 CSOP PD16

1
CELLS CSOP PR56 2 1 2
2.2_0603_5%

3
1

D 1SS355_SOD323-2 PQ41
1 2 5 20 2 1
3

ICOMP CSIN

5
6
7
8

1
PQ15 PR58 PC31 6800P_0402_25V7K PR57 18_0603_5% PQ16 D RHU002N06_SOT323-3
2

1
0.1U_0603_25V7K
G RHU002N06_SOT323-3 150K_0402_1% PC33 PC32 2 PACIN

D
D
D
D

PC143
S 1 2 1 PR59 2 6 19 0.1U_0603_25V7K G
3

1
10K_0402_1% VCOMP CSIP
S
2

3
0.01U_0402_25V7K 1 2

G
S
S
S
PC34 1 PR60 2 7 18 LX_CHG SI4800BDY-T1-E3_SO8
100P_0402_50V8J 100_0402_1% ICM PHASE

4
3
2
1
2
<33> ADP_I 6251VREF 8 17 DH_CHG PL3 2

PC35 VREF UGATE 16UH_D104C-919AS-160M_3.7A_20%


PR64 1 2 PR63 PC36 1 2 CHG 1 4 BATT+
1

22K_0402_5% D PR65 BST_CHG 1 BST_CHGA 2


9 CHLIM BOOT 16 2 1

1
PACIN 1 2 2 1 2 0.1U_0402_16V7K 2.2_0603_5% 0.1U_0603_25V7K 2 3
<39> PACIN <33> IREF
G 1
S PQ17 15.4K_0402_1% 10.7K_0402_1% 10 15 6251VDDP CH751H-40PT_SOD323-2 PR62
3

ACLIM VDDP

5
6
7
8
RHU002N06_SOT323-3 6251VREF 1 PR66 2 PD10 0.02_2512_1%

1
PR68 1 26251VDD PQ18

D
D
D
D
2
ACON 10K_0402_1% 11 14 4.7_0603_5% SI4810BDY-T1-E3_SO8
<39> ACON VADJ LGATE

1
2 PR69 1 PR67
2

2
10K_0402_1% PC38 PC39
1

G
S
S
S
12 13 PC37 10U_1206_25V6M 10U_1206_25V6M

2
PQ42 GND PGND 4.7U_0805_6.3V6K

4
3
2
1
DTC115EUA_SC70-3 6251VREF 3 11 2
PR70 ISL6251AHAZ-T_QSOP24 DL_CHG
1

2 @ 28.7K_0402_1%
<33> ACOFF PR71
@ 47K_0402_1%
PQ43
IREF=1.016*Icharge
3

@ SI2301BDS-T1-E3_SOT23-3
IREF=0.6V~3.048V
2

CC=0.6~3A
CV=12.6V(6 CELLS LI-ION)
CHGSEL
CV=16.8V(8 CELLS LI-ION)

3 3

BATT Type ALI/MH# CELLS Charge Current IREF


8

PU5B VMB
5
4S2P 0V HIGH 3A 3.048V
P

499K_0402_1% 340K_0402_1%
7 0

1
- 6 VS
G

PR73
LM358DT_SO8
3S2P 2.5V LOW 3A 3.048V
4

0.01U_0402_25V7K

2
1

PC40
4S1P 0V HIGH 1.5A 1.524V LI-3S :13.5V----BATT-OVP=1.5V

1
PR74
LI-4S :18V----BATT-OVP=2V

2
Trickle Charge = 600mA 0.61V BATT-OVP=0.111*BATT+

2
8
PR183 PU5A
10K_0402_1% 3

P
+
<33> BATT_OVP 1 2 1 0
- 2

105K_0402_1%
Charging Voltage

0.01U_0402_25V7K
LM358DT_SO8
BATT Type ALI/MH# CHGSEL CV mode

1
PR75
(0x15)

PC41
2
2800mAH 4S pack 17400mV LOW LOW 17.20V

2
4 4

2800mAH 3S pack 13050mV HIGH LOW 12.90V

Normal 4S LI-ON Cells 16800mV LOW HIGH 16.80V

Normal 3S LI-ON Cells


Security Classification Compal Secret Data Compal Electronics, Inc.
12600mV HIGH HIGH 12.60V 2006/05/18 2007/05/18 Title
Issued Date Deciphered Date
Wake up charge while THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
Size Document Number Rev
no communication - HIGH HIGH 12.60V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 41 of 48
A B C D
5 4 3 2 1

PJ18
B+ 2 2 1 1
@ JUMP_43X118

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC42

PC43

1
PC44

PC45
+VCC_TPS51120 VL

2
D PR76 D

2
5.1_0603_5%
2 1

10U_1206_25V6M
1U_0603_10V6K
1

1
PC47
PC46

5
6
7
8
0.1U_0603_25V7K

D
D
D
D
PQ21

1
PC48
SI4800BDY-T1-E3_SO8
OCP=8A

8
7
6
5

G
S
S
S
2
PQ22 +5VALWP

D
D
D
D

4
3
2
1
SI4800BDY-T1-E3_SO8 PU6
OCP=8A
22 21 PR77 PC49 3.3UH_PCMB104E-3R3MS_11A_20%
VIN VREG5

G
S
S
S
0_0603_5% 0.1U_0603_25V7K 1 2
+3VALWP

1000P_0402_50V7K
10K_0402_1%
20 28 1 2 1 2

1
2
3
4
V5FILT VBST1 PL5

5
6
7
8

2
PC50 PR79 9 27 DH_5V
PL6 EN5 DRVH1

1
PR78

PC51
0.1U_0603_25V7K 0_0603_5%

D
D
D
D
1000P_0402_50V7K

330U_D3L_6.3VM_R25M
2 1 2 1 1 2 13 32 QFN 5X5 LL1 26 LX_5V PQ23
VBST2 SI4810BDY-T1-E3_SO8 1

2
10K_0402_1%
330U_D3L_6.3VM_R25M

3.3UH_PCMB104E-3R3MS_11A_20% DH_3V 14 25 DL_5V

1
DRVH2 DRVL1
1

8
7
6
5

G
S
S
S
+
PC53

PC52
PQ24 LX_3V 15 24 @

D
D
D
D

4
3
2
1
+ LL2 PGND1
PR80

SI4810BDY-T1-E3_SO8
2

2
2
PC54

2.49K_0402_1%
C DL_3V 16 1 C
DRVL2 VO1
1

G
2
S
S
S

PR81
@ 17 3 FB5
PGND2 VFB1
2
1
2
3
4 COMP1
8 7

1
VO2 COMP2 TPS51120_CS1
CS1 23
2
4.22K_0402_1%

FB3 6 18 TPS51120_CS2
VFB2 CS2
VREF2 4
PR82

12 EN2 TONSEL 31

1000P_0402_50V7K
29 EN1 GND 5
30
1

SKIPSEL
PGOOD1
19 VREG3 PGOOD2 11

0_0402_5%
+VCC_TPS51120

PAD
2

1
PC55

14.7K_0402_1%
10 EN3

PR186

14.7K_0402_1%
32

33

2
VL

2
PR83
TPS51120RHBR_QFN32_5X5

PR84
1

2
+3.3V_RTC_LDO

0_0402_5%
806K_0603_1%
1

2
1
PR86

PR87
10U_0805_6.3V6M

1
PR85

1
PC56
10K_0402_1%

1
PR88
PD11
2

1
0_0402_5%

2
2 1 1 2 1 PR89 2 +3VALWP
<21,39,40> MAINPWON VS

100K_0402_1%
2.2U_0805_25V6K
1

PC57 10K_0402_1%

2
0.047U_0603_16V7K RLZ5.1B_LL34
1

B B
PC58

PR90
2

1
@
POK <40>

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title
+5V/+3V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IAYAA (LA-3391P) 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 42 of 48
5 4 3 2 1
A B C D

PJ14
2 1 B+
2 1

1
@ JUMP_43X118

1
PC59 PC60 PR91

1
4.7U_1206_25V6K 4.7U_1206_25V6K 0_1206_5%
PC61 PC62

2
4.7U_1206_25V6K 4.7U_1206_25V6K

2
1
+5VALWP 1

2
PC63 PD12

1
4.7U_0805_6.3V6K PC64 PR92 PC65

8
7
6
5
0.1U_0603_25V7K 2.2_0603_5% 2.2U_0805_10V6K

2
PQ25

1
SI4892DY-T1-E3_SO8
DAP202U_SOT323-3

3
4
BST_1.5V-1
+1.8VP

BST_1.8V-1
PC66 PC67

14

28
1
2
3
+1.8VP 0.01U_0402_25V7K PU7 0.01U_0402_25V7K

5
6
7
8
PL7 2 1 12 SOFT1 17 2 1

VIN

VCC
1.0UH_PCMC104T-1R0MN_20A_20% SOFT2

D
D
D
D
1 2LX_1.8V PC68 PC69 PQ26
0.1U_0402_16V7K 0.1U_0402_16V7K SI4800BDY-T1-E3_SO8
1 2 1 1 2BST_1.8V-2 6 23 BST_1.5V-2
1 2 2 1
BOOT1 BOOT2
+1.5VSP
2

G
S
S
S
PR93 PR94

8
7
6
5
PC70 + PR95 0_0603_5% 0_0603_5%

4
3
2
1
330U_D2E_2.5VM_R9M PQ27
@ 4.7_1206_5% IRF8113PBF_SO8 1 2 DH_1.8V-1 5 24 DH_1.5V-1 1 2 DH_1.5V-2 PL8 +1.5VSP
2 PR96 UGATE1 UGATE2 PR97 4.7U_LF919AS-4R7M-P3_5.2A_20%
1
1

PR98 0_0603_5% 4 25 0_0603_5% LX_1.5V 1 2


PHASE1 PHASE2
1

PC71 4
2

5
6
7
8

2
0.01U_0402_25V7K PR100 PR101
2
10K_0402_1% PC72 1K_0402_1% 1.5K_0402_1% PR99 2

D
D
D
D
2

@ 680P_0603_50V8J 1 2 ISE_1.8V 7 22 ISE_1.5V 1 2 @ 4.7_1206_5% 1


2

ISEN1 ISEN2

1
PQ28
1
2
3

PR102 2 27 SI4810BDY-T1-E3_SO8 PR103 + PC73

2 1
LGATE1 LGATE2

1
G
S
S
S
0_0402_5% 0_0402_5% PC74 PR104 220U_D2_4VM_R15
PC75 0.01U_0402_25V7K
1

4
3
2
1
@ 680P_0603_50V8J 2

2
DL_1.8V 3 26 6.81K_0402_1%

1
PGND1 PGND2 DL_1.5V

9 VOUT1 VOUT2 20
VSE_1.8V 10 19 VSE_1.5V
VSEN1 VSEN2
+3VALWP 1 2 8 EN1 EN2 21 1 2
PR105 15 16 PR106 SUSP# <19,27,33,34,38,44,45>
@ 0_0402_5% PG1 PG2/REF 0_0402_5%

GND

DDR
11 OCSET1 OCSET2 18
1

1
<27,29,33,36,38> SYSON 1 2

1
PR108 PR107 ISL6227CAZ-T_SSOP28 PR109 PR110

13
2

1
10K_0402_1% 0_0402_5% PC76 @ 0_0402_5% 10K_0402_1%
PR111 @ 0.1U_0402_16V7K PR113 PR112 PC77
@ 0_0402_5% 100K_0402_1% 100K_0402_1% @ 0.1U_0402_16V7K
2

2
2
1

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title
1.8V / 1.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 43 of 48
A B C D
5 4 3 2 1

PJ15
2 1 B+
2 1

1
@ JUMP_43X118

1
PC78 PC79 PR114

1
4.7U_1206_25V6K 4.7U_1206_25V6K 0_1206_5%
PC80 PC81

2
4.7U_1206_25V6K 4.7U_1206_25V6K

2
+5VALWP

D D

2
PC82

1
4.7U_0805_6.3V6K PD13 PC83 PR115 PC84
0.1U_0603_25V7K 2.2_0603_5% 2.2U_0805_10V6K

2
1
DAP202U_SOT323-3

3
8
7
6
5
BST_1.05V-1

D
D
D
D
+1.25VS PQ29

BST_1.25V-1
SI4800BDY-T1-E3_SO8

5
6
7
8
PC85 PC86

14

28
G
S
S
S
+1.25VSP 0.01U_0402_25V7K PU8 0.01U_0402_25V7K PQ30
PL9 2 1 12 SOFT1 17 2 1 SI4892DY-T1-E3_SO8

VIN

VCC
1
2
3
4
4.7U_LF919AS-4R7M-P3_5.2A_20% DH_1.25V-2 SOFT2
1 2 LX_1.25V PC87 PC88
0.1U_0402_16V7K 0.1U_0402_16V7K 4
1 2 1 1 2BST_1.25V-2 6 23 BST_1.05V-2
1 2 2 1
+ PC89 PR118
2
PR116
0_0603_5%
BOOT1 BOOT2 PR117
0_0603_5%
+1.05VS
8
7
6
5
220U_D2_4VM_R15 @ 4.7_1206_5%

3
2
1
1 2 DH_1.25V-1 5 24 DH_1.05V-1 1 2DH_1.05V-2 PL10 +1.05VSP
D
D
D
D
2 PR119 UGATE1 UGATE2 PR120 1.0UH_PCMC104T-1R0MN_20A_20%
1
1

PQ31 0_0603_5% 4 25 0_0603_5% LX_1.05V 1 2


PHASE1 PHASE2
1

PR121 PC90 SI4810BDY-T1-E3_SO8


2

5
6
7
8

2
G
S
S
S
2.61K_0402_1% 0.01U_0402_25V7K PR123 PR124
PC91 1K_0402_1% 1K_0402_1% PR122
2

1
2
3
4
2

@ 680P_0603_50V8J 1 2 ISE_1.25V 7 22 ISE_1.05V 1 2 @ 4.7_1206_5% 1


2

ISEN1 ISEN2

1
C PQ32 C
PR125 DL_1.25V 2 27 IRF8113PBF_SO8 PR126 + PC92

2 1
LGATE1 LGATE2

1
0_0402_5% DL_1.05V 4 0_0402_5% PC93 PR127 330U_D2E_2.5VM_R9M
PC94 0.01U_0402_25V7K 1.18K_0402_1%
1

@ 680P_0603_50V8J 2

2
3 26

1
PGND1 PGND2

3
2
1
9 VOUT1 VOUT2 20
VSE_1.25V 10 19 VSE_1.05V
VSEN1 VSEN2
1 2 8 EN1 EN2 21 1 2
<19,27,33,34,38,43,45> SUSP# PR128 15 16 PR129 SUSP# <19,27,33,34,38,43,45>
0_0402_5% PG1 PG2/REF 0_0402_5%

GND

DDR
11 OCSET1 OCSET2 18
1

1
2

1
PR130 ISL6227CAZ-T_SSOP28 PR131 PR132

13
1

1
6.81K_0402_1% PR133 PC95 @ 0_0402_5% 6.81K_0402_1%
@ 0_0402_5% @ 0.1U_0402_16V7K PR135 PR134 PC96
100K_0402_1% 100K_0402_1% @ 0.1U_0402_16V7K
2

2
1

2
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05V / 1.25V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 44 of 48
5 4 3 2 1
5 4 3 2 1

+3VALW

D D
+5VALW

1
+1.8V
PJ17

1
JUMP_43X79
@

1
2
PC102
PJ16

1
2
1U_0603_6.3V6M @ JUMP_43X79

2
6

1
PU10 PU9

2
5 PC103 1 6

VCNTL
VIN VIN VCNTL +3VALWP
7 22U_1206_6.3V6M

2
POK
VOUT 4 2 GND NC 5

1
PR139

1
3 +2.5VSP PC97 3 7 PC98
12K_0402_1% VOUT 10U_1206_6.3V7K PR136 VREF NC 1U_0603_6.3V6M

2
1
1 2 8 2 1K_0402_1% 4 8
EN FB VOUT NC

1
<19,27,33,34,38,43,44> SUSP#

22U_1206_6.3V6M
GND

PC104
9 PR140 PC106 9

2
VIN TP
1

2
PC107 2.15K_0402_1% APL5331KAC-TRL_SO8
1

1U_0603_10V6K
2

1
APL5912-KAC-TRL_SO8 PR138 +0.9VSP

1
0_0402_5% D PR137
1 2 2 PQ33
1K_0402_1% PC99

1
0.01U_0402_25V7K <38> SUSP G RHU002N06_SOT323-3

2
1
S PC100

2
PR141 PC101 10U_1206_6.3V7K

2
1K_0402_1% @ 0.1U_0402_16V7K

2
C C

2
0.1U_0402_16V7K

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05V / 0.9V / 1.5V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 45 of 48
5 4 3 2 1
5 4 3 2 1

+5VS

2
<33>

<5>

<5>

<5>

<5>

<5>

<5>

<5>
VR_ON
+CPU_B+

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR142
1_0603_5% PL11
D D
1 2 B+

10U_1206_25VAK

10U_1206_25VAK
1

1U_0603_6.3V6M

10U_1206_25VAK
FBMA-L18-453215-900LMA90T_1812

1
PC110

PC111

PC112
+

0.01U_0402_25V7K

0.01U_0402_25V7K
<8,22> PM_DPRSLPVR PR143 0_0402_5%

1
1U_0603_6.3V6M
PC114

PC115
1 2

1
PC113

PC116
PC108

2
PR144 0_0402_5% 2

2
<5,8,21> H_DPRSTP# 1 2 100U_25V_M

5
PR145 0_0402_5% PQ34
<22> CLK_ENABLE# 1 2 SI7840DP-T1-E3_SO8

0_0402_5%
PR184
PR147 0_0402_5% 0_0603_5%

PR146
+3VS 1 2 1 2 4
+3VS

1U_0603_6.3V6M

2
1.91K_0402_1%
0.36UH_MPC1040LR36_24A_20%

1
PC117
PR148 PC118

3
2
1
1
BOOT_CPU1 1 2 1 2 2 1 +VCC_CORE
2

PR149

4.7_1206_5%
PR150

5
6
7
8

5
6
7
8

1
10K_0402_1%
3.65K_0805_1%
0_0603_5% 0.22U_0603_10V7K PL12

PR151

PR153
499_0402_1% PR154

49

48

47

46

45

44

43

42

41

40

39

38

37

PR152
1_0402_5%
2

PQ35

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

680P_0603_50V8J
PQ36

1 2

2
1 36 4 4 @ PR155 @ 0_0603_5%
<8,22,33> VGATE PGOOD BOOT1

PC119
1 2
<5> H_PSI# 2 35 UGATE_CPU1 VSUM PC120
PSI# UGATE1
1 2

2
PGD_IN 1 PR181 2 0_0402_5% 3 34 PHASE_CPU1 VCC_PRM

3
2
1

3
2
1
PR156 147K_0402_1% PMON PHASE1 ISEN1
C 0.22U_0603_10V7K C
1 2 4 RBIAS PGND1 33
IRF8113PBF_SO8 IRF8113PBF_SO8 @
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1

10U_1206_25VAK

10U_1206_25VAK
PR157 @ 4.22K_0402_1% PH3

1
1 2 1 2 6 NTC PVCC 31

PC121

PC122
PQ37
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2 SI7840DP-T1-E3_SO8

2
SOFT LGATE2
1 2
@ 0.015U_0402_16V7K PC123 8 29
0.022U_0603_25V7K PC124 OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
1 2 4
1 2 9 28 PHASE_CPU2 PR185
VW PHASE2 0_0603_5%
PR158 13K_0402_1% 10 27 0.36UH_MPC1040LR36_24A_20%
COMP UGATE2 PR159 PC125
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PL13
1 2

5
6
7
8

5
6
7
8

1
1000P_0402_50V7K PC126 0_0603_5% 0.22U_0603_10V7K
DROOP

12 FB2 NC 25

1
VDIFF

ISEN2

ISEN1
VSUM

10K_0402_1%
VSEN

PR161 3.57K_0402_1% PR160


GND

VDD
RTN

DFB

1
VIN

PR162
3.65K_0805_1%
PQ38 PQ39 @ 4.7_1206_5% PR164
VO

1 2

PR163
1 2 PU11
13

14

15

16

17

18

19

20

21

22

23

24

1 2
4 4 1_0402_5%

2
PC127 5600P_0402_25V7K

2
ISEN1 PC128 PR165 @ 0_0603_5%
ISEN2 @ 680P_0603_50V8J 1 2

2
2

PR167 61.9K_0402_1% PC129 1500P_0402_50V7K 1 2 +5VS

3
2
1

3
2
1
1

1 2 2 1 PR168 VSUM PC130


1

@ 0_0402_5% PR166 1_0603_5% 1 2


PR169 PC131
1 2 1U_0402_6.3V4Z
1

@ 0_0402_5% IRF8113PBF_SO8 IRF8113PBF_SO8 0.22U_0603_10V7K


2

B PC132 390P_0402_50V7K VCC_PRM B


PR171 ISEN2
3.4K_0402_1% PC133 470P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 +CPU_B+
1

PR170 1 2
PC134
2

PR172 1.82K_0402_1% 0.1U_0603_25V7K


PC135 0.018U_0603_50V7J
<5> VCCSENSE 1 2 1 2
VSUM
1

PR173 0_0402_5%
1

2.61K_0402_1%

PC136 PC137
PR175

+VCC_CORE
1 2 0.018U_0603_50V7J 0.018U_0603_50V7J
2

PR174 20_0402_5%
2

<5> VSSSENSE 1 2
PR176 0_0402_5%
2
1

11K_0402_1%

PC138 180P_0402_50V8J
PR178

PR177 1 2 10KB_0603_5%_ERTJ1VR103J
2

20_0402_5% 1 2 1 2 PH4
2

PR179 1K_0402_1% PR180 5.36K_0402_1%


PC139 0.068U_0402_10V6K
1

VCC_PRM 1 2

PC141 0.22U_0402_6.3V6K
PC140 2 1 2 1
0.22U_0603_10V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/23 Deciphered Date 2006/06/23 Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Cleveland 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 22, 2006 Sheet 46 of 48
5 4 3 2 1
5 4 3 2 1

HW4 Product Improvement Record (P.I.R.)


Phase: A to B Date: 2006/01/04 Writer: Timo Teng
Page# Action Plan Location or Before value After value
D

(add; del; change) Net_List (Attached file) (Attached file) Detail Discretion and Root Cause Rev. DL/DM Check
D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/05/18 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 47 of 48
5 4 3 2 1
5 4 3 2 1

U20

LAN
RTL8101E
100M@

U22

D D

TRANSFORMER
TST1284-LF
100M@

ZZZ1

PCB
PCB LA-3441P REV0

U3 U3 U3

NB
965GM 965GM 965PM
GMR3@ GMR1@ PMR1@

R547
C C

SKU ID
8.2K_0402_5%
PM@

PJP1

DC-JACK
SINGA_2DW-0005-B03
45@

U15

8412

TI8412
8412@
B B
U15

8402
TI8402
8402@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/05/18 Deciphered Date 2007/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ISPD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 48 of 48
5 4 3 2 1

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