2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)

Compact Modeling of Body Effect for “Extrinsic”

MOSFETs
2022 Moscow Workshop on Electronic and Networking Technologies (MWENT) | 978-1-6654-9666-7/22/$31.00 ©2022 IEEE | DOI: 10.1109/MWENT55238.2022.9802241

Valentin Turin Maxim Shcherbina Roman Shkarlat

Dept. of Experimental and Theoretical Dept. of Experimental and Theoretical JSC “Bolkhov Plant of Semiconductor
Physics. Orel State University named Physics. Orel State University named Devices”,
after I.S. Turgenev after I.S. Turgenev Bolkhov, Orel region, Russia
Orel, Russia Orel, Russia shkarlatroman@ya.ru
voturin@mail.ru m.sherbina2016@yandex.ru
Gennady Zebrev
Oleg Kshensky Vyacheslav Poyarkov Dept. of Micro- and Nanoelectronics.
JSC “Bolkhov Plant of Semiconductor JSC “Bolkhov Plant of Semiconductor National Research Nuclear University
Devices” Devices” “MEPhI”
Bolkhov, Orel region, Russia Bolkhov, Orel region, Russia Moscow, Russia
kshensky@yandex.ru oaobzpp@list.ru gizebrev@mephi.ru
Sergey Kokin Sergey Makarov Badurdin Rakhmatov
Integrated Solutions LLC Integrated Solutions LLC Tajik National University
Zelenograd, Moscow, Russia Zelenograd, Moscow, Russia Dushanbe, Tajikistan
kokinsa@mail.ru makarov@is-eda.ru badriddin.rakhmatov.91@mail.ru

Abstract — One of the MOSFET compact modeling

challenges is a correct account of the finite output resistance in
saturation due to different short channel effects. Previously, we
proposed a new “improved” smoothing function that ensures a
monotonic increase in output resistance from the minimum
value at the beginning of the triode regime to the maximum
value at saturation. We used this smoothing function for
compact modeling of an “intrinsic” (with neglecting the contacts
parasitic resistances) MOSFET. Later, we proposed a linear
approximation for the drain current dependence on drain bias
in the saturation regime for the “extrinsic” (taking into account
contact parasitic resistances) MOSFET without taking into
account body effect. This approximation is based on the
proposed by us equations for the output resistance of the
“extrinsic” MOSFET in the saturation regime (one for Level 1
and second for BSIM3 / 4 models). Later, we generalized this
equation on the case with accounting for the body effect, that
was considered in the linear approximation. Note that modern
transistors with steep retrograde body doping profiles exhibit
approximately linear relationship between a threshold voltage
and a source-to-body bias. In addition, we have shown how it is
possible to convert a transistor with a body terminal to an
equivalent transistor without a body terminal. In this paper, we
use an “improved” smoothing function for compact modeling of
the drain current of an “extrinsic” MOSFET operating in the
above threshold regime that accounts for the body effect in the
linear approximation. The resulting model yields a monotonic
decrease in output conductance, which is important for
improving the accuracy of MOSFET compact modeling in CAD
software. Furthermore, we analyze in detail the relationship
between the equation obtained for the output resistance of the
“extrinsic” MOSFET in the saturation regime with the output
resistance of a common-source amplifier with source
degeneration. Note that in the theory of a common-source
amplifier the circuit that consists of an NMOS transistor with a
resistor in series with its source terminal is known as a transistor
with source degeneration.
Keywords — “extrinsic” MOSFET, body effect, saturation
regime, smoothing function, source degeneration
I. INTRODUCTION
The entry-level MOSFET compact models use the
parameter 𝜆 to account for finite output resistance in
saturation due to short-channel effects [1], [2]. In “intrinsic”
(with neglecting the contacts parasitic resistances) MOSFET
a linear approximation for the drain current dependence on the
drain bias in the linear regime and in the saturation regime is
used. To bridge the transition between the linear and the
saturation regimes a smoothing function must be used.
However, the traditional smoothing function [2] suffers from
the nonmonotonic behavior of the output resistance with
increasing drain-to-source bias. To overcome this
disadvantage, we offer a new “improved” smoothing function
that gives the proper monotonic increase in output resistance
[4], [5]. Furthermore, in modern MOSFET compact modeling,
parasitic source and drain resistances [6] should be taken into
account analytically. Such a model is named “extrinsic”
(taking into account contact parasitic resistances). Hence, in
[8] we proposed a linear approximation for the drain current
dependence on the drain bias in the saturation regime for the
“extrinsic” MOSFET with three terminals (still without
accounting for the body effect). This approximation is based
on two equations (one for Level 1 and second for BSIM3 / 4
MOSFET models) proposed in [8] for the output conductance
of the “extrinsic” MOSFET with three terminals in the
saturation regime. Note that in the theory of a common-source
amplifier the circuit that consists of an NMOS transistor with
a resistor in series with its source terminal is known as a
transistor with source degeneration [1]. In [9] for compact
modeling of an “extrinsic” MOSFET, we used the new
“improved” smoothing function to bridge the transition
between the linear and saturation regimes. In [10] we
generalized the equation for the “extrinsic” MOSFET output
resistance in saturation in the case that accounts for the body
effect, which was considered in the linear approximation.
Note that modern transistors with steep retrograde body
doping profiles exhibit an approximately linear relationship
between a threshold voltage and a source-to-body bias [6]. In

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 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)
earlier generations of MOSFETs with more or less uniform
body doping density, the theory predicts that threshold voltage
is a sublinear function of the source-to-body bias [6]. But even
in this case, the sublinear function can be linearized by the
first-order Taylor expansion. In addition, in [10] we showed
how it is possible to convert a transistor with a body terminal
to an equivalent transistor without a body terminal. In this
paper, we use the new “improved” smoothing function for
compact modeling of the drain current of an “extrinsic”
MOSFET operating in the above threshold regime with
accounting for the body effect in the linear approximation.
The resulting model yields a monotonic decrease in output
conductance, which is important for improving the accuracy
of MOSFET compact modeling in CAD. Furthermore, we
analyze in detail the relationship between the equation
obtained for the output resistance of the “extrinsic” MOSFET
in the saturation regime and the output resistance of a
common-source amplifier with source degeneration.
II. THE “INTRINSIC” MOSFET WITH THREE TERMINALS
Fig. 1 (a) shows the physical structure of the three-
terminal (without the fourth (body) terminal) n-channel
enhancement-type MOSFET and (b) the symbol of the
MOSFET. Two heavily doped n-type regions, indicated in the
figure as the n+ source and the n+ drain regions, are created
in the p-type substrate. A thin layer of gate insulator is grown
on the surface of the substrate, covering the area between the
source and drain regions. Thus, there are three terminals: the
gate terminal (G), the source terminal (S), and the drain
terminal (D).
A. Triode Regime
The gate-to-source bias VGS at which a sufficient number
of mobile electrons accumulate in the MOSFET channel
region to form a conducting channel is called the threshold
voltage and is denoted 𝑉 . For gate-to-source voltages less
than 𝑉 , it is normally assumed that the transistor is off and no
current flows between the drain and the source. In fact, for
gate-to-source voltages slightly less than threshold voltage,
small amounts of subthreshold current can flow.
The excess of VGS over 𝑉 is termed the overdrive voltage
and is denoted as:
𝑉 =𝑉 −𝑉 .
For the MOSFET triode regime, we have:
𝐼TRD = β VGT 𝑉DS − 𝑉 . (2)
Fig. 1. (a) Schematic cross section of an n-channel MOSFET with three
terminals (without the fourth (body) terminal) and (b) the symbol of the
MOSFET.
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Here VDS - the drain-to-source bias and 𝛽 - the
transconductance parameter:
𝛽=𝜇 𝐶 . (3)
Here 𝐶 = 𝜀 𝜀 ⁄𝑑 , 𝜀 and 𝑑 are the oxide dielectric
permittivity and thickness, 𝜀 - electric constant, 𝐿 and 𝑊
are the transistor channel length and width.
B. The Linear Approximation of the Triode Regime
In case when drain-to-source bias VDS is small we can
apply linear approximation to triode regime:
𝐼LIN = 𝑔ch 𝑉DS . (4)
The differential conductance in linear regime is
𝑔ch = βVGT . (5)
The output resistance for the “intrinsic” MOSFET in linear
part of triode regime:
𝑟 = . (6)
ch
In Fig. 2 you can see the large-signal equivalent circuit
model of the n-channel “intrinsic” MOSFET in the linear part
of the triode regime, incorporating the output resistance 𝑟 .
Note, that it is the linear approximation of the triode
regime that is used in compact modeling by substitution into
smoothing function.
C. Saturation Regime
In MOSFET theory, the velocity saturation can be
accounted for by assuming a simple approximation for the
drift velocity 𝑣 dependence on electric field 𝐸 [11] - [14] as:
𝜇 𝐸, 𝐸 < 𝐸
𝑣= . (7)
𝑣 ,𝐸 ≥ 𝐸
(1) Here 𝜇 – is a constant electron mobility, 𝐸 = 𝑣 ⁄𝜇 - is
the saturation field, 𝑣 – is the saturation velocity.
The characteristic voltage 𝑉 is related to the drift velocity
saturation in a high electric field as follows:
𝑉 =𝐸 𝐿 . (8)
As the drain voltage is increased, the current saturates.
Once the electric field on the drain side of the channel
exceeds 𝐸 , the electron velocity saturates, leading to the
current saturation. The saturation current of an “intrinsic”
MOSFET is
𝐼 = 𝛽𝑉 1+ −1 . (9)
 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)

Fig. 2. Large-signal equivalent circuit of the n-channel “intrinsic” Fig. 3. Large-signal equivalent circuit of the n-channel “intrinsic”
MOSFET in the linear part of the triode regime, incorporating the output MOSFET in saturation that incorporates the current source 𝐼 (9) that is
resistance 𝑟 . controlled by the gate-to-source bias 𝑉 .

The “intrinsic” MOSFET saturation voltage is Here we use parameter 𝜆 = 1⁄𝑉 [15]. And 𝑉 is the
analog of the Early voltage from the bipolar junction
transistor theory.
𝑉 =𝑉 1+ − 1+ . (10) Note, that in compact modeling, in addition to the linear
approximation of the triode regime, it is the linear
approximation of the saturation regime used by substituting
Hence: both into smoothing function. For the saturation regime, a
linear approximation for the dependence of the “intrinsic”
MOSFET drain current on the “intrinsic” drain-to-source bias
𝐼 = 𝐼TRD , 𝑉 ≤ 𝑉DS ≤ 𝑉 . (11) is generally considered in two forms. The first form is used
𝐼 , 𝑉DS > 𝑉 for entry-level compact models as MOSFET Level 1 [12],
[16], [17]:
Note that 𝐼 → 𝛽𝑉 ⁄2 and 𝑉 → 𝑉 if 𝑉 ≪
𝑉 . Moreover, 𝐼 → 𝛽𝑉 𝑉 and 𝑉 → 𝑉 if 𝑉 ≫ 𝑉 .
𝐼 =𝐼 + 𝑉 ⁄𝑟 . (16)
The transconductance 𝑔 = in the saturation
DS In Fig. 4 you can see the large-signal equivalent circuit of
regime characterizes the change of the saturation current with the n-channel “intrinsic” MOSFET in saturation,
gate-to-source bias change as follows: incorporating the controlled by gate-to-source voltage 𝑉
current source 𝐼 and the output resistance 𝑟 [1].

𝑔 = . (12) The second form is used for more advanced compact

models as BSIM3 / 4 [18]:

𝐼 =𝐼 + (𝑉 −𝑉 )⁄𝑟 . (17)
In addition, we will use 𝑏 = parameter, that
DS
characterizes the change of the saturation voltage with gate- In Fig. 5 you can see the large-signal equivalent circuit of
to-source bias change as follows: the n-channel “intrinsic” MOSFET in saturation,
incorporating the output resistance 𝑟 , current source 𝐼 , and
voltage source 𝑉 , all controlled by gate-to-source voltage
𝑏 = 1− . (13) 𝑉 [19].

Note that: III. THE “EXTRINSIC” TRANSISTOR

An “extrinsic” MOSFET has parasitic resistors 𝑅 in
𝑔 → 𝛽𝑉 and 𝑏 → 0 if 𝑉 ≫𝑉 . (14) series with its source terminal and a 𝑅 in series with its drain
terminal (see Fig. 6) [11], [12], [13]. The total parasitic
resistance is 𝑅 = 𝑅 + 𝑅 . For “intrinsic” and “extrinsic”
In Fig. 3 you can see the large-signal equivalent circuit
gate-to-source and drain-to-source biases, we have:
model of the n-channel “intrinsic” MOSFET in the saturation
regime saturation, that incorporates the controlled by the gate-
to-source bias 𝑉 current source 𝐼 (9). 𝑉 = 𝑉 − 𝐼𝑅 , (18)

D. The Output Resistance in the Saturation Regime

The output resistance due to channel length modulation in 𝑉 = 𝑉 − 𝐼𝑅 . (19)
the saturation regime of the “intrinsic” MOSFET is
Determine the “extrinsic” overdrive voltage as:

𝑟 = . (15)
𝑉 =𝑉 −𝑉 . (20)

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 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)

𝑔ch = 𝛽𝑉 . (23)

Note that here the argument of function 𝑔ch (see (5)) is 𝑉

instead of 𝑉 . Hence, the output resistance for the “extrinsic”
MOSFET in the linear approximation of the linear regime
𝑅 = 1/𝐺 is

𝑅 =𝑟 +𝑅 . (24)

Here, the resistance of the transistor channel is

Fig. 4. Large-signal equivalent circuit of the n-channel “intrinsic”

MOSFET in saturation, incorporating the output resistance 𝑟 and the current 𝑟ch = . (25)
source 𝐼 , both controlled by the gate-to-source bias 𝑉 . See (16) for Level
1 model.
In Fig. 7 you can see the large-signal equivalent circuit of
the n-channel “extrinsic” MOSFET in the linear part of the
triode regime, incorporating the output resistance 𝑅 .

B. Saturation Regime in the “Extrinsic” Case

The equation for an “extrinsic” saturation current is as
follows:

Fig. 5. Large-signal equivalent circuit of the n-channel “intrinsic”

𝐼 = . (26)
MOSFET in saturation, incorporating the output resistance 𝑟 , the current
source 𝐼 , and voltage source 𝑉 , all controlled by the gate-to-source bias
𝑉 . See (17) for BSIM3 / 4 model.
The saturation voltage in the “extrinsic” regime is:

𝑉 =𝑉 +𝐼 ∙𝑅 . (27)

The argument of the function 𝑉 here is 𝑉 − 𝐼 ∙𝑅

instead of 𝑉 . The transconductance 𝐺 = in the
“extrinsic” case is

⎛ ⎞
𝐺 = ⎜ − 𝛽𝑉 𝑅 ⎟. (28)

⎝ ⎠
Fig. 6. A three-terminal “extrinsic” MOSFET schematic with parasitic
contact resistors 𝑅 and 𝑅 is in the box drawn with long-dashed line. The The relationship between the “intrinsic” 𝑔m and
corresponding “intrinsic” MOSFET is in the box drawn with short-dashed “extrinsic” 𝐺m transconductances is
line.

A. The Linear Approximation of the Triode Regime in the 𝑔 = . (29)

“Extrinsic” Case
For an “extrinsic” MOSFET current in the linear or
approximation of the triode regime, we have:
= +𝑅 . (30)
𝐼lin = 𝐺 𝑉ds . (21)
Note that:
Here:

𝐺ch = ch
. (22) 𝐺 → and 𝑔 → 𝛽𝑉 if 𝑉 ≫ 𝑉 . (31)
ch

with

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 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)

Fig. 7. Large-signal equivalent circuit of the n-channel “extrinsic” Fig. 8. Large-signal equivalent circuit of the n-channel “extrinsic”
MOSFET in the linear part of the triode regime, incorporating the output MOSFET in saturation, incorporating the output resistance 𝑅 and the
resistance 𝑅 (see (24)). current source 𝐼 controlled by the gate-to-source voltage 𝑉 (see (33) for
Level 1).
The parameter 𝐵 = in the “extrinsic” case is
Here the argument of function 𝑔m (see (12)) and 𝑏m (see
(13)) is 𝑉 − 𝐼 𝑅 instead of 𝑉 . And 𝑟 is given by (35).
With use of (13) for 𝑏m , we can rewrite equation (37) as
𝐵 =1− −𝑅 𝐺 . (32) follows:

C. The MOSFET Output Resistance in the Saturation 𝑅 =𝑟 + 𝑅 +𝑅 +𝑔 𝑟 𝑅 . (38)

Regime in the “Extrinsic” Case
Similarly to the case of the “intrinsic” MOSFET, two
variants of the linear approximation for the asymptotic
dependence of the “extrinsic” MOSFET drain current on the
“extrinsic” drain bias in the saturation regime were proposed
in [8]. The first form is as for the entry-level compact models,
like Level 1 (see (16)):
𝐼 =𝐼 + 𝑉 ⁄𝑅 . (33)
For this case in [8] an equation was derived for the output
resistance of an “extrinsic” MOSFET:
𝑅 =𝑟 +𝑅 +𝑔 𝑟 𝑅 . (34)
Here the argument of function 𝑔m (see (12)) is 𝑉 −
𝐼 𝑅 (instead of 𝑉 ) and
𝑟 = . (35)
Moreover, we can calculate 𝑔m with use of (29) in which
we use 𝐺 from (28).
In Fig. 8 we presented the large-signal equivalent circuit
of the n-channel “extrinsic” MOSFET in the saturation,
incorporating the output resistance 𝑅 and the current source
𝐼 , both controlled by the gate-to-source voltage 𝑉 .
The second form is as for more advanced compact models
like BSIM3 / 4 (see (17)):
With accounting (31), we can see that 𝑅 →𝑅 if
𝑉 ≫𝑉.
In Fig. 9 presented the large-signal equivalent circuit of the
n-channel “extrinsic” MOSFET in the saturation,
incorporating the output resistance 𝑅 , current source 𝐼
and voltage source 𝑉 , all controlled by gate-to-source
voltage 𝑉 .
IV. BODY EFFECT IN THE CASE OF AN “INTRINSIC” FOUR-
TERMINAL MOSFET
Fig. 10 shows the physical structure of the four-terminal
(with body terminal) n-channel enhancement-type MOSFET.
In addition to the gate terminal (G), the source terminal (S),
and the drain terminal (D), we have the substrate or body
terminal (B).
The fact that the threshold voltage 𝑉 is a function of the
source-to-body bias 𝑉 (see Fig. 10) is called the body
effect. In earlier generations of MOSFETs, the body doping
density was more or less uniform. In that case, the theory
predicts that the threshold voltage is a sublinear function of
the source-to-body bias [6], [12]:
𝑉 =𝑉 +𝛾 2𝛷 + 𝑉 − 2𝛷 . (39)

𝐼 =𝐼 + (𝑉 − 𝑉 )⁄𝑅 . (36)

For this case in [8] an equation was derived for the output
resistance of an “extrinsic” MOSFET:
𝑅 = 𝑟 + 𝑅 + (𝑔 𝑟 − 𝑏 ) 𝑅 .
Fig. 9. Large-signal equivalent circuit of the n-channel “extrinsic”
(37) MOSFET in saturation, incorporating the output resistance 𝑅 , the current
source 𝐼 , and the voltage source 𝑉 controlled by the gate-to-source
voltage 𝑉 (see (36) for BSIM3 / 4).

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Note that to transform all equations with accounting for

the body effect into equations without accounting for the
body effect, it is enough to put into all equations 𝛼 = 0
(note, that in this case 𝛼 = 1).

A. Triode Regime in the “Intrinsic”Case with Accounting

for the Body Effect
With accounting for the body effect for the MOSFET
triode regime, we have:
Fig. 10. Schematic cross-section of an n-channel MOSFET with four
terminals (including the fourth (body) terminal) and symbol of MOSFET
with the body terminal. 𝐼TRD = β VGT 𝑉DS − 𝑉 . (46)
The back-gate transconductance parameter [1], [17] 𝜒 =
And here 𝛼 is
is

𝛼= = . (47)
𝜒= . (40)
where 𝑚 = 1 + 𝛼 is the bulk-charge factor [6].
Equation (39) can be linearized by the first-order Taylor
expansion as follows: B. The Linear Approximation of the Triode Regime in the
“Intrinsic” Case with Accounting for the Body Effect
𝜕 In case when drain-to-source bias VDS is small we can
𝑉 ≈𝑉 + 𝑉 , (41)
𝜕 apply linear approximation to the triode regime. And we have
the same equations (4), (5), and (6), as for the linear
so that 𝑉 can be approximated as a linear function of 𝑉 approximation of the triode regime in the “intrinsic” case
in case when one is small enough (𝑉 ≪ 𝛷 ): without accounting for the body effect only with overdrive
voltage 𝑉 from (45).

𝑉 ≈ 𝑉 + 𝜒0 𝑉 . (42) C. Saturation Regime in the “Iintrinsic” Case with

Accounting for the Body Effect
𝑉𝑡
Here 𝜒 = 𝑉𝑆𝐵 𝑉 =0
is The saturation current of an “intrinsic” MOSFET with
𝑆𝐵 accounting for the body effect is
𝛾
𝜒 = . (43)
2 2𝛷𝑓
𝐼 = 1+ −1 . (48)

Modern transistors with steep retrograde body doping

profiles exhibit a more or less linear relationship between a For the “intrinsic” MOSFET saturation voltage, we have:
threshold voltage 𝑉 and a source-to-body bias 𝑉 [6] is

𝑉 =𝑉 1+ − 1+ . (49)
𝑉 =𝑉 +𝛼 𝑉 . (44)

Here 𝛼 is called the body-effect coefficient, which is

The transconductance 𝑔 = is
constant and can be extracted from the slope of the 𝑉 (𝑉 ) DS
curve [6]. The polarity of the body bias is normally that which
would reverse bias the body-source p-n junction. Hence, for
NMOS transistors, usually, for the source-to-body bias, we 𝑔 = . (50)
have 𝑉 > 0 and for the body-to-source we have 𝑉 =
−𝑉 < 0 .
Note that we will use the same notation in equations as in For the 𝑏 parameter we have:
the case without accounting for the body effect.
Note, that in in following equations we will use the
overdrive voltage 𝑉 (see (1)). However, instead of the 𝑏 =𝛼 1− . (51)
constant threshold voltage 𝑉 in the equation for 𝑉 , we will
use (44) that accounts the source-to-body bias 𝑉 as follows: Again 𝑔 → 𝛽𝑉 and 𝑏 → 1 if 𝑉 ≫ 𝑉 (see (14)).
The relationship between the body transconductance
𝑉 = 𝑉 −𝑉 −𝛼 𝑉 . (45)

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 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)

𝑔 = and transconductance 𝑔 is
DS

𝑔 =𝜒𝑔 . (52)

For modern transistors with steep retrograde body doping

the body transconductance is

𝑔 =𝛼 𝑔 . (53)

D. The Output Resistance in the Saturation Regime in the

“Intrinsic” Case with Accounting for the Body Effect
We have the same equations (15) – (17), like for the
saturation regime in the “intrinsic” case without accounting
for the body effect only with overdrive voltage 𝑉 from (45)
in 𝐼 and 𝑉 .

V. BODY EFFECT IN CASE OF AN “EXTRINSIC” FOUR-

TERMINAL MOSFET

A. Equivalent Parameters and Equivalent a Three-Terminal

(Without Body Tetrminal) “Extrinsic” Transistor with
Accounting for the Body Effect
In [10] we have shown how it is possible to convert a
transistor with a body terminal (see Fig. 10) into an
equivalent transistor without a body terminal (see Fig. 1).
Here, we will repeat our reasoning.
A four-terminal “intrinsic” MOSFET with parasitic
contact resistors and the body (fourth) terminal presented in
Fig. 11(a). We can substitute 𝑉 from (44) into (1) for 𝑉 .
Hence, in the “intrinsic” case, the overdrive voltage 𝑉 can
be presented as follows:

𝑉 =𝑉 −𝛼 𝑉 (54)
Fig. 11. (a) A four-terminal “intrinsic” MOSFET with contact resistors and
with the body (fourth) terminal. (b) A three-terminal equivalent “intrinsic”
MOSFET with an equivalent threshold voltage 𝑉 ∗ and equivalent contact
resistors 𝑅 ∗ and 𝑅 ∗ . (c) A three-terminal equivalent single “extrinsic”
𝑉 =𝑉 −𝑉 . (55) MOSFET.

After substitution of equation (56) for 𝑉 and the

After substitution 𝑉 from (18) into (55) we have:
equation (59) for 𝑉 into (54) for 𝑉 we have:

𝑉 =𝑉 − 𝐼𝑅 (56)
𝑉 = 𝑉 − (𝑉 + 𝛼 𝑉 ) − 𝐼(1 + 𝛼 )𝑅 . (60)
with
From this equation, we can see that it is possible to
introduce the equivalent transistor without the body terminal
𝑉 =𝑉 −𝑉 . (57) (see Figs. 11(b) and 11(c)) with the equivalent threshold
voltage as follows:
For “intrinsic” and “extrinsic” body-to-source bias, we
have: 𝑉∗ = 𝑉 + 𝛼 𝑉 , (61)

𝑉 = 𝑉 − 𝐼𝑅 . (58) and with equivalent source resistance:

We can rewrite this equation in terms of source-to-body 𝑅 ∗ = (1 + 𝛼 )𝑅 , (62)

bias, taking into account the fact that 𝑉 = −𝑉 and
𝑉 = −𝑉 , as follows: and with equivalent drain resistance:

𝑉 = 𝑉 + 𝐼𝑅 . (59) 𝑅∗ = 𝑅 − 𝛼 𝑅 . (63)

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 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)

Note, that 𝑅 = 𝑅 + 𝑅 = 𝑅∗ + 𝑅 ∗ . C. Saturation Regim with Accounting for the Body Effect
Furthermore, let us determine the equivalent “extrinsic” For an “extrinsic” MOSFET in the saturation regime, with
overdrive voltage as follows: accounting for the body effect, we have the equation for the
saturation current:

𝑉∗ = 𝑉 − 𝑉∗ (64)
∗
∗ ∗ ∗ ∗
∙⎛ ⎞
or
𝐼 = ⎝
∗
⎠ . (72)
∙
∗
𝑉 =𝑉 −𝛼 𝑉 . (65)
The transconductance 𝐺 = is:
Therefore, we can rewrite equation (60) for 𝑉 by use of
the equivalent overdrive voltage 𝑉 ∗ and the equivalent source
resistance 𝑅∗ as follows:
∗
∗
∗ ∗ ⎛ ⎞
𝑉 = 𝑉 − 𝐼𝑅 . (66) 𝐺 = − 𝛽𝑉 𝑅∗ ⎟ (73)
∗ ⎜ ∗
∗ ∗
Now we can use all equations from (18) to (38), which ⎝ ⎠
were previously derived for the three-terminal “extrinsic”
MOSFET (without accounting for the body effect), for the Note that:
modeling of the four-terminal “extrinsic” MOSFET (with
accounting for the body effect). Hence, if we will substitute in
these equations equivalent threshold voltage 𝑉 ∗ (61) and 𝐺 → ∗ if 𝑉 ∗ ≫ 𝑉 . (74)
equivalent source 𝑅 ∗ (62) and drain 𝑅 ∗ (63) parasitic
resistances instead of 𝑉 , 𝑅 , and 𝑅 , we will obtain results for
the four-terminal “extrinsic” MOSFET with accounting for The relationship between the “intrinsic” 𝑔m and
the body effect. “extrinsic” 𝐺m transconductances for an “extrinsic” MOSFET
with accounting for the body effect is
B. The Linear Approximation of the Triode Regime with
Accounting for the Body Effect 𝑔 = (75)
∗
For an “extrinsic” MOSFET current in the linear
approximation of the triode regime with accounting for the
or
body effect we have:

𝐼lin = 𝐺 𝑉ds . (67) = + 𝑅∗ . (76)

Here: Note that, similar to (14), we have:

𝑔 → 𝛽𝑉 if 𝑉∗ ≫ 𝑉 . (77)
ch
𝐺ch = . (68)
ch
The parameter 𝐵 = is:
with

𝑔ch = 𝛽𝑉 ∗ . (69) 𝐵 =𝛼 1− +𝐺 𝑅 . (78)

Note that here the argument of function 𝑔ch (see (5)) is 𝑉 ∗ The body transconductance 𝐺 = is:
instead of 𝑉 . Hence, the output resistance 𝑅 = 1/𝐺 in
the linear approximation of the linear regime for the
“extrinsic” four-terminal and equivalent three-terminal
𝐺 =𝛼 𝐺 . (79)
MOSFET with accounting for the body effect is
The relationship between the “intrinsic” 𝑔mb and
𝑅 = 𝑟 +𝑅 . (70) “extrinsic” 𝐺 = body transconductances is

Here, the resistance of the transistor channel is

𝑔 = (80)
𝑟ch = ∗ . (71)

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 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)

or And 𝑟 is given by (86), the same as in the previous case.

Moreover, we can calculate 𝑔m with use of (75) in that we use
𝐺 , that can be calculated from (73), the same as in the
= +𝑅 . (81) previous case.
With use of (13) for 𝑏m , we can rewrite (88) in form for an
The body parameter 𝐵 = is “extrinsic” equivalent three-terminal transistor as follows:

𝑅 =𝑟 +( )
𝑅∗ + 𝑅 + 𝑔 𝑟 𝑅 ∗ . (90)
𝐵 =𝐺 𝑅 − +1−𝛼. (82)
Or we can rewrite (88) in the form of an “extrinsic” four-
terminal transistor as follows:
D. Output Resistance in the Saturation Regim with
Accounting for the Body Effect
Again, there are two variants of the linear approximation 𝑅 =𝑟 + 𝑅 +𝑅 +𝑔 𝑟 𝑅 . (91)
for the asymptotic dependence of the “extrinsic” MOSFET
drain current on the “extrinsic” drain bias in the saturation With accounting (77), we can see that 𝑅 →𝑅 if
regime. The first form is as for the entry-level compact
𝑉∗ ≫ 𝑉 .
models like MOSFET Level 1 (see (33)). For this case, the
output resistance of an “extrinsic” equivalent three-terminal
transistor is VI. SMOOTHING FUNCTION
An important task for MOSFET compact modeling is to
𝑅 = 𝑟 + 𝑅 + 𝑔 𝑟 𝑅∗ . (83) bridge the transition between the linear and saturation regimes
with one single expression. For this purpose, traditionally the
Or, the output resistance of an “extrinsic” four-terminal following smoothing function with saturation knee parameter
transistor is 𝑚 [2], [13] is used:

𝑅 =𝑟 +𝑅 +𝑔 𝑟 𝑅 . (84) ,
𝐼= . (92)
with the effective transconductance 𝑔 , that is
However, this approach suffers from nonmonotonic
𝑔 = (1 + 𝛼 ) 𝑔 . (85) behavior of the differential conductance with increasing drain-
to-source bias for both (16) and (17) drain current asymptotic
in the saturation regime [5] and see Figs. 12(b) and 13(b).
Here the argument of function 𝑔m (see (12)) is 𝑉 ∗ −
𝐼 𝑅 ∗ (instead of 𝑉 ) and In [4] we proposed a new smoothing function that ensures
a monotonic decrease in differential conductance from the
maximum value in the linear regime to the minimum value in
𝑟 = . (86) the saturation:

Moreover, we can calculate 𝑔m with use of (75) in that we ,

use 𝐺 , that can be calculated from (73). 𝐼= . (93)
,
The second form is as for more advanced compact models,
like BSIM3 / 4 (see (36)). For this case, the output resistance with
of an equivalent three-terminal MOSFET is

𝐼 , = 𝐼 , . (94)
𝑅 = 𝑟 + 𝑅 + (𝑔 𝑟 − 𝑏 ) 𝑅 ∗ . (87)

Or, the output resistance of an “extrinsic” four-terminal Here:

transistor is

𝑔ch = (95)
𝑅 = 𝑟 + 𝑅 + (𝑔 𝑟 −𝑏 )𝑟 𝑅 . (88)

with 𝑔 from (85) and with the effective parameter 𝑏 and

from this equation:
𝑔ASY = . (96)
𝑏 = (1 + 𝛼 ) 𝑏 . (89)
Adaptation of the traditional smoothing function for the
Here again, the same as in the previous case, the argument
of function 𝑔m (see (12)) is 𝑉 ∗ − 𝐼 𝑅 ∗ (instead of 𝑉 ).

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 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)
“extrinsic” case is:
,
𝐼= . (97)
In our calculations, we use the “improved” smoothing
function [4] that is adopted for the “extrinsic” MOSFET, that
is:
, traditional smoothing function red dotted line is used. Orange
𝐼= (98)
,
with
𝐼 , = 𝐼 , . (99)
,
Here:
𝐺ch = (100)
and
𝐺01,02 = . (101)
, “intrinsic” and “extrinsic” MOSFET with and without body
with 𝑅 from (70), 𝑅 from (83), and 𝑅 from (90),
respectively.
VII. PARAMETERS AND RESULTS
In our calculations we used MOSFET parameters of 180
nm technology mainly from [15] Table 1.5. Channel length
𝐿 = 180 nm; gate width 𝑊 = 1 m; characteristic electric
field for velocity saturation 𝐸 = 8 ∙ 10 V/cm; 𝑉 = 𝐸 𝐿 =
1.44 V; the body-effect coefficient 𝛼 = 0.2 and 𝛼 = (1 +
𝛼 ) = 0.83 ; 𝑉 = 0.45 V; the Early voltage 𝑉 = 4 V
[20] and 𝜆 = 1⁄𝑉 = 0.25 V-1 (𝜆 ∙ 𝐿 = 0.08 m/V); 𝑅 =
𝑅 = 125 ; (parasitic contact resistances are chosen with
use of RDSW=250 parameter [18] from Predictive
Technology Model 180 nm NMOS SPICE Parameters file
[21]); SiO2 thickness 𝑑 = 5 nm and relative permittivity
𝜀 = 3.9; 𝐶 = 𝜀 𝜀 ⁄𝑑 = 6.9 fF/m2. We suppose the
process transconductance parameter 𝑘′ = 𝜇 𝐶 = 270
A/V2. Hence, the transconductance parameter 𝛽 =
𝑘′ 𝑊 ⁄𝐿 = 1500 A/V2. In smoothing functions we use 𝑚 =
4.
In Fig. 12 blue dash-dotted lines are used for the set of
output current-voltage characteristics (a) and for the set of
output conductance (b) in the “intrinsic” case, without body
effect (𝛼 = 0)), with (17) (BSIM3 / 4) for the drain current
in the saturation, and with “intrinsic” improved smoothing
function (93)-(94). For the case of traditional smoothing
function (92) a blue dotted line is used. Green lines are used
for the case of the “intrinsic” equation (16) (Level 1) for the
drain current in the saturation. For the case with improved
smoothing function, the green dash-dotted line is used, and
with the traditional smoothing function, the green dotted line
is used. In both cases when the traditional smoothing function
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was used we can see nonmonotonic behavior of the
differential conductance with increasing drain-to-source bias
for both (16) and (17) drain current asymptotic in the
saturation regime [5].
In Fig. 13 red dash-dotted lines are used for the sets of
output current-voltage characteristics (a) and output
conductance (b) in the “extrinsic” case, without body effect
(𝛼 = 0), with “extrinsic” equation (36) (BSIM3 / 4) for the
drain current in the saturation regime, and with “extrinsic”
improved smoothing function (98)-(99); for the case of
lines are used for the case of “extrinsic” equation (33) (Level
1) for the drain current in the saturation regime. For the case
with improved smoothing function orange dash-dotted line is
used and with traditional smoothing function orange dotted
line is used. In both cases when traditional smoothing function
was used, we can see nonmonotonic behavior of the
differential conductance with increasing drain-to-source bias
for both (33) and (36) drain current asymptotic in the
saturation regime.
In Fig. 14 (a) output current-voltage, (b) output
conductance, and (c) transconductance characteristics are
presented for an “intrinsic” and “extrinsic” MOSFET with and
without body bias. Equations (16) and (33) from Level 1
model for the drain current in the saturation regime, and
improved smoothing function are used. The same way, in Fig.
15 (a) output current-voltage, (b) output conductance, and (c)
transconductance characteristics are presented for an
bias. Equations (17) and (36) from BSIM3 / 4 model for the
drain current in the saturation regime, and improved
smoothing function are used.
VIII. APPLICATION TO THE THEORY OF A COMMON-SOURCE
AMPLIFIER WITH SOURCE DEGENERATION
In the theory of a common-source amplifier, the circuit
that consists of an NMOS transistor with a resistor 𝑅 in series
with its source terminal is known as a transistor with source
degeneration [1], [17], [22], [23]. In this case, the output
resistance is
𝑅 =𝑟 +𝑅 +𝑔 𝑟 𝑅 . (102)
Note, that this equation was derived in [1] for the output
resistance of the common-gate amplifier (see Fig. 16 (a)) and
was applied directly to the case of a source-degenerated
common-source amplifier (see Fig. 16 (b)).
Furthermore, in [1] it is shown, that the body effect can be
taken into account simply by replacing transconductance 𝑔
by the effective transconductance 𝑔 , that is:
𝑔 =𝑔 +𝑔 = (1 + 𝜒) 𝑔 . (103)
Here, the back-gate transconductance parameter 𝜒 is given
by (40). In case of the linear relationship between a threshold
voltage 𝑉 and a source-to-body bias 𝑉 we have:
𝑔 = (1 + 𝛼 ) 𝑔 . (104)
 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)

Fig. 12. Blue dash-dot line is for the output current-voltage characteristic (a)
and for the output conductance (b) in the “intrinsic” case, without body effect
(𝛼 = 0), with (17) (BSIM3 / 4) for the drain current asymptote in the
saturation regime, and with improved smoothing function (92)-(96); for the
case of traditional smoothing function (92) blue dot line is used. Green lines
are used for the case of equation (16) (Level 1) for the drain current
asymptote in the saturation regime. For the case with improved smoothing
function green dash-dotted line is used and with a traditional smoothing
function the green doted line is used. All curves are for the gate-to-source
bias 4 V. We can see non-monotonic behavior of the output resistance with
increasing drain-to-source bias in case of traditional smoothing function
usage in both asymptotes cases.
Fig. 13. Red dash-dot line is for the output current-voltage characteristic (a)
and for the output conductance (b) in the “extrinsic” case, without body
effect (𝛼 = 0), with equation (36) (BSIM3 / 4) for the drain current in the
saturation regime, and with improved smoothing function (98)-(101); for the
case of traditional smoothing function red dot line is used. Orange lines are
used for the case of equation (33) (Level 1) for the drain current asymptote
in the saturation regime. For the case with improved smoothing function
orange dash-dot line is used and with traditional smoothing function orange
dot line is used. All curves are for the gate-to-source bias 4 V. We can see
non-monotonic behavior of the output resistance with increasing drain-to-
source bias in case of traditional smoothing function usage in both
asymptotes cases.

A. Neglecting the Body Effect
Let’s put 𝑅 = 0 in (34) and (38).
1. From (34) (which corresponds to Level 1 model), we
have:
𝑅 =𝑟 + 𝑅 +𝑔 𝑟 𝑅 .
In Fig. 17 (a), we presented the corresponded large-signal
equivalent circuit of a degenerated n-channel MOSFET (with
a resistor 𝑅 in series with its source terminal) in saturation,
incorporating the output resistance 𝑟 and the controlled
current source 𝐼 (compare with Fig. 4).
2. From (38) (corresponding to the BSIM3 / 4 model), we
have:
𝑅 =𝑟 + 𝑅 + 𝑔 𝑟𝑅 .
In Fig. 17 (b) we presented the corresponded large-signal
equivalent circuit of a degenerated n-channel MOSFET (with
a resistor 𝑅 in series with its source terminal) in saturation,
incorporating the output resistance 𝑟 , the controlled current
source 𝐼 , and controlled voltage source 𝑉 (compare
with Fig. 5).
Note that the equation (105) for 𝑅 , obtained for the case
when 𝑅 = 0, is in full agreement with (102) from [1] for an
output resistance 𝑅 of a common-gate amplifier with a signal
source with a resistance 𝑅 and of a common-source amplifier
with a source degeneration resistor 𝑅 .
To the best of our knowledge, the equation (38) is derived
(105) in [8] for the first time. And equation (106), based on equation
(38), was used for the common-source amplifier with a source
degeneration in [10] for the first time. Note that this equation
is derived for the large-signal equivalent circuit model of a
degenerated n-channel MOSFET (with a resistor 𝑅 in series
with its source terminal) in saturation, incorporating the output
resistance 𝑟 , the controlled current source 𝐼 , and
controlled voltage source 𝑉 (see Fig. 17).
In contrast, the equivalent circuit related to the well-
known equation (105) does not take into account controlled
voltage source 𝑉 .
(106)
B. Accounting for the Body Effect
Let’s put 𝑅 = 0 in (84) and (91):
1. From (84) we have:
𝑅 =𝑟 + 𝑅 + 𝑔 𝑟𝑅 . (107)

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 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)
Fig. 14. (a) Output current-voltage characteristics. (b) Output conductance.
(c) Transconductance. Equations (16) and (33) from the Level 1 model are
used for the drain current asymptote in the saturation regime and an improved
smoothing function is used. Blue lines – “intrinsic” case. Red lines –
“extrinsic” case. Dash-dotted lines – no body effect (𝛼 = 0). Solid lines –
zero body bias. Dashed lines – body bias 𝑉 = −𝑉 = −1 V in the
“intrinsic” case and 𝑉 = −𝑉 = −1V in the “extrinsic” case. In (a) and (b)
red and blue top curves are for gate-to-source bias 4 V. Next, 3 V, 2 V, and
1 V. In (c) red and blue top curves are for drain-to-source bias 4 V. Next, 3
V, 2 V, and 1 V.
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Fig. 15. (a) Output current-voltage characteristics. (b) Output conductance.
(c) Transconductance. Equations (17) and (36) from the BSIM3 / 4 model
are used for the drain current asymptote in the saturation regime and an
improved smoothing function is used. Blue lines – “intrinsic” case. Red lines
– “extrinsic” case. Dash-dotted lines – no body effect (𝛼 = 0). Solid lines
– zero body bias. Dashed lines – body bias 𝑉 = −𝑉 = −1V in the
“intrinsic” case and 𝑉 = −𝑉 = −1V in the “extrinsic” case. In (a) and (b)
red and blue top curves are for gate-to-source bias 4 V. Next, 3 V, 2 V, and
1 V. In (c) red and blue top curves for drain-to-source bias 4 V. Next, 3 V,
2 V, and 1 V.
 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)

Fig. 16. (a) The common-gate stage with a signal source 𝑣 having a
resistance 𝑅 has an output resistance 𝑅 . (b) Common-source stage based
on a degenerated n-channel MOSFET transistor (with a resistor 𝑅 in series
with its source terminal) has an output resistance 𝑅 (see (102)).

Fig. 17. (a) Large-signal equivalent circuit of a degenerated n-channel

MOSFET (with a resistor 𝑅 in series with its source terminal) in saturation,
incorporating the output resistance 𝑟 and the controlled current source 𝐼
(see (33) for Level 1 model). (b) Large-signal equivalent circuit of a
degenerated n-channel MOSFET (with a resistor 𝑅 in series with its source
terminal) in saturation, incorporating the output resistance 𝑟 , the controlled
current source 𝐼 , and controlled voltage source 𝑉 (see equation (36) for
BSIM3 / 4 model).

2. From (91) we have:

𝑅 =𝑟 + 𝑅 + 𝑔 𝑟𝑅 . (108)

In both equations, the effective transconductance 𝑔 is

given by (104).
Note that, to the best of our knowledge, equation (91), that
is a generalization of equation (38) in the case with accounting
for the body effect, is derived in [10] for the first time. And
the equation (105), based on equation (91), for the first time
was used in [10] for the common-source amplifier with a
source degeneration and with accounting for the body effect.
In Fig. 18 presented the comparison of the transistor with
source degeneration output resistance, calculated with (105)
(that is corresponding to equation (33) for Level 1 model) and
with (106) (that is corresponding to equation (36) for BSIM3/4
model) without body effect (𝛼 = 0) for the case of MOSFET
with channel length 180 nm (a) and 350 nm (b). Upper curve
for the Early voltage 𝑉 = 2.25 𝑉 [15], next down 𝑉 = 4 𝑉 Fig. 18. Comparison of the transistor with source degeneration output
[20]. All parameters are from [15] for the 180 nm (Fig. 18 (a) resistance, calculated with (105) (that is corresponding to equation (33) for
and (b)) and 350 nm (Fig. 18 (c)) NMOS process technology. Level 1 model) and with (106) (that is corresponding to equation (36) for
For 350 nm technology we used 𝑉 = 0.57 V, 𝑉 = 2.19 V, BSIM3/4 model) without body effect (𝛼 = 0) for the case of technology
180 nm with channel length 𝐿 = 180 nm (a) and 𝐿 = 350 nm (b), and with
𝜆 = 0.46 V-1, 𝜆 ∙ 𝐿 = 0.16 m/V [15], and 𝑉 = 3.89 V, technology 350 nm with 𝐿 = 350 nm (c). All parameters are from [15] for
𝑑 = 8 nm, 𝑘′ = 190 A/V2, 𝛽 = 543 A/V2. 180- and 350 nm technology. Solid lines are for the case of source resistance
𝑅 = 125 -m and dash lines are for the case of source resistance 𝑅 =
In Fig. 18 solid lines are for the case of source resistance 500 -m. In (a) and (b) upper curves (red) for the Early voltage 𝑉 =
125 Ω-m and dash lines are for the case of source resistance 2.25 𝑉 [15] and dowm curves (blue) for the Early voltage 𝑉 = 4 𝑉 [20]. In
(c) upper curves (red) for the Early voltage 𝑉 = 2.19 𝑉 [15] and dowm
500 Ω-m. We can see that the difference between equations curves (blue) for the Early voltage 𝑉 = 3.89 𝑉.

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 2022 Moscow Workshop on Electronic and Networking Technologies (MWENT)
(105) and (106) is from 1% up to 8%. Note that Fig. 18 (a) can
be approximately transformed into Fig. 18 (b) by
multiplication factor 𝐿( ) ⁄𝐿( ) = 350𝑛𝑚 ⁄180𝑛𝑚 ≈ 1.9 for
both vertical and horizontal axes, that can be explained by
analyzing equations (105) and (106).
CONCLUSION
In Fig. 14 (b) and 15 (b) we see a proper monotonic
decrease of the output conductance from the maximum value
to the minimum, both for an “intrinsic” and an “extrinsic”
MOSFET with accounting for the body effect, both for Level
1 (Fig. 14) and BSIM3 / 4 (Fig. 15) types asymptotes for the
drain current in the saturation regime. Remember, that the
Level 1 type asymptote in “extrinsic” case is given by (33)
with corresponding output resistance 𝑅 given by (34). And
the BSIM3 / 4 type asymptote in “extrinsic” case is given by
(36) with corresponding output resistance 𝑅 given by (38).
We can see a significant difference in the calculated output and
transfer MOSFET characteristics for two different types of
asymptotes used for the drain current in the saturation regime.
Note that the equation (102) was derived in [1] for the output
resistance of the common-gate amplifier and was applied
directly to the case of a source-degenerated common-source
amplifier. Hence, we can apply new equations (106) (without
accounting for the body effect) and (108) (with accounting for
the body effect) to a common-gate amplifier with a signal
source with a resistance 𝑅 and to a common-source amplifier
based on the degenerated transistor (with a resistor 𝑅 in
series with its source terminal). We can see, that the difference
between well-known equation (105) and new one (106) is
from 1% up to 8% in considered cases. Moreover, we have a
plan to apply the discussed approach of the accounting the
body effect to the theory of cascode amplifier.
ACKNOWLEDGMENT
The authors acknowledge the JSC “Bolkhov Plant of
Semiconductor Devices” for support of Roman Shkarlat in his
Ph.D. project at the Orel State University named after I.S.
Turgenev, which we also acknowledge. The authors thank
Vladimir Shcheglov (CJSC “Electrum AV”, Orel, Russia) for
helpful discussion. The authors thank Prof. Michael Shur
(Rensselaer Polytechnic Institute, Troy, NY, USA) and Prof.
Benjamin Iniguez (Rovira i Virgili University, Tarragona,
Spain) for helpful discussions during previous collaboration.
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