CoreEl

Mentor Graphics IC
Design Flow

M.Sharath Kanth
Application Engineer

www.coreel.com
OUTLINE OF AGENDA

Overview FPGA & ASIC design flow

Full Custom & Semi custom design flow

Mentor Graphics Tool flow

Overview of CMOS Technology under
Submicron Condition

Tool Demo

Lab

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FPGA & ASIC Design Flow:

Specifications

Graphical Design Entry

ASIC Specific Flow

Simulation Functional Verification

Synthesizer Synthesis DFT

Post-syn simulation Post-Synthesis Verification Verification Formal Verificatio

Layout Layout Editor

PAR
Physical Verification Physical Verification
Post-PAR Verification Simulation
Fabrication
Bit-Format
Verification

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 FPGA & ASIC Flow
Specifications
HDL Designer Design Entry ASIC Specific
Flow
ModelSim Functional Verification
Leonardo Spectrum
Precision Synthesis Synthesis DFT

ModelSim Post-Synthesis Verification Verification Formal Pro

Layout IC Station
PAR
Physical Verification Calibre
Post-PAR Verification ModelSim

Fabrication
Bit-Format
Verification
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FPGA Design flow

Advantages:

• Faster time to market

• No upfront NRE cost
• Simpler Design cycle
• Field Programmability

Disadvantages

• Not suitable for high volume production

• Design customization options are limited

Courtesy: Getting started with FPGAs, Xilinx

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 ASIC Design Flow

Behavioral Verify
Model Function
VHDL/Verilog
Synthesis
DFT/BIST Premitive Verify
& ATPG Netlist Function
Test vectors Full-custom IC
Transistor-Level Verify Function
Standard Cell IC Netlist & Timing
& FPGA/CPLD
DRC & LVS Physical Verify
Verification Layout Timing
Map/Place/Route

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IC Mask Data/FPGA Configuration File
Need for ASIC prototyping
Increase in Design complexity posing more complex challenges to leading-
edge ASIC design solutions

Key challenges the ASIC vendors facing are:

Expensive design solutions because of increasing cost of mask sets

Increased simulation runtime and inaccuracy of stimulus models.

Need for large scale engineering verification effort

What’s the result of above challenges?

• Only one third of the SoC designs are bug free in first silicon
• Half of the designs force re-spin due to functional errors

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Chip Fabrication

Designer Design Kit

GDSII
Foundry
(Fabricator)

Chip

GDS = Graphic Database System

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 Transistors
Gate Drain
Drain Source

Gate Width

Source Bulk
a) Circuit Symbol Length
b) Physical Realiza
Minimum Length=2λ Drain

Gate Ron Cdrain

Source Drain Width=4λ Gate
Csource
Cgate
Source
c) Layout View d) Simple RC Mo
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Design Kit

Digital Design Kit

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Files in Design Kit

Library Database: Layout, schematic, symbol, abstract, and

other logical or simulation views.

Timing Abstract - provides functional definitions, timing,

power, and noise information for each cell

DRC, LVS, PEX rule files.

Technology files: Layer specifications

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 Mentor Graphics ASIC Design Kit (ADK)

Technology files & standard cell libraries

AMI: ami12, ami05 (1.2, 0.5 µm)

TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 µm)

IC flow & DFT tool support files:

Simulation

VHDL/Verilog/Mixed-Signal models (Modelsim/ADVance MS)
VHDL/Verilog/Mixed-

Analog (SPICE) models (Eldo/Accusim)

Post--layout timing (Mach TA)
Post

Digital schematic (Quicksim II, Quicksim Pro) (exc. tsmc025,tsmc018)

Synthesis to std. cells (LeonardoSpectrum)

Design for test & ATPG (DFT Advisor, Flextest/Fastscan)

Schematic capture (Design Architect-
Architect-IC)

IC physical design (standard cell & custom)

Floorplan, place & route (IC Station)

Design rule check, layout vs schematic, parameter extraction (Calibre)

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Cell List in Digital Design Kit

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 VLSI Design
Methodologies

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VLSI Design Methodologies

Full Custom Design

Semi Custom Design

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Full Custom Design

Specifications

W & L Calculations
(fix W & L values)

Layout

Physical Verification

Parasitic Extraction

Post Layout Simulation TapeOut

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Full Custom Design

Entire Chip Designed at transistor level with no

standard cells.

Very high development cost.

Small die area, less power consumption, high speed.

Suitable for large volume productions.

Used only if the ASIC technology is new or if there are no
existing cells.

Even non-conventional circuit shapes are possible to save
space on the chip.

It is a slow process.

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Full Custom Design

Full custom design entails the complete design of the

circuit.

All cells, circuit elements etc. are designed right from
scratch.

Time taking approach.

Error prone.

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 Semi Custom Design

RTL

Functional Verification

Synthesis (target to ASIC library)

Pre-Layout Verification

Layout

Physical Verification

Parasitic Extraction

Post-Layout Verification

TapeOut

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Semi Custom Design

Part of the design is already done. Other part of the

design is done by the designers.

Results in the reuse of designs.

Expert designers can focus their attention on the
designs that can be reused.

Because of interfaces, certain disciplines are to be
maintained by the designers of the libraries.

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Semi Custom Design

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Semi Custom Design

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Semi Custom Design

The basic logic gate designs are available as library.

Circuits are then designed, wherein these elements are placed

at various places and appropriate terminals are connected.

Requirement is only to do the placement and routing of the cells

present in the library.

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Semi Custom Design

Advantages

Saves time. Only placement and routing needed.

Cells are well tested by the cell library provider

(typically a design house within the foundry).

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Full Custom Vs Semi Custom

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 Mentor Graphic Tool
Flow

CoreEl confidential
HEP Categories

• IC Nanometer Design Flow  HEP1

• Design, Verification and Test  HEP2

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Introduction to Mentor Tools of HEP
Category-1

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HEP -1

HEP Category 1

Advance Design IC-Station / Calibre

MS Architect-IC
Pyxis Assemble

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 DLA Flow

Back End Device Level Automation Flow

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Physical Design Flow Subtasks

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Physical Design—Inputs and Outputs

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 Process File
Process file contains:

Layer definitions

Layer name aliases

Layer appearance

Layer spacing

Minimum path widths

Device generation design rules

Process parameters
– Routing levels
– Port styles
– Etc.

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 Rule File

Rule File provides design rule and connectivity data for cells

All elements one of two categories:

Operations—work on the layout data

Statements—prepare the environment for the operations

Rule Files contain four data types:

Design rule data—specifies physical design rules and design
rule checks

Connectivity data—specifies layers connected electrically

Parasitic data—provides the proportionality constants used to
determine the capacitance and resistance effects on a layer

Device data—specifies object combinations on various layers
that create devices; for example, a CMOS transistor or a
capacitor

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 Sample Rule File

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Category 1 Tool Combination

HEP Category 1

Eldo Advance Design IC -Station

Calibre
d MS Architect-IC

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 Physical Design

CoreEl confidential
CMOS Inverter
N Well VDD

VDD PMOS

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

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 Physical
Verification

CoreEl confidential
Physical Verification : DRC & LVS

DRC : Design Rule Checking

Inputs
Layout -- GDSII, OASIS, etc.
Rule File

Outputs
DRC Results
Report

LVS : Layout Versus Schematic

Inputs
Layout -- GDSII, OASIS, etc.
Logic (for LVS) i.e SPICE or Verilog
Rule File

Outputs
LVS Results
Report

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Calibre DRC (Design Rule Checking)

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DRC Errors
oxide
poly

Internal Internal: Width

Width:
INT oxide <=3

Overlap:
INT Oxide poly <=3

External External

EXT oxide <=2

EXT oxide poly <= 2

Internal: Overlap

Enclosure
ENC poly oxide < 2
Enclosure

Extension
ENC oxide poly < 2
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Calibre LVS (Layout vs. Schematic)

Extraction: The software program takes a database file containing all

the layers drawn to represent the circuit during layout.

Reduction: During reduction the software combines the extracted
components into series and parallel combinations

Comparison: The extracted layout netlist is then compared to the
netlist taken from the circuit schematic

Connectivity Device Schematic HDL

Extraction Extraction Compilation Compilation

COMPARISON
PHASE

LAYOUT NETLIST VERIFICATION SOURCE NETLIST

RESULTS
EXTRACTION PHASE

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 CG-CoreEl

Thank You

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