Module-1 Part 1 Assemblers

MACHINE ARCHITECTURE SYSTEM SOFTWARE
Module 1
Part-1
MACHINE ARCHITECTURE
Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 1

Chapter 1
Introduction
The subject introduces the design and implementation of system software. Software is set of
instructions or programs written to carry out certain task on digital computers. It is classified into
system software and application software. System software consists of a variety of programs that
support the operation of a computer. Application software focuses on an application or problem to
be solved. Examples for system software are Operating system, compiler, assembler, macro
processor, loader or linker, debugger, text editor, database management systems (some of them)
and, software engineering tools. These software’s make it possible for the user to focus on an
application or other problem to be solved, without needing to know the details of how the machine
works internally.
System Software & Machine Architecture

One characteristic in which most system software differs from application software is machine
dependency. (Machine Dependent).
There are aspects of system software that do not directly depend upon the type of computing system
(Machine Independent).
Machine Dependent
• System software – support operation and use of computer
• Application software - solution to a problem
• Assembler translate mnemonic instructions into machine code
• Compilers must generate machine language code
Machine Independent
• There are aspects of system software that do not directly depend upon the type of
computing system
• general design and logic of an assembler
• general design and logic of a compiler
• code optimization techniques
Definition
System software consists of a variety of programs that support the operation of a computer.
One characteristic in which most system software differ from application software is
machine dependency.

The differences between application software and system software
SL No Application software System software

1. Not machine dependency Machine dependency
2. Focuses on an application or problem to be solved Support the operation of a computer
3. Not direct concerned with the architecture Related to the architecture of the machine
4. Examples for Application software are M.S.Word, Examples for system software are
spreadsheets etc, Operating system, compiler, assembler,
macro processor, loader or linker,
debugger, text editor, database
management systems
The Simplified Instructional Computer (SIC)

SIC is a hypothetical computer that includes the hardware features most often found on real machines.
There are two versions of SIC,
they are,
1. Standard model (SIC)
2. XE version (SIC/XE extra equipment or extra expensive)
SIC Machine Architecture

We discuss here the SIC machine architecture with respect to its Memory and Registers, Data Formats,
Instruction Formats, Addressing Modes, Instruction Set, Input and Output.
l Memory
» Consists of 8-bit bytes.
» Any 3 consecutive bytes form a word. ( 1 WORD = 3 bytes = 24 bits)
» 215 bytes in the computer memory
» 32,768 bytes (total memory in SIC machine)
» Uses Little Endian
2. Registers There are five registers, all of which have special uses. Each register is 24 bits in length.
The following table indicates the mnemonics, numbers and use of these registers.
Mnemonic Number Special Use

A 0 Accumulator: Used for arithmetic purpose
X 1 Indexed Register: Used for indexing
L 2 Linkage Register: Jump to subroutine (JSUB) instruction stores the
return address in this register
PC 8 Program counter: Contains the address of the next instruction to be
fetched for execution
SW 9 Status Word: Contains a variety of information, including a condition
code (CC)

3. Data Formats
a. Integers are stored as 24-bit binary numbers.
b. 2’s complement representation is used for negative values.
c. No floating-point hardware on the standard version of SIC.
d. Characters are stored using 8 bit ASCII codes.
4. Instruction Formats
All machine instructions on the standard version of SIC have the 24-bit format as shown below.
Opcode (8) X (1) Address (15)
Example: LDA FIVE

Code stored address part
in 8 bits
X is known as flag bit and used to indicate indexed addressing mode
5. Addressing Modes
Supports only 2 addressing modes, which are as shown in the below table. Parentheses are
used to indicate the contents of a register or a memory location.
Mode Indication Target Address Calculation

Direct X=0 TA = Address
Indexed X=1 TA = Address + (X)
Example: Direct addressing mode

LDA FIVE
OPCODE X ADDRESS
0000 0000 0 001 0000 0000 0000
Opcode (LDA) = 00 = 0000 0000

Effective address (EA) = 1000
Content of the address 1000 is loaded to Accumulator.
Example: Indexed addressing mode
STCH BUFFER, X
OPCODE X ADDRESS
0000 0000 1 001 0000 0000 0000
Opcode (STCH) = 54 = 0101 0100

Effective address (EA) = 1000 + [X]
= 1000 + content of the index register X
The Accumulator content, the character is loaded to the effective address.

6. Instruction Set
SIC provides a basic set of instructions that are sufficient for most simple task. These include
instructions that
a. Load and store registers: LDA, LDX, STA, STX, etc.
b. Integer arithmetic operations: ADD, SUB, MUL, DIV, etc.
i. All arithmetic operations involve register A and a word in memory, with the result
being left in the register
c. comparison: COMP
i. COMP compares the value in register A with a word in memory, this instruction
sets a condition code CC to indicate the result
d. conditional jump instructions: JLT, JEQ, JGT
i. these instructions test the setting of CC and jump accordingly
e. subroutine linkage: JSUB, RSUB
– JSUB jumps to the subroutine, placing the return address in register L
– RSUB returns by jumping to the address contained in register L
– J addr jumps to specified location.
–
7 Input and Output
a. Input and output are performed by transferring 1 byte at a time to or from the rightmost 8
bits of register A (accumulator).
b. Each device is assigned a unique 8 bit code.
c. The Test Device (TD) instruction tests whether the addressed device is ready to send or
receive a byte of data.
d. Read Data (RD) is used for reading data.
e. Write Data (WD) is used writing the data.
Data movement: All uses 3-byte word 3-byte word: LDA, STA, LDL, STL, LDX, STX
A- Accumulator, L – Linkage Register, X – Index Register
LDCH, STCH associated with characters uses 1-byte.
There are no memory-memory move instructions.
Storage definition
– WORD, RESW,BYTE, RESB
WORD - ONE-WORD CONSTANT
RESW - ONE-WORD VARIABLE
BYTE - ONE-BYTE CONSTANT
RESB - ONE-BYTE VARIABLE
Arithmetic
Arithmetic operations are performed using register A, with the result being left in register A
Looping (TIX)
a. (X)=(X)+1
b. compare with operand
c. set CC

Special symbols (SIC & SIC/XE)

# Immediate addressing
@ Indirect addressing
+ Format 4
* Current value of PC
C’ ’ Character string
OP m, x x denotes the index addressing
SIC Programming Examples
Example Program 1 (SIC)

LDA FIVE LOAD CONSTANT 5 INTO REGISTER A
STA ALPHA STORE IN ALPHA
LDCH CHARZ LOAD CHARACTER ‘Z’ INTO REGISTER A
STCH C1 STORE IN CHARACTER VARIABLE C1
.
.
.
ALPHA RESW 1 ONE-WORD VARIABLE
FIVE WORD 5 ONE-WORD CONSTANT
CHARZ BYTE C’Z’ ONE-BYTE CONSTANT
C1 RESB 1 ONE-BYTE VARIABLE
(a)
LDA #5 LOAD CONSTANT 5 INTO REGISTER A

STA ALPHA STORE IN ALPHA
LDA #90 LOAD ASCII CODE FOR ‘Z’ INTO REG A
STCH C1 STORE IN CHARACTER VARIABLE C1
.
.
.
C1 RESB 1 ONE-BYTE VARIABLE
(b)
Sample data movement operations for (a) SIC and (b) SIC/XE
Example Program 2 (SIC)
All arithmetic operations are performed using register A, with the result being left in register A
LDA ALPHA LOAD ALPHA INTO REGISTER A

ADD INCR ADD THE VALUE OF INCR
SUB ONE SUBTRACT 1
STA BEETA STORE IN BETA
…….
…….
ONE WORD 1
ALPHA RESW 1
BEETA RESW 1
I NCR RESW 1

SIC/XE Machine Architecture
1.Memory
a) Consists of 8-bit bytes.
b) Any 3 consecutive bytes form a word. (1 WORD = 3 bytes = 24 bits)
c) Maximum memory available on a SIC/XE system is 1 Megabyte (220 bytes)
d) Uses Little Endian.
2. More Registers
The following additional registers are provided by SIC/XE.
Mnemonic Number Special Use

B 3 Base Register: Used for addressing
S 4 General Working Register
T 5 General Working Register
F 6 Floating – point Accumulator (48 Bits)
3.Data Formats
a. Integers are stored as 24-bit binary numbers;
b. 2’s complement representation is used for negative values
c. Characters are stored using 8 bit ASCII codes.
d. Supports floating point data apart from integers.
There is a 48-bit floating-point data type

» Floating-point data type: frac*2(exp-1024)
– frac: 0~1( the fraction is interpreted as a value between 0 and 1)
– exp: 0~2047 ( the exponent is interpreted as an unsigned binary number between 0
to 2047)
S(1) Exponent (11) Fraction (36)
The sign of the floating point number is indicated by the value of s =0 positive,s=1 negative. A value of
zero is represented by setting all bits (including sign, exponent, and fraction) to 0.
4. Instruction Formats
The large memory available on SIC/XE means that an address will no longer fit into 15-bit
field , thus the instruction format used on the standard version is no longer suitable. There are two
possible options- either use some form of relative addressing, or extend the address field to 20 bits.
The new set of instruction formats for SIC/XE machine architecture is as follows.

i). Format 1 (1 byte): Contains only operation code (straight from table).
Format – 1 (one byte instruction contains only Opcode)
OPCODE (8 bits)
0100 1100
Eg: RSUB (return to subroutine) 4 C
Format 2 (2 bytes):
ii). Format-2 (two byte instruction format)

This instruction uses 2 registers.
OPCODE (8 bits) r1(4 bits) r2 (4 bits)
Eg: ADDR r1 r2 (add the contents of r2 to r1 and store in r1)
OPCODE (8 bits) r1(4 bits) r2 (4 bits)

ADDR A S
1001 0000 0000 0100
In format-2 the First eight bits for operation code, next four for register 1 and following four for
register 2. The numbers for the registers go according to the numbers indicated at the registers
section (ie, register A is replaced by hex 0, S is replaced by hex 4).
Formats 1 and 2 are instructions do not reference memory at all.
Format 3 (3 bytes):
iii) Format-3 (three byte instruction format)
Format 3 e=0
op(6) n I x b p e disp(12)
Example :
LDA #3 (Load 3 to Accumlator A)
Opcode(6 bits) n (1) i(1) x(1) b(1) p(1) e(1) Disp (12 bits)
0000 00 0 1 0 0 0 0 0000 0000 0011
0 1 0 0 0 3 object code
In format-3 the First 6 bits contain operation code, next 6 bits contain flags, last 12 bits contain
displacement for the address of the operand. Operation code uses only 6 bits, thus the second hex
digit will be affected by the values of the first two flags (n and i). The flags, in order, are: n, i, x, b,
p, and e. The last flag e indicates the instruction format (0 for 3 and 1 for 4).

Format 4 (4 bytes): same as format 3 with an extra 2 hex digits (8 bits) for addresses that require
more than 12 bits to be represented.
Format 4 e=1
op(6) n I x b p e address (20)
Example : +JSUB RDREC (Jump to the address,1036(assume))
Opcode (6 bits) n (1) i(1) x(1) b(1) p(1) e(1) Address (20 bits)
0100 10 1 1 0 0 0 1 0000 0001 0000 0011 0110
4 B 1 0 1 0 3 6
• e  e = 0 means format 3, e = 1 means format 4

• Bits x, b, p: Used to calculate the target address using relative, direct, and indexed addressing
Modes
• Bits i and n: Says, how to use the target address
5. Addressing Modes
Two new relative addressing modes are available for the use with instructions assembled using format 3.
These are described in the following table.
Mode Indication Target Address Calculation

Base Relative b = 1, p = 0 TA = (B) + Disp ( 0 <= Disp <= 4095
Program Counter Relative b = 0, p = 1 TA = (PC) + Disp ( -2048 <= Disp <= 2047
Direct b = 0, p = 0 TA = Disp (format 3) or address (format 4)
Indexed X=1 TA = TA + (X)
Base relative addressing mode: For Base relative addressing, the displacement field in a format 3
instruction is interpreted as a 12-bit unsigned integer.
Example: STX LENGTH
Opcode (6 bits) n (1) i(1) x(1) b(1) p(1) e(1) Disp (12 bits)
0001 00 1 1 0 1 0 0 0000 0000 0000
1 3 4 0 0 0 object code
EA= LENGTH= 0033 EA = Disp + [B]

[B]= 0033 Disp = EA – [B] = 0033 – 0033
Disp = 0
The content of the address 0033 is loaded to the index register X.

Program counter relative addressing mode :For program counter relative addressing, the
displacement field is interpreted as a 12-bit unsigned integer, with negative values represented in 2’s
complement notation.
Example: STL RETADR
Opcode (6 bits) n (1) i(1) x(1) b(1) p(1) e(1) Disp (12 bits)
0001 01 1 1 0 0 1 0 0000 0010 1101
1 7 2 0 2 D object code
EA= RETADR = 0030

[PC]= 0003 (Address of the next instruction ) EA = Disp + [PC]
Disp = 002D Disp = EA – [PC] = 0030 – 0003 = 002D
Linkage register contains the content of RETADR 0030
Direct (x, b, and p all set to 0): operand address goes as it is. n and i are both set to the same value, either
0 or 1. While in general that value is 1, if set to 0 for format 3 we can assume that the rest of the flags (x,
b, p, and e) are used as a part of the address of the operand, to make the format compatible to the SIC
format.
Immediate (i = 1, n = 0): The operand value is already enclosed on the instruction (ie. lies on the last
12/20 bits of the instruction)
Indirect (i = 0, n = 1): The operand value points to an address that holds the address for the operand
value.
Indexed (x = 1): value to be added to the value stored at the register x to obtain real address of the
operand. This can be combined with any of the previous modes except immediate.
The various flag bits used in the above formats have the following meanings
e - e = 0 means format 3, e = 1 means format 4
Bits x,b,p: Used to calculate the target address using relative, direct, and indexed addressing Modes
Bits i and n: Says, how to use the target address
b and p - both set to 0, disp field from format 3 instruction is taken to be the target address. For a format
4 bits b and p are normally set to 0, 20 bit address is the target address
x - x is set to 1, X register value is added for target address calculation

i=1, n=0 Immediate addressing, TA: TA is used as the operand value, no memory reference
i=0, n=1 Indirect addressing, ((TA)): The word at the TA is fetched. Value of TA is taken as the address
of the operand value

i=0, n=0 or i=1, n=1 Simple addressing, (TA):TA is taken as the address of the operand value
Two new relative addressing modes are available for use with instructions assembled using format
How the target address is used?
Mode Indication Operand Value

Immediate Addressing i = 1, n = 0 TA
Indirect Addressing i = 0, n = 1 (TA)
Simple Addressing i = 0, n = 0 SIC instruction (All end with 00)
i = 1, n = 1 SIC/XE instruction
Note: Indexing cannot be used with immediate or indirect addressing modes.
Addressing modes examples
SL. Addressing modes Example Explanation

No
1 Implied RSUB PC  (L) returns by jumping to the address contained
in register L
2 Direct LDA ALPHA A  (ALPHA) TA = address
3 Register ADDR r1,r2 r2 (r1) + (r2)
DIVR r1,r2 r2 (r2) / (r1)
4 Indirect JSUB @RETADR The content of memory location RETADR contains
the address where the jump will be made.
The content of memory location 050 contains the
ADD @050 address. This address contains the data which is added
to Accumulator
5 Immediate LDA #20 A  20
TA is the operand value. No memory reference
6 Indexed LDA ALPHA,X A  [ ALPHA + X ]
7 Program counter LDA ALPHA TA = addr + [PC]
relative
8 Base relative LDA ALPHA TA = addr + [B]

Q) The following figure shows contents of registers B, PC, and X along with the memory locations. What
will happen if the following program is executed? Show the target address calculation along with content
of register A.
Convert every HEX digit to 4 bit binay

1. 032600 -----> PC relative addressing mode
Target address = disp + (PC)
600 + 3000 = 3600.
2. 03C300 -----> Index and Base relative

Target address = (disp + X) + [B]
3100 + 000090 + 006000 = 006390

3. 0022030 ------> Indirect and PC relative

= 30 + 003000
= 003030
since n = 1(indirect addressing mode)
Target address = 103000
4. 0100300 -----> Immediate addressing mode

Target address = 030
5. 003600 ----> PC relative and extended mode

600 + 003000 = 003600
6. 0310C303 ------> extended format (e=1)
Target address = address

= 0C303
6. Instruction Set
SIC/XE provides all of the instructions that are available on the standard version. In addition we have,
a. An instruction to load and store the new registers LDB, STB, etc.
b. floating-point arithmetic operations : ADDF, SUBF, MULF, DIVF
c. register move instruction : RMO
d. register-register arithmetic operations : ADDR, SUBR, MULR, DIVR
e. supervisor call: SVC
i. generates an interrupt for OS
7. Input/output
a. There are I/O channels that can be used to perform input and output while the CPU is
executing other instructions.
b. Allows overlap of computing and I/O, resulting in more efficient system operation
c. The instructions SIO, TIO, and HIO are used to start, test and halt the operation of I/O
channels.
8. data movement
» immediate addressing for SIC/XE
9. Looping (TIXR)
» (X)=(X)+1
» compare with register specified
» set CC

Example Program 1A
Write a sequence of instruction for SIC to compute BETA=(ALPHA + INCR -1) and
DELTA = (GAMMA + INCR -1)
COMPUTE START 1000
FIRST LDA ALPHA LOAD ALPHA INTO REGISTER A

SUB ONE SUBTRACT 1
STA BETA STORE IN BETA
LDA GAMMA LOAD GAMMA INTO REGISTER A
SUB ONE SUBTRACT 1
STA DELTA STORE IN DELTA
ONE WORD 1 ONE-WORD CONSTANT

BETA RESW 1 ONE-WORD VARIABLE
GAMMA RESW 1 ONE- WORD VARIABLE
DELTA RESW 1 ONE- WORD VARIABLE
INCR RESW 1 ONE- WORD VARIABLE
END FIRST
Example Program 1B
Write a sequence of instruction for SIC –XE to compute BETA=(ALPHA + INCR -1) and
DELTA = (GAMMA + INCR -1)
COMPUTE START 1000
FIRST LDS INCR LOAD THE VALUE OF INCR INTO REGISTER S

LDA ALPHA LOAD ALPHA INTO REGISTER A
ADD S,A ADD THE VALUE OF INCR
SUB #1 SUBTRACT 1
STA BETA STORE IN BETA
LDA GAMMA LOAD GAMMA INTO REGISTER A
ADD S,A ADD THE VALUE OF INCR.
SUB #1 SUBTRACT 1
STA DELTA STORE IN DELTA

BETA RESW 1 ONE-WORD VARIABLE
GAMMA RESW 1 ONE- WORD VARIABLE
DELTA RESW 1 ONE- WORD VARIABLE
INCR RESW 1 ONE- WORD VARIABLE
END FIRST

Example 2A: Write a sic program to copy a string consisting of 11 characters from the memory location
str1 to str2
COPY START 1000
LDX ZERO INITIALIZE INDEX REGISTER TO 0

MOVECH LDCH STR1, X LOAD CHARACTER FROM STRI INTO REG A
STCH STR2, X STORE CHARACTER INTO STR2
TIX ELEVEN ADD 1 TO INDEX, COMPARE RESULT TO 11
JLT MOVECH LOOP IF INDEX IS LESS THAN 11
STR1 BYTE C’ ENGINEERING’ 11-BYTE STRING CONSTANT

STR2 RESB 11 11- BYTE VARIABLE
ZERO WORD 0 0NE-WORD CONSTANT
ELEVEN WORD 11
END COPY
Example 2B:
Write a SIC-XE program to copy a string consisting of 11 characters from the memory location str1 to
str2.
COPY START 1000
LDT #11 INITIALIAZE REGISTER T TO 11

LDX #0 INITIALIZE INDEX REGISTER TO 0
MOVECH LDCH STR1, X LOAD CHARACTER FROM STRI INTO REG A
STCH STR2, X STORE CHARACTER INTO STR2
TIXR T ADD 1 TO INDEX, COMPARE RESULT TO 11
STR1 BYTE C’ ENGINEERING’ 11-BYTE STRING CONSTANT

STR2 RESB 11 11- BYTE VARIABLE
END COPY
Example 3A:
Write a sequence of instruction for SIC to clear a 20 byte string to all blanks.
CLEAR START 1000
LDX ZERO INITIALIZE INDEX REGISTER TO 0

MOVECH LDCH BLANK LOAD CHARACTER FROM BLANK INTO REG A
STCH STR , X STORE CHARACTER INTO STR
TIX LENGTH ADD 1 TO INDEX, COMPARE RESULT TO 20
RSUB
STR BYTE C’ ABCDEFGHIJKLMNOPQRST’ 20-BYTE STRING CONSTANT
BLANK BYTE C ‘ ‘
LENGTH WORD 20
END CLEAR

Example 3B: Write a sequence of instruction for SIC-XE to clear a 20 byte string to all blanks.
CLEAR START 1000
LDX #0 INITIALIZE INDEX REGISTER TO 0

LDB #20
MOVECH LDCH #C‘‘ LOAD CHARACTER FROM BLANK INTO REG A
STCH STR, X STORE CHARACTER INTO STR
TIXR B ADD 1 TO REG B, COMPARE RESULT TO 20
STR BYTE C’ ABCDEFGHIJKLMNOPQRST’ 20-BYTE STRING CONSTANT

BLANK BYTE C ‘ ‘
END CLEAR
Example 4A:
The variable ALPHA, BETA and GAMMA are arrays of 100 words each. Write an SIC program to add
corresponding elements of ALPHA and BETA and store the result in GAMMA.
SUMAB START 1000
LDA ZERO INITIALIZE INDEX REGISTER TO 0

STA INDEX
LDX INDEX LOAD INDEX VALUE INTO REG X
ADDAB LDA ALPHA, X LOAD WORD FROM ALPHA INTO REG A
ADD BETA, X ADD WORD FROM BETA
STA GAMMA, X STORE THE RESULT IN A WORD IN GAMMA
LDA INDEX ADD 3 TO INDEX VALUE
ADD THREE
STA INDEX
COMP K300 COMPARE NEW INDEX VALUE TO 300
JLT ADDAB LOOP IF INDEX IS LESS THAN 300
INDEX RESW 1
ALPHA RESW 100 ARRAY VARIABLES – 100 WORDS EACH
BETA RESW 100
GAMMA RESW 100
K300 WORD 300
THREE WORD 3
END SUMAB

Example 4B:
The variable ALPHA, BETA and GAMMA are arrays of 100 words each. Write an SIC-XE program to
add corresponding elements of ALPHA and BETA and store the result in GAMMA.
SUMAB START 1000
LDS #3 INITIALIZE INDEX REGISTER TO 0

LDT #300
LDX #0 LOAD INDEX VALUE INTO REG X
ADDAB LDA ALPHA, X LOAD WORD FROM ALPHA INTO REG A
ADD BETA, X ADD WORD FROM BETA
STA GAMMA, X STORE THE RESULT IN A WORD IN GAMMA
ADDR S, X ADD 3 TO INDEX VALUE
COMPR X, T COMPARE NEW INDEX VALUE TO 300
JLT ADDAB LOOP IF INDEX IS LESS THAN 300
ALPHA RESW 100 ARRAY VARIABLES – 100 WORDS EACH

BETA RESW 100
GAMMA RESW 100
END SUMAB
Example 5:
Write a sequence of instruction for SIC/XE to divide BETA by GAMMA setting ALPHA to integer
portion of result and DELTA to remainder. Use register to register instruction to make calculations as
efficient as possible.
Eg: ALPHA=BETA/GAMMA 9/4=2 and DELTA= 9-4*2=1
DIVISION START 1000
FIRST LDB GAMMA REG B CONTAINS GAMMA

LDT BETA REG T CONTAINS BETA
RMO T, X X CONTAINS BETA
DIVR B, T
STT ALPHA
MULR B, T REG T CONTAINS DR*QUOTIENT
SUBR T, X X CONTAIN REMAINDER
STX DELTA
BETA WORD 9
GAMMA WORD 4
ALPHA RESW 1
DELTA RESW 1
END FIRST

Example 6:
Write a sequence of instruction for SIC to read 1 byte of data from device F5 and copy it to device 05.
COPY START 1000
INLOOP TD INDEV : TEST INPUT DEVICE

JEQ INLOOP : LOOP UNTIL DEVICE IS READY
RD INDEV : READ ONE BYTE INTO A
STCH DATA : STORE A TO DATA
.
.
OUTLP TD OUTDEV : TEST OUTPUT DEVICE
JEQ OUTLP : LOOP UNTIL DEVICE IS READY
LDCH DATA : LOAD DATA INTO A
WD OUTDEV : WRITE A TO OUTPUT DEVICE
.
INDEV BYTE X ‘F5’ : INPUT DEVICE NUMBER
OUTDEV BYTE X ‘05’ : OUTPUT DEVICE NUMBER
DATA RESB 1 : ONE-BYTE VARIABLE
END COPY
Example 7:
Write a sequence of instruction for SIC to transfer two hundred bytes of data from input device to
memory.
TRANSFER START 1000
LDX ZERO
CLOOP TD INDEV
JEQ CLOOP
RD INDEV
To transfer
two hundred bytes
of data from input
device to memory
STCH RECORD, X
TIX B200
JLT CLOOP
INDEV BYTE X ‘F5’

RECORD RESB 200
ZERO WORD 0
B200 WORD 200
END TRANSFER

Example 8:
Write a sequence of instruction for SIC-XE to transfer two hundred bytes of data from input device to
memory.
TRANSFER START 1000
LDT #200
LDX #0
CLOOP TD INDEV
JEQ CLOOP
RD INDEV To transfer
two hundred bytes
of data from input
device to memory
STCH RECORD, X
TIXR T
JLT CLOOP

RECORD RESB 200
END TRANSFER
Example 9:
Write a subroutine for SIC to transfer two hundred bytes of data from input device to memory.
JSUB READ
.
.
READ LDX ZERO
CLOOP TD INDEV
JEQ CLOOP
RD INDEV
STCH RECORD, X
Subroutine to transfer
two hundred bytes of
data from input device
to memory
TIX B200 : add 1 to index compare 200 (B200)
JLT CLOOP
RSUB
.
RECORD RESB 200
ZERO WORD 0
B200 WORD 200

Example 9:
Write a subroutine for SIC-XE to transfer two hundred bytes of data from input device to memory.
JSUB READ
.
.
READ LDT #200
LDX #0
CLOOP TD INDEV
JEQ CLOOP
RD INDEV
STCH RECORD, X
TIXR T : add 1 to index compare T
Subroutine to transfer
two hundred bytes of
data from input device
to memory
JLT CLOOP
RSUB
.
.
RECORD RESB 200
Example 10A:
Alpha is an array of 100 words. Write a sequence of instruction for SIC to set all hundred elements of the
array to 0(zero).
SETALL START 1000
BEGIN LDX ZERO

STX INDEX
BACK LDA ZERO
STA ALPHA, X
LDA INDEX
ADD THREE
STA INDEX
LDX INDEX
COMP THUND
JLT BACK
RSUB
ALPHA WORD 10,20,30………
ZERO WORD 0
THUND WORD 300
THREE WORD 3
INDEX RESW 1
END BEGIN

Example 10B:
Alpha is an array of 100 words. Write a sequence of instruction for SIC-XE to set all hundred elements of
the array to 0(zero).
SETALL START 1000
BEGIN LDX #0
LDA #0
LDT #3
LDB #300
BACK STA ALPHA, X

ADDR T, X
COMP X, B
JLT BACK
RSUB
ALPHA WORD 10,20,30………
ZERO WORD 0
THUND WORD 300
THREE WORD 3
INDEX RESW 1
END BEGIN
Example 11:
Write a subroutine for SIC that will read a record into a buffer. The record may be any length from 1 to
100 bytes. The end of record is marked with null character (ASCII CODE 0 ). Subroutine should place the
length of the record read into a variable named length.
Solution
for i = 0 to 99
LENGTH START 1000 ch = getch()
if ( ch = =0)
RDREC LDX ZERO Break
LDA ZREO
BACK TD INPUT
Buff[i] = ch
JEQ BACK end for
RD INPUT Length=i
COMP ZERO
JEQ EXIT
STCH BUFFER, X
TIX HUND
JLT BACK
EXIT STX LENGTH
RSUB
INPUT BYTE X ’F1’

ZERO WORD 0
HUND WORD 100
LENGTH RESW 1
BUFFER RESB 100
END LENGTH

Questions
1. Why do we require system software? List atleast four system software and mention how it is used?
2. List all instruction in SIC m/c which affects condition code. Give examples and explain.
3. Explain different instruction formats used in SIC/XE machine.
4. List all instruction that are not available in SIC machine but available in SIC/XE machine.
5. Write a program for SIC m/c with comments to access data from input device. Assume the port
address to be FH. Read 20 data and save it in memory.
6. Write a sequence of instructions for SIC to clear a 20-byte string to all blanks.
7. Suppose that ALPHA is an array of 100 words. Write a sequence of instruction for SIC to set all
100 elements to zero.
8. Suppose that ALPHA is an array of 100 words. Write a sequence of instruction for SIC/XE to
arrange the 100 words in ascending order and store result in an array BETA of 100 words.
9. Suppose that ALPHA is an array of 100 words. Write a sequence of instruction for SIC/XE to find
the maximum element in the array and store results in MAX.
****************************************************

Module-1 Part 1 Assemblers

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Module-1 Part 1 Assemblers

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MACHINE ARCHITECTURE SYSTEM SOFTWARE

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 1

System Software & Machine Architecture

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 2

The differences between application software and system software

SL No Application software System software

The Simplified Instructional Computer (SIC)

SIC Machine Architecture

Mnemonic Number Special Use

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 3

Opcode (8) X (1) Address (15)

Example: LDA FIVE

Mode Indication Target Address Calculation

Example: Direct addressing mode

Opcode (LDA) = 00 = 0000 0000

Example: Indexed addressing mode

Opcode (STCH) = 54 = 0101 0100

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 4

7 Input and Output

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 5

Special symbols (SIC & SIC/XE)

SIC Programming Examples

Example Program 1 (SIC)

LDA #5 LOAD CONSTANT 5 INTO REGISTER A

Example Program 2 (SIC)

LDA ALPHA LOAD ALPHA INTO REGISTER A

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 6

SIC/XE Machine Architecture

The following additional registers are provided by SIC/XE.

Mnemonic Number Special Use

There is a 48-bit floating-point data type

S(1) Exponent (11) Fraction (36)

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 7

Format – 1 (one byte instruction contains only Opcode)

ii). Format-2 (two byte instruction format)

OPCODE (8 bits) r1(4 bits) r2 (4 bits)

Eg: ADDR r1 r2 (add the contents of r2 to r1 and store in r1)

OPCODE (8 bits) r1(4 bits) r2 (4 bits)

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 8

Example : +JSUB RDREC (Jump to the address,1036(assume))

• e  e = 0 means format 3, e = 1 means format 4

Mode Indication Target Address Calculation

Example: STX LENGTH

EA= LENGTH= 0033 EA = Disp + [B]

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 9

Example: STL RETADR

EA= RETADR = 0030

Linkage register contains the content of RETADR 0030

e - e = 0 means format 3, e = 1 means format 4

Bits i and n: Says, how to use the target address

x - x is set to 1, X register value is added for target address calculation

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 10

How the target address is used?

Mode Indication Operand Value

Note: Indexing cannot be used with immediate or indirect addressing modes.

Addressing modes examples

SL. Addressing modes Example Explanation

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 11

Convert every HEX digit to 4 bit binay

2. 03C300 -----> Index and Base relative

Dr. C.K. SRINIVAS. Professor. DEPT OF CS&E, BITM, BALLARI 12

3. 0022030 ------> Indirect and PC relative

4. 0100300 -----> Immediate addressing mode

5. 003600 ----> PC relative and extended mode