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SALEM COLLEGE
OF ENGINEERING AND TECHNOLOGY
B.E/B.Tech. DEGREE EXAMINATION-APR/MAY 2024
INTERNAL ASSESSMENT TEST-II
DEPARTMENT OF BIOMEDICAL ENGINEERING
BM3402-ANALOG AND DIGITAL INTEGRATED CIRCUITS Year/Sem: II/IV
Date:10.06.2024 Time:3 hours Maximum:100 marks
Answer All the Questions
PART –A (10x2=20Marks)
Q.No Question CO PO BTL

1 Interpret the given expression in canonical SOP form Y=AB+AIC+BCI 3 1

2 Convert the following binary code into a gray code: 10101110002 3 2
3 Construct half adder and full adder circuit. (Apr/May 2023) 4 2

4 Evaluate logic circuit of 2 bit comparator. (Apr/May 2023) 4 2

5 What is a multiplexer? (Nov/Dec 2022) 4 1

6 What is meant by decoder circuit? (Apr/May 2019) 4 1

7 Distinguish sequential logic with combinational logic. (Apr/May 2023) 5 2

8 Give the excitation table of JK flip flop. (Apr/May 2023) 5 2

9 Define a latch and flip flop. (Nov/Dec 2022) 5 1

10 Define race around condition in flip flop. (Nov/Dec 2016) 5 2
Answer All The Questions
PART--B-(5X13=65 Marks)
Q.No Question CO PO BTL
11.a) What is a K-map? Simplify the Boolean function
F(w,x,y,z)=∑(0,1,3,10,12,13,14) + ∑d (2,5,6,11) using k-map. (Nov/Dec 3
2022) (13)
(OR)
11.b) (i) Convert FACE16 into its binary, octal and decimal equivalent. (7) 3
(ii) Write the comparison of logic families. (6) 3
12.a) With a neat diagram explain in detail about the concept and working
4
principle of a carry look ahead adder circuit. (Nov/Dec 2019) (13)
(OR)
 (i) Build a 4 bit priority encoder using gates. (Apr/May 2023) (7)
12.b)
(ii) Design BCD to Excess-3 code converter. (6)
Design a 4 bit BCD adder using full adder and explain its structure and
13.a) compute the circuit to add 1001 and 0101. Write the sum and carry output
of the given binary number. (Nov/Dec 2017) (13)
(OR)
(i) Construct 8-to-3 line encoder circuit and explain its functions with logic
13.b) circuit. (7)
(ii) Explain with neat sketch about the binary parallel adder circuit. (6)
Explain the functions with the state table diagram and characteristic
14.a)
equation of T, D and JK flip flop. (Apr/May 2023) (13)
(OR)
(i) Explain the operation of JK master slave flip flop. (6)
14.b) (ii) Explain the state minimization using portioning procedure with a
suitable example. (7)
What is a shift register? Outline the design of a four bit shift register with a
15.a)
diagram. (Nov/Dec 2022) (13)
(OR)
(i) Realize D flip flop using SR flip flop. (Apr/May 2023) (7)
15.b)
(ii) Construct a 4 bit down counter using logic gates. (Apr/May 2023) (6)
Answer All The Questions
PART--C-(1X15=15 Marks)
Q.No Question CO PO BTL
Simplify the following Boolean function by using the Quine-McCluskey
16.a) 3
method. F(A,B,C,D)= ∑m(0,2,3,6,7,8,10,12,13). (15)
(OR)
(i) Explain about the Boolean postulates and laws briefly. (7)
16.b) 3
(ii) Explain about the basic and universal logic gates with neat diagrams. (8)
BTL:1-Remembering,2-Understanding,3-Applying,4-Analyzing,5-Evaluating,6Creating

SUBJECT INCHARGE HOD PRINCIPAL