PHYSICAL DESIGN FLOW

Projects Info:
Row to row: 0.48 track to track (pitch): 0.080 offset:0.040 M6 Layer width= 0.440

Scorpio Freq: 1415mhz (TP:706ps) for worst corner,

Dorado Freq: 892mhz (1.12ns) for edf_cdte, 970mhz (TP:1.03ns) for edf_bottom
Func2worstcor Freq: 1206mhz (TP:0.829ps)- edf_cdte; 1317mhz(TP:0.759ps)-edf_bottom
clocks: Main clocks are 2, except service and dft clocks
Upf voltage: VDD_DTU ON1: 0.95v, ON2: 0.72v VDD_SOC ON: 0.85v

Block size: x=1532.16 and Y =1196.16 Latency:0.570ps/1.2 target skew: 0.080ps

Synthesis: It is the process of converting RTL code to gate level netlist by meeting the Area
Optimization (Congestion, density), Power Optimization and Timing Constraints for the
targeted technology. {Synthesis = Translation(No timing)+ Opti + Mapping (Timing Info)}
Inputs:

 RTL codes (It contains the design information/module functionality)

 Number of modules, ports, Instances and their connections.
 Libraries (Lib and Lef)
 SDC file (design constraints)
 UPF and technology file (Metal & Via Info).
Notes:

 Based on the synthesis inputs, we can check the pre_timing violations and setup
timing should be clean or with lesser slack violation is acceptable and 80% of the
timing should met here only. If we get the huge violation at pre_timing, should be
resynthesize the netlist.
 Synthesis tools are capable of inserting scan chains and verifying scan drc’s, using
scan flops during synthesis is to have the accurate estimation on area, power and
timing.
 Logic synthesis is helps to minimize the size of the logic gate cell count and cell size,
helps to minimize power while switching gates and improves performance in terms
of clock and synchronous system and produce accurate results.
Type of Synthesis:

 Logical Synthesis:
 Physical Synthesis: DCG Def, effective core area, will run quick PNR
Flow:

 Read Lib and Read RTL (load tech libraries into database)
  Elaborate: (Translate RTL into Boolean structure, binds all the cells & make libraries
again)- It will compare the Std cells in the Libraries and RTL code.
 1.Build Data structure (all RTL code files > 1 file) 2. Infers reg
 3.Perform HDL optimization, such as dead code removal.
 Read SDC: (Design Rule constraints and Design Optimization Constraints)
 Select Wire load
 We have to select wire load model to get the best QOR.
 We use Zero wire load model for better area.
 Optimization: (Pre_Map_Opt – it will minimize the multi-level logics) -tries to reduce
the logic gates and make simple logic code, so it reduces iteration time.
 Post_Map_Opt: -It changes gate designs to meet constraints related to techn.
 Check Design
 Report timing Synthesis gen Synthesis map Synthesis opt

Design Setup Environment:

Before a design can be placed and routed, the environment for the design needs to be
created. The goal of the design setup stage in the physical design flow is to prepare the
design for floor planning. The first step is to create a design library. Without a design library,
the physical design process using will not work. This library contains all of the logical and
physical data that will need.
In Our projects View definition.tcl contains all the inputs details required for the pd. Without
Viewdefination.tcl, we can’t setup the flow for PD.
Inputs for PD:

.Tech file .sdc file

Tlu+

.v (netlist) PD Inputs
def

.lib .lef
Netlist (.v): Synthesized netlist consist of logical connections.

 Logical interconnections of cell, pins, ports and nets.

 Information about type of cell used and drive strength of cell used.
 Module information: it operates overall by its connection.
 Symbolic represent of cell

Cell type &

Drivestrength

and

.Lef: layout exchange format

 It is a physical library file

 It contains all the physical information of cells, macros and IO’s.
 Metal info: direction of layers(vertical/Horizental) and type of metals used and Via
Infor.
 Orientation and size information of cells (like L*W and fits in single row or 2 rows).
 Class info of cells (like whether it is cell or macro ex: AND.lef <lef extension>)
 Pin information (direction, layer, location and use <signal, power,bidirectionla>)
.Lib: Library file

 Lib is a Timing Library

 Which contains complete timing information of standard cells/macros.
 PVT conditions (process, voltage and temp): delays may vary at diff Voltage & Temp.
 Process Variation: Process variations will be occurred at fabrication stage, it
will happen due to Wavelength of the UV light and manufacturing defects.
 effects on doping concentration level, gate width and oxidation.
  Voltage Variation: Threshold voltage depends on oxide thickness. If thickness
reduced, have to change threshold voltage value from expected.
 Max Cap/Min Cap/rise time/fall time/Min delay/Max delay information of cells.
Cell Delay =input transition/output load
 Delays occurs based on the lib calculations (Lookup table).
.Tech File: Technology file

 Tech file is related to foundry

 We need to follow all the rules of foundry (TSMC) while designing chip.
 Metal scheme: (all the metal information/no.of metals used) and Via info( type of
cut[H/V] and their L*W)

Direction(H/V) Use (Routing) width offset min offset Pitch min pitch spacing min spacing

 Site Info: core row height (0.13) will be same for all the rows throughout design.
 Colour Info: every metal have diff colours to identify.
.sdc file: Synopsys design constraints

 It contains all the clock information.

Created clock generated clock virtual clock

Timing Constraints:

 Created clock: These are main clocks which are directly generated from source point
(crystal oscillator) and defined as below.
Ex: Create clock -name -Time period -waveform -source (crystal osc <master clock>)

 Generated clock: Generated clocks are frequency divider/multiplier. Means we can

reduce or increase frequency through generated clock without disturbing main
clocks. It will define at Flipflops/Mux in the design.
 When we define a generated clock, its source clock, the generation point, division
ratio and uncertainty value should be provided.
 Virtual clock: These are clocks used to time the input/output port and used for
specifying input/output delay values. These are imaginary clocks defined only with
the clock waveform and not having any source/generation point.
 Design Rule Constraints: (Max Tran/max Cap/Max Fanout)
 The maximum time taking from 0 to 1 is called max transition.
 The capacitance values should be less than specified cap value.
 Limit of the output fanouts won’t cross.
  Drive constraints: Input delay and output delay.
 Path exceptions:
 Half Cycle path: if the path completed in half cycle instead of one cycle.
 Multi Cycle Path: if the path won’t complete in single cycle and takes more
than one cycle.
 False path: Physically exist but logically/Functionally inactive path, means no
data transferred from start point to endpoint. It removes only timing
constraints.
 Asynchronous path: If the Time period of the launch clock and capture clock
are different for the same path then we considered as Asynchronous path.
 Disable path: These paths are timing less. We won’t use these paths in overall
process of circuit designs. It removes total path from timing calculation.
 Min delay/Max delay of clock path -used for Asynchronous path.
 Clock uncertainty:
 Uncertainty is a estimating margin value. Due to gitter, skew and crosstalk, time
period will affect so giving this margin won’t impact on actual time period.
 Applying uncertainty value can reduce the target time period which helps to get the
better timing.
Ex: Actual TP: 3sec
Here, Time period: 3sec -2.5sec =0.5sec is benefit

False TP: 2.5sec Which makes the timing better

.Spec file: spec file is used to give the sdc information to the tool in CTS stage. Which
contains all the clock information to build the clock tree, like NDR rules, clock time period,
latency and min skew/useful skew.

Skew groups to balance non generated clocks.

.Def: Design exchange Format
It saves the data when we stop and to continues further and it stores in .def format.
which is created while doing partitioning. which includes

 Design name: noc_top_blk304

 Property section: It provides width*Height of the block/tile (core X= 1531.2, Y=1195.)
 Design units: Die area should divide with units (*/ with 1000)
Die are (0 0) (X2= 1532.2+0.96 [0.96 means row height 0.48*2] Y2=1195.2+096)
 Core row information.
 Pin Information: it defines no.of pins were placed in our block.
 Pin name and net name should be same as defines then only data flows.
Pin Information

Pin name Net name Location Layer Direction use (Signal/power)

  Net Section: It includes net names which is connected to the particular pins.
 Special Nets information: If we use the nets for ground (VSS) and power (VDD) then
we call it as special nets.
 Blockage Information

Hard Blockage Soft Blockage Partial Blockage

 Hard blockage: It blocks all the cells to avoid placement.

 Soft blockage: It allows only Inverter/Buff and avoids complex cells. To
optimize better to achieve in time.
Complex cells: contains more pins, so needs more routing tracks/layers.
Inverter/Buff: contains 1 or 2 pins, easy for routing.
 Partial blockage: It allows limited cells (like 60%) both complex/standard cells.
Ex: createplaceblockage -type soft -loc BB -perc 40%
Tlu+:

 Complete Delay = cell delay + Net delay

 Cell delay calculated based on lib calculation i/p trans and o/p load(MT,MC
and MF) and
 Net delay calculated based on RC value extraction of metal layer
 Tlu+ is lookup table which is a binray file contains that can be used to extract RC from
interconnects.
UPF Unified power format: It is one of the inputs for multi voltage domain blocks. In which
power intent is given to the design.

 Upf consists of level shifter types, Voltage shifting levels, supply ports and supply
nets for power domains. Voltage= Soc: 0.85, DTU: 0.95 -ON1, 0.72-ON2.
 DTU domain is used for power saving and it creates one region for all the unused
cells to save power.
 Level shifters: we are using LS to shift signal from high voltage 3.5v to 2.5v vicevsa.
 If we not use the LS, then the High Voltage will damage the cell.
 Isolation cells: we place for every connections b/w SOC and DTU regions.
 Isolation cells clamp/hold the data of the cell in DTU when its power off and
then sends output to the SOC cell.
 Since Domain D1 is power off mode then it can propagate invalid logic to
domain D2.
 Isolation cells should be placed in always on domain to serve it’s functionality.
 Power Switches:
  Power switches are used in power gating technique.
 Power gating is used to reduce the static (Leakage) power in the design.
 Power gating is performed by shutting down the power for portion of design.
 Power switches are used to turn off the portions of design which are inactive at a
point of time to reduce leakage power.

Sanity checks before start PD:

 Check Netlist: netlist should be “unique”. It won’t allow same module for diff
operations and should be “no empty modules”.
 Assigned statements: once netlist finalised means there should be no assigned
statements.so we won’t create area for future purpose.
 Check design: to check the design quality. There should not be input & output
floating pins and dangling
 Input floating: no connection to the input of the cell & input floating are not
allowed.
 Dangling: cell connects to the power either VSS or VDD. Both will not
connect.
 Port mismatch: Should be no port mismatch b/w netlist (.V) & .def {Ex: ABC_1, ABC}
 Multidriven (ports/nets): Only one net should be connected for one port.
 No multiple nets can access for single port.
 No Unconstrained paths: It doesn’t transfer the data, it can only stores the data.
 Check library: have to check, missing physical information/Timing information.
For all the cells should not miss.

Partitioning: It is the process of dividing chip area to small blocks based on logic gate count.

Input Files: netlist, Lef and tech file

Type of Partitioning:

 Flot Level: It consist of only one block

 Hierarchical: Chip divides into multiple blocks.

Benefits:

 To reduce the design complexity

 To reduce the run time
 Design efficiency/accuracy will increase.

Flow:

 Importing design: It imports all the blocks netlist in design

 Block box creation: we need to give rough length*width for sub blocks based on
logic gate count and then check the initial utilization.
  Pins/ports creations: pin to pin mapping will be done with sub blocks. Should not be
illegal pins.
 Commit Floorplan: It saves the floorplan design and exports the design in .def
format in the given path (path includes all sub blocks .def)

Floor Planning: Floor planning is the process of estimating the core of the design based on
the gate count. we can check the initial utilization of the design while deciding the floorplan.
Utilization = cell area+ Blockage area+ macro area/Total area
Aspect ratio: is nothing but shape of the design
Input files: netlist(.V), Lef, .tech, .def .

Flow:

 Creating core area/die area

 Initialising core rows for placing cells.
 Pins placement around core area.
 Physical cells (End cap and well tap) are placed in FP stage.
Macro Placement:

 Based on Macro fly line, we can place macros. fly line indicates connections b/w
them.
1. Macro to I/O port placement
2. Macro to Macro placement
3. Macro to standard cell placement.
Guidelines while placing macros:
1. Macro Spacing: If the macro height is 200um and the logic connectivity b/w one
cell at top of macro and other cell at bottom of macro then if we not giving
proper spacing b/w macros there will be chance of getting trans violation.
2. Macro orientation: orientation should be correct; it might be 0 or 180 deg
3. Macro blockages: To reduce routing congestion at particular area.

Macro spacing guidelines

 Channelled placement: space b/w 2 macros
 Abutted: no space b/w macros
 Mixed macro placement: design with both channelled and abutted macros.
Channel calculation: No.of pins of macro * pitch*2/ available routing resources
Power Planning:
Power planning is a process to distribute power to each part of the design equally. But we
did power planning automatically through the tool not manually and we used power bumps
over core area to distribute power instead of power pads.
Input files: netlist(.v), Lef, .tech, .def
Checks after power:

Power layers created properly or not? Masking is correct or Not?

Any overlaps? and any drc’s occurred at Pin
Place and place_opt:
Placement is the process of finalizing the exact location and orientation for standard cell
instead of appropriate loc and placement will be done at 3 stages.
Before the start of placement optimization all wire load models are removed. Placement
uses RC values from the virtual route to calculate timing. The virtual route is the shortest
distance between two pins.
Input Files: netlist (.v), .lef, .lib .tech .def and .sdc file
Flow:

 Global placement: here just place the cells in core rows.

 Legalization placement: It assigns a legal position for cell as per
 HFNS: It will break high fanouts to reduce the load and recreates logic for HF
which connect to single Net.
 Scan chain Re-Ordering: Standard cell will place based on their
interconnection cells and helps in optimizing the routing resources and make
design decongested.
 Detail Placement: Optimization will be done based on PPA.
Here cells will move just around legal locations, and mostly size cell, VT swap and
buffers will be added.
 Placement constraints: or Bounds
 Guide: it allows the cells each other if connections b/w the modules.
 Region: It allows the cell but won’t sends out.
 Fence: It won’t allow and send out the cells.

Checks after Placement:

 Have to check, is that any unplaced cells are present and overlaps.
 Utilization of the placement
 Congestion and timing
 Check PG connections to all the cells? Should be no physical and logical disconnect of
power.
Cts and Ctsopt:
After cells placement, the transmission delay of the clock signal for all the flops will not be
the same, so CTS will build clock
CTS is a process of distributing/propagate clock signals to all the Flops equally at the same
time with the minimal/zero skew.
The main goal of CTS is to meet design rule constraints, skew and insertion delay.

In Cts Process, anyone of the standard Tree topology structures will be implemented in the
design with an intension of making the length of all the wires equal in clock distribution.

H -type, X- type, Pi-type and Fishbone type.

Input files: netlist (.v), .lef, .lib .tech .def, .sdc file and clock spec file
Clock spec file contains all the clock information to build the clock tree, like Insertion delay,
time period, NDR rules, type of cell and drive strength used at CTS
CTS exception: it will defind in clock spec file.

 Stop pin: sync pin/end point -No buffer/inverter insertion beyond this point (Don't
touch scenario)
 Nonstop- It is like a clock port pin
 Float pin - No DRV, No Balance (skew/latency)
 Exclude pin - DRV Fixing but no balancing.
 Exclude pins are clock tree endpoints that are excluded from clock tree timing
calculations and optimizations but included in calculations and optimizations
for design rule constraints.
 Through pin or Leaf pin - DRV Fixing as well as Balancing.
Skew grouping:

 Skew group is nothing but a group of clock sinks.

 The clocks sink which have similar source (and which are synchronous to each other)
are placed in a group.
 Hence, the tool will try to improve skew and balance latencies of the groups
independently.
 If we not done skew grouping, the same group cells placed at long distance then tool
add more inverts/buffers to balance latency which leads to required more area and
chance of routing congestion.
 However, two different groups are logically exclusive.
Useful Skew:

 useful skew is a technique to improve timing violations.

 If we intentionally add the inverter/buffers to the capture edge and balancing skew
to reduce setup timing violation is called useful skew.
To Reduce Latency:

 NDR Rules (2w2s): 2w is using to avoid Em violation and 2S for avoid crosstalk.
 I will prefer 2S instead of shielding to avoid crosstalk because shielding takes
more routing resources and lack of tracks this leads to more congestion.
 Clock Inverter over buffers: clock inverter has uniform duty cycle which reduce
transition time and reduce the latency.
 Early and Late skewing:
Checks after Cts_Opt:
Skew report :> Latency report :> congestion :>Drv’s :> Timing violation (Setup/Hold)
:>utilization
Routing:

Routing is a physical connection made between the 2 cells pins and clock nets will be
skipped at Route.

Input files: netlist (.v), .lef, .lib .tech .def, .sdc file.
Routing will be done in 4 stages.
Global Routing: finds shortest path and assigns nets to specific metal layers and creates
temporary routing to calculating timing.
Track Assignment: It assigns tracks for every net in the design and it tries to make long,
straight meta traces to avoid the number of vias and DRC is not followed in TA stage.
Detail Routing: It removes all the trail nets and place the actual nets and tries to fix all DRC
violations after track assignment.
Search & Repair: It creates multiple block boxes in the design and will be fix the remaining
drc’s.
Checks: Timing and DRC
Phyv:

The physical layout must obey the design rules given by the foundry and the layout is
manufacturable with minimum fabrication faults.
DRC:
Inputs: Routed. v, GDS II/OASIS file (physical layers in binary format) and Rule Deck file
Flow:
Primary merge oasis:

Beol Fill: Beol Oasis (Poly, sub)

Feol Fill: metal Fill Oasis, Metal layer extraction.
Final merged oasis will be dumped with the input of beol oasis and feol oasis.
Type of Drc Violations:
Minimum Spacing :>Minimum width :> Minimum Encloser :> Minimum Cut

LVS: Layout vs schematic

1. Layout Versus Schematic (LVS) verifies the connectivity of a Verilog Netlist and Layout
Netlist (Extracted Netlist from GDS).
2. Tool extracts circuit devices and interconnects from the layout and saved as Layout Netlist
(SPICE format).
Routed Data
Verilog Netlist

GDS II/Oasis File

extract
It contains cell with Source Netlist
LVS Netlist
net interconnects

Compare both files

Check in LVS:
 missing/extra terminals or unmatched nets will compare, shorts and opens and PG
netlist, Pin mismatch/Inst mismatch.
Input files: GDS II -> LVS Netlist, Verilog Netlist, Rule Deck File.
ERC: Electrical Rule Check (ERC) is used to analyze or confirm the electrical connectivity of an IC
design. ERC checks are run to identify the following errors in layout.

 To locate devices connected directly between Power and Ground (nwell disconnecty)
 To locate floating Devices, Substrates and Wells
 To locate devices which are shorted
 To locate devices with missing connections.
Antenna Effect:

 During plasma etching, charge carriers may accumulation on the metal/poly, once it
is reaches certain potential, it tries to discharge through gate and damages the gate
oxide.
 it occurs during manufacturing process, When the long net connected to the gate
terminal
Antenna ratio = METAL AREA /GATE AREA.
Fixes:

Layer hoping: must be with the higher layer because lower layers fabricated first.
Reverse bias diode: Preferred because it will conduct at less threshold voltage.
Starrc:
Input files: Routed.def, BeolOsasis file, tech Lef,
Flow: In Starrc actual RC values of the metal will be extracted after nets routed at RouteOpt.

STA:
Static Timing Analysis will be done on the final routed netlist for validating the performance
of the chip.
To ensure the design works fine at target frequency without any setup and Hold violations.
InPut Files: Routed.V, Spef , Sdc, Lib.

ECO:

Input Files: Eco generated file, previous data spef, sdc and lib
Flow:
Load the routed data base :> remove filler cells :> source ECO file
Eco Place :> Eco Route :> add filler cells :> generate spef
Then send this data base to the sign off stages

IREM:
Dynamic IR(VDD): at high switching activity area, needs high power dissipation so requires
more power, clock cells and flops are high switching activities, so dynamic IR violations will
be popped up.

 Clock gating: Clock Gating reduces the dynamic power by disconnecting the clock
from an unused circuit block to limit switching activity of clock.
Fixes: Splitting instances, reduce drive strength, add VDD stripes and decap cells.
Static IR(VSS): Static IR is a leakage power even the cell is in inactive state leakage will be
occurred.it is independent of switching activity

 Power Switch (PS) cell is basic element which is used in power gating technique to
shutting down the power for a portion of the design to reduce the static leakage
power in the design.

Fixes: Splitting instances, reduce drive strength, add VSS stripes.

Electron migration:

 When a high current density passes through a metal interconnect, due to the high
momentum of current-carrying electrons, metal ions will drift from its original
position in the direction/motion of electrons is called Electron migration. Or
 The gradual displacement of metal ions along with the charge carriers due to the
flow of high-density current is called electron migration.

Fixes: Increase Metal width to reduce current density and reduce buf size in clk lines.

Crosstalk:

 Crosstalk is the undesirable electrical interaction (potential difference) b/w the

adjacent nets due to cross coupling capacitance.

Crosstalk Noise:

 It is generated when anyone of the nets is stable and other net is switching and due
to mutual capacitance, the switching net is affected to the victim net and the net
may have Falling/raising glitch depends on triggering & this mutual capacitance has
leaky nature. Ex: Aggressor -switching Victim-Stable
 If Glitch or spike with in the noise margin then it is safe glitch and the glitch
height is depending on coupling capacitance, Aggressor drive strength and
victim drive strength.
Crosstalk delay:

 Delay is generated when both the nets are switching for instance and delay is
depends on the direction of switching
 Same direction switching: Increase the transition time and reduces delay (hold
violation)
 Opposite direction switching: decreases the transition and increases delay (Setup
violation)

Crosstalk noise:
 Crosstalk delay:

Noise Margin:

 The Noise margin depends on the applying voltage and if we apply more voltage
noise margin will be more.
 As the technology node shrinks, the supply voltage also gets lowered. In lower
supply voltage, noise margin will be lesser. If the noise margin is lesser, it is more
prone to have a potentially unsafe glitch.
 External environment has more noise, coupling capacitance and we can’t operate
external environment with the core voltage. so, we need a compatibility b/w core
and external voltage. we can overcome by using I/O buffers.
 Input to I/O buffer must be compatible to core voltage (1V).
 Output to I/O buffer must be compatible to PCB voltage(5V).
Latch-up:

 Latch up is the existence of low resistive/impedance path (short circuit) between

VDD and VSS and this leads to static current flow from VDD to VSS and this high
current damage the IC.
 Well taps cells avoid the Latch up issue by controlling the base voltage.
Explanation:

 due to the positive feedback a low resistance path between Vdd to ground is formed,
This effect is called latch up.
 positive feedback? Which is unstable
A small leakage in Nwell. Means a small amount of free holes drifting in nwell, Makes
the PNP transistor switch on and the collector current of pnp transistor becomes
base current for npn transistor. which the emitter part of npn is the source of
electrons and by turning on the npn makes more electrons will drift towards base of
PNP making more holes (holes movement is opposite to electrons movement) which
 makes it as more strong base input for pnp, Making It as more ON state and so the
collector current. In this way you can think the

PBA vs GBA:

 In PBA mode, it will take the delay whatever the pin is connected to the path.
 If the Path connected to input A then Y =1.5 orelse connected to B then Y=2ps
 In GBA mode: Setup analysis
 irrespective of path connected to pin. It just takes the worst delay (max delay)
by comparing the 2 input pins.
 Ex: even path passing through the A pin, it will take B pin delay (worst delay)
means Y=2ps
 For Hold analysis, it will take min delay by comparing the 2 input pins, whichever is
less.
Gitter:
 Jitter is the variations of the clock period from edge to edge. i.e +/- jitter.
 and it will be caused by thermal noise, power supply variations, loading conditions.
 the effect/variation of time period we can manage by adding uncertainty.

setup violation

Hold violation
Setup/hold – setup capture at next rising edge and hold analysis with same edge point.
Clock uncertainty:

 We are applying estimation margin value for uncertain factors such as Gitter, skew in
some part of the time period. which is not affect on the original time period.

Ex: Actual TP: 3sec

Here, Time period: 3sec -2.5sec =0.5sec is benefit
False TP: 2.5sec Which makes the timing better

PreCTS Uncertainty = Gitter + skew

Cloning:
 It will split the fanouts with the same replica of cell.
 Ex: if And gate has 6 fanouts then we can split by placing same AND gate by devide
3/3.
 Load splitting means, split the fanouts with buffer/inverter.
Why scan chain reordering, if we don’t what happens.
 the scan chain helps in optimizing the routing resources and make design
decongested and it will benefit the timing. scan chain will be done in shift/test mode
and scan clocks has more clock frequency than the normal clocks, so it won’t effect
on timing.

DPT:
 DPT is a double pattern layer means we can use same layer with two diff maskings.it
will useful for lower nodes to overcome shorts in routing congested area. we are
used more DPT layers in 6nm compared to 12nm.
 Masking we can use for pattern matching.
What is load?
 Load is a capacitance, when we have the HF on single net, cell won’t drive to all the
endpoint cells and it will affect the transition time which affect the delay of cell.so
Cell delay will depend on input trans/output load and depend on PVT condition.
Lower node vs higher node difference and where you are used more corners?
 Gate Chanel length is different, Channel length is smaller compared to 12nm
 Row height is different and Site width difference
 Number of layers increased and DPT layers got increased
 Std cell height and width is reduced so that we can accommodate more of transistors
in the given area
 Colour shifting / mask shifting technique is enabled in 6nm
Means: tsmc std cell provides 1 frame view, 1 timing view and 4 gds cells
 Mainly we can use MO layer for routing in 6nm whereas not in 12nm

Why we use Clock Inverter Over clock buffer?

 Duty Cycle Maintenance: Clock inverters are designed to maintain uniform duty
cycle.
 Lower Delay: Clock inverters typically have lower delay compared to clock buffers.
 Smaller Skew: Due to their faster response time, they help maintain smaller clock
skew.
 Reduced Area: Using inverters allows driving the signal to the same distance
with fewer cells compared to buffers.

Normal inverters (also known as logic inverters) are used for various logic operations.
  Slew Rate: Normal inverters may have better slew rates and drive capabilities.
 Balance: They aim for better balance between rise and fall times.

What is Latch?

 Latches are digital circuits that store a single bit of information and hold its value
until it is updated by new input signals.
 D (Data) Latches: D latches are also known as transparent latches and are
implemented using two inputs: D (Data) and a clock signal. The output of
the latch follows the input at the D terminal as long as the clock signal is
high. When the clock signal goes low, the output of the latch is stored and
held until the next rising edge of the clock.
 ICG cells are used to save dynamic power by turning off the clock network when not
in use. Simple AND gate can be used along with a latch as ICG cell to control the
clock network.
setup/hold clear but how can you fix crosstalk.
 If there is no impact on timing with the crosstalk then no need of fixing crosstalk.

If data and clock path is fully optimized and then how can fix setup violation.
 By swapping buffers with pair of inverters.
OCV: On Chip variations
 On chip variations means the cell delays varies with the different PVT conditions, and
these variations affect on timing at fabrications stage, so we are applying Derate
values at STA to overcome timing violations at fabrication.
 Hold timing is critical at fabrication because it is independent of clock period.
 In OCV, applying same derate value for all the cells in the design, so it takes over
pessimistic delay for which has the low delay paths. Applicable for above 90nm.

Setup Analysis:
we can take the worst scenario and applying high derate values (late/max delay) at launch
and low derate (early/min delay) values at captured clock. Then tool optimize better to avoid
setup violation. Ex: +20% variation/-20% variation of cell.
Hold Analysis:
we can take the worst scenario and applying low derate values (early/min delay) at launch
and high derate (late/max delay) values at captured clock. Then tool optimize better to avoid
hold violation.
AOCV:
 In Advance on chip variations, the derate values applies depends on the path depth
and Net distance of the cell. If path depth and net delays increase then the applying
derate values also increase and it is not accurate In below 40nm technologies.
POCV:
 In POCV, Cell delay is calculated based on delay variation (σ) and tool performs 3σ
from its mean value
 The delay variation means it takes the tolerance value from the mean delay. So in
between that tolerance the data will pass without any path violation.
Cell delay = Mean delay ± delay variations
 Tool considered every cell in three estimated delays (3 sigma values) instead of
min/max value of delay.

CPPR:
 CPPR is the difference of cell delays in the common clock path.
 A cell can’t have 2 delay values at same instant of time.
 If 2 cells in the common path, it takes max delay of the cell for setup and min delay
for the hold calculation. For setup,
2 cells delay (2*10ps =20ps)
Launch path: 20ps * max derate value (+20% of 20 =+4ps) = 20ps+4ps =24ps

Capture path: 20ps * min derate value (-20% of 20 =-4ps) = 20ps -4ps =16ps.
CPPR =24 -16ps = 8ps is over pessimism, it happened due to it might be removed from
capture clock or else extra added to launch clock.so if I add 8ps to capture then it will be
24ps.no Violation.
Min pulse width violation:

 If we have variation in rise and fall transition from the input transition of rise and fall,
then the threshold (50%) will go worse. Hence the pulse width will decrease.
 If pulse width decreases, then we might lose data which was about to be captured at
some time.
Diff b/w power domain and voltage domain.
 voltage domains, do not have the same voltage values so required level
shifters. power domains mean, power on-off, required isolator cell.
 Common techniques include multi-voltage domains (MVDs), which are regions of the
circuit that operate at different voltages, and power gating, which shuts down the
power supply to some parts of the circuit when they are not in use
Why multiVDD domains?

 Mv design means, there is some part of the design which need not to run with high
voltage to reduce the overall power of chip.
 Performance will affect by reducing voltage. if V decrease means I also decrease
Because current is function of voltage then power also decrease.
Design Constriants:
Max Transition:

 The maximum time taken by a pin to change the logic from 0 to 1 or 1 to 0 is called
 Due to MTT, large dynamic power dissipation can happen.
set_max_transition -data_path 0.200 [get_clocks {edf_clk_cdte}]
set_max_transition -clock_path 0.120 [get_clocks {edf_clk_cdte}]

Max Capacitance:

 It is the capacitive load on output pin can drive.

 The maximum driving capability of output pin to all the interconnects capacitance
and cell capacitance.
 If large capacitance load is there, it will take more time to charge or discharge. So to
avoid this high drive strength cells are used.
Ex: set_max_capacitance 0.2
Max Fanout:

 If more fanout are connected from single cell then load Increases on driver cell and
current will decrease then automatically transition time decrease and performance
will decrease.
Ex: set_max_fanout 32
Input/output delay:

 Interface timing analysis will be done at Input and output ports, so I/O delays are
required to calculated and these I/O delays are not accurate.
 If I/O delays not specified then tool consider as 0 delay and it is affect on timing.
 Input/output delays used for In2Reg and Reg2Out path group timing optimization
 Input delay is the delay to the input port of our block
 Output delay is the delay from the output port of our block to the other block input.
Ex: set_input_delay -add delay 0.5 -clock edf_clk_cdte
set_output_delay -add delay 0.5 -clock edf_clk_cdte

Min/Max delay:

 The min/Max time taken by the system to respond w.r.t Input and we can specify the
min/max delay on Asynchronous timing path as lunch and capture triggered with
different clocks.so we can’t estimate. these delays are defined in SDC.
 In synchronous path, data captured with the same clock, so we can estimate delay
and no need of defining min/max delay.
 Cell min/max delay are depend on PVT condition, so defined in lib file.
 It is the highest time taken by the critical path in the combinational logic (data
path) is called Max delay
Ex: set_min_delay 3 -from ffl/Q-to ff2/D
set_max_delay 6 -from ffl/Q-to ff2/D
 min/max delay for edf_clk cdte is min 0.460ps and max: 0.524ps
Type of Power Cells used in MV:
Level Shifters:

 The main functionality of the level shifters is to shift the voltage from one voltage to
another voltage level depending upon the signal crossing different voltage domains.
Isolation Cells:

 Isolation cells are used between the domains. If the domain D1 is power shut down
mode and other domain D2 is in active mode. Since Domain D1 is power down
mode, it can propagate invalid logic to domain D2. To prevent this, Isolation cells are
inserted between the domains to clamp a known value at its output. Isolation cells
should be placed in always on domain to serve its functionality.
 Shut down domain outputs may be floating outputs and this could be a problem
when other active domains get these floating outputs as an input. This could affect
the proper functioning of the active domain.
Power switches:

 Power switches are used in power gating technique.

 Power gating is used to reduce the static (Leakage) power in the design.
 Power switches are used to turn off the power for portions of design which are
inactive at a point of time to reduce leakage power.
Retention cells:

 In power down mode, the data of F/F will be lost, so by using retention cells we can
retain the data (retain state as before power down) when the power is on.
 Retention register requires D flip-flop and latch and required always-on supply to
retain the data. Using the retention register area required more as compared to
normal flop because here we are using flip-flop with always-on supply.

Always On cells:

 These cells are always on irrespective of where they are placed. generally, buffer and
inverters are used for always ON cells.
 If they are special cells, they have their own secondary power supply and placed
anywhere in the design
 If they are regular buffer/inverters they require always-on cells and restrict the
placement of these types of cells in the specific region
 Ex: if data needs to be routed through or from the sleep block domain to active block
domain and distance between both domains is very long or driving load is also very
large then buffer might be needed to drive the long nets from one domain to
another.
 AON cell

Clock gating:

 Clock Gating reduces the dynamic power by disconnecting the clock from an unused
circuit block to limit switching activity of clock.
 The clock to the flipflop is applied through AND gate. This technique is called clock
gating technique. When the gate of Enable pin is at low and the clock is at high level,
the clock won’t toggle (Switch) because of AND gate. In this way the clock Gating
technique will reduce the switching activity of clock in order to save the power.
 When both the input of AND gate are high then only output high.

Physical cells:
End cap cells:

 These cells are Placed at End of the design and used to prevent the logic gate from
damage at fabrication stage and EC cells specifies the end of core rows.
Well Tap cells:

 WTC are used to prevent Latch-up issue at CMOS by controlling the base voltage.
 Used for nwell continuity and we placed for every 45um in regular intervals.
Spare cells:

 Spare cells used for any logic change in design in future

 after Routing any violations appear. It is reducing time & cost
Decap cells:

 Decap cells are store the power and provide instantaneous current to the driver cells
to reduce IR drop when it needs.
Tie cells:

 Tie cells are used to give the stable power to cmos inverter to prevent the damage of
cmos cell.
 Ex: suppose, If we you have floating pin in the design with logic 0 or 1 and this logic 0
might be change to 0.2 due to the adjacent signal noise/glitch then start leakaging
and damage the cell.

DbGet commands:
dbGet top.name
dbGet top.fPlan.box.size
dbGet top.fPlan.groups.pd.name
dbGet top.terms.name -block level ports

dbGet top.numTerms
dbGet[dbGet top.terms.isClk 1 -p].name
dbGet top.insts.name
dbGet [dbGet top.insts.cell.isPhyOnly 1 -p].name
llength [dbGet top.insts.cell.name <*TAP*> -p2]

dbGet [dbGet top.insts.cell.name <*TAP*> -p2].name

dbGet head.libCells.name - Get the information of a cell which is present in std. cell library
but not in design. all available Drive strengths, Vt type etc.
dbGet [dbGet head.libCells.isInverter 1 -p].name
dbGet head.layers.name
dbGet[dbGet head.layers.type routing -p].name -only routing layers
dbGet [dbGet top.insts.cell.baseClass block -p2].name -name of all the macros in the design

dbGet [dbGet top.insts.pStatus fixed -p].name -to get the all fixed status cells in the design.
dbGet selected.cell.name
dbGet selected.cell.terms.name
dbGet selected.wires.layer.name
dbGet selected.pt
add_port_state VDD_DTU -state {VDD_DTU_ON 0.75} -state {VDD_DTU_OFF off}
create_ccopt_skew_group -name cxf_clk_left/func1 -sources cxf_clk_left -auto_sinks
create_clock [get_ports {edf_clk_cdte}] -name edf_clk_cdte -period 0,829041 -waveform
{0.000000 0.414521}
set_max_transition -clock_path 0.138167 [get_clocks {edf_clk_cdte}]
set_max_transition -data_path 0.22 [get_clocks {edf_clk_cdte}]

set_input_delay - add_delay 0,497425 -clock [get_clocks {edf_clk_cdte}] [get_ports

{cdtel_edf_axi_R_DataInfo[100]}]
set_clock_uncertainty 0.035 -hold [get_clocks {edf_clk_cdte}]
set_clock_uncertainty 0.041 -setup [get_clocks {edf_clk_cdte}]
set_ccopt_mode -cts_target_skew 0.080
set_multicycle_path 10 -setup -to $_coll_8 (port names)

set_multicycle_path 9 -hold -to $_coll_9

set_false_path -setup -from $_coll_10
set_max_delay 7 -from [get_ports {cxf_rstn_left noc_ecf_rst_n TestMode_en
noc_edf_rst_n}]

Related commands:
FloorPlan:

redirect bottom_pins {puts [dbget selected.name]}

SelectPin [exec cat <saved file path or pin list >]
Power:
Create_placement_blkg -loc
Create_routing_blockage -loc -layer -via

globalNetConnect VDD -type pgpin -pin VDD

globalNetConnect VDD_DTU -type pgpin -pin VDDO -singleInstance
u_ecf_blk304/snps_PD_VDD_DTU__LS_VDD_VDD_DTU_snps_TestMode_en_LS_VDD_VDD_
DTU -override -verbose
route_secondary_pg
createInstGroup modulel -guide {70.105 395.459 402.6065 862.994}
addInstToInstGroup module u_edf_top_u_edfior_top_edfior300/ro_edfio_s_edfcore0_axi_T
main*
Place:
setDesignMode -congEffort high
setOptMode -maxLocalDensity 0.75

setPlaceMode -place_global_max_density 0.70

## to reduce the utilization of ULVT cells ##
setHighEffort0ptCells *UL
set_path_adjust -0.050 -setup -path_adjust_group MVR2R -view $view.
group_path -name PG -from */CK -to */D

setpathgroupoptions mohan -effert high -weigh 5 -slackadj -100

specifyCellPad -left 8 -right 5 $cell
Eco:
setAttribute -net {} -preferred_routing_layer_effort high -bottom_preferred_routing_layer -
top_preferred_routing_layer -weight 10 -skip_routing false -avoid_detour true
attachDiode -diodeCell F_DIODE_96S7P5T24R -pin (Instaname_ D) -prefix AntDiode2 -loc {}
dbChangeInstCell u_ecf_blk305/dtu/U_MARS_RouteOptFE_ECOC0_ls_7065
CLKBUFV4_96S7P5T16UL ;# BUFV4_96S7P5T16L
report_noise -all_vio -nosplit
neport_constraint -pba_mode path -nosplit -all_violators -max_transition
report_delay_calculation -from * -to * -crosstalk

Skew group creation:

Create_clock_skew_group -clock [get_clock {clk_name mention here}] -name <mention
name > here}] -objects [get_pins {list of sinks cp pinsl
get_attribute [get_pins <pin name>] clocks.