EDA Tools

Electronic Design Automation Tools

Electronic Design Automation (EDA) tools are software applications used by engineers
and designers to design, analyze, and simulate electronic systems and integrated circuits
(ICs). These tools are essential in the development of electronic products across various
industries, including telecommunications, automotive, aerospace, and consumer
electronics.
key stages and components involved in electronic design automation (EDA)
• Schematic Capture.
• PCB Layout Design.
• Simulation and Analysis.
• Verification and Validation.
• Design Optimization.
• Design Reuse and Collaboration.
• Manufacturing Preparation.

EDA tools play a crucial role in the design and development of electronic systems and ICs,
offering comprehensive capabilities for design creation, simulation, analysis, and
validation. They contribute to faster time-to-market, improved product quality, and
innovation in the field of electronics.
 History of EDA Tools
Early Beginnings:
• - EDA tools started in the 1960s with the need to
design complex electronic systems.
• - The first tools were created to automate the
design of circuits and layouts.
• - Key milestones in the 1980s include the
introduction of VLSI design tools.
• - Today, EDA tools are essential in designing ICs,
PCBs, and embedded systems.
 Major EDA Tool Manufacturers
• Companies:
• - Synopsys: Provides tools for semiconductor design,
verification, and intellectual property (IP) integration.

• - Cadence: Synopsys: Provides tools for semiconductor

design, verification, and intellectual property (IP) integration.
Offers tools like Virtuoso and Allegro for IC and PCB design.

• - Mentor Graphics (Siemens): Known for tools like ModelSim

and PADS. For PCB design, FPGA verification, and IC design.

• - Xilinx: Known for FPGA (Field-Programmable Gate Array)

design and verification tools.
 XILINX
• Xilinx is a prominent company in the field of programmable logic devices, particularly known for its
FPGA (Field-Programmable Gate Array) products and associated development tools.
Xilinx develops and sells a range of programmable logic devices, including FPGAs and
SoCs (System-on-Chips) with integrated FPGA fabric. These devices are used in a wide variety of
applications across industries such as telecommunications, automotive, aerospace, industrial
automation, and data centers.
• Founded in 1984, the introduction of the first FPGA in 1985.
• Acquired by AMD: 2020 (completed in 2022)
Tools Used:
1. Vivado Design Suite: This is Xilinx's primary software suite for FPGA design and development. -
Features: Integrated Design Environment (IDE), High-Level Synthesis (HLS), and IP Integrator.
2. Xilinx SDK: Part of the Vivado Design Suite, the SDK is used for software application
development.
3. ISE Design Suite: Although Vivado has largely replaced ISE, it was Xilinx's previous generation of
design tools for FPGA development.
4. SDSoC Environment: This tool combines Xilinx’s Vivado HLS with development environments
such as Eclipse to enable system-level C/C++ development targeting Xilinx Zynq SoCs and
MPSoCs.
• Xilinx has seen significant growth, with strong market presence in data centers, automotive, and 5G
networks.
 ALTERA
• Altera Corporation was a prominent American manufacturer of programmable logic
devices, particularly known for its FPGA (Field-Programmable Gate Array) products.
• Founded in 1983, Altera was a key player in the programmable logic device market.
• Altera was a leading provider of FPGA technology before its acquisition by Intel. Its
products and solutions continue to play a crucial role in enabling flexible and
customizable computing solutions across various industries.
• Acquired by Intel in 2015, now part of Intel's programmable solutions group.

Tools Used:
1. Quartus Prime: This was Altera's integrated development environment (IDE) for FPGA
design and development.
2. Nios II: This suite provided tools for designing and implementing embedded systems
using Altera's Nios II soft-core processor.
3. DSP Builder: A tool that integrated DSP (Digital Signal Processing) design flow into
Quartus Prime. It allowed designers to model, simulate, and implement DSP
algorithms on Altera FPGAs using a graphical environment.
4. PowerPlay: An analysis tool for estimating and optimizing power consumption in FPGA
designs.

• - Market Share: Strong presence in telecommunications, industrial, and consumer

electronics.
 JTAG
• JTAG, which stands for Joint Test Action Group, is a standard interface used in
electronics for testing and debugging printed circuit boards (PCBs) and integrated
circuits (ICs). It was originally developed in the 1980s as a method to improve the
testing and programming of ICs during manufacturing.
- Developed in the 1980s as a standardized method for testing PCBs and ICs.
- Standardized as (Institute of Electrical and Electronics Engineers) IEEE 1149.1 in
1990.
• Tools Used: - Various software and hardware tools for implementing and
utilizing JTAG
Programming Libraries and APIs, Simulation and Verification Tools, Boundary Scan
Description Language (BSDL) Files, Integrated Development Environments
(IDEs), Flash Programmers, JTAG Emulators and Debuggers, JTAG Boundary Scan
Testers.

• -Applications: Crucial for testing, debugging, and programming in various

electronics sectors.
Programmable Logic Device (PLD)
is an electronic component used to build reconfigurable digital circuits.
PLDs can be programmed to perform a wide array of logic functions.
• Simple Programmable Logic Devices (SPLDs):Simple, limited
capacity, used for basic logic functions.
• Complex Programmable Logic Devices (CPLDs):Intermediate
complexity, predictable timing, used for moderately complex logic
functions.
• Field-Programmable Gate Arrays (FPGAs):Highly complex, large
capacity, suitable for high-performance and complex applications.
Applications of PLDs:
• Digital signal processing
• Control systems
• Communication systems
• Custom hardware accelerators
• Rapid prototyping of digital circuits
PLDs play a crucial role in modern digital circuit design, providing
designers with the flexibility to create custom logic solutions tailored
to specific applications.
Major PLD Manufacturers
• Intel (formerly Altera)
• AMD (formerly Xilinx)
• Microchip Technology (formerly Atmel)
• Lattice Semiconductor
• Microsemi (a subsidiary of Microchip Technology)
• QuickLogic
• Efinix
• Achronix Semiconductor
 Testbench
• A testbench is a crucial component in the
verification process of digital circuit design,
especially when using hardware description
languages (HDLs) like VHDL or Verilog. The
testbench provides a controlled environment to
simulate and verify the behavior of a Design
Under Test (DUT).
• Purpose of a Testbench:- Verification,
Debugging, Validation.
 Languages Used in EDA Tools
VHDL(Very High Speed Integrated Circuit (VHSIC)):
• - Hardware Description Language Used for describing the
behavior and structure of electronic systems.
• - Key Features: Strong typing, concurrency, and abstraction
capabilities.

Verilog:
• - Hardware description language which describes the
behavior of electronic circuits, especially digital circuits.
• - Key Features: Simple syntax, widely used in industry for
synthesis and verification.
 VHDL Verilog

1. Strongly typed 1. Weakly typed

2. Easier to understand 2. Less code to write
3. More natural in use 3. More of a hardware
4. Non-C like syntax modeling language
5. Widely used for FPGAs 4. Similarities to the C
and military language
6. More difficult to learn 5. A better grasp on hardware
modeling
6. Simpler to learn
 Study of Quartus Compilations
• Quartus II software is used for the design and compilation of FPGA and
CPLD designs.
• The compilation process involves multiple stages: Analysis & Synthesis,
Fitting, Assembler, Timing Analysis, and Programming File Generation.

• Stages in Detail:
• Analysis & Synthesis: Converts the high-level design into a gate-level
representation.
• Fitting: Maps the design onto the physical resources of the FPGA or CPLD.
• Assembler: Creates the binary programming file for the device.
• Timing Analysis: Ensures that the design meets the required timing
constraints.
• Programming File Generation: Generates the file used to program the
FPGA or CPLD.