QUIZ on VLSI design concept duration: 1 Hour

1. Effective channel length of a MOSFET in saturation decreases with increase in

Drain voltage
2. What happens to delay if you increase load capacitance?
Delay increases. Delay increases due to load capacitance effect, taking longer time to charge the capacitor
and hence stable to drive the output load.
X = 1/(2*pi*f*c)
X = capacitive reactance
pi = 3.14
f = frequency
c = capacitance

If X is to be maintained constant, with increase in capacitance, frequency should decrease and freq is
inversion of time period so T will increase meaning the gap between two clock pulses will increase
hence DELAY will increase.

3. Voltage scaling is a power reduction technique that relies on reducing the supply voltage of a circuit
without affecting any of the other circuit parameters.

False

4. Write a short note on Layout Design Rules. Difference between Layout and Stick diagrams.
Layout Design: The process of creating an accurate physical representation of an engineering drawing
(netlist) that conforms to constraints imposed by the manufacturing process, the design flow, and the
performance requirements shown to be feasible by simulation.

Design rules are the rules that have to be respected when a given design is laid out. There are design rules
for all of the components we have been introduced to: polygons and paths, transistors, and contacts.
Fundamentally, these design rules represent the physical limits of the manufacturing process. Design rules
are put in place to help layout designers understand and account for physical three-dimensional limitations
and manufacturing tolerances within the CAD and layout tool environment.

The various rules are:

1. Well rules
2. Transistor rule
3. Contact rules
4. Metal rules
5. Via rules
6. Other rules

Designs often use the -based scalable CMOS design rules from MOSIS. MOSIS actually has three sets of
rules: SCMOS, SUBM, and DEEP.The other rule is micron design rules

The initial phase of layout design can be simplified significantly by the use of stick diagrams. A stick diagram
is a simplified layout form, which contains information related to each of the process steps, but does not
contain the actual size of the individual features.
The purpose of the stick diagram is to provide the designer a good understanding of the topological
constraints, and to quickly test several possibilities for the optimum layout without actually drawing a
complete mask diagram. The stick diagram can easily be drawn by hand and is a handy intermediate form
between the circuit diagram and the physical layout since it can easily be modified and corrected.

5. What is body effect? Is it due to parallel or serial connection of MOSFETs?

Increase in Vt (threshold voltage), due to increase in Vs (voltage at source), is called as body effect. It is due
to serial connection. In general multiple MOS devices are made on a common substrate. As a result, the
substrate voltage of all devices is normally equal. However while connecting the devices serially this may
result in an increase in source-to-substrate voltage as we proceed vertically along the series chain (Vsb1=0,
Vsb2 0). Which results Vth2>Vth1.

6. What is latch up in CMOS design and ways to prevent it?

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled
rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously
flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the
amount of current flow produced by this mechanism can be large enough to result in permanent
destruction of the device due to electrical overstress (EOS).

Latch-up is a condition in which the parasitic components give rise to the Establishment of low resistance
conducting path between VDD and VSS with Disastrous results

Latchup prevention is easily accomplished by minimizing Rsub and Rwell. Some processes use a thin
epitaxial layer of lightly doped silicon on top of a heavily doped substrate that offers a low substrate
resistance.

7. Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits?
1) In digital design, decide the height of standard cells you want to layout. It depends upon how big your
transistors will be. Have reasonable width for VDD and GND metal paths. Maintaining uniform Height for all
the cell is very important since this will help you use place route tool easily and also incase you want to do
manual connection of all the blocks it saves on lot of area.

2) Use one metal in one direction only; this does not apply for metal 1. Say you are using metal 2 to do
horizontal connections, and then use metal 3 for vertical connections, metal4 for horizontal, metal 5
vertical etc.

3) Place as much substrate contact as possible in the empty spaces of the layout.

4) Do not use poly over long distances as it has huge resistances unless you have no other choice.

5) Use fingered transistors as and when you feel necessary. Try maintaining symmetry in your design. Try to
get the design in BIT Sliced manner.

8. Draw a transistor schematic and layout of NAND and NOR gate.

NAND GATE
NOR GATE

9. What is glitch? What causes it (explain with waveform)? How to overcome it?
A glitch is a short-lived fault in a system. It is often used to describe a transient fault that corrects itself,
and is therefore difficult to troubleshoot. An electronics glitch is an undesired transition that occurs
before the signal settles to its intended value. In other words, glitch is an electrical pulse of short
duration that is usually the result of a fault or design error, particularly in a digital circuit. For example,
many electronic components, such as flip-flops, are triggered by a pulse that must not be shorter than a
specified minimum duration; otherwise, the component may malfunction. A pulse shorter than the
specified minimum is called a glitch. A related concept is the runt pulse, a pulse whose amplitude is
smaller than the minimum level specified for correct operation, and a spike, a short pulse similar to a
glitch but often caused by ringing or crosstalk. A glitch can occur in the presence of race condition in a
poorly designed digital logic circuit.

The following diagram shows gated clock.The corresponding timing diagram shows glitches which causes
the flip flop to clock at the wrong time.
 The following figure shows an alternative to the gated clock using a data path.

The flip-flop is clocked at every clock cycle and the data path is controlled by an enable. When the
enable is Low, the multiplexer feeds the output of the register back on itself. When the enable is High,
new data is fed to the flip-flop and the register changes its state.

10. What is the minimum no. of NAND gate required to implement XOR gate.

Five

11. What is fingering? What is antenna rule in physical layout design?

Putting together transistors with fixed aspect ratio will not result in a compact layout. Fortunately, the
aspect ratio of the transistor can be modified by using the transistor current equation. For example, the
transistor with a width of 20um and a length of 0.2um is similar to having four transistors connected in
parallel, each with a width of 5um and a length of 0.2um. The MOS is said to have 4 fingers.
 When a metal wire contacted to a transistor gate is plasma-etched, it can charge up to a voltage
sufficient to break down thin gate oxides. The metal can be contacted to diffusion to provide a path for
the charge to bleed away. Antenna rules specify the maximum area of metal that can be connected to a
gate without a source or drain to act as a discharge element. They are somewhat hard to visualize, but
are fixed by placing jumpers to a higher layer of metal to shorten the metal segment or by placing
diffusion diodes on wires.

The design rule normally defines the maximum ratio of metal area to gate area such that charge on the
metal will not damage the gate. The ratios can vary from 100:1 to 5000:1 depending on the thickness of
the gate oxide (and hence breakdown voltage) of the transistor in question. Higher ratios apply to
thicker gate oxide transistors (i.e., 3.3 V I/O transistors).

12. What are the different regions in which the MOS transistor operates?
 (1) Cut-Off Region In this region the gate voltage is less than the pinch-off voltage Vp and therefore very
little current flows.

(2) Triode Region In this mode the device is operating below pinch-off and is effectively a variable
resistor. ROUT is ~ linear but only over a small range of VDS.

(3) Saturation Region This is the main operating region for the device. The drain voltage has to be greater
than the gate voltage less the pinch-off voltage this sets the minimum supply voltage.

13. What is the difference between latches and flip-flops based designs?

Latches are level-sensitive and flip-flops are edge sensitive. Difference between latch based design and flop
based design is that latch allowes time borrowing which a tradition flop does not. That makes latch based
design more efficient. But at the same time, latch based design is more complicated and has more issues in
min timing (races).

14. Give two ways of converting a two input NAND gate to an inverter?

(a) Short the 2 inputs of the NAND gate and apply the single input to it.
(b) Connect the output to one of the input and the other to the input signal.

15. For CMOS logic, give the various techniques you know to minimize power consumption?

1. Clock Gating
2.Multi-VDD
3.Multi-Vth
4.DVFS (Dynamic Voltage Frequeny Scaling)
5. Reducing Output Load Capacitance
6. Power Gating

Or we can say: Reduce the supply voltage,Reduce the operating frequency,reduce output load capacitance,
reduce leakage current in standby operation, use clock gating/sleep mode, use multi threshold and multiple
supply device, use efficient coding and algorithms, partition the circuit if it is mixed signal, reduce swing
voltage (memory design).