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CTL51 LA-E841P r0.1
CTL51 LA-E841P r0.1
5 4 3 2 1
N N N
Compal Confidential
C C
Schematic Document
N AMD Stoney Ridge
B
AMD R17M-M1-30/70 B
N
2016/10/12
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. NFL-C CTL51 LA-E841P
Date: Thursday, March 09, 2017 Sheet 1 of 48
5 4 3 2 1
2014-06-20 Rev:
.c
cs s
0.1
kS Sc
5 4 3 2 1
k
b oo
ot
N
P.9~10
DP0 8GB
eDP Conn.
P.21 eDP x2
AMD
Stoney Ridge
HDMI Conn. DP1 Processor USB3.0
P.22 BGA 769 5Gb/s
USB2.0 Port 0
480Mb/s USB2.0 port (SB) P32
CRT Conn DP to VGA Transmitter DP2
P23 Port 2
om m
RTD2166 P23 DP x2 Touch Screen
co
P21
c
s. s.
ic tic
at
Port 3
PCIE x2ma
C
LAN(GbE) BT(NGFF Slot) P28 C
e m RTL8111HSH-CG
Port 0
e
ch P.24
ch Port 4
kS kS
Camera P21
WLAN
booPort 2 Port 5 Port 1
e
ot
P.28 USB3.0 port P29
N Port 6 Port 2
USB3.0 port P29
h
Sc o
ok e b
o Aduio codec ot
SMBUS
eb HDA
HDA 24MHz
ALC3227
Internal SPK N
P25
at SPI ROM
P32 FAN TPM
Lid switch SLB 9665 P33
e m
ch ch
On small board 8M P6
c
S kSkS
Thermal sensor
o ok o
oo o
G753T11U b
eb e eb
P8
ot ot t
A A
N NNo
m
Issued Date Deciphered Date
Block diagram
co
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
s.
Size Document Number Re
R ev
m
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
ic
NFL-C CTL51 LA-E841P
ic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
at at
Date: Thursday, March 09, 2017 Sheet 2 of 48
5 4 3 2 1
m m
he c he h
c
kS ScSc
kS k k
oo bo
oo
eb e bo
ot oto te
N NN
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i i c i i c
atat atat atat
hem em h emem hemem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok o okok o o ok
o o o
eb eb ebeb eb eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
o o o
bobo bo
bo eb
o o
ete e
te eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch ch
ch chc
kS o kSkS o kS
kS okS kS
o o o
e bobo e bo
bo b
e eb
oo
oto te ot
o te ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat at
at
h em
e m
h eme m
heme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS okokS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
A B C D E
b oo o o
b oo o o
b oo
o o
b eb eb
te e te
+3V_LID X X
<USB Port>
VIN X X
@ is NO SMT part
t e
(empty)
SOC SMBUS Address Table ot t t
o opad , don't pop. o o
NN Power RailNN NNo
BATT + X X USB3.0 USB2.0
+19VB X X
short@ : short SOC_SMBUS Net Name Device Address (7 bit)
Address (8bit) Port Port DESTINATION
+VL X X
Write Read
+3VL X X
@EMI@,@ESD@,@RF@ : Reserve , don't pop. DIMMA
X 0 USB 2.0 (SB)
0x40 TBC TBC
+5VALW EC_ON X
+3VS0x41
APU_SCLK0
DIMMB 0x41 TBC TBC X 1 TO SATA
1 +3VALW EC_ON X RF@ : RF team request, must add. APU_SDATA0 1
+3VALW_EC EC_ON X
mm mm om
X 2 TS
+1.35V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4# EMI@ : EMI team request, must add.
m
co o co o o
APU_SMB_SCLK1
Xc
s.s.c s.s.c s.s.c
+0.675VS SUSP# Touch Pad 0X2C TBC TBC
APU_SMB_SDAT1 3 BT
+5VS SUSP# PM_SLP_S3# ESD@ : ESD team request, must add.
ici c ic i c EC
i c c
i 0
at t t
+3VS SUSP# PM_SLP_S3# 0x1A TBC TBC
at t t 4 Camera
+APU_CORE VR_ON LVDS@ : Support LVDS panel. a a APU_SIC Thermal Sensor 0x48 TBC TBC aa
em m em m em m
+APU_GFX GFX_VR_OFF +3VS
APU_SID
e e e
1 5 USB 3.0 (MB)
eDP@ : Support eDP panel.
h h h h
LVDS TBC TBC
Sc ch S c ch S c ch Sc
Sc
kS S S
2 6 USB 3.0 (MB)
PX@ : GPU BOM conf i g.
k k
o oNote : oo k k ook k
bo bo bo o bo o
3 7 Card Reader
Symbol
ete te eb Address (8bit) te eb
ot
EC SMBUS Address Table
t t
UAPU1
+3VS
o o o o o
NN NN NN
: means Digital Ground
EC_SMBUS Port Power Rail Device Address (7 bit)
R=2.2K
Write Read <PCI-E Port>
BA15 APU_SCLK0
AY17 APU_SDATA0 BAT 0x16 TBC TBC
SO-DIMM A : means Analog Ground PCI-E
SMBUS Port 1 +3VALW_EC Port DESTINATION
2
+3VALW CHGR 0x12 TBC TBC 2
SO-DIMM B 0 LAN
R=2.2K APU Int sensor 0x98 TBC TBC
co o co o
1
o
AG4 APU_SMB_SDAT1
CPU ticisc.sc.c
TP +3VS
+1.8VS
c s.s.c DGPU Int sensor 0x82 TBC TBC
c s.s.2 c WLAN
i i c i i c
a at at
at SMBUS Port 3 at
at
R=1K
BB10 APU_I2C0_SCL_TS APU Ext sensor 0x90 TBC TBC 3
emem
mm mm
BB9 APU_I2C0_SDS_TS
he he
+3VS_VGA
h e e
h ch ch ch
DGPU Ext sensor 0x98 TBC TBC
Sc c Sc Sc kS Sc
kS +1.8VS +1.8VS
o k
o k S
o k
o k S <SATA Port>
o o k
o o o o o o
eb eb eb eb eb eb
SATA
R=1K
Port DESTINATION
ot ot t ot t
B18 APU_SIC
ot +3VS_VGA
C17 APU_SID
NNo NNo
2N7002
NN+3VS_VGA
EC_SMB_CK2 0 HDD
EC_SMB_DA2
R=10K
1 SSD
3 2N7002 GPU 3
Z1 DAX
U44:+3VALW_EC +3VS
45@
R=2.2K
mm mm mm
79 EC_SMB_CK2 @ HDMI PCB
Part Number = RO0000003HM Part Number = DA6001R9000
CRT Bridge
co co co
R=0 ROYALTY HDMI W/LOGO+HDCP PCB CTL51 LA-E841P
RTD2168
at
at 77 at
at at
at
e mm 78
e mm UC1 A9_R1@ SA0000AH600
e mm
e e e
+3VALW_EC (+3VL)
hh ch ch ch
S IC A32 A9-9420 AM9420AYN23AC 3G BGA 769P APU
Sc c ch ch c
kS kSkS kSkS kSkS
R=2.2K
EC_SMB_CK1
o o o
EC_SMB_DA1
o o o
R=100 UC1 E2_R1@ SA0000AH800
BAT
bo bo o
S IC A32 E2-9000E EM900EANN23AC 1.5G BGA
bo bo eb eb
o
+3VS te te
oCharger ot
ete ot t
NN o U666 U666
NN o NNo
R=2.2K R30_R1@ R70_R1@
EC_SMB_CK3
4 4
EC_SMB_DA3 APU External
Thermal Sensor R17M-M1-30 FCBGA
SA000087TF0
R17M-M1-70 FCBGA
SA000098V80
+3VS_VGA S IC A32 216-0867-071 R17M-M1-30 FCBGA S IC A32 216-0864032 R17M-M1-70 FCBGA
83 R=2.2K
mm mm mm
84
@
co o co o co o
GPU External Security Classification Compal Secret Data Compal Electronics, Inc.
at at
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
at at at
at
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. NFL-C CTL51 LA-E841P
Date: Thursday, March 09, 2017 Sheet 3 of 48
mm mm mm
A B C D E
e
hh e e e e e
Sc c chch chch chc
kS o kSkS okSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
9,10 DDRAB_SMA[15..0]
b oo
o o UC1A
DDRAB_SDQ[63..0] 9,10
b oo
o o
b ooo o
eb eb eb
MEMOR Y
e e e
DDRAB_SMA0 AG38 A34 DDRAB_SDQ0
ot ot ot
DDRAB_SMA1 M_ADD0 M_DATA0 DDRAB_SDQ1
t t t
W35 B34
DDRAB_SMA2 W38 M_ADD1 M_DATA1 A38 DDRAB_SDQ2
mm mm mm
M_ADD15/M_ACT_L M_DATA14 DDRAB_SDQ15 P_GPP_RXP1 P_GPP_TXP1
F40 R10 C1
co o co o co o
AJ38 M_DATA15 P_GPP_RXN1 P_GPP_TXN1
9,10 DDRAB_SBS0# M_BANK0 DDRAB_SDQ16 PCIE_PTX_DRX_P2
c c c c c c
9,10 DDRAB_SDM[7..0] DDRAB_SDM0 DDRAB_SDQ19
i i i
B35 M_DATA18 N41 N4 A3
i i i
at at at
DDRAB_SDM1 M_DM0 M_DATA19 DDRAB_SDQ20 P_GPP_RXP3 P_GPP_TXP3
at at at
D40 H40 N5 B3
DDRAB_SDM2 M_DM1 M_DATA20 DDRAB_SDQ21 P_GPP_RXN3 P_GPP_TXN3
K40 H41
DDRAB_SDM3 M_DM2 M_DATA21 DDRAB_SDQ22
T41 M40
em em em
DDRAB_SDM4 M_DM3 M_DATA22 DDRAB_SDQ23
m m m
AE41 M41
DDRAB_SDM5 M_DM4 M_DATA23
AL40
e e e
DDRAB_SDM6 M_DM5 DDRAB_SDQ24 PCIE_CTX_GRX_P0
AU40 R40 L5 A4 2 1 PX@
h h h h
0.22U_0402_10V6K CC1
ch ch ch
DDRAB_SDM7 BA37 M_DM6 M_DATA24 T40 DDRAB_SDQ25 14 PCIE_CRX_GTX_P0 L4 P_GFX_RXP0 P_GFX_TXP0 B4 PCIE_CTX_GRX_N0 2 1 PX@ PCIE_CTX_C_GRX_P0 14
0.22U_0402_10V6K CC2
Sc Sc Sc Sc
Sc
M_DM7 M_DATA25 DDRAB_SDQ26 14 PCIE_CRX_GTX_N0 P_GFX_RXN0 P_GFX_TXN0 PCIE_CTX_C_GRX_N0 14
W40
M_DATA26 DDRAB_SDQ27 PCIE_CTX_GRX_P1
kS kS kS
Y40 J5 A5 0.22U_0402_10V6K 2 1 PX@ CC3
ok ok k
M_DATA27 DDRAB_SDQ28 14 PCIE_CRX_GTX_P1 P_GFX_RXP1 P_GFX_TXP1 PCIE_CTX_GRX_N1 PCIE_CTX_C_GRX_P1 14
k
B36 P40 J4 B5 0.22U_0402_10V6K 2 1 PX@ CC4
9,10 DDRAB_SDQS0 M_DQS_H0 M_DATA28 DDRAB_SDQ29 14 PCIE_CRX_GTX_N1 P_GFX_RXN1 P_GFX_TXN1 PCIE_CTX_C_GRX_N1 14
oo
A36 P41
o o
9,10 DDRAB_SDQS0# M_DQS_L0 M_DATA29 DDRAB_SDQ30 PCIE_CTX_GRX_P2
E40 V40 G5 A6 0.22U_0402_10V6K 2 1 PX@ CC5
o o o o bobo
9,10 DDRAB_SDQS1 M_DQS_H1 M_DATA30 DDRAB_SDQ31 14 PCIE_CRX_GTX_P2 P_GFX_RXP2 P_GFX_TXP2 PCIE_CTX_GRX_N2 PCIE_CTX_C_GRX_P2 14
D41 V41 G4 B6 0.22U_0402_10V6K 2 1 PX@ CC6
eb eb
9,10 DDRAB_SDQS1# M_DQS_L1 M_DATA31 14 PCIE_CRX_GTX_N2 P_GFX_RXN2 P_GFX_TXN2 PCIE_CTX_C_GRX_N2 14
eb eb
L40
9,10 DDRAB_SDQS2 AD41 DDRAB_SDQ32 PCIE_CTX_GRX_P3
e
K41 M_DQS_H2 D7 A7 2 1 PX@
te
0.22U_0402_10V6K CC7
ot t ot t ot
9,10 DDRAB_SDQS2# U41 M_DQS_L2 M_DATA32 AD40 DDRAB_SDQ33 14 PCIE_CRX_GTX_P3 E7 P_GFX_RXP3 P_GFX_TXP3 B7 PCIE_CTX_GRX_N3 2 1 PX@ PCIE_CTX_C_GRX_P3 14
0.22U_0402_10V6K CC8
9,10 DDRAB_SDQS3 U40 M_DQS_H3 M_DATA33 AH41 DDRAB_SDQ34 14 PCIE_CRX_GTX_N3 P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_N3 14
NNo NNo o
9,10 DDRAB_SDQS3#
AF41 M_DQS_L3 M_DATA34 AH40 DDRAB_SDQ35
NN
9,10 DDRAB_SDQS4 AE40 M_DQS_H4 M_DATA35 AB40 DDRAB_SDQ36 1 2 196_0402_1% P_ZVDDP U8 W8 P_ZVSS 1 2 196_0402_1%
C +0.95VS_APU_GFX R1 R2 C
9,10 DDRAB_SDQS4#
AM40 M_DQS_L4 M_DATA36 AC40 DDRAB_SDQ37 P_ZVDDP P_ZVSS
9,10 DDRAB_SDQS5
AM41 M_DQS_H5 M_DATA37 AF40 DDRAB_SDQ38
9,10 DDRAB_SDQS5#
AV40 M_DQS_L5 M_DATA38 AG40 DDRAB_SDQ39
9,10 DDRAB_SDQS6 M_DQS_H6 M_DATA39 A6-9200E_BGA769
AV41
9,10 DDRAB_SDQS6# BA36 M_DQS_L6 AK41 DDRAB_SDQ40
9,10 DDRAB_SDQS7
AY36 M_DQS_H7 M_DATA40 AK40 DDRAB_SDQ41
9,10 DDRAB_SDQS7# M_DQS_L7 M_DATA41 AP41 DDRAB_SDQ42
M_DATA42 AP40 DDRAB_SDQ43
M_DATA43 AJ41 DDRAB_SDQ44
AC35 M_DATA44 AJ40 DDRAB_SDQ45
10 DDRA_CLK0
AC34 M_CLK_H0 M_DATA45 AN41 DDRAB_SDQ46
mm mm mm
10 DDRA_CLK0#
AA34 M_CLK_L0 M_DATA46 AN40 DDRAB_SDQ47
co o co o co o
10 DDRA_CLK1 AA32 M_CLK_H1 M_DATA47
10 DDRA_CLK1# M_CLK_L1 AT40 DDRAB_SDQ48
c c c c c c
9 DDRB_CLK1 M_CLK_H3 M_DATA50 BA40 DDRAB_SDQ51
i i i
AA38
i i i
at at at
9 DDRB_CLK1# M_CLK_L3 M_DATA51 AR40 DDRAB_SDQ52
at at at
G38 M_DATA52 AT41 DDRAB_SDQ53
9,10 MEM_MAB_RST# MEM_MAB_EVENT# AA41 M_RESET_L M_DATA53 AW40DDRAB_SDQ54
9,10 MEM_MAB_EVENT# AY41 DDRAB_SDQ55
em em em
M_EVENT_L M_DATA54
em em em
J38 M_DATA55
10 DDRA_CKE0 J34 M0_CKE0 BA38 DDRAB_SDQ56
h h h h h h ch
10 DDRA_CKE1
L34 M0_CKE1 M_DATA56 AY37 DDRAB_SDQ57
Sc c Sc Sc
9 DDRB_CKE0 BA34 DDRAB_SDQ58
Sc Sc Sc
J37 M1_CKE0 M_DATA57
kS
9 DDRB_CKE1 M1_CKE1 M_DATA58 BA33 DDRAB_SDQ59
kS
M_DATA59 AY39 DDRAB_SDQ60
ok ok
AN37
ok ok k
10 DDRA_ODT0 M0_ODT0 M_DATA60 AY38 DDRAB_SDQ61
o
AU38
o
10 DDRA_ODT1
AL34 M0_ODT1 M_DATA61 AY35 DDRAB_SDQ62
o o o
9 DDRB_ODT0 AY34 DDRAB_SDQ63
o o o
B
AN34 M1_ODT0 M_DATA62 B
eb eb eb
9 DDRB_ODT1 M1_ODT1 M_DATA63
eb eb eb
AL35
ot t ot t ot t
10 DDRA_SCS0# M0_CS_L0
AR37
10 DDRA_SCS1# AJ34 M0_CS_L1
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic 0.6V reference voltage
icic
at at at
+1.2V_VDDQ
at at at
2
e m m
EVENT# pull high R4
e mm e mm
e e e
A 1K_0402_1% +MEM_VREF A
hh 15milh h
ch ch
ch
@
Sc c cc c
1
1 2
o o o
Security Classification
o o o
R6
MEM_MAB_EVENT#
eb eb
R5 1K_0402_1% @ C5 C6 Issued Date 2013/02/26 2015/07/08 Title
Deciphered Date
te
@ 1000P_0402_50V7K @ 0.1U_0402_16V7K
ot t ot t te
2 1
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
oLA-E841P
Size Document Number Re v
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS okSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o ooo
+1.8VS
b
o
eb eb eb
+1.8VS +3VS +1.8VS
e
Place resistor(0ohm) for SVT on VRM side
e e
UC1C
ot ot ot
5
t t t
DISPL AY/SVI2 /JTAG/TEST U15
1 2 APU_SVT 2 1 0_0402_5% APU_SVT_R H27 B23 PANEL_BKLEN_EC 1
P
42 APU_SVT APU_SVC_R SVT DP_BLON ENVDD_R NC
R7 R9 2 short@ 1 0_0402_5% E27 B24 @ RC1 4
42 APU_SVC APU_SVD_R SVC DP_DIGON BKL_PWM_CPU_R BKL_PWM_CPU_R Y BKL_PWM_CPU 21
5
1K_0402_5% R10 2 short@ 1 0_0402_5% D27 A24 U16 2.2K_0402_5% 2
APU_SVC 42 APU_SVD SVD DP_VARY_BL A
G
1 @ 2 short@ 1
P
APU_SIC DP_AUX_ZVSS EDP_HPD_R
1
R11 B30 D21 R12 1 2 150_0402_1% NC 4 NL17SZ07DFT2G_SC70-5
APU_SID DP_ZVSS DP0_HPD
3
1K_0402_5% B29 SIC DP_AUX_ZVSS B18 R13 1 2 2K_0402_1% 2 Y SA00004BV00
APU_SVD APU_ALERT# SID DP_ZVSS 21 DP0_HPD A
G
1 @ 2 A30
R14 A31 ALERT_L G15 NL17SZ07DFT2G_SC70-5 +1.8VS
8,27,42 H_PROCHOT#
3
D
1K_0402_5% PROCHOT_L DP0_AUXP H15 EDP_AUXP 21 @ SA00004BV00
D
8,42 APU_PWRGD VDD_33
+1.8VS R15 1 2 300_0402_5% APU_PWRGD G25 DP0_AUXN D15 EDP_HPD_R EDP_AUXN 21
+1.8VS R16 1 2 300_0402_5% APU_RST# D29 PWROK DP0_HPD
RESET_L G17 R17
8 APU_RST# DP1_AUXP
5
H17 DP1_AUXP 22 1 short@ 2 U20
APU_TDI B25 DP1_AUXN D17 DP1_AUXN 22 1
mm mm mm
VDD_33 @
P
+3VS APU_TDO TDI DP1_HPD DP1_HPD 22 0_0402_5% NC
A27 4
co o co o co o
APU_TCK TDO ENVDD_R Y ENVDD 21
B27 G19 SOC_DP1_AUXP 23
2
2 APU_TMS TCK DP2_AUXP A
G
s.s.c s.s.c s.s.c
B26 H19 SOC_DP1_AUXN 23
APU_TRST# A29 TMS DP2_AUXN D19 CRT_HPD_R +3VS NL17SZ07DFT2G_SC70-5
APU_DBRDY
3
A26 TRST_L DP2_HPD
c c c
RC2 @ SA00004BV00
c c c
APU_DBREQ#
i i i
A25 DBRDY A9 1 2
i i i
2.2K_0402_5% ENVDD
at at at
DBREQ_L DP0_TXP0 EDP_TXP0 21
at at at
EC B9 R18
PANEL_BKLEN_EC EDP_TXN0 21
1
3 DP0_TXN0 R30
S
em em em
DP0_TXN1 EDP_TXN1 21
m m m
QC1 MESS138W-G_SOT323-3 A11 R19
CORETYPE 1 @ 2 DP0_TXP2 B11 4.7K_0402_5% 0_0402_5%
e e e
G
BKL_PWM_CPU_R
2
DP0_TXN2 A12 1 2
h h h h
R20
ch ch ch
+1.8VS DP0_TXP3
100K_0402_5% B12 R21
Sc Sc Sc Sc
Sc
DP0_TXN3 4.7K_0402_5%
kS kS kS
A14
ok ok k
DP1_TXP0 APU_DP1_TXP0 22
k
CORETYPE D9 B14
RSVD_1 DP1_TXN0 APU_DP1_TXN0 22
oo
D11 A15
o o
RSVD_2 DP1_TXP1 APU_DP1_TXP1 22
D13 B15
o o o o bobo
+1.8VS RSVD_3 DP1_TXN1 APU_DP1_TXN1 22
E4 A16 HDMI
eb eb
RSVD_4 DP1_TXP2 APU_DP1_TXP2 22
eb eb
100K_0402_5% RP12 E31 B16 VGA R24
PANEL_BKLEN_EC H_PROCHOT# APU_DP1_TXN2 22 CRT_HPD CRT_HPD_R
e
R138 1 2 8 1 H11 RSVD_5 DP1_TXN2 A17 1 short@ 2
ot t ot t ot te
7 2 APU_SID H13 RSVD_6 DP1_TXP3 B17 APU_DP1_TXP3 22 23 CRT_HPD APU_TEST36 1 2
C 100K_0402_5% 0_0402_5% +1.8VS C
ENVDD_R APU_ALERT# RSVD_7 DP1_TXN3 APU_DP1_TXN3 22
1
R139 1 2 6 3 L11 R22
NNo NNo o
APU_SIC RSVD_8
100K_0402_5% 5 4 AE34 A19 R25 1K_0402_5%
NN
EDP_HPD_R RSVD_9 DP2_TXP0 SOC_DP1_P0 23
R140 1 2 AM15 B19 100K_0402_5% 1 2
RSVD_10 DP2_TXN0 SOC_DP1_N0 23
1K_0804_8P4R_5% AM17 A20 DP to VGA Bridge R23
RSVD_11 DP2_TXP1 SOC_DP1_P1 23
AM19 B20 1K_0402_5%
SOC_DP1_N1 23
2
AN8 RSVD_12 DP2_TXN1 A21
RSVD_13 DP2_TXP2 @
AP13 B21
AP15 RSVD_14 DP2_TXN2 A22
AP17 RSVD_15 DP2_TXP3 B22
AR13 RSVD_16 DP2_TXN3
AR15 RSVD_17
AR17 RSVD_18 H29 APU_TEST4
RSVD_19 TEST4 APU_TEST5 T2
@ RP14 AU4 G29 T3
RSVD_20 TEST5 APU_TEST6
8 1 AU13 H25
mm mm mm
APU_TEST17 RSVD_21 TEST6 APU_TEST9 T4
7 2 ESD@ AU15 R32
co o co o co o
APU_TEST16 APU_PWRGD RSVD_22 TEST9 APU_TEST10 T5
6 3 C7 2 1 100P_0402_50V8J AU17 N32 T6
APU_TEST14 RSVD_23 TEST10 APU_TEST14
c c c
T9
c c c
RSVD_26 TEST16 APU_TEST17
i i i
AV13 E23
i i i
T10
at at at
RSVD_27 TEST17 APU_TEST18
at at at
AV15 A28 T11
RSVD_28 TEST18 APU_TEST19
AV17 B28 T12
AY3 RSVD_29 TEST19 N8 APU_TEST28_H
APU_TEST28_L T13
em em em
AY7 RSVD_30 TEST28_H N10
em em em
RSVD_31 TEST28_L APU_TEST31 T14 T15
H31 T16
+1.8VS TEST31 D25 APU_TEST36
h h h
DP_STEREOSYNC/TEST36 APU_TEST41 APU_VDD_SEN 42
B31
Sc Sc Sc
T18
c Sc c Sc
B TEST41 B
T19
kS
APU_VDD_SEN
kS S
D31
VDDCR_CPU_SENSE
ok k
5
E33
ok k k
VDDCR_NB_SENSE APU_VDDNB_SEN 42
o o
D35
G
o o
EC_SMB_CK2 APU_SIC VDDIO_MEM_S3_SENSE VDDIO_MEM_S3_SENCE1
3 4 AM21
o o o
15,23,27 EC_SMB_CK2 VDDP_SENSE1 APU_TCK
o o o
VDDP_SENSE
D
Q1A T306
eb eb eb
2
+1.8VS
eb eb eb
DMN63D8LDW_SOT363-6 D33
VSS_SENSE_A APU_VDD_RUN_FB_L 42 APU_TMS
AM23 RP4
G
VSS_SENSE1 T307
ot t ot t ot t
EC_SMB_DA2 APU_SID VSS_SENSE_B APU_TCK
6 1 1 8
15,23,27 EC_SMB_DA2 APU_TDI APU_TMS
D
Q1B 2 7
1000P_0402_50V7K
C8
T310
1 D1 2 1K_0804_8P4R_5%
EC_SMB_CK2
R123 1 @ 2 1K_0402_5% DB2J31400L_SOD323-2
EC_SMB_DA2 APU_RST#_BUF APU_RST# +1.8VS
R124 1 @ 2 1K_0402_5% T311
1 D2 2
2
DB2J31400L_SOD323-2 RP16
PU at EC side APU_DBRDY
@ 1 8
T312 APU_TRST# 2 7
APU_DBREQ#_R APU_DBREQ# APU_TEST19
T313 1 2 3 6
APU_TEST18 4 5
R32 33_0402_5%
APU_TEST19
T314
1K_0804_8P4R_5%
mm mm mm
+3VALW_EC +1.8VS APU_TEST18 APU_TRST# 1 2
T315
c.o
co c.o
co c.o
co
1
C9
A
s.s s .s R33
s .s APU_TRST# 1 2 APU_TRST#_R
0.01U_0402_16V7K
A
at at 5 at
U8 @
at at at
2
1
P
NC APU_RST#
4
APU_RST#_EC Y
mm mm mm
2
27 APU_RST#_EC A G Compal Secret Data
Security Classification Compal Electronics, Inc.
e
hh e e e NL17SZ07DFT2G_SC70-5
e e 2013/02/26 2015/07/08 Title
ch ch ch
Issued Date Deciphered Date
3
ch ch
SA00004BV00
SATA_USB_LPC_SPI
Sc c c
@
kS kS kS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2 1 0_0402_5%
kS kS kS kS
RH1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
@ Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
NFL-C CTL51 LA-E841P
o o o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
o o o
Date : Thursday, March 09, 2017 Sheet 5 of 48
bobo bo
bo
o o
5 4 3 2 1
ete ete eb eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS okSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
UC1E
CLK/SATA/U SB/SPI/L PC
BA10 AL8
30 SATA_CTX_DRX_P0 AY10 SATA_TX0P USBCLK/25M_48M_OSC
30 SATA_CTX_DRX_N0 SATA_TX0N USB_ZVSS
HDD AN7 R34 1 2 11.8K_0402_1%
AY12 USB_ZVSS
30 SATA_CRX_DTX_N0 SATA_RX0N USB20_P0
BA12 AW1
30 SATA_CRX_DTX_P0 SATA_RX0P USB_HSD0P USB20_N0 USB20_P0 32
AY9 USB_HSD0N
AW2
USB20_N0 32 USB 2.0 (SB) EHCI Port1 : DebugPort
28 SATA_CTX_DRX_P1 BA9 SATA_TX1P AV1 USB20_P1
28 SATA_CTX_DRX_N1 SATA_TX1N USB_HSD1P AV2 USB20_N1 USB20_P1 26
SSD
BA8 USB_HSD1N USB20_N1 26 To SATA
28 SATA_CRX_DTX_N1 SATA_RX1N USB20_P2
AY8 AU1
D 28 SATA_CRX_DTX_P1 SATA_RX1P USB_HSD2P AU2 USB20_N2 USB20_P2 21 TS D
mm mm mm
SATA_ZVSS USB_HSD2N USB20_N2 21
R35 2 1 1K_0402_1% AU11
co o co o co o
SATA_ZVDD SATA_ZVSS USB20_P3
R36 2 1 1K_0402_1% AP11 AT1
+0.95VS SATA_ZVDDP USB_HSD3P USB20_N3 USB20_P3 28 BT
c c c
Camera
c c c
32 SATA_LED# USB20_N4 USB20_P4 21
i i i
AV31 SATA_ACT_L/AGPIO130 USB_HSD4P AR2
i i i
DEVSLP HDD
at at at
DEVSLP_SSD DEVSLP0/EGPIO67 USB_HSD4N USB20_N4 21
at at at
AU31
28 DEVSLP_SSD DEVSLP1/EGPIO70 USB20_P5
AP1
USB_HSD5P AP2 USB20_N5 USB 3.0 (MB) USB20_P5 29
em em em
USB_HSD5N USB20_N5 29
m m m
H2
14 CLK_PCIE_GPU GFX_CLKP USB20_P6
H1 AN1
e e e
14 CLK_PCIE_GPU# GFX_CLKN USB_HSD6P USB20_N6 USB20_P6 29
AN2
Sc Sc Sc Sc
Sc
24 CLK_PCIE_LAN GPP_CLK0P USB20_P7
LAN M1 AM1
24 CLK_PCIE_LAN# GPP_CLK0N USB_HSD7P USB20_N7 USB20_P7 32
kS kS kS
AM2
Card Reader
ok ok k
USB_HSD7N USB20_N7 32
k
L2
GPP_CLK1P
oo
L1
o o
GPP_CLK1N USBSS_ZVSS
W4 R37 1 2 1K_0402_1%
o o o o bobo
USB_SS_ZVSS USBSS_ZVDD
K2 W5 R38 1 2 1K_0402_1%
eb eb
28 CLK_PCIE_WLAN GPP_CLK2P USB_SS_ZVDDP +0.95VALW
eb eb
WLAN K1
28 CLK_PCIE_WLAN#
e
GPP_CLK2N T1
ot t ot t ot te
J2 USB_SS_0TXP T2
J1 GPP_CLK3P USB_SS_0TXN
NNo NNo o
GPP_CLK3N V2
NN
USB_SS_0RXP V1
48M_X1_R EMI@
R66 1 2 33_0402_5% 48M_X1 F2 USB_SS_0RXN
X48M_X1 R1
EC_KBRST# 48M_X2_R EMI@
1 2 R1491 2 33_0402_5% 48M_X2 F1 USB_SS_1TXP R2 USB3_TX1_P 29
X48M_X2 USB_SS_1TXN USB3_TX1_N 29
10K_0402_5% 1 2 R39 DEVSLP HDD
DEVSLP_SSD USB 3.0 (MB)
+3VS 10K_0402_5% 1 2 RH2 W2
SATA_LED# USB_SS_1RXP USB3_RX1_P 29
10K_0402_5% 1 2 RH3 AU27 W1
X25M_48M_OSC USB_SS_1RXN USB3_RX1_N 29
10K_0402_5% @ RH4
P1
USB_SS_2TXP P2 USB3_TX2_P 29
USB_SS_2TXN USB3_TX2_N 29
Y2
USB 3.0 (MB)
mm mm mm
C LPC_CLK0_EC_R USB_SS_2RXP USB3_RX2_P 29 C
R40 1 short@ 2 0_0402_5% BA25 Y1
co o co o co o
8,27 LPC_CLK0_EC 1 2 0_0402_5% LPC_CLK1_R BA24 LPCCLK0/EGPIO74 USB_SS_2RXN USB3_RX2_N 29
R41 EMI@
33 LPC_CLK1 LPCCLK1/EGPIO75
c c c c c c
27,33 LPC_AD1 LAD1 SPI_DO/ESPI_DAT0/EGPIO121 APU_SPI_MISO EC_SPI_SI 27
i i i
AY25 BA17 1 short@ 2 0_0402_5%
i i i
R45
at at at
27,33 LPC_AD2 LAD2 SPI_DI/ESPI_DAT1/EGPIO120 APU_SPI_HOLD# EC_SPI_SO 27
at at at
AY23 BA18
27,33 LPC_AD3 LAD3 SPI_HOLD_L/ESPI_DAT3/EGPIO133 APU_SPI_WP#
OUTPUT BA20
1 2 33_0402_5% LPC_RST_A# AY27 SPI_WP_L/ESPI_DAT2/EGPIO122 AY21 APU_SPI_CS1# 1 short@ 2
R46 R47 0_0402_5%
8,27,33 LPC_RESET# APU_SPI_TPMCS# EC_SPI_CS0# 27
em em em
AY26 LPC_RST_L SPI_CS1_L/EGPIO118 BA21
em em em
27 LPC_CLKRUN_L AC1 LPC_CLKRUN_L/AGPIO88 SPI_TPM_CS_L/AGPIO76
RH5 100K_0402_5%
2 1 27 EC_SMI# AA8 LPC_PD_L/AGPIO21 AY18
h h h ch
VDD_33_S5 1
h h h
27 EC_SCI# LPC_PME_L/AGPIO22 ESPI_ALERT_L/LDRQ0_L EC_KBRST#
BA27 BA30
Sc c ScSc Sc
APU_SPI_CS1#_R EC_KBRST# 27
Sc Sc
1 2 AV27 LPC_SMI_L/AGPIO86 ESPI_RESET_L/KBRST_L/AGPIO129 AY19 C11
CZ-->S0, CZL->S5
kS
27,33 SERIRQ SERIRQ/AGPIO87 SPI_CS2_L/ESPI_CS_L/EGPIO119
kS
C10 150P_0402_50V8J @EMI@ 22P_0402_50V8J
ok ok
2
o o ok o o ok oo
oo k
bb eb eb
A6-9200E_BGA769
te eb eb
+1.8VALW +1.8VS
oROM
8MB SPI te 1 short@ 2
ot t ot t
NNo NNo NNo
APU_SPI_CS1# 1 2 APU_SPI_CS1#_R
R48 0_0402_5% @
1 2 R49 0_0402_5%
R51 @ 0_0402_5%
2
R50
1 APU_SPI_CS1#_R
UC2
48MHz CRYSTAL
APU_SPI_CS1# +1.8VS_ROM
10K_0402_5% 1 8
APU_SPI_CS1# APU_SPI_MISO CS# VCC APU_SPI_HOLD# 48M_X2_R
2 @ 1 2 7
APU_SPI_WP# 3 DO(IO1) HOLD#(IO3) 6 APU_SPI_CLK
R53
WP#(IO2) CLK APU_SPI_MOSI 48M_X1_R
10K_0402_5% 4 5 1 R54 2
2 1 APU_SPI_TPMCS# GND DI(IO0)
1 1M_0402_5%
R55 W25Q64DWSSIG_SO8
10K_0402_5% SA00006ZV10 C12
B
mm mm .1U_0402_16V7K 2
mm 1 B
co co co
@
s.s s .s s .s
icic icic icic
Y1
at at at
48MHZ_8PF_X3S048000D81H-W
at at at
SJ10000AF00
e mm +1.8VS +1.8VALW
e mm e mm 3 4
e e e
3 4
hh ch ch ch
1 1
ch ch
1 short@ 2
Sc c c
R56 0_0402_5% C13 C14
kS kS kS
1 2 4P7_0402_50V8D 4P7_0402_50V8D
kS kS kS kS
R57 @ 0_0402_5% 2 2
2 1 APU_SPI_HOLD#
o o o o o o
bobo bo
bo
o o
R58 10K_0402_5%
APU_SPI_WP#
eb
2 1
e e eb
R59 10K_0402_5%
te te
APU_SPI_CS1#
ot ot ot t
2 1
R60 10K_0402_5%
NN o NN o NNo
mm mm mm
co o co o co o
A A
Sc
Deciphered Date
c SATA_USB_LPC_SPI
c
kS kSkS
S S kSkS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
kk
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 0.1
o o o
NFL-C CTL51 LA-E841P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
o o o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
oo oo oo
Date : Thursday, March 09, 2017 Sheet 6 of 48
eb eb
b
e eb e ebb
5 4 3 2 1
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo +1.2V_VDDQ
NNo NNo
C15
C38
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
UC1G UC1H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GND GND
@ @ @ UC1F AJ31 L13 AC21 AU39
R19 VSS_215 VSS_59 L19 AC23 VSS_120 VSS_182 AW3
POWER
22U_0603_6.3V6M VSS_214 VSS_60 VSS_121 VSS_183
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
180P_0402_50V8J
+1.2V_VDDQ
J35 E9 +APU_CORE_NB
H23 L21 AC25 AW5
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 L32 VDDIO_MEM_S3_1 VDDCR_NB_1 E11 A2 VSS_213 VSS_61 L23 AC27 VSS_122 VSS_184 AW7
L37 VDDIO_MEM_S3_2 VDDCR_NB_2 E13 A8 VSS_1 VSS_62 L25 AC29 VSS_123 VSS_185 AW9
N35 VDDIO_MEM_S3_3 VDDCR_NB_3 E15 A13 VSS_2 VSS_63 L27 AC31 VSS_124 VSS_186 AW11
R37 VDDIO_MEM_S3_4 VDDCR_NB_4 E17 A18 VSS_3 VSS_64 L29 AC38 VSS_125 VSS_187 AW13
D VDDIO_MEM_S3_5 VDDCR_NB_5 VSS_4 VSS_65 VSS_126 VSS_188 D
U32 E19 A23 L31 AC39 AW15
mm mm mm
U35 VDDIO_MEM_S3_6 VDDCR_NB_6 G7 A32 VSS_5 VSS_66 L39 AC41 VSS_127 VSS_189 AW17
co o co o co o
W32 VDDIO_MEM_S3_7 VDDCR_NB_7 J7 A35 VSS_6 VSS_67 L41 AE3 VSS_128 VSS_190 AW19
VDDIO_MEM_S3_8 VDDCR_NB_8 VSS_7 VSS_68 VSS_129 VSS_191
ic c ic c i c c
AC37 VDDIO_MEM_S3_11 VDDCR_NB_11 K17 B32 VSS_10 VSS_71 N39 AG3 VSS_132 VSS_194 AW27
i i i
at at at
VDDIO_MEM_S3_12 VDDCR_NB_12 VSS_11 VSS_72 VSS_133 VSS_195
at at at
AE32 K19 B39 R3 AG7 AW29
AE35 VDDIO_MEM_S3_13 VDDCR_NB_13 L7 C3 VSS_12 VSS_73 R11 AG10 VSS_134 VSS_196 AW31
+1.2V_VDDQ VDDIO_MEM_S3_14 VDDCR_NB_14 VSS_13 VSS_74 VSS_135 VSS_197
AG32 L10 C5 R13 AG11 AW33
em em em
VDDIO_MEM_S3_15 VDDCR_NB_15 VSS_14 VSS_75 VSS_136 VSS_198
C33
C89
C90
C91
C92
C93
m m m
AG37 L15 C7 R15 AG13 AW35
AJ32 VDDIO_MEM_S3_16 VDDCR_NB_16 L17 C9 VSS_15 VSS_76 R17 AG15 VSS_137 VSS_199 AW37
e e e
1 1 1 1 1 1 VDDIO_MEM_S3_17 VDDCR_NB_17 VSS_16 VSS_77 VSS_138 VSS_200
AJ35 N7 C11 R21 AG17 AW39
h h h h
ch ch ch
AL32 VDDIO_MEM_S3_18 VDDCR_NB_18 N11 C13 VSS_17 VSS_78 R23 AG19 VSS_139 VSS_201 AW41
Sc Sc Sc Sc
Sc
+1.8VS VDDIO_MEM_S3_19 VDDCR_NB_19 VSS_18 VSS_79 VSS_140 VSS_202
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
180P_0402_50V8J
180P_0402_50V8J
AL37 N13 C15 R25 AG21 AY1
To Power VDDIO_MEM_S3_20 VDDCR_NB_20 VSS_19 VSS_80 VSS_141 VSS_203
kS kS kS
2 2 2 2 2 2 AR35 N15 C17 R27 AG23 AY11
ok ok k
VDDIO_MEM_S3_21 VDDCR_NB_21 VSS_20 VSS_81 VSS_142 VSS_204
k
N17 C19 R29 AG25 BA7
VDDCR_NB_22 VSS_21 VSS_82 VSS_143 VSS_205
oo
RC3 1 short@ 2 0_0402_5% N19 C21 R31 AG27 BA11
o o
APU_VDDIO 42 VDDCR_NB_23 VSS_22 VSS_83 VSS_144 VSS_206
K21 R7 C23 R39 AG29 BA15
o o bo
+APU_CORE
o o bo
K23 VDDCR_CPU_1 VDDCR_NB_24 U7 C25 VSS_23 VSS_84 R41 AG31 VSS_145 VSS_207 BA19
eb eb
VDDCR_CPU_2 VDDCR_NB_25 VSS_24 VSS_85 VSS_146 VSS_208
eb eb
K25 U11 C27 U1 AG39 BA23
e
K27 VDDCR_CPU_3 VDDCR_NB_26 U13 C29 VSS_25 VSS_86 U2 AG41 VSS_147 VSS_209 BA31
ot t ot t ot te
K29 VDDCR_CPU_4 VDDCR_NB_27 U15 C31 VSS_26 VSS_87 U3 AJ3 VSS_148 VSS_210 BA35
DIMMS/GND K31 VDDCR_CPU_5 VDDCR_NB_28 U17 C33 VSS_27 VSS_88 U10 AJ5 VSS_149 VSS_211 BA39
NNo NNo o
N21 VDDCR_CPU_6 VDDCR_NB_29 U19 C35 VSS_28 VSS_89 U39 AJ10 VSS_150 VSS_212
NN
N23 VDDCR_CPU_7 VDDCR_NB_30 U21 C37 VSS_29 VSS_90 W3 AJ29 VSS_151
N25 VDDCR_CPU_8 VDDCR_NB_31 W7 C39 VSS_30 VSS_91 W10 AJ39 VSS_152
FOR DEBUG ONLY N27 VDDCR_CPU_9 VDDCR_NB_32 AA11 C41 VSS_31 VSS_92 W11 AL1 VSS_153
R61 N29 VDDCR_CPU_10 VDDCR_NB_33 AA13 E1 VSS_32 VSS_93 W13 AL2 VSS_154
1 short@ 2 N31 VDDCR_CPU_11 VDDCR_NB_34 AA15 E2 VSS_33 VSS_94 W15 AL3 VSS_155
+3VS +3VS_APU VDDCR_CPU_12 VDDCR_NB_35 VSS_34 VSS_95 VSS_156
+1.8VS +1.8VS
U23 AA17 E3 W17 AL7
VDDCR_CPU_13 VDDCR_NB_36 VSS_35 VSS_96 VSS_157
C39
C41
C42
C43
C44
C45
1 1 1 U29 AA23 E29 W23 AL39
U31 VDDCR_CPU_16 VDDCR_NB_39 AE11 E35 VSS_38 VSS_99 W25 AL41 VSS_160
1 1 1 VDDCR_CPU_17 VDDCR_NB_40 VSS_39 VSS_100 VSS_161
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
mm mm mm
C VDDCR_CPU_19 VDDCR_NB_42 VSS_41 VSS_102 VSS_163 C
2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AA29 AE17 G1 W31 AM29
co o co o co o
2 2 2 AA31 VDDCR_CPU_20 VDDCR_NB_43 AE19 G2 VSS_42 VSS_103 W39 AM31 VSS_164
VDDCR_CPU_21 VDDCR_NB_44 VSS_43 VSS_104 VSS_165
c c c
+VDDCR_FCH_ALW
c c c
VDDCR_FCH_S5_1 VDDCR_NB_47 VSS_46 VSS_107 VSS_168
i i i
AR5 AE27 G23 AA3 AR3
i i i
at at at
VDDCR_FCH_S5_2 VDDCR_NB_48 VSS_47 VSS_108 VSS_169
at at at
AR7 AE29 G27 AA5 AR11
AU7 VDDCR_FCH_S5_3 VDDCR_NB_49 AE31 G31 VSS_48 VSS_109 AA10 AR19 VSS_170
VDDCR_FCH_S5_4 VDDCR_NB_50 G35 VSS_49 VSS_110 AA39 AR23 VSS_171
em em em
AJ11 G37 VSS_50 VSS_111 AC3 AR27 VSS_172
em em em
+0.95VALW VDDP_S5_1 VSS_51 VSS_112 VSS_173
AL11 AJ15 G39 AC7 AR31
0.8A AL13 VDDP_S5_2 VDD_18_1 AL17
+1.8VS
G41 VSS_52 VSS_113 AC10 AR39 VSS_174
1.5A
h h h h h h ch
VDDP_S5_3 VDD_18_2 J3 VSS_53 VSS_114 AC11 AR41 VSS_175
Sc Sc Sc
+3VALW +1.8VALW +VDDCR_FCH_ALW
c Sc Sc Sc
AJ13 J8 VSS_54 VSS_115 AC13 AU3 VSS_176
+1.8VALW
kS
VDD_18_S5_1 VSS_55 VSS_116 VSS_177
C46
C47
C48
C49
C50
C51
C52
kS
AJ21 AL15 J39 AC15 AU9
+0.95VS_APU_GFX VDDP_1 VDD_18_S5_2 0.5A VSS_56 VSS_117 VSS_178
ok ok
AJ23 L3 AC17 AU21
ok ok k
1 1 1 1 7A 1 1 1 VDDP_2 VSS_57 VSS_118 VSS_179
o
AJ25 AJ19 L8 AC19 AU25
o
VDDP_3 VDD_33_1 +3VS_APU VSS_58 VSS_119 VSS_180
AJ27 AL21 AU29
0.2A
o o o o o o
VDDP_4 VDD_33_2 VSS_181
10U_0603_6.3V6M
0.22U_0402_10V6K
10U_0603_6.3V6M
0.22U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
AL23
b bb eb
2 2 2 2 2 2 2 VDDP_5
b eb
AL25 AJ17 +3VALW
VDDP_6 VDD_33_S5_1
ee e
AL27 AL19
0.2A
e
ot t ot t ot t
AL29 VDDP_7 VDD_33_S5_2 A6-9200E_BGA769 A6-9200E_BGA769
VDDP_8
1
VDDIO_AUDIO
CC9 +1.8VS RC4 1 short@ 2 0_0402_5%
0.22U_0402_6.3V6K
+0.95VALW/+0.95VS OF APU +VDDP_VS 2 +APU_CORE_NB
C53
C55
C54
C56
C57
B
mmVDD_095_GFX VDD_095
mm mm 1 1 1 1 1 B
c.o
co c.o
co c.o co
+0.95VS +0.95VS_APU_GFX +RTCVCC +RTCBATT
+VDDP_ALW W>=15mils
.s .s .s
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
L1 U10 W>=15mils
s s s
2 1 AP2138N-1.5TRG1_SOT23-3 DC1 2 2 2 2 2
at at at
C58
C59
C60
C61
C62
C63
10K_0402_5% 1 1 1K_0402_5%
at at at
2 Vin 3
20mils
1 1 1 1 1 1 GND +3VLP
1
mm mm mm
BAV70W_SOT323-3 JRTC1
+
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
0.22U_0402_10V6K
e e e
LOTES_AAA-BAT-054-K01
e e e
2 2 2 2 2 2
L DC3 close to UCPU1
hh ch hh ch
SA000066U00 CONN@
ch
2
Sc Sc
SP07000H700
c Sc c
JC1 1
2
kS kSkS kSkS
@
k
JUMP_43X39 CC10
k
1
o oo o
1U_0402_16V6K
o o
2
bo bo o
1
e bo e eb
o
eb eb
o
-
ot te t t ot t
+0.95VS_APU_GFX
2
o oo
NNo
+0.95VS_APU_GFX
C64
C65
C66
C67
C68
C69
NN NN
C70
C71
1 1 1 1 1 1
1 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
180P_0402_50V8J
2 2 2 2 2 2
10U_0603_6.3V6M
0.22U_0402_10V6K
2 2
Under APU
mm mm mm
co o co o co o
A A
Sc c ch ScSc c
Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title
kS kSkS kSkS
POWER & DECOUPLING
o ok k
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
o
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
o o o
Custom 0.1
NFL-C CTL51 LA-E841P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
oo oo oo
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
eb b b
Date : Thursday, March 09, 2017 Sheet 7 of 48
eb e eb e eb
5 4 3 2 1
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
+3VS
ot t ot t ot t
NNo NNo NNo
UC1D
2
ACPI/SD /AZ/GPIO/R TC /MISC
APU_PCIE_RST#_C
AE4 BA28 R65 PX@
PCIE_RST_L/EGPIO26 SD_WP/EGPIO101 AY29 VGA_CORE_EN
OUTPUT
EC_RSMRST#_R SD_PWR_CTRL/AGPIO102 VGA_CORE_EN 44 10K_0402_5%
RH7 2 @ 1 0_0402_5% AG1 AY13 AGPIO25 R62 1 @ 2 0_0402_5%
VGATE 27,34,42 RSMRST_L SD_CD/AGPIO25 H_PROCHOT# 5,27,42
BA14 T20
APU_FCH_PWRGD ODD_PWR_R
2 ODD_PWR
1
RH8 1 short@ 2 0_0402_5% AD2 SD_CLK/EGPIO95 AY15 RT1 1 short@
APU_FCH_POK 27 +3VALW 27 PBTN_OUT# APU_FCH_PWRGD_R PWR_BTN_L/AGPIO0 SD_CMD/EGPIO96 DGPU_PWR_EN ODD_PWR 30 UMA: LOW
AE2 BA29 0_0402_5% AGPIO85
SYS_RESET_L AF1 PWR_GOOD SD_LED/EGPIO93 DGPU_PWR_EN 16,27,44,46 DIS: HIGH
APU_PCIE_WAKE#_R SYS_RESET_L/AGPIO1
2
@ESD@ T21 AE7 AY14 T22
CH1 100P_0402_50V8J WAKE_L/AGPIO2 SD_DATA0/EGPIO97 BA13 R67 UMA@
APU_FCH_PWRGD SD_DATA1/EGPIO98 T23
2 1 BA16 T24 SD no used can NC 10K_0402_5%
SLP_S3#_R SD_DATA2/EGPIO99
D
AC2 AY16 T25 D
SLP_S5#_R AG4 SLP_S3_L SD_DATA3/EGPIO100
mm mm mm
CE23 close to UC1
1
S0A3 AB1 SLP_S5_L
co o co o co o
S5_MUX_CTRL S0A3_GPIO/AGPIO10 APU_SCLK0
AA7 AY33
I/O 34 S5_MUX_CTRL S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 APU_SDATA0 APU_SCLK0 9,10
c c c
R63 AGPIO8 10K_0402_5%
c c c
2 15K_0402_5% APU_TEST1 APU_SMB_SDATA1 APU_SMB_SCLK1 31
i i i
+3VALW_EC +1.8VALW +3VALW +3VS 1 AE1 TEST0 SCL1/I2C3_SCL/AGPIO19 AC4
i i i
R69
at at at
2 15K_0402_5% APU_TEST2 TEST1/TMS SDA1/I2C3_SDA/AGPIO20 APU_SMB_SDATA1 31
at at at
R70 1 AC8
TEST2
1
1
@
em em em
MEM_VOLT_SEL VGA_CORE_EN
m m m
R71 @ R73 VDD_33_S5 AH2 AJ7 High 10K_0402_5% 2 1 R74
30 ODD_PLUG# AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO3 SERR#_R
4.7K_0402_5% 4.7K_0402_5% VDD_33_S5 AA4 AK2 R75 2 1 0_0402_5% SERR#
e e e
21 TS_GPIO_SOC IR_TX0/USB_OC5_L/AGPIO13 AGPIO4 ODD_DA# SERR# 27
AG8 AK1
h h h h
R72 VDD_33_S5 short@
ch ch ch
APU_RST#_R APU_RST# ODD_DA# 30
2
2
4.7K_0402_5% AL5 IR_TX1/USB_OC6_L/AGPIO14 AGPIO5 AL4 R76 1 @ 2 0_0402_5%
Sc
VDD_33_S5/OD28
Sc Sc Sc
APU_RST# 5
Sc
APU_WL_OFF# IR_RX1/AGPIO15 AGPIO6/LDT_RST_L APU_PWRGD_R APU_PWRGD
5
kS kS kS
1 AJ4 AGPIO8 ESD@
P
ok ok k
NC APU_FCH_PWRGD_R AGPIO8
k
4 AG5 SERR# C72 2 1 100P_0402_50V8J
APU_FCH_PWRGD Y LAN_CLKREQ# AGPIO9
oo
2 AY32 AD1
o o
A 24 LAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40
G
AY31
o o o o bobo
WLAN_CLKREQ# CLK_REQ1_L/AGPIO115
NL17SZ07DFT2G_SC70-5 AV29
eb eb
28 WLAN_CLKREQ#
3
CLK_REQ2_L/AGPIO116
eb eb
SA00004BV00 AP31
VGA_CLKREQ#
e
AV35 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 AJ8
te
@ AGPIO11
ot t ot t ot
15 VGA_CLKREQ# CLK_REQG_L/OSCIN/EGPIO132 BLINK/USB_OC7_L/AGPIO11 AR29 HVB_FUNCTION
RH9 1 short@ 2 0_0402_5%
GENINT2_L/AGPIO90 AP29
NNo NNo o
USB_OC0#
AB2 SPKR/AGPIO91 AU35 EC_GA20 APU_SPKR 25
NN
USB_OC1# AG2 USB_OC0_L/TRST_L/AGPIO16 GA20IN/AGPIO126 EC_GA20 27
CH2 @ 0.1U_0402_16V7K
+3VALW AJ1 USB_OC1_L/TDI/AGPIO17 AV33 1 2
28 APU_BT_ON# USB_OC2_L/TCK/AGPIO18 FANIN0/AGPIO84
AH1 AU33 AGPIO85
44 GPU_PGD USB_OC3_L/TDO/AGPIO24 FANOUT0/AGPIO85
2
1 T2722–
33Ω (± 5
%) BA5 AV25
33Ω (± 5
%) HDA_RST# 22– 33Ω (± 5
%) AY4 AZ_SDIN2/I2S_DATA_PLAYBACK UART0_TXD/EGPIO138 AU23 VDDP_ALW_VCTRL SLP_S5#_R 1 short@ 2
R112 T28
1 2 10K_0402_5% PBTN_OUT# 22– 33Ω (± 5
%) HDA_SYNC BA3 AZ_RST_L/I2S_LR_MIC UART0_INTR/AGPIO139 1 2 HDA_RST# SLP_S5# 27
R79 @EMI@C73 10K_0402_5% RH11 0_0402_5%
HDA_SDOUT AZ_SYNC/I2S_BCLK_PLAYBACK HDA_BITCLK
@ 22– 33Ω (± 5
%) BA4 AP21 R80 1 2 1K_0402_5%
mm mm mm
C 22P_0402_50V8J AZ_SDOUT/I2S_DATA_MIC1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140 HDA_SYNC C
2 AV21 R81 1 2@ 1K_0402_5%
co o co o co o
HDA_SDOUT
1
UART1_RXD/BT_I2S_SDI/EGPIO141 AP19 R82 1 2 1K_0402_5%
UART1_RTS_L/EGPIO142
c c c c c c
HVB_FUNCTION APU_I2C1_SCL_TP I2C0_SDA/EGPIO146
i i i
R84 1 2 10K_0402_5% AU19
i i i
at at at
APU_I2C1_SDA_TP I2C1_SCL/EGPIO147
at at at
@ AV19 AP27
ODD_DA# I2C1_SDA/EGPIO148 HVBEN_L
R85 1 2 10K_0402_5%
@
RTC_CLK
em em em
AN4
em em em
RTCCLK
32K_X1 BA2
h h h h h h ch
X32K_X1
Sc c ScSc ScSc kS Sc
kS
32K_X2
ok ok
AY2
ok ok k
X32K_X2
o
RP7
o
HDA_RST#
1 8
o o o
25 HDA_RST_AUDIO# HDA_SYNC
o o o
2 7
eb eb eb
25 HDA_SYNC_AUDIO HDA_SDOUT
eb eb eb
3 6 For PCIE device reset on FS1
25 HDA_SDOUT_AUDIO +3VS A6-9200E_BGA769 +3VALW
4 5 (GFX,GLAN,WLAN,LVDS Travis)
ot t ot t ot t
CH3 @
33_0804_8P4R_5% +1.8VALW APU_PCIE_RST #: Reset PCIE device on APU 1 2
5
R148 1 @ 2 MC74VHC1G08DFT2G SC70 5P
2
10K_0402_5% RH13 2
P
APU_TEST0 APU_PCIE_RST#_C B
1
R86 1 @ 2 2.2K_0402_5% RH12 1 short@ 2 0_0402_5% RC900 1 2 4
APU_TEST2 Y PLT_RST_BUF# 14,24,28
R88 1 @ 2 2.2K_0402_5% R87 10K_0402_5% 33_0402_5% 1
APU_TEST1 A
G
R89 1 @ 2 1K_0402_5% 47K_0402_5% UH1 QCL10 LAN-APU,WLAN&ExCARD-FCH 20110803
8.2K_0402_5%
X76@
2
1
150P_0402_50V8J
1
1
@ @
CH4
RH14
EC_RSMRST# @ EC_RSMRST#_R VRAMCLK_SEL 1000MHz:HIGH
2
1 2 RH15
27 EC_RSMRST#
D3 900MHz:LOW @ 0_0402_5%
2
RB751V-40 SOD-323 2
1
+1.8VS +3VS RC901
mm mm mm
2
B RP8 RB751 Max Vf=0.37V 10K_0402_5% B
co co co
1 8 2
2 7 APU_SCLK0 X76@ LPC_RESET# 6,27,33
UMA@ RSMRST# C74
.s .s .s
VGA_CLKREQ#
1
3 6 +3VALW R90 1 2 1.8V /EC program to 1.8V OUTPUT EMI@
s 4 5 10K_0402_5%
s Check RSMRST delay 10ms .1U_0402_16V7K
s
icic icic cic
1
LAN_CLKREQ#
it
at at at
2.2K_0804_8P4R_5% R113 1 2
at at
EC_GA20
R114 1 10K_0402_5%
2
a
+1.8VS WLAN_CLKREQ#
R117 1 10K_0402_5%
2 GEVENT2_L ???? RTC_CLK BLINK/GPIO11 SYS_RST#
mm mm mm
R137 1 10K_0402_5%
2 S0A3 LPC_CLK0_EC LPC_CLK1 LPC_FRAME#
APU_I2C1_SCL_TP <INT PU> <INT PU> <INT PU> <INT PU>
e e e
2 R143 1 10K_0402_5%
hh e 10K_0402_5%
e e CZL CZ LDT_RST#/PG
ch H ch ch
APU_I2C1_SDA_TP
ch h
2 R144 1 +1.8VS +1.8VS BOOT FAIL CLKGEN SPI ROM COIN BATT NORMAL
OUTPUT TO
Sc c c c
10K_0402_5% TIMER ENABLE (DEFAULT) 1.8V SPI ROM ENHANCED ON BOARD APU RESET MODE
HDA_SDIN1
kS S kS
2 R145 1
kS kS S kS
ENABLED (DEFAULT) (Default) RESET (DEFAULT) (DEFAULT) (DEFAULT)
2
2
k
10K_0402_5%
k
2 R146 1 HDA_SDIN2 +1.8VS (AOAC)
o oo o
TS@ @
o o
10K_0402_5% RC8 RC10 BOOT FAIL
bobo bo o L o o
10K_0402_5% 10K_0402_5% TIMER CLKGEN TRADITION COIN BATT OUTPUT SHORT RST
eb eb eb
ID_1 ID_2 DISABLED DISABLED LPC ROM 3.3V SPI ROM RESET NOT ON TO PADS MODE
1
1
2
ot t ot t
R91 R92
t
2
2
oo
10K_0402_5% 10K_0402_5%
+3VALW
NN o APU_I2C0_SDA_TS
nTS@
RC11 RC13
@
NN
+3VS +3VALW
NNo
1
1
10K_0402_5% 10K_0402_5%
APU_I2C0_SCL_TS
@
USB_OC0#
1
2
100K_0402_5%
6,27,33 LPC_FRAME#
6,27 LPC_CLK0_EC
32.768KMHz CRYSTAL APU THERMAL SENSOR 6 LPC_CLK1_R MEM_VOLT_SEL
RTC_CLK
32K_X1 SYS_RESET_L
Thermal sensor SMBus address -->100-1_000xb : 0x48
mm 32K_X2
mm (x=0)Write Address(0x98h)
mm AGPIO11
co o co o co o
A
2 1 (x=1)Read Address(0x99h) A
1
10M_0402_5% R100
c c c
SMBCLK SMBDATA EC_SMB_DA3 27
i ic i ic i ic
Y2 32.768KHZ_12.5PF_1TJF125BJ1A000 27 EC_SMB_CK3 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
at at at
1 2 2
at at at
2
GND
2 1 THERMAL_ALERT#_R 3 4
1 SJ10000OA00 1 +3VS +3VS
ALERT# +Vs
mm mm Compal m
0.1U_0201_10V6K
e e
27P_0402_50V8J 27P_0402_50V8J
e e
1 2 G753T11U_SOT23-5
1
CC11
e e m
Secret Data
Security Classification Compal Electronics, Inc.
hh ch ch ch
27 THERMAL_ALERT#
ch ch
2 2 R150 @ 0_0402_5% 2013/02/26 2015/07/08 Title
Issued Date
Sc
Deciphered Date
c GEVENT_GPIO_SD
c
kS S kS
2
kS kS S kS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
kk
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 0.1
o o o
NFL-C CTL51 LA-E841P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
o o o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
oo oo oo
Date : Thursday, March 09, 2017 Sheet 8 of 48
eb eb
b
e eb e ebb
5 4 3 2 1
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b ooo o
b oo
o o
b ooo o
b eb eb
Stoney JDIMM1 ot
NNo
e
t e
REVERSE TYPE
JDIMM1B CONN@
ot
NNo
e
t 4
4
4
4
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
137
139
138
140
JDIMM1A
CK0(T)
CK0#(C)
CK1(T)
CK1#(C)
CONN@
STD
DQ0
DQ1
DQ2
DQ3
8
7
20
21
DDRAB_SDQ4
DDRAB_SDQ0
DDRAB_SDQ2
DDRAB_SDQ7
DDRAB_SDQ5
ot
NNo
et
DDRAB_SDQ[63..0] 4,10
STD 4
111 141 109 DQ4 3 DDRAB_SDQ1
+1.2V_VDDQ 112 VDD1 VDD11 142
+1.2V_VDDQ 4 DDRB_CKE0
110 CKE0 DQ5 16 DDRAB_SDQ3
117 VDD2 VDD12 147 4 DDRB_CKE1 CKE1 DQ6 17 DDRAB_SDQ6
+3VS +3VS_DA 118 VDD3 VDD13 148 149 DQ7 13
VDD4 VDD14 4 DDRB_SCS0# S0# DQS0(T) DDRAB_SDQS0 4,10
short@ 123 153 157 11
VDD5 VDD15 4 DDRB_SCS1# S1# DQS0#(C) DDRAB_SDQS0# 4,10
1 2 124 154 162
co o co o co o
D VDD7 VDD17 S3#/C1 DQ8 DDRAB_SDQ9 D
+3VS +3VS +3VS 130 160 29
c c c
VDD10 4 DDRB_ODT1 ODT1 DQ11 DDRAB_SDQ12
1
1
i c i c i c
@ @ 24
i i i
at at at
DQ12 DDRAB_SDQ13
at at at
RD2 RD3 RD4 255 258 115 25
10K_0402_5% 10K_0402_5% 10K_0402_5% VDDSPD VTT +0.6VS_VTT 4,10 DDRAB_SBS2# 113 BG0 DQ13 38 DDRAB_SDQ10
4,10 DDRAB_SMA14 BG1 DQ14 DDRAB_SDQ15
0.1U_0201_10V6K
164 257 150 37
2.2U_0402_6.3V6M
em em em
+0.6V_DDR_VREFCA +2.5V
m m m
VREFCA VPP1 4,10 DDRAB_SBS0# BA0 DQ15
2 2 259 145 34
4,10 DDRAB_SBS1# DDRAB_SDQS1 4,10
e e e
2
2
SA0_DIM1 SA1_DIM1 SA2_DIM1 VPP2 BA1 DQS1(T) 32
h h h h
DDRAB_SDQS1# 4,10
ch c ch ch
DQS1#(C)
CD1
CD2
1 99 144
Sc Sc Sc
Sc
2 VSS VSS 102 4,10 DDRAB_SMA0 133 A0 50 DDRAB_SDQ21
kS
VSS VSS 4,10 DDRAB_SMA1 A1 DQ16 DDRAB_SDQ20
kS kS kS
1
1
@ 1 1 5 103 132 49
ok k
VSS VSS 4,10 DDRAB_SMA2 A2 DQ17 DDRAB_SDQ22
k
RD5 RD6 RD7 6 106 131 62
o oo
VSS VSS 4,10 DDRAB_SMA3 A3 DQ18 DDRAB_SDQ18
o o
10K_0402_5% 10K_0402_5% 10K_0402_5% 9 107 128 63
o o bo
VSS VSS 4,10 DDRAB_SMA4 A4 DQ19 DDRAB_SDQ16
b bo o bo
10 167 126 46
4,10 DDRAB_SMA5 DDRAB_SDQ17
eb
VSS VSS A5 DQ20
PLACE NEAR TO PIN 14 168
eb
127 45
4,10 DDRAB_SMA6
2
2
VSS VSS A6 DQ21 DDRAB_SDQ19
e e
15 171 122 58
ot te ot t ot te
VSS VSS 4,10 DDRAB_SMA7 A7 DQ22 DDRAB_SDQ23
18 172 125 59
VSS VSS 4,10 DDRAB_SMA8 A8 DQ23
o NNo o
19 175 121 55
VSS VSS 4,10 DDRAB_SMA9 A9 DQS2(T) DDRAB_SDQS2 4,10
NSODIMM NN
22 176 146 53
N 23 VSS VSS 180 4,10 DDRAB_SMA10 120 A10_AP DQS2#(C) DDRAB_SDQS2# 4,10
PLACE ALL THE BELOW RESISTORS CLOSE TO 26 VSS VSS 181 4,10 DDRAB_SMA11 119 A11 70 DDRAB_SDQ29
27 VSS VSS 184 4,10 DDRAB_SMA12 158 A12 DQ24 71 DDRAB_SDQ24
VSS VSS 4,10 DDRAB_SMA13 A13 DQ25 DDRAB_SDQ27
30 185 151 83
VSS VSS 4,10 DDRAB_SWE# A14_WE# DQ26 DDRAB_SDQ31
31 188 156 84
35 VSS VSS 189 4,10 DDRAB_SCAS# 152 A15_CAS# DQ27 66 DDRAB_SDQ28
VSS VSS 4,10 DDRAB_SRAS# A16_RAS# DQ28 DDRAB_SDQ25
36 192 67
SPD ADDRESS FOR CHANNEL B : 39 VSS
VSS
VSS
VSS
193
4,10 DDRAB_SMA15
114
ACT#
DQ29
DQ30
79 DDRAB_SDQ30
DDRAB_SDQ26
40 196 80
SA0 = 1; SA1 = 0; SA2 = 0. VSS VSS DDR_B_PAR DQ31
mm mm mm
43 197 143 76
44 VSS VSS 201 DDR_B_ALERT# 116 PARITY DQS3(T) 74 DDRAB_SDQS3 4,10
co o co o co o
47 VSS VSS 202 134 ALERT# DQS3#(C) DDRAB_SDQS3# 4,10
c c c c c c
VSS VSS DQ33 DDRAB_SDQ35
i i i
52 209 187
i i i
at at at
VSS VSS DQ34 DDRAB_SDQ38
at at at
C 56 210 254 186 C
VSS VSS 8,10 APU_SDATA0 SDA DQ35 DDRAB_SDQ37
57 213 253 170
VSS VSS 8,10 APU_SCLK0 SCL DQ36 DDRAB_SDQ32
60 214 169
mm em em
em em
61 VSS VSS 217 SA2_DIM1 166 DQ37 183 DDRAB_SDQ34
h e e Note: h
64 VSS VSS 218
h
SA1_DIM1 260 SA2 DQ38 182 DDRAB_SDQ39
h h h ch
65 VSS VSS 222 SA0_DIM1 256 SA1 DQ39 179
Sc Sc Sc
Layout Layout Note:
c Place near JDIMM1.257,259 Sc Sc Sc
68 VSS VSS 223 SA0 DQS4(T) 177 DDRAB_SDQS4 4,10
kS
Place near JDIMM1.258
kS
69 VSS VSS 226 DQS4#(C) DDRAB_SDQS4# 4,10
ok ok okok k
72 VSS VSS 227 92 195 DDRAB_SDQ41
o o
73 VSS VSS 230 91 CB0_NC DQ40 194 DDRAB_SDQ45
o o o
VSS VSS CB1_NC DQ41 DDRAB_SDQ42
o o o
77 231 101 207
10uF*2 b b
eb eb
VSS VSS CB2_NC DQ42 DDRAB_SDQ43
eb eb
78 234 105 208
ee
+2.5V +0.6VS_VTT 81 VSS VSS 235 88 CB3_NC DQ43 191 DDRAB_SDQ44
10uF*2
ot t ot t ot t
VSS VSS CB4_NC DQ44 DDRAB_SDQ40
1uF*2 1uF*1 82 238 For ECC DIMM 87 190
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 1 1 1 1 89 244 97 200
90 VSS VSS 247 95 DQS8(T) DQS5(T) 198 DDRAB_SDQS5 4,10
VSS VSS DQS8#(C) DQS5#(C) DDRAB_SDQS5# 4,10
CD3
CD4
CD5
CD6
CD7
CD8
CD9
93 248
94 VSS VSS 251 216 DDRAB_SDQ49
2 2 2 2 2 2 2 98 VSS VSS 252 4,10 DDRAB_SDM[7..0] DDRAB_SDM0 12 DQ48 215 DDRAB_SDQ52
VSS VSS DDRAB_SDM1 33 DM0#/DBI0# DQ49 228 DDRAB_SDQ55
262 261 DDRAB_SDM2 54 DM1#/DBI1# DQ50 229 DDRAB_SDQ50
GND GND DDRAB_SDM3 75 DM2#/DBI2# DQ51 211 DDRAB_SDQ48
DDRAB_SDM4 178 DM3#/DBI3# DQ52 212 DDRAB_SDQ53
DDRAB_SDM5 DM4#/DBI4# DQ53 DDRAB_SDQ54
mm mm+1.2V_VDDQ mm
FOX_AS0A827-H2RB-7H 199 224
DDRAB_SDM6 DM5#/DBI5# DQ54 DDRAB_SDQ51
co co co
DDRAB_SDM7 241 DM6#/DBI6# DQ55 221
icic
tnear icic icic 1K_0402_5%
at JDIMM1. 164 at
at at
at
1 2 DDR_B_ALERT#
Layout Note: RZ1
PLACE THEa 1 short@ 2 DDR_B_PAR 237 DDRAB_SDQ57
CAP RZ2
+1.2V_VDDQ DQ56 DDRAB_SDQ61
mm mm mm
236
0_0402_5% DQ57 DDRAB_SDQ58
e e e
249
e e e
DQ58 DDRAB_SDQ63
hh ch ch ch
B 250 B
ch ch
DQ59 DDRAB_SDQ60
Sc
232
c c
DQ60 DDRAB_SDQ56
kS kS kS
RF@ RF@ RF@ RF@ 233
kS kS kS kS
DQ61 245 DDRAB_SDQ59
2 C77 2 C78 2 C79 2 C80 DQ62 DDRAB_SDQ62
+0.6V_DDR_VREFCA
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1000pF*1 246
o o o o
DQ63 242
o o
bo bo o
0.1uF*1
bo bo o
DQS7(T) 240 DDRAB_SDQS7 4,10
eb
DDRAB_SDQS7# 4,10
eb
1 1 1 1 DQS7#(C)
e e
2 2
CD10 CD11
oto te ot
o te ot t
NNo
0.1U_0201_10V6K 1000P_0402_50V7K FOX_AS0A827-H2RB-7H
NN NN+1.2V_VDDQ
1 1
DIMM Side
2
Layout Note: RD8 +0.6V_DDR_VREFCA
mm
Place near JDIMM1
mm 2@
mm
1K_0402_1%
co o co o co o
CD12
1
1
c
titic 10uF*6 c
i ic c
i ic
+1.2V_VDDQ a a 1uF*8 at at at
at
mm mm mm
+1.2V_VDDQ 2
330uF*1
2
e e e
+1.2V_VDDQ
hh e e e
ch ch ch
RD9 CD13
c
S Sc ch ch c
1K_0402_1% 0.1U_0201_10V6K
1
kS kS kS
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
kS kS kS
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
k
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
o o o
CD14
CD15
CD16
CD17
CD18
CD19
CD20
CD21
+ CD30
o o o
A A
CD22
CD23
CD24
CD25
CD26
CD27
CD28
CD29
oo oo oo
330U_2.5V_M
SF000006S00
eb
eb eb eb
b
e eb
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ot t ot t ot t
NNo NNo NNo
@ @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P11-DDR4_CHB: JDIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. NFL-C CTL51 LA-E841P
mm mm mm Date: Thursday, March 09, 2017 Sheet 9 of 48
co o co o co o
5 4 3 2 1
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b ooo o
b oo
o o
b ooo o
b eb eb
Stoney JDIMM2 ot
NNo
e
t e
STD ot
NNo
e
t
4 DDRA_CLK0
137
CONN@
JDIMM2A
CK0(T)
STD
DQ0
8
ot
NNo
et
DDRAB_SDQ4
DDRAB_SDQ0
DDRAB_SDQ[63..0] 4,9
139 7
4 DDRA_CLK0# CK0#(C) DQ1 DDRAB_SDQ2
138 20
4 DDRA_CLK1 CK1(T) DQ2 DDRAB_SDQ7
JDIMM2B 140 21
STD 4 DDRA_CLK1# CK1#(C) DQ3 4 DDRAB_SDQ5
111 141 109 DQ4 3 DDRAB_SDQ1
+1.2V_VDDQ 112 VDD1 VDD11 142
+1.2V_VDDQ 4 DDRA_CKE0
110 CKE0 DQ5 16 DDRAB_SDQ3
VDD2 VDD12 4 DDRA_CKE1 CKE1 DQ6 DDRAB_SDQ6
117 147 17
co o co o co o
D VDD4 VDD14 4 DDRA_SCS0# S0# DQS0(T) DDRAB_SDQS0 4,9 D
+3VS +3VS_DB 123 153 157 11
1
@ @ @ 1 2 129 159 165 28
c c c
VDD7 VDD17 S3#/C1 DQ8 DDRAB_SDQ9
i c i c i c
RD10 RD11 RD14 RD13 0_0402_5% 130 160 29
i i i
at at at
VDD8 VDD18 DQ9 DDRAB_SDQ14
at at at
10K_0402_5% 10K_0402_5% 10K_0402_5% 135 163 155 41
+3VS_DB 136 VDD9 VDD19 4 DDRA_ODT0 161 ODT0 DQ10 42 DDRAB_SDQ11
VDD10 4 DDRA_ODT1 ODT1 DQ11 DDRAB_SDQ12
24
em m em m em m
2
2
SA0_DIM2 SA1_DIM2 SA2_DIM2 255 258 115 DQ12 25 DDRAB_SDQ13
+0.6VS_VTT 4,9 DDRAB_SBS2#
e e e
VDDSPD VTT 113 BG0 DQ13 38 DDRAB_SDQ10
h h h h
4,9 DDRAB_SMA14
ch ch ch
BG1 DQ14 DDRAB_SDQ15
1
0.1U_0201_10V6K
164 257 150 37
2.2U_0402_6.3V6M
Sc Sc Sc Sc
+0.6V_DDRB_VREFCA +2.5V
Sc
VREFCA VPP1 4,9 DDRAB_SBS0# BA0 DQ15
1
1
2 2 259 145 34
VPP2 4,9 DDRAB_SBS1# BA1 DQS1(T) DDRAB_SDQS1 4,9
kS kS kS
RD16 RD15 RD12 32
ok ok k
DQS1#(C) DDRAB_SDQS1# 4,9
CD31
CD32
10K_0402_5% 10K_0402_5% 10K_0402_5% 1 99 144
oo
VSS VSS 4,9 DDRAB_SMA0 A0 DDRAB_SDQ21
o o
2 102 133 50
o o bo
4,9 DDRAB_SMA1
2
o o bo
5 103 132 49
4,9 DDRAB_SMA2
2
2
DDRAB_SDQ22
eb eb
VSS VSS A2 DQ17
eb
131 62
VSS VSS 4,9 DDRAB_SMA3 A3 DQ18 DDRAB_SDQ18
e
9 107 128 63
ot ot t ot te
VSS VSS 4,9 DDRAB_SMA4 A4 DQ19 DDRAB_SDQ16
ot
10 167 126 46
VSS VSS 4,9 DDRAB_SMA5 A5 DQ20 DDRAB_SDQ17
NNo o
14 168 127 45
VSS VSS 4,9 DDRAB_SMA6 A6 DQ21 DDRAB_SDQ19
N NN
15 171 122 58
mm mm mm
36 192 67
39 VSS VSS 193 114 DQ29 79 DDRAB_SDQ30
co o co o co o
40 VSS VSS 196 4,9 DDRAB_SMA15 ACT# DQ30 80 DDRAB_SDQ26
c c c c c c
VSS VSS ALERT# DQS3#(C) DDRAB_SDQS3# 4,9
i i i
47 202 134
Layout Note: t t i i i
at at
VSS VSS 4,9 MEM_MAB_EVENT# EVENT# DDRAB_SDQ36
at at
C 48 205 108 174 C
aJDIMM2.257,259
VSS VSS 4,9 MEM_MAB_RST# RESET# DQ32 DDRAB_SDQ33
em em em
Place near Place near JDIMM2.258
em em em
56 VSS VSS 210 254 DQ34 186 DDRAB_SDQ38
57 VSS VSS 213 8,9 APU_SDATA0 253 SDA DQ35 170 DDRAB_SDQ37
h h h h h h ch
60 VSS VSS 214 8,9 APU_SCLK0 SCL DQ36 169 DDRAB_SDQ32
c c Sc Sc
Sc Sc Sc
61 VSS VSS 217 SA2_DIM2 166 DQ37 183 DDRAB_SDQ34
S S +2.5V 64 VSS VSS 218 SA1_DIM2 260 SA2 DQ38 182 DDRAB_SDQ39
kS
k okok okok k
+0.6VS_VTT 65 VSS VSS 222 SA0_DIM2 256 SA1 DQ39 179
10uF*2 10uF*2
o
DDRAB_SDQS4 4,9
o
68 VSS VSS 223 SA0 DQS4(T) 177
1uF*2 1uF*1
o o o
VSS VSS DQS4#(C) DDRAB_SDQS4# 4,9
o o o
69 226
eb eb eb
VSS VSS DDRAB_SDQ41
eb eb eb
72 227 92 195
VSS VSS CB0_NC DQ40 DDRAB_SDQ45
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
73 230 91 194
ot t ot t ot t
1 1 1 1 1 1 1 VSS VSS CB1_NC DQ41 DDRAB_SDQ42
77 231 101 207
CD34
CD35
CD36
CD37
CD38
CD39
mm mm mm
262 261 54 229
GND GND DDRAB_SDM3 DM2#/DBI2# DQ51 DDRAB_SDQ48
co co co
+1.2V_VDDQ DDRAB_SDM4 178 DM3#/DBI3# DQ52 212 DDRAB_SDQ53
at at at
PLACE THE CAP WITHIN 200 MILS CONN@ DDRAB_SDQS6 4,9
at at at
RZ3 1 2 DDR_A_ALERT# 96 DM7#/DBI7# DQS6(T) 219
FROM THE JDIMM2 RZ4 1 short@ 2 DDR_A_PAR DM8#/DBI8# DQS6#(C) DDRAB_SDQS6# 4,9
e mm e mm e mm 0_0402_5%
e e e
DDRAB_SDQ57
hh ch ch ch
B 237 B
ch ch
DQ56 DDRAB_SDQ61
Sc
236
c c
+0.6V_DDRB_VREFCA DQ57 DDRAB_SDQ58
kS kS kS
1000pF*1 249
kS kS kS kS
DQ58 250 DDRAB_SDQ63
0.1uF*1 DQ59 232 DDRAB_SDQ60
o o Part Number:LTCX0069FA0 o o
DQ60 233 DDRAB_SDQ56
o o
bo bo o
2 2
bo bo o
DQ61 245 DDRAB_SDQ59
Part Value:S SOCKET FOX AS0A827-H2SB-7H 260P DDR4
eb eb
CD40 CD41 DQ62 246 DDRAB_SDQ62
ete ete
DQ63 242
ot ot ot t
0.1U_0201_10V6K 1000P_0402_50V7K
1 1 +1.2V_VDDQ DQS7(T) DDRAB_SDQS7 4,9
240
o o NNo
DQS7#(C) DDRAB_SDQS7# 4,9
NN NN FOX_AS0A827-H2SB-7H
Layout Note:
2
@
DIMM Side
2
CD42
Place near JDIMM2 0.1U_0201_10V6K RD17
om mm mm
1
m
1K_0402_1%
c.o co
+0.6V_DDRB_VREFCA
co
c.10uF*6
.s .s co co
. . be at least 20 mils
1
s s sshould
c c cs
ici20
VREF traces
i ic 330uF*1 i ic
at at
1uF*8 wide t
at at a at
+1.2V_VDDQ +1.2V_VDDQ with mils spacing to other
signals
mm mm emem
2
2
e
hh e e e
2
ch ch ch
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
RD18 CD44
Sc ch ch
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
c c
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD43 1K_0402_1% 0.1U_0201_10V6K
1
kS S kS
CD45
CD46
CD47
CD48
CD49
CD50
CD51
CD52
0.1U_0201_10V6K
kS kS S kS
1
ok
CD53
CD54
CD55
CD56
CD57
CD58
CD59
CD60
ok
1
o o o o
A A
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
oo bo oo
eb
eb e e bo b
e eb
ot t ot t ot t
@ @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P12-DDR4_CHA: JDIMM2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. NFL-C CTL51 LA-E841P
mm mm mm Date: Thursday, March 09, 2017 Sheet 10 of 48
co o co o co o
5 4 3 2 1
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
D D
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
hem
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch Sc
Sc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
C C
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
at
at atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok o okok oo o k
o o o
eb eb eb eb eb eb
ot t ot t ot t
NNo NNo NNo
B
mm mm mm B
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
o o o
bobo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
A A
kS SITINC. kS kS
B
k k
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION
k k
BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
CONTAINS
LA-D712P
o
oo o oo o o Date: Thursday, March 09, 2017 Sheet 11 o f o48
oo o
eb eb eb eb eb
eb
5 4 3 2 1
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
D D
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
hem
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch Sc
Sc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
C C
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
at
at atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok o okok oo o k
o o o
eb eb eb eb eb eb
ot t ot t ot t
NNo NNo NNo
B
mm mm mm B
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
o o o
bobo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
A A
kS SITINC. kS kS
B
k k
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION
k k
BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
CONTAINS
NFL-C CTL51 LA-E841P
o
oo o oo o o Date: Thursday, March 09, 2017 Sheet 12 o f o48
oo o
eb eb eb eb eb
eb
5 4 3 2 1
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
eb +19VB eb eb
+APU_CORE
e e e
ot ot ot
PUZ1
t PLZ11 PWM P49
t t
NNo NNo NNo
RT3661ABGQW +APU_CORE_NB
Max:3.4A Max:5.5A
PJPDC1 +19V_ADPIN +19V_VIN
AC Adapter
+19V_ADPIN
PL11
PL12
PQB11
NMOSFET
PQB12
NMOSFET
Charger
PWM PUB1 PQB13
+19VB
PQB1 NMOSFET
P41
ISL95520 P42
mm mm mm
co o c.o co o
D D
65W
s.s.c
PR765
1206 co PWM
s.sPJF1 PUF1 PJF2
s.s.c
c c c
+0.95VALWP +0.95VALW
i c i c i c
P41
i i i
at at at
B671GQ-Z
at +16.8V_BATT+
at at
hem
AMD e m
Stoney LA-E841P
h em e m INVPWR_B+ For LCD
h em e m
h
Sc ch Sc ch Sc ch Sc
Sc
RD34
PL13 Backlight U19 +0.95VS
S kS kS AO4304L P34
ok ok k
NMOSFET
k 2016/10/12 o o oo k
o o o bo
eb eb eb bo +0.6VS_VTT
ePJM3 e bo
te
+0.6VSP
ot t ot t ot
+17.4V_BATT++ PUM1 0603
NNo +1.2VP o o
PJM1 PWM P44 +3VS_CAM
N NN
RT8207PGQW +1.2V_VDDQ RX27
PBATT1
N PJM2
Battery (4S)
UG1 +LCDVDD
LOAD SWITCH
P36 G524B1T11U
+APU_CORE
mm mm mm+3VS_WLAN
co o co o co o
+APU_CORE_NB
i ci c i ci c i ci c
+APU_CORE_GFX t t
at t t
C C
aa a t a a
e mm mm mm
h h e
(+0.775VALW)
hehe he h e +3VS
ch
Sc c c c LOAD SWITCH c c Sc
+VDDCR_FCH_ALW) PU301 PJ302 +3VALW U17 +3VS_TOUCH
kS kS kS
3VS
kS +1.35V S S
PWM J511
k k k
RT6575DGQW EM5209VF P26
o o o +19VB o o o oo o
o o o
eb eb eb eb ebeb
ot t ot t otot
+0.95VS
NNo NNo
+0.95VALW
+1.8VS
VIN_0.775VALW
N N
+1.8V_ALW PUC1 +0.775VALW
PJC1 G2992F1U PJC2
+3VS
+3VALW
For Stoney Only
Q2515, Q2514
+VDDCR_FCH_ALW
+1.5VS
mm mm mm
P26
+RTCBATT
c.o
.s co c.o
.s co .sc.o co
s s s
icic icic icic
atat at
at at at
e mm e mm e mm
B
hh e e e B
Sc c chch
PU1801 h
PWM c P46 h
SY8003DFC c
+1.8VALW
chc
kS kSkS kSkS kSkS
PJ1802 PJ1801
o o o o o o
bo o o
U18 +1.8VS
bo o o
LOAD SWITCH
eb eb eb eb
AOZ1336
ete
oto ot t ot t
NNo NNo
+LAN_VDD_3V3
+APU_CORE
+APU_CORE_NB
NN J1
+APU_CORE_GFX +5VALW
PJ303
(+0.775VALW)
mm
+VDDCR_FCH_ALW
mm mm
co o co o co o
U17 +5VS 5VS J509 +5VS
c c c
+1.35V
titic at
i ic
at
i ic
a a
+0.95VS
at US1 +USB_VCCA
at
mm mm mm
USB Power SW
e e e
SY6288
hh e e e
ch ch ch
+0.95VS
c
S Sc ch ch c
+0.95VALW QOD2 +5VS_ODD
kSkS kS kS kSkS
LP2301ALT1G
kA
+1.8VS
o o o o o o
A
oo oo oo
eb eb
b
e eb b
e eb
+1.8V_ALW
ot t ot t ot t
NNo NNo NNo
+3VS
+RTCBATT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserved Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. NFL-C CTL51 LA-E841P
mm mm mm
Date: Thursday, March 09, 2017 Sheet 13 of 48
co o co o co o
5 4 3 2 1
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
1 2 3 4 5
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
AC Coupling Capacitor
U666A @ PCIe Gen3: Recommended value is 220 nF
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
mm mm mm
co o co o co o
A A
i i i
4 PCIE_CTX_C_GRX_P0 PCIE_CRX_GTX_P0 4
at at at
PCIE_RX0P PCIE_TX0P PCIE_CRX_C_GTX_N0
at at at
AE31 AG31 0.22U_0402_10V6K 2 1 PX@ C82
4 PCIE_CTX_C_GRX_N0 PCIE_RX0N PCIE_TX0N PCIE_CRX_GTX_N0 4
em m em m em m
AE29 AG29 PCIE_CRX_C_GTX_P1 0.22U_0402_10V6K 2 1 PX@ C83
4 PCIE_CTX_C_GRX_P1 PCIE_CRX_GTX_P1 4
e e e
AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1 2 1 PX@
0.22U_0402_10V6K C84
h h h h
4 PCIE_CTX_C_GRX_N1 PCIE_CRX_GTX_N1 4
ch ch ch
PCIE_RX1N PCIE_TX1N
Sc Sc Sc Sc
Sc
PCIE_CRX_C_GTX_P2
kS kS kS
AD30 AF27 0.22U_0402_10V6K 2 1 PX@ C85
ok ok k
4 PCIE_CTX_C_GRX_P2 PCIE_RX2P PCIE_TX2P PCIE_CRX_C_GTX_N2 PCIE_CRX_GTX_P2 4
k
AC31 AF26 0.22U_0402_10V6K 2 1 PX@ C86
oo
4 PCIE_CTX_C_GRX_N2 PCIE_RX2N PCIE_TX2N PCIE_CRX_GTX_N2 4
o o o o
o o bobo
PCIE_CRX_C_GTX_P3
eb eb eb
AC29 AD27 2 1 PX@
eb
0.22U_0402_10V6K C87
4 PCIE_CTX_C_GRX_P3 PCIE_RX3P PCIE_TX3P PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_P3 4
e
AB28 AD26 2 1 PX@
te
0.22U_0402_10V6K C88
ot t ot t ot
4 PCIE_CTX_C_GRX_N3 PCIE_RX3N PCIE_TX3N PCIE_CRX_GTX_N3 4
No Use GPU Display Port outpud
NNo NNo NN o
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N U666F @
+VGA_CORE
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N AB11 R108 1 R70@ 2 0_0402_5%
VARY_BL AB12 R109 1 R70@ 2 0_0402_5%
Y30 AB27 DIGON
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
mm mm mm
co o co o co o
W29 Y27 AL15
c c c c c c
B B
i i i
AH16
i i i
at at at
TX0P_DPA2P
at at at
V30 W24 AJ15
U31 NC#V30 NC#W24 W23 TX0M_DPA2N
NC#U31 NC#W23 AL17
kS kS
TX2M_DPA0N
o o
R31 NC#T30 NC#U24 U23 NC_TXOUT_L3P AK18
o o o
NC#R31 NC#U23 NC_TXOUT_L3N
o o o
eb eb eb eb eb eb
R29 T26 TMD P
ot t ot t ot t
P28 NC#R29 NC#T26 T27
mm mm mm
L31 P23
NC#L31 NC#P23
co co co
NC_TXOUT_U3P AJ23
s.s s .s L29
K30 NC#L29 NC#M27
M27
N26
s .s NC_TXOUT_U3N
at
at at
at at
at
mm mm mm
C CLOCK 216-0841018 A0 SUN?PRO S3 C
CLK_PCIE_GPU
e e e
AK30
e e e
6 CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_REFCLKP
hh ch ch ch
AK32
ch ch
6 CLK_PCIE_GPU# PCIE_REFCLKN +0.95VS_VGA
Sc c
kS kS kS
c
kS kS kS kS
CALIBRATI ON
Y22 R134 1 PX@ 2 1.69K_0402_1%
o o
PCIE_CALR_TX
o o o o
bobo bo
bo
o o
R136 1 PX@ 2 1K_0402_5% N10 AA22 R135 1 PX@ 2 1K_0402_1%
eb eb
TEST_PG PCIE_CALR_RX
ete ete
ot ot ot t
GPU_RST# AL27
o o NNo
PERSTB
short@ R125
R128 @ 0_0402_5%
0_0402_5%
2
2
mm mm mm PX@
co o co o co o
5
U14
8 PXS_RST# B 4 GPU_RST#
Y
c c c
1
i ic i ic i ic
8,24,28 PLT_RST_BUF# A
G
at
at at
at at
at
1
PX@ R70@
3
mm mm mm
MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
e e e e e e
SCS00003500
hh ch ch ch
ch ch
2
Sc c c
D D
kS kS kS
R116 1 R30@ 2 0_0402_5%
kS kS kS kS
TO PWR VGA_PWRGD 44
o
oo o o
oo o oo o o
b
e eb b
e eb b
e eb
ot t ot t ot ot
NNo NNo 2015/09/01 Compal
NNElectronics, Inc.
Security Classification Compal Secret Data
Title
Issued Date Deciphered Date 2017/09/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
SUN_PCIE/DP
Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
NFL-C CTL51
Thursday, March 09, 2017 Sheet 14
LA-E841P
of 48
1 2 3 4 5
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
1 2 3 4 5
+3VS_VGA
b oo
o o
b oo
o o
b ooo o
eb eb eb
+1.8VS_VGA
PS_0[3:1]=001 Strap Name :
e e te
ot t ot t t
PS_0[5:4]=11
o
EC_SMB_DA2 VGA_SMB_DA3
NNo NNo
1
o
1 @ 2 U666B @ U? PS_0[1] ROM_CONFIG[0]
1
N
R129 0_0402_5% PX@
EC_SMB_CK2 1
R164
@ 2
0_0402_5%
VGA_SMB_CK3
PX@R118
10K_0402_5%
PX@R119
10K_0402_5%
AF2
R120
8.45K_0402_1%
PS_0[2]
PS_0[3]
N
ROM_CONFIG[1]
ROM_CONFIG[2]
2
PS_0
2
NC#AF2 AF4
2
NC#AF4
VGA_SMB_DA3 PS_0[4] N/A
1
6 1 1 N9 AG3
5,23,27 EC_SMB_DA2 T201 DBG_DATA16 NC#AG3
1 L9 AG5 PX@
PX@ Q2A
T202
1 AE9 DBG_DATA15 NC#AG5 R5166
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
T29 D PA C=NC
5
ME2N7002D1KW-G 2N_SOT363-6 1 Y11 DBG_DATA14 AH3 2K_0402_1%
T204 DBG_DATA13 NC#AH3
1 AE8 AH1 Resistor Divider Lookup Lable
2
VGA_SMB_CK3 T30 DBG_DATA12 NC#AH1
mm mm mm
3 4 1 AD9
5,23,27 EC_SMB_CK2 T206 DBG_DATA11
1 AC10 AK3
co o co o co o
A T31 DBG_DATA10 NC#AK3 A
PX@ Q2B 1 AD7 AK1 R_pu (ohm) R_pd (ohm) Bitd [3:1]
T32
c c c
+3VS_VGA 1 AB9 AM3
c c c
NC 4.75k 000
i i i
T211
atat at at
T33 DBG_DATA5 +1.8VS_VGA
1 AB7 AK6
aPS_1[5:4]=11
8.45k 2k 001 PS_1[3:1]=001 Strap Name :
a
T34 DBG_DATA4 NC#AK6
1 AB4 AM5
T214 DBG_DATA3 NC#AM5
2
em em 011 m
1 AB2 4.53k 2k 010
m m m
T215 DPB
VGA_AC_BATT_R
1
+3VS_VGA 1 Y8 DBG_DATA2 AJ7
e
R1451 PS_1[1] STRAP_BIF_GEN3_EN_A
e e e
T216 DBG_DATA1 NC#AJ7
10K_0402_5% 1 Y7 AH6 6.98k 4.99k PX@
h h h h
T217
ch ch c ch
6
DBG_DATA0 NC#AH6 R5167
PS_1[2] TRAP_BIF_CLK_PM_EN
Sc Sc Sc
ME2N7002D1KW-G 2N_SOT363-6
@
Sc
@ Q16A AK8 8.45K_0402_1%
4.53k 4.99k 100
S
1
NC#AK8
kS kS S
R1444 1 @ 2 100K_0402_5% ACIN AL7 PS_1[3] N/A
2
VGA_AC_BATT_R PS_1
ok k k
2 R1445 1 PX@ 2 1K_0402_5% NC#AL7
k k
3.24k 5.62k 101
o oo PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
oo
3
2
W6
o bo bo
3.4k 10k 110
follow AMD check list o o NC bo
ME2N7002D1KW-G 2N_SOT363-6
1
@ Q16B V6 NC#W6 PX@
11/15: PS_1[5] STRAP_TX_DEEMPH_EN
keepb
NC#V6
R1445 e e e
NC#V4
ot t ot ot
27 VGA_AC_BATT GPIO_5 NC#AC5 NC#U5
AC5
1
NC#AC6
NNo o o
W3
4
NC#W3
NN NN
AA5 V2
AA6 NC#AA5 NC#V2
DPC
NC#AA6 Y4
1 @ 2 +1.8VS_VGA NC#Y4 W5
R174 0_0402_5% NC#W5
BP_0 PLL_ANALOG_OUT
R1470 2 R70@ 1 10K_0402_5% U1 AA3 R1469 1 @ 2 16.2K_0402_1%
W1 NC#U1 NC#AA3 Y2 +1.8VS_VGA
1 2 BP_1 NC#W1 NC#Y2 PS_2[3:1]=000 Strap Name :
+3VS_VGA R1471 2 R70@ 1 10K_0402_5% U3
R1463 10K_0402_5% Y6 NC#U3 J8
R1440 1 @ 2 GPU_GPIO6
T71 1 AA1 NC#Y6 NC#J8 PS_2[5:4]=11
27,44 GPU_PROCHOT#
1K_0402_5% NC#AA1 PS_2[1] N/A
1 @ 2
2
@
R=NC
mm mm mmPS_2[3] STRAP_BIOS_ROM_EN
PS_2[2] N/A
R1464 10K_0402_5% C442
co o co o
PS_2
1
c c c
R1
c c c
1
i i i
SCL
i i i
R3 PX@ PX@
at at t t
PS_2[5] N/A
t at
+3VS_VGA +1.8VS_VGA SDA C5203 R5164
B Cap (nF) Bitd [5:4] B
a R
AM26
AK26 a a
0.082U_0402_16V6K
2
4.75K_0402_1%
mm em mm
em
GENERAL PURPOSE I/O
2
T292 1 R169 1 @ 2 0_0402_5% GPU_GPIO0 U6 AVSSN#AK26
680nF 00
he e
2
he h he
2 0_0402_5% GPU_GPIO1
2
h ch
+VGA_CORE
2 0_0402_5% GPU_GPIO2 GPIO_1 G
h
R1455 R1454 C439 @R30@ R5186 1 R70@ T10 AJ25
82nF 01
c Sc Sc
VGA_AC_BATT_R VGA_SMB_DA3 GPIO_2 AVSSN#AJ25
c Sc
10 c
Sc
10K_0402_5% 10K_0402_5% 0.1U_0402_10V6K C441 1 2 U8
VGA_SMB_CK3 SMBDATA
SS kS
1 0.1U_0402_10V6K R1661 short@ 0_0402_5% U7 AH24
S
@ @R30@ 1 GPU_GPIO5 SMBCLK B 10nF
ok k
ACIN 1 @ 2 T9 AG25
k ok k k
1
o o
R165 0_0402_5% NC 11
o o
UV1 @R30@ T7 GPIO_6 DAC1 AH26 +1.8VS_VGA
o o o
PS_3[3:1]=000 Strap Name :
o o o
33_0402_5% A1 A2 33_0402_5% P10 GPIO_7_BLON HSYNC AJ27 1 2
eb eb bb
GPU_VID3 GPU_VID3_GPIO15 VCCA VCCB GPU_SVD GPIO_8_ROMSO VSYNC
eb eb
R1449 1 @R30@ 2 B1 B2 R1452 1 @R30@ 2 P4 PX@ R1467 PS_3[5:4]=11
e
GPU_VID1 R1450 GPU_VID1_GPIO20 A1 B1 GPU_SVC GPIO_9_ROMSI
1
te ID)
1 @R30@ 2 C1 C2 R1453 1 @R30@ 2 P2 4.7K_0402_5% PS_3[1] BOARD_CONFIG[0] (Memory ID)
ot t ot t ot
33_0402_5% D2 A2 B2 D1 33_0402_5% N6 GPIO_10_ROMSCK AD22 X76@
DIR GND GPIO_11 RSET
2
@R30@ GPU_VID3 N1 GPIO_14_HPD2 AVSSQ PS_3
10K_0402_5% 10K_0402_5%
@R30@ C366 2 1 M4 GPIO_15_PWRCNTL_0 AE23
@ GPU_GPIO17 PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
1
R6 GPIO_16 VDD1DI AD23
1
2
10K_0402_5% N8 GPIO_21
AK10 GPIO_22_ROMCSB AK12 SVI2_SVD
0.1U_0402_10V6K R1664 1 R70@ 2 0_0402_5%
GPIO_29 RSVD#AK12 SVI2_SVT GPU_SVD 44
AM10 AL11 R1665 1 R70@ 2 0_0402_5%
mm mm mm
GPU_VID3 GPU_SVD VGA_CLKREQ#_R GPIO_30 RSVD#AL11 SVI2_SVC R1666 1 R70@ GPU_SVT 44
R1662 1 R30@ 2 0_0402_5% 1 2 N7 AJ11 2 0_0402_5%
co co co
R1663 1 R30@ 2 0_0402_5% R167 @ 0_0402_5%
JTAG_TRSTB L6
.s .s .s
@ 1 JTAG_TDI L5 JTAG_TRSTB
s s s
C5213
JTAG_TCK L3 JTAG_TDI
tic
iFOR
JTAG_TMS L1 JTAG_TCK AL13
11/15
at at at
follow AMD check list JTAG_TDO JTAG_TMS GENLK_CLK
at at
XO_IN 2 T70 1 K4 AJ13
R1447 1 PX@ 2 JTAG_TDO GENLK_VSYNC
R167 non-pop by vendor
a
+3VS_VGA TESTEN K7
XO_IN/XO_IN2 must PD
10K_0402_5%
XO_IN2 AF24 TESTEN OPTIAN 3.3V tolerance VR, H2G@
m mm mm
R1448 1 PX@ 2
e em
NC#AF24
10K_0402_5% AG13 Check with VR vendor
e e
SWAPLOCKA
e e
@ RP34 AH12 VRAM
h ch h ch
GPIO19_CTF JTAG_TRSTB SWAPLOCKB
h ch h
R1446 1 PX@ 2 1 8 +VGA_CORE R179 1 R70@ 2 0_0402_5% AB13 Part Number = X7667032L51
44 +VGA_VDDIO
Sc Sc
C JTAG_TDI GENERICA C
c Sc c
10K_0402_5% 2 7 W8 Hynix
VGA_CLKREQ# JTAG_TMS GENERICB
kS kS
R1443 1 PX@ 2 3 6 R5187 1 R70@ 2 0_0402_5% W9
kS kS kS
JTAG_TCK GENERICC PS_0 +1.8VS_VGA +3VS_VGA
ok
10K_0402_5% 4 5 W7 AC19 VRAM2
ok
R1439 1 PX@ 2 TESTEN AD10 GENERICD PS_0
o o o o
AJ9 GENERICE AD19 PS_1
1K_0402_5% 10K_8P4R_5% R1673 1 R70@ 2 R1674 1 R30@ 2
bo o o
NC#AJ9 PS_1
bo o o
AL9 0_0402_5% 0_0402_5%
PS_2 S2G@
eb eb
2
NC#AL9 AE17
eb eb
PS_2
te
R5188 1 R70@ 2 0_0402_5% AC14 R1459 R1460
te ot t ot t
1 AB16 HPD1 AE20 PS_3
T218 PX_EN PS_3 10K_0402_5% 10K_0402_5% VRAM
SizeoR5174
o NNo NNo
PX@ @ Part Number = X7667032L52
Memory ID Memory Type Conf i gur a t i o
n R5169 X76 P/N Samsung
NN
1
AE19 GPU_SVD
1 AC16 TS_A
T221 DBG_VREFG GPU_SVC
VRAM3
2
DDC/AUX
001 SA00008DN60 Hynix H5TC4G63EFR-N0C 2GB 8.45K 2K X7667032L51 PLL/CLOCK DDC1CLK
AE6
AE5
R1461 R1462
DDC1DATA
10K_0402_5% 10K_0402_5% VRAM
Part Number = X7667032L53
+VGA_CORE @ PX@
010 SA000076P80 Samsung K4W4G1646E-BC1A 2GB 4.53K 2K X7667032L52 AD2 Micron
1
AUX1P AD4
om mm mm
AUX1N
om co o co o
011 SA00009HF00
Micron MT41J256M16LY-091G:N 4GB 6.98K 4.99K X7667032L56 AC11 R1667 1 R70@ 2 0_0402_5%
cH5TC4G63EFR-N0C
DDC2CLK AC13 R1668 1 R70@ 2 0_0402_5%
.s .c s.s.c s.s.c
DDC2DATA
100
c sHynix SA00008DN60 4GB 4.53K 4.99K
c
X7662732L54 XTALIN AM28 AD13
c
i ic i ic i icExternal VGA Thermal Sensor
XTALOUT AK28 XTALIN AUX2P AD11
at at at
XTALOUT AUX2N
at Samsung K4W4G1646E-BC1A at at
XO_IN FB_GND +3VS_VGA
101 SA000076P80 4GB 3.24K 5.62K X7662732L55 XO_IN2
AC22
AB22 XO_IN NC#AD20
AD20
AC20 FB_VDDC
R1670 1 R70@
R1669 1 R70@
2 0_0402_5%
2 0_0402_5%
VGA_VSSSENSE 44
110 m mm mm
XO_IN2 NC#AC20 VGA_VCCSENSE 44 VGA_EXT_CK1
m
+3VS_VGA RV135 1 @PX@ 2 2.2K_0402_5%
e e
3.4K 10K
e e e e
AE16 @PX@
NC#AE16 VGA_VSSSENSE R5183 1 PX@ VGA_EXT_DA1 RV136
h111 ch ch ch
AD16 2 10_0402_5% 2 1 1 @PX@ 2 2.2K_0402_5%
ch ch ch
NC#AD16
Sc
CV271 0.1U_0402_16V4Z @PX@
4.75K NC
c
AC1 VGA_VCCSENSE
R1672 1 PX@ 2 10_0402_5% +VGA_CORE
Enable MLPSS S
kS kS
SEYMOUR/FutureASIC UV13
kS kS kS
THERM_D+ T4 DDCVGACLK AC3 1 8
kk
THERM_D- DPLUS THERMAL DDCVGADATA 1 VDD SCL VGA_EXT_CK1 27
T2 @PX@
o o o
DMINUS THERM_D+
o o o
CV272 2 7
oo oo oo
D+ SDA VGA_EXT_DA1 27
D 2200P_0402_50V7K THERM_D-
D
2 @PX@ 1
eb b b
R1442 1 R30@ 2 10K_0402_5% GPIO28 R5 2 3 6
eb e eb e eb
GPIO28_FDO D- ALERT# +3VS_VGA
XTALIN R349 1 PX@ 2 XTALOUT +TSVDD AD17 RV134 2.2K_0402_5%
TSVDD @PX@ GPU_GPIO17
ot t ot t ot t
10M_0402_5% AC17 2 1 4 5 1 @ 2
TSVSS +3VS_VGA T_CRIT# GND
RV133 2.2K_0402_5% R168 0_0402_5%
PX@C341
8.2P_0402_50V_NPO
2
2 4
2
PX@C350
8.2P_0402_50V_NPO
PX@C421 2 1 1U_0402_6.3V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
PX@C438 2 1 0.1U_0402_10V6K
Issued Date 2013/01/11 Deciphered Date 2013/12/31 Title
SUN_MSIC
1 27MHZ_10PF_XRCGB27M000F2P18R0 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
mm mm mm
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
NFL-C CTL51 LA-E841P
co o co o co o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date : Thursday, March 09, 2017 Sheet 15 of 48
i ci c i ci c i ci c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
1 2 3 4 5
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
U666E @ U?
AA27 A3
370mA (HDMI) No Use GPU Display Port outpud AB24 GND GND A30
GND GND
+1.8VS_VGA 188mA (Display Port) AB32
AC24 GND GND
AA13
AA16
R319 1 short@ 2 +DP_VDDR U666G @ AC26 GND GND AB10
U?
0_0603_5% AC27 GND GND AB15
AD25 GND GND AB6
C446
C447
DP POWER NC/DP POWER
AD32 GND GND AC9
mm mm mm
1 1 GND GND
AG15 AE11 AE27 AD6
co o co o co o
A A
AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 AG17 AF13 AH32 AG12
c c c
DP_VDDR#AG17 NC#AF13 GND GND
i c i c i c
@
AG18 AG8 K28 AH10
i i i
at at at
DP_VDDR#AG18 NC#AG8 GND GND
at at at
AG19 AG10 K32 AH28
AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
DP_VDDR#AF14 M32 GND GND B12
e e e
N27 GND GND B16
h h h h
ch ch c ch
P25 GND GND B18
Sc Sc Sc
Sc
AG20 AF6 P32 GND GND B20
280mA kS
DP_VDDC#AG20 NC#AF6 GND GND
kS kS S
AG21 AF7 R27 B22
ok k
DP_VDDC#AG21 NC#AF7 GND GND
o ok k
+0.95VS_VGA AF22 AF8 T25 B24
oo
DP_VDDC#AF22 NC#AF8 GND GND
o
AG22 AF9 T32 B26
o o bo
+DP_VDDC DP_VDDC#AG22 NC#AF9 GND GND
o o bo
R320 1 short@ 2 AD14 U25 B6
eb b
DP_VDDC#AD14 GND GND
eb b
0_0603_5% U27 B8
GND GND
ee e
V32 C1
te
C450
C451
ot t ot t ot
W25 GND GND C32
1 1 GND GND
NNo NNo o
AG14 AE1 W26 E28
DP_VSSR NC#AE1 GND GND
NN
AH14 AE3 W27 F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
DP_VSSR NC#AG1 GND GND
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 AM16 AG6 Y32 F14
DP_VSSR NC#AG6 GND GND
@
AM18 AH5 F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
DP_VSSR NC#AG7 GND GND
mm mm mm
AF20 AG11 N18 F6
AE14 DP_VSSR NC#AG11 N21 GND GND F8
co o co o co o
GND
DP_VSSR P6 GND GND G10
toc+3VS_VGA
c c c c c
B GND GND B
+3VS i i i
AF17 AE10 R15 G8
i i i
at at at
DPAB_CALR NC#AE10 GND GND
at to +1.8VS_VGA (311mA) at at
R17 H14
R20 GND GND H17
T13 GND GND H2
em em em
+1.8VALW
em em em
T16 GND GND H20
PX@ @ 216-0841018 A0 SUN PRO?S3 T18 GND GND H6
h h h h h h T21 GND
ch
GND J27
Sc Sc Sc
U4103 60mA JG3
c Sc Sc Sc
1 14 1 2 T6 GND GND J31
kS
+3VS +3VS_VGA
kS
2 VIN1 VOUT1 13 1 2 U15 GND GND K11
okok okok k
VIN1 VOUT1 GND GND
0.1U_0402_16V7K
0.1U_0402_16V7K
U17 K2
o
1 1
o
DGPU_PWR_EN JUMP_43X39 GND GND
C4111
C4124
3 12 C4112 1 2 @ U20 K22
o o o
ON1 CT1 GND GND
o o o
470P_0402_50V7K U9 K6
eb eb eb
GND GND
eb eb eb
+5VALW 4 11 V13
2 PX@ VBIAS GND 2 PX@ V16 GND
ot t ot t ot t
DGPU_PWR_EN 5 10 C4126 1 2 PX@ V18 GND
0.1U_0402_25V6
1 15 1 R11 A32
GPAD JUMP_43X39 GND VSS_MECH
2
C4123
C4125
T11 AM1
TPS22966DPUR_SON14_2X3 PX@ AA11 GND VSS_MECH AM32
R346 M12 GND VSS_MECH
2 PX@ 2 PX@ 10_0603_5% N11 GND
V11 GND
1
GND
m m mm 1
D
mm
c.o c.o c.o
Main: SA00004MM00, TI, TPS22966
co co co
2 PXS_PWREN# ? S3
216-0841018 A0 SUN PRO
.s .s .s
2nd: SA00006FD00, A-Power, APE8990GN3B
s s s
G
3rd: AOS, AOZ1331 (engineering sample available on 2013/Jan/18)
ME2N7002D1W-G 1N_SC70-3
atat at
at at
at
mm mm mm
C C
e
hh e e e e e
Sc c ch ch chch chc
kS o kS kS o kSkS o kSkS
o o o
bo o bo
bo eb
o o
+0.95VALW to +0.95VSG (4.016A) te eb ete eb
o ot oto ot t
NN +0.95VALW PX@
U4102
+0.95VS_VGA NN +5VALW +VGA_CORE NNo
AO4354_SO8
2
8 1 PX@ PX@
7 2 R4113 R4114
2
0.1U_0402_16V7K
6 3 100K_0402_5% 470_0603_5%
10U_0603_6.3V6M
1U_0402_6.3V4Z
1 5 1 1 PX@
C4113
C4114
C4115
R4107
ME2N7002D1KW-G 2N_SOT363-6
3 1
6 1
PXS_PWREN#
10_0603_5%
ME2N7002D1KW-G 2N_SOT363-6
mm mm mm
4
3 1
co o co o co o
2 PX@ 2 PX@ 2 PX@
c c c
PX@ PX@
i ic i ic i ic 5 PXS_PWREN#
1
Q4105B Q4105A
at
at at
at at
at
1
1 PX@ 2 0.95VSG_GATE @ R4115
+19VB
R4109 200K_0402_5% PX@Q4102B 100K_0402_5%
4
mm mm mm
ME2N7002D1KW-G 2N_SOT363-6
1
e e e e
1
e e
2
6
hh ch ch ch
@ R4104 PX@C4122
Sc c ch ch c
1.5M_0402_5% 0.01U_0402_50V7K
D D
kS kSkS kSkS kS kS
PXS_PWREN# 2 2
2
o o o
PX@
Q4102A
oo o oo o oo o
1
ME2N7002D1KW-G 2N_SOT363-6
b
e eb b
e eb b
e eb
ot t ot t ot ot
NNo NNo 2013/01/11 Compal
NNElectronics, Inc.
Security Classification Compal Secret Data
Title
Issued Date Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
SUN_Power/GND
Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
NFL-C CTL51
Thursday, March 09, 2017 Sheet 16
LA-E841P
of 48
1 2 3 4 5
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
1 2 3 4 5
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
+1.5VS_VGA
10uF mm mm mm
co co o co o
A A
+VGA_CORE 1uF 0.1uF
co
s.s5.(1@) s.s.c s.s.c
C365
C367
C375
C370
C371
C372
C373
C374
C5269
C5270
C5271
1 1 1 1 1 1 1 1 1 1 1
ici c ici c i c c
ti (PCIE2.0)
VDDC TBD 10 (2@) 0 +PCIE_PVDD:
at at 3.5A 1 atat at 50mA +1.8VS_VGA
a80mA
U666D @ U?
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2 2 2 2 2 2 2 2 2 2 2
(PCIE3.0)
mm em m em m
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
AM30
eVDDCI
e
3 0
e
1A
e
MEM I/O PCIE_PVDD
PCIE
C380
C387
C394
h h h h
ch ch h
H13 AB23
Sc Sc c Sc
1 1 1
c Sc
H16 VDDR1 NC#AB23 AC23
kS
VDDR1 NC#AC23
S kS kS
H19 AD24
ok k
VDDR1 NC#AD24
k k
J10 AE24
oo oo
VDDR1 NC#AE24
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2
o oo
J23 AE25
+0.95VS_VGA 10uF 1uF 0.1uF
o bo
VDDR1 NC#AE25
o bo
PX@
PX@
PX@
J24 AE26
eb b
VDDR1 NC#AE26
eb
J9
b
AF25
VDDR1 NC#AF25
ee e
K10 AG26
ot ot t ot te
VDDR1 NC#AG26
ot
K23
PCIE_VDDC 2.5A 2 (1@) 5 (1@) 0 VDDR1
NNo o
K24
VDDR1
N NN
K9 L23
C389
C390
C391
C381
C392
N
C3719
C3720
C3721
C3722
C3723
VDDR1 PCIE_VDDC
0.01U_0402_50V7K
0.01U_0402_50V7K
0.01U_0402_50V7K
0.01U_0402_50V7K
0.01U_0402_50V7K
2 2 2 2 2 1 1 1 1 1 L11 L24
L12 VDDR1 PCIE_VDDC L25
BIF_VDDC 1.4A 0 0 0 +PCIE_VDDC: L13 VDDR1 PCIE_VDDC L26
L20 VDDR1
VDDR1
PCIE_VDDC
PCIE_VDDC
M22 1.88A (PCIE2.0) +0.95VS_VGA
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 1 1 1 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
L21 N22
VDDR1 PCIE_VDDC 2.5A (PCIE3.0)
PX@
PX@
PX@
PX@
PX@
L22 N23
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC T22
C384
C386
C398
C399
C383
C403
C388
C3724
C3725
+1.8VS_VGA 13mA PCIE_VDDC
om mm mm
LEVEL U22
m
1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
TRANSLATI ON PCIE_VDDC V22
co o co o
L56 PX@
o1uF
+VDD_CT PCIE_VDDC
c10uF
1 2 AA20
+1.5VS_VGA 0.1uF
s.s.c s.s.c s.s.c
BLM15BD121SN1D_0402 AA21 VDD_CT
VDD_CT
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
AB20 AA15 2 2 2 2 2 2 2 2 2
C404
C405
C422
c c c c c c
B VDD_CT VDDC B
i i i
PX@
PX@
PX@
PX@
PX@
PX@
PX@
CORE
@
AB21 N15
i i i
1 1 1
at at at
VDD_CT VDDC
at at at
N17
VDDR1 1.5A 3 5 5 +3VS_VGA VDDC R13
25mA I/O VDDC R16
em em em
L24 PX@
em em em
VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 1 2 +VDDR3 AA17 R18
VDDR3 VDDC
PX@
PX@
PX@
BLM15BD121SN1D_0402 AA18 Y21
C410
C428
C429
C417
c +1.8VS_VGA Sc Sc Sc
AB18 VDDR3 VDDC T15 +VGA_CORE
kS
10uF 1uF 0.1uF 1 1 1 1
kS
VDDR3 VDDC T17
okok okok k
V12 VDDC T20
o o
Y12 VDDR4 VDDC U13
o o o
VDDR4 VDDC
o
10U_0603_6.3V6M
o o
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_10V6K
2 2 2 2 U12 U16
PCIE_PVDD 100mA 1 1 1
eb eb eb
VDDR4 VDDC
eb eb eb
PX@
PX@
PX@
@
U18
VDDC V21
ot t ot t ot t
VDDC V15
POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
VDDC M11
VDDC N12 21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3))
VDDC U11
VDDR4 (300mA) 0 0 0 VDDC
+1.8VS_VGA
90mA
m1m mm mm
short@ L47 PLL
+MPLL_PVDD
co co co
VDD_CT 113mA 1
C406
C407
C433
s .s 0_0603_5%
s .s 1 1 1
s .s R21
1.4A +0.95VS_VGA
ic icic icic
R398
ic 1
BIF_VDDC U21 +BIF_VDDC 1 2
at at at
+TSVDD 13mA 1 1
at at at
BIF_VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 L8 0_0805_5%
MPLL_PVDD
mm mm mm
+1.8VS_VGA
PX@
PX@
PX@
C short@ C
75mA +VGA_CORE
e e e
L48 PX@
C413
C415
C416
e
+DP_VDDR 0 0 0
e e
ISOLATED
+SPLL_PVDD
hh ch ch ch
1 2
ch ch
CORE I/O 1 1 1
Sc
BLM15BD121SN1D_0402 M13
C408
C409
C434
c +DP_VDDC c
VDDCI
kS kS kS
H7 M15
kS kS kS kS
1 1 1 SPLL_PVDD VDDCI M16
0 0 0 VDDCI
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
M17 2 2 2
o o
+0.95VS_VGA
o o
VDDCI
o o
@
M18
bo bo o
100mA
bo bo o
VDDCI
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
eb eb
+SPLL_VDDC VDDCI
PX@
PX@
PX@
1 2 H8 M21
ete e te
SPLL_VDDC VDDCI N20
ot ot ot t
BLM15BD121SN1D_0402
C411
C412
C435
J7 VDDCI
+3VS_VGA 10uF 1uF 0.1uF 1 1 1
o o NNo
SPLL_PVSS
NN NN
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2
VDDR3 25mA 0 2 (1@) 1
PX@
PX@
PX@
216-0841018 A0 SUN PRO S3 ?
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc
D
c chch ch ch chc D
kS o kSkS okSkS o kS kS
oo o oo o oo o
b
e eb b
e eb b
e eb
ot t ot t ot ot
NNo NNo 2013/01/11 Compal
NNElectronics, Inc.
Security Classification Compal Secret Data
Title
Issued Date Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
SUN_Power Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
NFL-C CTL51
Thursday, March 09, 2017 Sheet 17
LA-E841P
of 48
1 2 3 4 5
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
1 2 3 4 5
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
M_DA[63..0]
19 M_DA[63..0]
M_MA[15..0]
19 M_MA[15..0]
M_DQM[7..0]
19 M_DQM[7..0]
M_DQS[7..0]
mm mm mm
19 M_DQS[7..0]
M_DQS#[7..0]
co o co o co o
A 19 M_DQS#[7..0] A
c s.s.c c s.s.c @
c s.s.c
i i c i i c U666C
i i c
at at at
U666C
at at at
GDDR5/DDR3 GDDR5/DDR3
M_DA0 M_MA0
em em em
K27 K17
m m m
M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
e e e
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M_MA2
h h h h
ch ch ch
M_DA3 DQA0_2 MAA0_2/MAA_2 M_MA3
Sc Sc Sc Sc
H32 G23
Sc
M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M_MA4
kS kS kS
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
ok ok k k
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M_MA6
o o oo
+1.5VS_VGA +1.5VS_VGA M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
o o bo
M_DA8 DQA0_7 MAA0_7/MAA_7 M_MA13
o o bo
C30 G20
eb eb
M_DA9 DQA0_8 MAA0_8/MAA_13 M_MA15
eb eb
F27 L17
e
M_DA10 DQA0_9 MAA0_9/MAA_15
te
A28
ot t ot t ot
M_DA11 DQA0_10 M_MA8
1
1
C28 J14
M_DA12 DQA0_11 MAA1_0/MAA_8 M_MA9
NNo NNo o
PX@ PX@ E27 K14
M_DA13 DQA0_12 MAA1_1/MAA_9 M_MA10
NN
R363 R365 G26 J11
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
2
E23 L16
MEMORY INTERFACE
1 1 M_DA21 DQA0_20 MAA1_9/RSVD
PX@ PX@ PX@ PX@ F23
R364 C467 R457 C514 M_DA22 D22 DQA0_21 E32 M_DQM0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
mm mm mm
2 2 M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
co o co o co o
2
c c c
M_DA28 DQA0_27 WCKA1B_0/DQMA1_1 M_DQM6
c c c
D18 E3
i i i i
M_DA29 DQA0_28 WCKA1_1/DQMA1_2 M_DQM7
i i
at at at
F17 F4
at at at
M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
B B
em em em
M_DA32 DQA0_31 EDCA0_0/QSA0_0 M_DQS1
em em em
E17 C27
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
h h h ch
M_DA34 DQA1_1 EDCA0_2/QSA0_2 M_DQS3
h h h
F15 E19
Sc Sc Sc
M_DA35 DQA1_2 EDCA0_3/QSA0_3 M_DQS4
c Sc Sc Sc
A15 E15
M_DA36 DQA1_3 EDCA1_0/QSA1_0 M_DQS5
kS
D14 D10
kS
M_DA37 DQA1_4 EDCA1_1/QSA1_1 M_DQS6
ok ok
PX@ PX@ F13 D6
ok ok k
M_DA38 DQA1_5 EDCA1_2/QSA1_2 M_DQS7
o
R5160 R455 A13 G5
o
M_DA39 DQA1_6 EDCA1_3/QSA1_3
o o o
49.9_0402_1% 10_0402_1% C13
o o o
1 2 2 1 DRAM_RST M_DA40 E11 DQA1_7 H27 M_DQS#0
eb eb eb eb eb eb
19 DRAM_RST# M_DA41 DQA1_8 DDBIA0_0/QSA0_0B M_DQS#1
A11 A27
M_DA42 DQA1_9 DDBIA0_1/QSA0_1B M_DQS#2
ot t ot t ot t
C11 C23
M_DA43 DQA1_10 DDBIA0_2/QSA0_2B M_DQS#3
1
1 F11 C19
mm mm mm
E1 G9
Place close to GPU (within 25mm) M_DA56 DQA1_23 CLKA1 M_CLK1 19
co co co
and place componment close to each other M_DA57 G6 DQA1_24 CLKA1B M_CLK#1 19
.s .s .s
M_DA58 G1 DQA1_25 G22
s s s
M_DA59 DQA1_26 RASA0B M_RAS#0 19
G3 G17
at at at
M_DA61 DQA1_28
at at at
J1 G19
M_DA62 DQA1_29 CASA0B M_CAS#0 19
J3 G16
M_DA63 DQA1_30 CASA1B M_CAS#1 19
J5
e mm e mm DQA1_31 H22
e mm
e e e
CSA0B_0 M_CS0B#0 19
+MVREFDA K26 J22
hh ch ch ch
ch ch
MVREFDA CSA0B_1 M_CS0B#1 19
+MVREFSA J26
Sc c c
MVREFSA G13
kS kS kS
M_CS1B#0 19
kS kS kS kS
J25 CSA1B_0 K13
C NC#J25 CSA1B_1 M_CS1B#1 19 C
R5162 1 PX@ 2 120_0402_1% K25
o o o
MEM_CALRP0
o o o
K20
bo bo o
CKEA0 M_CKE0 19
bo bo o
J17
CKEA1 M_CKE1 19
e e eb eb
G25
ot te ot te ot t
DRAM_RST WEA0B M_WE#0 19
L10 H10
DRAM_RST WEA1B M_WE#1 19
NN o R460
R373
1
1
@
@
2 51.1_0402_1%
2 51.1_0402_1%
C542
C541
@1
@1
2 0.1U_0402_16V4Z
2
K8
L7 CLKTESTA
CLKTESTB NN o NNo
0.1U_0402_16V4Z
Route 50ohms single-ended/100ohm dif f and keep s hort 216-0841018 A0 SUN PRO S3
?
debug only, for clock observat i on,if not need, DNI.
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS okSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
D D
i i i
atat atat atat
Date: Thursday, March 09, 2017 Sheet 18 of 48
1 2 3 4 5
h em
e m
h eme m emem
Sc ch Sc ch chch Sc
h
kS kS
S S Sc
o oko
k
oo k oo k k
eb
o bobo bo bo
eb ete ete
ot t ot ot
NNo NN o NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k S k kS k kS
32ok
1 2 3 4 5
mm M_MA7 R2 A6 D7 M_DA5
mm M_MA7 R2 A6 D7 M_DA8
mm
M_MA7 R2 A6 D7 M_DA41 M_MA7 R2 A6 D7 M_DA60
co o co o co o
A A
M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA14 M_MA8 T8 A7 DQU0 C3 M_DA44 M_MA8 T8 A7 DQU0 C3 M_DA59
c c c
M_MA11 A10/AP DQU3 M_DA6 M_MA11 A10/AP DQU3 M_DA10 M_MA11 A10/AP DQU3 M_DA42 M_MA11 A10/AP DQU3 M_DA62
i c i c i c
R7 A7 R7 A7 R7 A7 R7 A7
i i i
at at at
M_MA12 A11 DQU4 M_DA0 M_MA12 A11 DQU4 M_DA15 M_MA12 A11 DQU4 M_DA46 M_MA12 A11 DQU4 M_DA57
at at at
N7 A2 N7 A2 N7 A2 N7 A2
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA11 M_MA13 T3 A12 DQU5 B8 M_DA40 M_MA13 T3 A12 DQU5 B8 M_DA61
M_MA14 T7 A13 DQU6 A3 M_DA2 M_MA14 T7 A13 DQU6 A3 M_DA13 M_MA14 T7 A13 DQU6 A3 M_DA47 M_MA14 T7 A13 DQU6 A3 M_DA58
em m em m em m
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
e e e
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
h h h h
Sc ch Sc ch Sc ch Sc
Sc
M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2
18 M_BA0 BA0 VDD M_BA1 BA0 VDD M_BA1 BA0 VDD M_BA1 BA0 VDD
kS kS kS
N8 D9 N8 D9 N8 D9 N8 D9
ok ok k
18 M_BA1 BA1 VDD M_BA2 BA1 VDD M_BA2 BA1 VDD M_BA2 BA1 VDD
k
M3 G7 M3 G7 M3 G7 M3 G7
oo
18 M_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
o o
K2 K2 K2 K2
o o bo
VDD VDD VDD VDD
o o bo
K8 K8 K8 K8
eb eb
VDD N1 VDD VDD VDD
eb
N1
eb
N1 N1
M_CLK0 VDD M_CLK0 VDD M_CLK1 VDD M_CLK1 VDD
e
J7 N9 J7 N9 J7 N9 J7 N9
ot t ot t ot te
18 M_CLK0 M_CLK#0 CK VDD M_CLK#0 CK VDD 18 M_CLK1 M_CLK#1 CK VDD M_CLK#1 CK VDD
K7 R1 K7 R1 K7 R1 K7 R1
18 M_CLK#0 M_CKE0 CK VDD M_CKE0 CK VDD 18 M_CLK#1 M_CKE1 CK VDD M_CKE1 CK VDD
NNo NNo o
K9 R9 K9 R9 K9 R9 K9 R9
18 M_CKE0 CKE/CKE0 VDD CKE/CKE0 VDD 18 M_CKE1 CKE/CKE0 VDD CKE/CKE0 VDD
NN
+1.5VS_VGA +1.5VS_VGA +1.5VS_VGA +1.5VS_VGA
K1 A1 VRAM_ODT0 K1 A1 K1 A1 VRAM_ODT1 K1 A1
18 VRAM_ODT0 L2 ODT/ODT0 VDDQ A8 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 18 VRAM_ODT1 L2 ODT/ODT0 VDDQ A8 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
18 M_CS0B#0 CS/CS0 VDDQ M_RAS#0 CS/CS0 VDDQ 18 M_CS1B#0 CS/CS0 VDDQ M_RAS#1 CS/CS0 VDDQ
J3 C1 J3 C1 J3 C1 J3 C1
18 M_RAS#0 RAS VDDQ M_CAS#0 RAS VDDQ 18 M_RAS#1 RAS VDDQ M_CAS#1 RAS VDDQ
K3 C9 K3 C9 K3 C9 K3 C9
18 M_CAS#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2 18 M_CAS#1 L3 CAS VDDQ D2 M_WE#1 L3 CAS VDDQ D2
18 M_WE#0 WE VDDQ WE VDDQ 18 M_WE#1 WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS3 F3 VDDQ H2 M_DQS4 F3 VDDQ H2 M_DQS6 F3 VDDQ H2
M_DQS0 DQSL VDDQ M_DQS1 DQSL VDDQ M_DQS5 DQSL VDDQ M_DQS7 DQSL VDDQ
mm mm mm
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
co o co o co o
s.s.c s.s.c s.s.c
M_DQM2 E7 A9 M_DQM3 E7 A9 M_DQM4 E7 A9 M_DQM6 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM1 D3 DML VSS B3 M_DQM5 D3 DML VSS B3 M_DQM7 D3 DML VSS B3
c c c c c c
B DMU VSS DMU VSS DMU VSS DMU VSS B
i i i
E1 E1 E1 E1
i i i
at at at
VSS VSS VSS VSS
at at at
G8 G8 G8 G8
M_DQS#2 G3 VSS J2 M_DQS#3 G3 VSS J2 M_DQS#4 G3 VSS J2 M_DQS#6 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#1 B7 DQSL VSS J8 M_DQS#5 B7 DQSL VSS J8 M_DQS#7 B7 DQSL VSS J8
h h
VSS
h h
P1 VSS P1
h h
VSS P1
ch
VSS P1
Sc c ScSc ScSc Sc
T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
kS kS
18 DRAM_RST# RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
okok okok k
1 RV67 2 L8 VSS T9 1 RV68 2 L8 VSS T9 1 RV69 2 L8 VSS T9 1 RV70 2 L8 VSS T9
o o
240_0402_1% ZQ/ZQ0 VSS 240_0402_1% ZQ/ZQ0 VSS 240_0402_1% ZQ/ZQ0 VSS 240_0402_1% ZQ/ZQ0 VSS
PX@
o o
PX@
o o
PX@ PX@
o o
eb eb eb
VRAM_ODT0 VRAM_ODT0 J1 VRAM_ODT1 J1 VRAM_ODT1 J1
eb eb eb
J1 B1 B1 B1 B1
M_CS0B#1 L1 NC/ODT1 VSSQ B9 M_CS0B#1 L1 NC/ODT1 VSSQ B9 M_CS1B#1 L1 NC/ODT1 VSSQ B9 M_CS1B#1 L1 NC/ODT1 VSSQ B9
ot t ot t ot t
18 M_CS0B#1 M_CKE0 NC/CS1 VSSQ M_CKE0 NC/CS1 VSSQ 18 M_CS1B#1 M_CKE1 NC/CS1 VSSQ M_CKE1 NC/CS1 VSSQ
J9 D1 J9 D1 J9 D1 J9 D1
mm mm mm
c.o
co c.o
co c.o
co
1
s.s
RV71 RV72
s .s M_CLK1
s .s +1.5VS_VGA +1.5VS_VGA
at
at at
at at
at
2
1
mm mm mm
C C
e e e
RV75 RV76
CV126
CV127
CV128
CV129
CV130
CV131
CV132
CV133
CV134
CV135
CV136
CV137
CV138
CV139
CV142
CV141
CV140
hh e e e
ch ch ch
40.2_0402_1% 40.2_0402_1%
ch ch
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sc
PX@ PX@ PX@
c c
kS kS kS
CV143
kS kS kS kS
2
0.01U_0402_25V7K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
o o o o o o
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
PX@
PX@
PX@
PX@
@
@
bobo bo
bo eb
o o
1
eb
PX@
ete ete
ot ot ot t
CV166
0.01U_0402_25V7K
o o NNo
2
NN NN
+1.5VS_VGA +1.5VS_VGA +1.5VS_VGA +1.5VS_VGA
1
mm mm mm
CV156
CV146
CV147
CV148
CV149
CV150
CV151
CV152
CV153
CV154
CV155
CV157
CV158
CV159
CV160
CV161
CV162
CV163
CV164
CV165
co o co o co o
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
c c c
4.99K_0402_1% 0.1U_0402_10V6K 4.99K_0402_1% 0.1U_0402_10V6K 4.99K_0402_1% 0.1U_0402_10V6K 4.99K_0402_1% 0.1U_0402_10V6K
i ic i ic i ic
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
at
at at
at at
at
2
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
e mm e mm e mm
hh e e e
Sc
D
c chch ch ch chc D
kS o kSkS okSkS o kS kS
oo o oo o oo o
b
e eb b
e eb b
e eb
ot t ot t ot ot
NNo NNo 2013/01/11 Compal
NNElectronics, Inc.
Security Classification Compal Secret Data
Title
Issued Date Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
SUN_VRAM A Upper
Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
NFL-C CTL51
Thursday, March 09, 2017 Sheet 19
LA-E841P
of 48
1 2 3 4 5
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
1 2 3 4 5
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
A A
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
c c c
B B
i i i i i i
at
at atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok o okok oo o k
o o o
eb eb eb eb eb eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
mm mm mm
C C
e
hh e e e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
o o o
bobo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc
D
c chch ch ch chc D
kS o kSkS okSkS o kS kS
oo o oo o oo o
b
e eb b
e eb b
e eb
ot t ot t ot ot
NNo NNo 2013/01/11 Compal
NNElectronics, Inc.
Security Classification Compal Secret Data
Title
Issued Date Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
SUN_VRAM A Lower
Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
NFL-C CTL51
Thursday, March 09, 2017 Sheet 20
LA-E841P
of 48
1 2 3 4 5
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
6U@
b oo o o
b oo
o o
b oo
o o
e eb e eb e eb
UG1
G517C1T11U_SOT-23-5
o t t ot t o t t
NNo NNo NNo
SA0000A4F00 Touch Screen
+3VS
Main:SA00006Y800 Panel Power W=60mils W=60mils
UG1 Non6U@ 2nd:SA00008R900 INVPWR_B+ +19VB
1 EMI@ L3 SD002000080
VOUT +LCDVDD USB20_P2_R
5 2 1 Non6U@
VIN 6 USB20_P2
RD34 1 2
1 2 0_0805_5%
GND USB20_N2_R
0.1U_0201_10V6K
4.7U_0402_6.3V6M
4 3 4
CG2
EN 6 USB20_N2
CG1
2 1 FU1
0.1U_0201_10V6K
3 MCM1012B900F06BP_4P
2 /OC
CG3
SM070003Z00 1 2
mm G524B1T11U_SOT23-5
mm mm
co o co o co o
D 1 2 1 1 D
SA00006Y800 @EMI@ C117 C118
c c c c c c
2 2
i
t ti i i i i
@ESD@
atat atat
DM10
<CPU> a a
USB20_N2_R 2
RG3 1 short@ 2 0_0402_5%
em em em
1
m m m
5 ENVDD USB20_P2_R 3
h e h e h e h
Sc ch Sc ch Sc ch Sc
SCA00001L00
kS <EC CTRL> kS kS Sc
ok ok k k
RT24 1 short@ 2 0_0402_5% DISOFF#
oo
27 BKOFF#
o o o o
bo
1
o 1
o bo
eb eb eb eb
R1677
e
+3VALW
te
10K_0402_5% C122
ot t ot t ot
220P_0402_50V7K
1
2
NNo NNo o
Touch Screen Power
2
NN
@
RTS3
+3VS_TOUCH 100K_0402_5%
2
1 2
1
RD35 0_0402_5% @
1
D
@ RTS1 @
<CPU> 5 BKL_PWM_CPU R258 1 short@ 2 0_0402_5% INVTPWM TS@ 1K_0402_5% QTS1 2
TOUCH_ON 27
FG2 2N7002_SOT23 G
mm mm mm
CTS2 S
3
1
1 2
co o co o co o
@ 1 3
R163 OUT +3VS_TOUCH_IN @
2
100K_0402_5% C121 TS@ 1 +3VS_TOUCH_IN
0.047U_0402_16V7K
G
IN
c c c
220P_0402_50V7K CTS3
i c i c i c
2 1 3LP2301ALT1G 1P SOT-23-3
i i i
4.7U_0402_10V6M 2 1
at at at
+3VS
2
at at at
C C
S
2 GND TS@
CTS1 @
em em em
AP2330W-7_SC59-3 0.1U_0201_10V6K QTS2
em em em
2
SA000080300
1 2
h h h h h h ch
Sc Sc Sc
RG5 0_0402_5%
c Sc Sc
TS@
Sc
kS kS
+5VALW
okok okok o o k
1 @ 2 TS_GPIO
o o o
8 TS_GPIO_SOC
o o o
1
R260 0_0402_5%
Touch Screen Power
eb bb eb
TS_GPIO_EC
eb eb
1 short@ 2 @
e
27 TS_GPIO_EC
te
R261 0_0402_5% RTS7
ot t ot ot t
100K_0402_5%
NNo o NNo
2
NN
1
Camera @
1
D
RTS2 @
1K_0402_5% QTS3 2
TOUCH_ON
EMI@ L12 +5VS_TOUCH 2N7002_SOT23 G
3 4 USB20_N4_R CTS4 S
6 USB20_N4
3
1 2
1 2 +5VS_TOUCH_IN @
USB20_P4_R
2
2 1 RD36 0_0402_5%
6 USB20_P4 0.047U_0402_16V7K
mm mm mm
G
@
co co co
TS@ 1 +5VS
S
SM070003Z00 TS@
.s .s .s
FG4
CTS5 @
s s s
icic icic icic
3 0.1U_0201_10V6K QTS4
OUT 2
at at at
at at
at
1 +5VS_TOUCH_IN 1 2
TS@ 1
CTS6 IN RG8 0_0402_5%
mm mm mm
4.7U_0402_10V6M 2 TS@
e e e
CC103~108 close JLVDS <1000mil 2 GND
hh e e e
ch ch ch
B B
e
5 EDP_TXN0 EDP_LN0P EDP_LN1P
te
1 2 1
ot ot t ot t
CC106 .1U_0402_16V7K
5 EDP_TXP0 EDP_LN1N 1
2
o NNo NNo
3 2
NN
EDP_LN0P 4 3
CC107 1 2 .1U_0402_16V7K EDP_LN1P EDP_LN0N 5 4
5 EDP_TXP1 EDP_LN1N 5
CC108 1 2 .1U_0402_16V7K 6
5 EDP_TXN1 EDP_AUXP_F 6
7
EDP_AUXN_F 8 7
9 8
+LCDVDD 9
10
1 short@ 2 DP0_HPD_R 11 10
5 DP0_HPD 11
RT19 0_0402_5% 12
USB20_P2_R 13 12
Touch Screen
mm mm mm
USB20_N2_R 14 13
DISPOFF#_R 14
co o co o co o
DISOFF# 1 2 15
15
c c c
18
i ic i ic i ic
EDP_AUXP_F 19 18
at
at at
at at
at
INVPWR_B+ 19
R5219 @ 20
1 2 EDP_AUXN_F 21 20
21
mm mm mm
0_0603_5% @ESD@ 1 1 22
+5VS_TOUCH 22
e e e
23
e e e
DM9 C119 @ @ C120 +3VS_TOUCH
USB20_N4_R +3V_CAMERA 23
hh ch ch ch
2 10P_0402_50V8J 10P_0402_50V8J 24
ch ch
24
Sc
25 36
c c
1
USB20_P4_R 2 2 USB20_N4_R 25 GND
kS kS kS
FG3 +3V_CAMERA 3 26 35
kS kS kS
Camera
kS
USB20_P4_R 27 26 GND 34
27 GND
o o o
3 28 33
o o o
A
OUT SCA00001L00 28 GND A
oo oo oo
1 1 29 32
1 @ 25 D_MIC_L_CLK 30 29 GND 31
eb eb b
+3VALW
eb eb e eb
IN C5274 C5275 25 D_MIC_L_DATA 30 GND
ot t ot t ot t
2 .1U_0402_16V7K 4.7U 6.3V M X5R ACES_50203-03001-002
GND 2 2 SE00000ZY80
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
co o co o co o
5 4 3 2 1
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
eb eb 0.1U_0402_16V7K 1 eb
APU_DP1_TXP3_C 0.1U_0402_16V7K 1 2 APU_DP1_TXP3
e e CLKte
C123
APU_DP1_TXP3 5
ot ot
APU_DP1_TXN3_C APU_DP1_TXN3
t t t
2 C124
o
APU_DP1_TXN3 5
NNo NNo 5N
o
APU_DP1_TXP2_C APU_DP1_TXP2
N
+3VS 0.1U_0402_16V7K 1 2 C125
APU_DP1_TXN2_C APU_DP1_TXN2 APU_DP1_TXP2
0.1U_0402_16V7K 1 2 C126
APU_DP1_TXN2 5 Data0
APU_DP1_TXP1_C 0.1U_0402_16V7K 1 2 C127 APU_DP1_TXP1
APU_DP1_TXN1_C 1 2 APU_DP1_TXN1 APU_DP1_TXP1 5
0.1U_0402_16V7K C128
APU_DP1_TXN1 5 Data1
APU_DP1_TXP0_C 0.1U_0402_16V7K 1 2 C129 APU_DP1_TXP0
APU_DP1_TXN0_C 1 2 APU_DP1_TXN0 APU_DP1_TXP0 5
0.1U_0402_16V7K C130
APU_DP1_TXN0 5 Data2
mm mm mm
co o co o co o
D D
8
7
6
5
8
7
6
5
RPH2 RPH1
ici c 4 3
i c c
HDMI_SCLK
i i ci c
at at at
499_0804_8P4R_1%
at at at
5 DP1_AUXP
m
2N7002KDW_SOT363-6 NET:mHDMIRES_GND
m +3VSm m e em mils
1
2
3
4
1
2
3
4
he e
Q6B
e h e WIDTH>20
h h
Sc ch Sc ch Sc ch Sc
Sc
kS ok kS ok kS k k
HDMIRES_GND
o o o o oo
o o bobo
2
eb eb eb
eb ete
ot t ot
ot ot
1 6 HDMI_SDATA
NNo o
5 DP1_AUXN
2N7002KDW_SOT363-6
NN NN
1
D
Q6A
+3VS R280 1 short@ 2 0_0402_5% 2 Q17
G SSM3K7002FU_SC70-3
1
S
3
+3VS R281
R200 2K_0402_5% 100K_0402_5%
DP1_AUXN 1 2
mm R202 2K_0402_5%
mm mm
co o co co o
2
o +HDMI_5V_OUT
DP1_AUXP 1 2
c c c
8 1
i i c i i c i i c
at at at
7 2
at at at
C 6 HDMI_SCLK 3 C
5 HDMI_SDATA 4
em m emem emem
1
e
EMI@
h h h ch
APU_DP1_TXP3_C R5222 1 2 20_0402_5% HDMI_R_CK+
h h h
4.7K_0804_8P4R_5% R183
Sc c cc cc
Sc
1M_0402_5%
S kS S kS S kS
1
k k k k
2
G
L16
o o o o o o
2
o o o
R184 short@
CG5
o @ESD@
o 1 HDMI_DETECT o
HP_DETECT
eb eb eb
3 1 2 1 2
0.1U_0402_16V7K 2
b
eHDMI_R_CK-
DM7
eb
5 DP1_HPD
e1b
D
10K_0402_5%
ot t ot
ot ot ot C131
APU_DP1_TXN3_C R5223 1 2 20_0402_5% HDMI_R_CK+ 1 9 HDMI_R_CK+ 0_0603_5%
1 Q15
NNo
10
SSM3K7002FU_SC70-3
8 HDMI_R_CK-N N
@
N N
EMI@
1
HDMI_R_CK- 2
2 9 SB000009Q80
EMI@ R185 220P_0402_50V7K
APU_DP1_TXP2_C R5224 1 20_0402_5% HDMI_R_D0+ HDMI_R_D0+ 4 HDMI_R_D0+ 2
2 4 7
HDMI_R_D0-
7
HDMI_R_D0-
Vf_max = 1.3V 100K_0402_5%
1 5 5 6 6
2
5V Level
3 3
CG6
m
0.1U_0402_16V7K 2
m mm 8
mm
co o c.o co c.o co
APU_DP1_TXN2_C R5225 1 2 20_0402_5% HDMI_R_D0-
t itic
at at
20_0402_5% HDMI_R_D1+
at DM8 at
2
aa @ESD@
mm mm mm
1
hehe 0.1U_0402_16V7K
e
hh e e
hh e HDMI Conn.
ch
HDMI_R_D1- 1 HDMI_R_D1-
1 9
Sc Sc Sc
10
c Sc Sc c
B CG7 B
kS
2
kS kS
HDMI_R_D1+ 2 8 HDMI_R_D1+
k k
2
k k
9
APU_DP1_TXN1_C R5227 1 2 20_0402_5% HDMI_R_D1-
o o o HDMI_R_D2- 4 7 HDMI_R_D2-
o o o HP_DETECT
JHDMI1 CONN@
o o o
o 4
o o
@ EMI@ 7 19
eb eb eb
18 HP_DET
eb eb eb
EMI@ +HDMI_5V_OUT
APU_DP1_TXP0_C R5228 1 2 20_0402_5% HDMI_R_D2+ HDMI_R_D2+ 5
5 6 HDMI_R_D2+ 17 +5V
ot t ot t ot t
6
HDMI_SDATA 16 DDC/CEC_GND
co o co o co o
6
HP_DETECT 1 1 9 HP_DETECT D1-
c c 8 HDMI_SCLK
c
2 2 HDMI_R_D2- D1+
i ic i ic ic
i HDMI_R_D2+
9 3
at at at
D2-
at at at
2
+HDMI_5V_OUT HDMI_SDATA 4 4 7 HDMI_SDATA D2_shield
7 1
mm mm mm
URH1 D2+
e e e
+HDMI_5V_OUT 6 +HDMI_5V_OUT
e e e
5 5 6
YUQIU_HD074-F19M1BR-A
hh 2
hh hh ch
Sc Sc Sc
W=40mils DC2381411060
c GND
Sc
3 3
Sc c
kS IN
1
o k k
+5VS
o k k o kSkS
o o o
8
A
3
b oo IP4292CZ10-TB o o
b b oo A
e eb SC300002C00 b
e eb
OUT
ee
ot ot ot t ot t
W=40mils
NNo NNo
1 SA00004ZA00
N N
AP2330W-7_SC59-3
CG4
0.1U_0402_16V7K 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
mm mm m
Custom 0.1
NFL-C mCTL51 LA-E841P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
co o co o co o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
i ci c i ci c i ci c
atat atat
t
aa t
em
e m eme m
he
mm
h
ch
h
ch he h
Sc Sc SSc c Sc Sc
kS oko kS k
oo k oo k k
o o bo bo
eb eb e bo e bo
ot t ot te ot te
NNo NN o NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
+3VS +3VS_CRT
mm mm mm
co o co o co o
0.1U_0201_10V6K
D D
4.7U_0402_6.3V6M
R234 1 2 0_0603_5%
C196
s.s.c s.s.c s.s.c
2 1
short@
+3VS_CRT_DVDD
C197
ici c ici c i ci c
at at at
1 2
at at at
R235 1 2 0_0603_5%
CRT@
em m em m em m
short@ CRT@
h e h e h e h
Sc ch c ch Sc ch Sc
Sc
kS o kS k S
ok kS k
oo k
o o o o
bo
Note: C3001,C3008,C3009,
b o o bo
ee b C3010,C3011,C3012,C3013
eb eb ete
ot t ot t ot
need to place to Chip
NNo NNo o
CRT@
NN
+3VS_CRT_DVDD VGA_VSYNC VGA_VSYNC_R
R236 1 2 47_0402_5%
CRT@
+3VS_CRT VGA_HSYNC VGA_HSYNC_R
C198 1 2 0.1U_0402_16V4Z R237 1 2 47_0402_5%
2P_0402_50V8C
2P_0402_50V8C
UCT1 CRT@ CRT@ 1 1
C5285
C5283
CRT@ 1 20 C200 1 2 2.2U_0402_6.3V6M
+1.2VO_VCCK AVC33 VDD_DAC_33
C201 1 2 0.1U_0201_10V6K 4 CRT@
AVCC_12 +1.2VO_VCCK
+3VS
14 25 C5279 1 2 0.1U_0402_16V4Z
VCC_33 VCCK_12 CRT@ 2 2
1 2 0.1U_0201_10V6K SOC_DP1_AUXP_R1_C 2 26 1 2 0.1U_0402_16V4Z
C5278 CRT@ +3VS C5284 CRT@ CRT@
5
5
SOC_DP1_AUXP
SOC_DP1_AUXN
C199 CRT@ 1 2 0.1U_0201_10V6K SOC_DP1_AUXN_R1_C 3 AUX_P
AUX_N
PVCC_33
CRT Connector
mm C5280 CRT@ 1
mm
2 0.1U_0201_10V6K SOC_DP1_P0_C1 5 17
mm
co o co o co o
5 SOC_DP1_P0 +HDMI_5V_OUT
C5282 CRT@ 1 2 0.1U_0201_10V6K SOC_DP1_N0_C1 6 LANE0_P HVSYNC_PWR 18 VGA_VSYNC
JCRT1 CONN@
5 SOC_DP1_N0
2 0.1U_0201_10V6K SOC_DP1_P1_C1 LANE0_N
RTD2166 VSYNC VGA_HSYNC
c c c c c c
POL1_SDA
i i i
R238 CRT@ 2 1 4.7K_0402_5% 10 23 BLM15BA220SN1D_0402 SM01000LU00 7
i i i
at at at
POL1/SPI_CEB RED_P VGA_SDA
at at at
+3VS_CRT R239 CRT@ 2 1 4.7K_0402_5% POL2 9 L59 6UEMI@ 12
C POL2 VGA_G VGA_G_2 C
22 1 2 2
2 1 4.7K_0402_5% GPI1_SCL 11 GREEN_P 8
R240 @ BLM15BA220SN1D_0402 SM01000LU00
VGA_HSYNC_R
em em em
12 GPI1/SPI_CLK 21 13
em em em W=40mils
L17 6UEMI@
+HDMI_5V_OUT 13 GPI2/SPI_SI BLUE_P VGA_B 1 2 VGA_B_2 3
GPI3/SPI_SO BLM15BA220SN1D_0402 SM01000LU00 9
h h h ch
+HDMI_5V_OUT
h h h
VGA_SCL VGA_VSYNC_R
R241 2 CRT@ 1 2.2K_0402_5% 15 14
R243 75_0402_1%
75_0402_1%
75_0402_1%
Sc c Sc Sc
VGA_SDA
Sc Sc Sc
R242 2 1 2.2K_0402_5% 16 VGA_SCL 4
kS
VGA_SDA
2P_0402_50V8C
2P_0402_50V8C
2P_0402_50V8C
2P_0402_50V8C
2P_0402_50V8C
2P_0402_50V8C
kS
CRT@ 27 1 10 G 16
RTD2166_SMB_SCL LDO_RSTB VGA_SCL
ok ok
30 28 @ 15 17
ok ok k
RTD2166_SMB_SDA SMB_SCL EXT_CLK_IN 1 1 1 1 1 1 G
C211
C212
C213
C214
C215
C5286
o
29 31 5
C217
o
0.1U_0201_10V6K
SMB_SDA EXT1.2V_CTRL
o o o
CRT_HPD
o o o
32 24 2
R5220
R5221
5 CRT_HPD
eb eb eb
2
HPD GND 2 2 2 2 2 2
eb eb eb
33 6UEMI@ 6UEMI@ C-H_13-12201560CP
EPAD_GND 6UEMI@ 6UEMI@ 6UEMI@ 6UEMI@ DC060006E00
ot t ot t ot t
CRT@ RTD2166-CG_QFN32_4X4 CRT@ CRT@ CRT@
Note:
@
2 1 RTD2166_SMB_SCL
R246 0_0402_5%
5,15,27 EC_SMB_CK2 2 1 RTD2166_SMB_SDA
R247 0_0402_5%
mm mm mm
5,15,27 EC_SMB_DA2
@ESD@
co co co
@ SC300001G00
VGA_HSYNC_R 6 3 VGA_VSYNC_R
.s .s .s
I/O4 I/O2
s s s +HDMI_5V_OUT
at at at
VDD GND
e mm e mm e mm VGA_SCL
4 1 VGA_SDA
e e e
I/O3 I/O1
hh ch ch ch
Sc ch ch
B B
AZC099-04S.R7G_SOT23-6
c c
kS o kSkS o kSkS @ESD@
o kSkS
o o o
D5
SC300001G00
bo bo o
VGA_R_2 VGA_G_2
bo bo o
6 3
I/O4 I/O2
e e eb eb
+HDMI_5V_OUT
oto te oto te 5 2
ot t
NNo
VDD GND
NN NN 4
I/O3 I/O1
1 VGA_B_2
AZC099-04S.R7G_SOT23-6
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS okSkS o kSkS
A
oo o oo o oo o A
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/09/01 Deciphered Date 2017/09/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DP to CRT RTD2166
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
mm mm mm
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
NFL-C CTL51 LA-E841P
co o co o co o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date : Thursday, March 09, 2017 Sheet 23 of 48
i ci c i ci c i ci c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS ok
ok
S k kS k kS
5 4 3 2 1
bo oo o oo o
bo Rising t i me b o b o
LDO mode Switcing mode
eb eb
+LAN_VDD_3V3
e e e
@
te
tneed>0.5mS ot t ot t
J1 LL1 SMT @
and <100mS
o
1 2
NNo o NNo
1 2 8/15 Change to LDO Mode
CL21 SMT @
+3VALW JUMP_43X79
@ UG5
NN LL2 @ SMT
CL8,CL23 @ SMT +LAN_VDD_1V0 CL13 & CL15 close UL1 Pin22
5 1 @
IN OUT +LAN_VDD_3V3
LL1 1 20_0603_5% CL14 & CL27 close UL1 Pin30
2
GND
RL35 1 @ 20_0201_5% 1 4 3 8111@ LL2
SS EN +LAN_REGOUT 1 2
mm mm mm
1U_0402_6.3V6K
1U_0402_6.3V6K
@ CL28 2.2UH +-5% NLC252018T-2R2J-N
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
co o co o co o
APL3512_SOT23-5 2 1 1 1 1 1 1 1 1
0.1U_0402_16V7K
D 2 D
CL23
@ 1
4.7U_0402_6.3V6M
CL11 CL12 CL13 CL14 CL15 CL26 CL27
c c c
CL21 8111@ 8111@ 8111@ @ @
CL8
8111@
i c i c i c
2 2 2 2 2 2 2 2
i i i
1
atat atat at at
RL29 2 @ LAN_PWR_EN_R
1 10K_0402_5% 2
27 LAN_PWR_EN 8111@
hem
e m
h eme m LL2, CL8, CL23 for 8161
h em
Place CL11~CL12
e m
close UL1 Pin 3,8
h
EC_LAN_ISOLATEB#_R 2 1
ch ch h
+3VS
Sc Sc Sc Sc
1K_0402_5% RM6
Sc Sc
1
CL8 & CL18 close LL2
kS kS
2
+LAN_VDD_3V3 +VDDREG @ CL29
ok k k
8151/8166 Co-Lay UL1
k k RM11
o o +LAN_VDD_3V3=40mil oo
0.1U_0402_16V7K
o
2 8111@
o o bo bo
bo L +VDDREG=40mil bo
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
RTL8111HSH 15K_0402_5%
CL20
CL19
CL10
b
0.1U_0402_16V7K
0.1U_0402_16V7K
b
2 2 1 1 2 1 8166@ SA000084T00
ee e e
1
te te
UL1 +LAN_VDD_1V0
CL16 ot t ot otot
0.1U_0402_16V7K
CL9 CL5
NNo o o
1 1
8111@
2 2 1 2 LAN_MDIP0 +LAN_REGOUT=60mil
NN NN
1 3 0923 PV CNG from DP00 E500
@ @ 8111@ LAN_MDIN0 2 MDIP0 AVDD10 8
LAN_MDIP1 4 MDIN0 AVDD10 30 +LAN_VDD_3V3 XTLI
LAN_MDIN1 5 MDIP1 AVDD10 22 +LAN_VDD_3V3
LAN_MDIP2 6 MDIN1 DVDD10 2 1 XTLO
LAN_MDIN2 7 MDIP2 11 +LAN_VDD_3V3 1M_0402_5% RL7
LAN_MDIP3 MDIN2 AVDD33
1
9 32
LAN_MDIN3 10 MDIP3 AVDD33 RL10 RL15
MDIN3 23 +VDDREG 1 short@ 2 10K_0402_5% YL1
CL9 & CL5 close to UL1: Pin 11,32 CL10& CL16 close to UL1: Pin 23 VDDREG(VDD33) 24 +LAN_REGOUT
RL6 2 short@ 1 0_0201_5% LAN_CLKREQ#_R 12 REGOUT 0_0603_5% 1 3
mm mm mm
CL19 close to UL1: Pin 32 8 LAN_CLKREQ# RTL8111G EC_PME# OD to EC
2
19 CLKREQB 21 1 3
co o co o co o
8,14,28 PLT_RST_BUF# PERSTB LANWAKEB EC_LAN_ISOLATEB#_R EC_PME# 27 NC NC
20
CL20 close to UL1: Pin 11
10P_0402_50V8J
10P_0402_50V8J
16 27
c c c
6 CLK_PCIE_LAN# REFCLK_N LED0
c c c
26
i i i
LED1/GPO TH1 CL25 CL24
i i i
LED1/GPO LAN_LINK#
at at at
13 25
at at at
4 PCIE_PTX_C_DRX_P0 HSIP LED2(LED1) 1 1
14 25MHZ_20PF_XRCGB25M000F2P18R0
4 PCIE_PTX_C_DRX_N0 PCIE_PRX_C_DTX_P0 17 HSIN
C CR11 1 2 0.1U_0402_10V7K 28 XTLI C
em em em
4 PCIE_PRX_DTX_P0 PCIE_PRX_C_DTX_N0 18 HSOP CKXTAL1
em em em
CR13 1 2 0.1U_0402_10V7K 29 XTLO
4 PCIE_PRX_DTX_N0 HSON CKXTAL2
h h h h h h ch
RSET 31 33
Sc cc cc
RSET GND
c Sc
2
kS kS S kS S kS
RL11
TSL1 @
o ok o o k o k
2.49K_0402_1%
o
SA000063500
o o o
25 XGND RL55 1 @ 2 0_0805_5%
o o o
+V_DAC 1 LANGND 24
eb eb eb
(SA000063500) 8166GSH 10/100
eb eb eb
LAN_MDIP3 RJ45_TX3+
1
2 TCT1 MCT1 23 RP5
LAN_MDIN3 TD1+ MX1+ RJ45_TX3- (SA000084T00) 8111HSH Giga
ot t ot t ot t
3 22 MCT1 1 8
Swap P/N 08/16 TD1- MX1- MCT2 2 7
11/18 modify vendor review results
NNo NNo NNo
4 21 MCT3 3 6
LAN_MDIP2 5 TCT2 MCT2 20 RJ45_TX2+ MCT4 4 5
LAN_MDIN2 6 TD2+ MX2+ 19 RJ45_TX2-
TD2- MX2-
LAN_MDIP1
7
TCT3 MCT3
18
RJ45_RX1+
75_0804_8P4R_1%
SD300002E80 2 11/15 change CONN.
8 17 CL2 +LAN_VDD_3V3
LAN_MDIN1 9 TD3+ MX3+ 16 RJ45_RX1- SE167100J80
TD3- MX3- 10P_1808_3KV JLAN1 CONN@
10 15 1 10
LAN_MDIP0 11 TCT4 MCT4 14 RJ45_TX0+ A2_AmberLED+
LAN_MDIN0 TD4+ MX4+ RJ45_TX0- 1 LAN_ACT# LAN_ACT#_R
12 13 CL3 EMI@ 2 1 9
TD4- MX4- A1_AmberLED-
3
mm mm mm
120P_0402_50V8J RL31 510_0402_5%
RJ45_TX3-
co co co
1 TX3-
8111@ DL1 2 @
.s .s .s
CAP_LAN-8700GS GIGA LAN CL35 RJ45_TX3+ 7
s s s
2 1 TX3+
@EMI@ SP050008Y00
at at at
RX1-
at at at
(SP050003P00) 10/100 0.01U_0402_50V7K 0.1U_0402_16V7K TSL1
1 2 8166@ RJ45_TX2- 5
(SP050006800) Giga TX2-
mm mm mm
10/100 LAN
1
he e e e e e
TX2+
h chch chch ch
RJ45_RX1+ 3
Sc c c
RX1+
kS kS kS
11/17 reserver for ESD request
kS kS kS
RJ45_TX0-
kS
2
B TX0- 13 B
@ESD@
o o o
RJ45_TX0+ GND1
o o o
1 14
bo bo o
DM12 TX0+ GND2
bo bo o
LAN_MDIP0 4 3 LAN_MDIN0
eb
11
eb
4 3 B2_WhiteLED+
ete ete
ot ot ot t
LAN_LINK# 2 1 LAN_LINK#_R 12
B1_WhiteLED-
o o NNo
RL30 2K_0402_5%
NN NN
SANTA_130456-701
1
powe rail need to check @
CL34 LANGND
68P_0402_50V8J
+LAN_VDD_3V3 5 2 2
Vbus GND
mm mm mm
co o co o co o
s.s.c s.s.c s.s.c
LAN_MDIP1 6 1 LAN_MDIN1
6 1
c
i ic c
i ic c
i ic
at at at
YSUSB2.0-5_SOT-23-6-6
at at at
SC300002E10
e mm e mm e mm
hh e e e
Sc c
@ESD@
chch chch chc
kS kSkS kSkS kSkS
DM13
LAN_MDIP2 4 3 LAN_MDIN2
o o o o o o
4 3
oo oo oo
eb eb eb eb
b
e eb
ot t ot t ot t
A A
c c c
SC300002E10
i c i c i c
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
i i i
atat atat atat
Date: Friday, March 10, 2017 Sheet 24 of 48
5 4 3 2 1
h em
e m
h eme m
h eme m
h
Sc ch Sc ch ScSc
h
ScSc
kS oko kS k
oo k k
oo k
o o bo bo
eb eb e bo e bo
ot t ot te ot te
NNo NN o NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o UA1
b oo
o o
b ooo o
eb eb eb
+3VS +DVDD +DVDD_IO LA3 +1.8VS
e e e
ot ot ot
20 1
t t t
+DVDD short@
19 MIC1_R DVDD 9 1 short@ 2 1 2
.1U_0402_16V7K
CA5
10U_0603_6.3V6M
CA6
.1U_0402_16V7K
CA7
10U_0603_6.3V6M
CA1 1 18 26 +5VS_AVDD RA2
INT_MIC RA3 1 2 1K_0402_5% CA4 1 2 4.7U_0402_6.3V6M INT_MICL_C 17 MIC2_R AVDD1 40 0_0603_5%
MIC2_L AVDD2 +1.8VS_AVDD 1 1 1 1
CA8
31 41 11/12 change bead to short pad
MIC1_VREFO_L PVDD1 +5VS_PVDD
30 46
27 MUTE_LED_IN MIC1_VREFO_R PVDD2 2 2 2 2
+MIC2_VREFO
29
MIC2_VREFO
1
23 45 SPK_R+
10K_0402_5% 24 LINE2_R SPK_OUT_R+ 44 SPK_R-
11/24 modify mute LED that controled by EC LINE2_L SPK_OUT_R-
RA30
mm m m
Internal Speaker
mm Place near Pin1 Place near Pin9
2
SPK_L+
co o c.o co o
16 42
co
D MONO_OUT SPK_OUT_L+ SPK_L- D
s.s.c s.s.c
43
.s
11/20 follow vendor review result
PC_BEEP 12 SPK_OUT_L- +5VS_AVDD LA4 +5VS
c c s PCBEEP
c
short@ +1.8VS_AVDD LA5 +1.8VS
i c i c i c
HPOUT_R RA4 HP_OUTR
i i i
+3VS 10 33 1 2 30_0402_1% 1 2 short@
at at
Headphone
at at at
at
8 HDA_SYNC_AUDIO SYNC HPOUT_R HPOUT_L RA5 HP_OUTL
32 1 2 30_0402_1% 1 2
HDA_RST_AUDIO# HPOUT_L 0_0603_5%
.1U_0402_16V7K
CA9
11
4.7U_0402_6.3V6M
CA10
8 HDA_RST_AUDIO# RESET# 0_0402_5%
em em em
.1U_0402_16V7K
CA12
4.7U_0402_6.3V6M
CPVDD
m m m
1
CA13
2
1 @ 2 5
e e e
2 +3VS SDATA_OUT SDATA_IN RA7 HDA_SDOUT_AUDIO 8 1 2
8 1 2 22_0402_5%
h h h h
RA6 4.7K_0402_5%
ch ch h
CA17 ALDO_CAP SDATA_IN HDA_SDIN0 8
Sc Sc Sc Sc
CA11 1 2 10U_0603_6.3V6M 7
Sc Sc
4.7U_0402_6.3V6M LDO3-CAP 6 2 1
kS kS
1 BCLK HDA_BITCLK_AUDIO 8 2 1
CA14 1 2 2.2U_0402_6.3V6M ACPVEE 34
ok ok kPlace k k
CPVDD 36 CPVEE 22
o o oo
CBN 35 CPVDD LINE1_L 21
MV: change LA7 footprint
o o bo
CBN LINE1_R MIC_JD
b bo b bo bo
CA15 1 2 2.2U_0402_6.3V6M CBP 37 48
near Pin26
MURATA BLM15PX221SN1D 0402 CBP SPDIFO/GPIO2
Place near Pin40
ete ete ete
SM01000NY00 LA7 EMI@ 15 JDREF RA9 2 1 20K_0402_1% GNDA
ot ot ot
D_MIC_L_CLK 2 1 D_MIC_CLK D_MIC_DATA 2 JDREF 28 AVREF CA16 2 1 .1U_0402_16V7K GNDA
21 D_MIC_L_CLK D_MIC_L_DATA 1 D_MIC_DATA D_MIC_CLK GPIO0/DMIC_DATA VREF
o o o
2 3 27 CA18 1 2 10U_0603_6.3V6M
21 D_MIC_L_DATA GPIO1/DMIC_CLK LDO1_CAP
NN NN NN
39 CA19 1 2 10U_0603_6.3V6M +5VS_PVDD LA6 +5VS
LA8 short@ LDO2_CAP short@
0_0603_5% PLUG_IN# RA10 1 2 39.2K_0402_1% SENSEA 13 25 1 2
14 SENSE_A AVSS1 38
11.18 change LA8 to short pad SENSE_B AVSS2 RA29
.1U_0402_16V7K
CA20
.1U_0402_16V7K
CA21
10U_0603_6.3V6M
CA22
10U_0603_6.3V6M
CA23
GNDA 0_0805_5%
1 2 GNDA
4 1 1 2 2
47 DVSS 49
+1.8VS +DVDD PDB Thermal Pad 100K_0402_5%
SI: remove DA8
1
1
mm RA25
mm mm
co o co o co o
2.2K_0402_5% 1K_0402_5%
GNDA
c c c
2
c c c
B
i i i i i i
at at t t
QA1
at at
HDA_RST_AUDIO#
3 1 PD#
11/17 change CONN
C
C C
emem
m m em m SPK
MMBT3904WH_SOT323-3
Power downe
SI: change CONN
1
e eRA13/RA14/RA15/RA16
SB000008E10
h h Internal
h
h h h ch
(PD#) power stage for save power
Sc
0V: c cc
10K_0402_5%
kS S
DA3
ok
CH751H-40PT_SOD323-2 3.3V: Power JSPK1
ok k k
2
SPK_R- SPK_R-_CONN
o o
short@ RA13 1 2 0_0603_5% 1
o o
SPK_R+ short@ RA14 1 SPK_R+_CONN 1
o bo o
2 0_0603_5% 2
o bo o
SPK_L- short@ RA15 1 2 0_0603_5% SPK_L-_CONN 3 2
eb eb eb eb
SPK_L+ short@ RA16 1 2 0_0603_5% SPK_L+_CONN 4 3
ete
4
ot t ot ot t
5
6 G1
NNo o NNo
G2
120P_0402_50V8J
120P_0402_50V8J
120P_0402_50V8J
CA473
2 2 2 2
120P_0402_50V8J
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at at at
PC Beep
at at at
e mm e mm e mm
hh e e e
chch ch ch ch
1 2 PC_BEEP_R
Sc
EC Beep 27 EC_BEEP# Reserve for ESD request.
c CA31
c
kS kSkS kS kS
INT_MIC_R HP_OUTR_R
kS
HP_OUTL_R
kS
.1U_0402_16V7K RA19 +MIC2_VREFO
B
47K_0402_5%
Jack detect
GNDA B
o o o
PC_BEEP
3
Combo Mic = High
o o o
APU Beep 8 APU_SPKR
1 2 1 2 1 2
bo o o
1
bo o o
CA33 CA34 DA4
Normal HP = Low
1
bb eb
.1U_0402_16V7K .1U_0402_16V7K DA6
eb
YSLC05CH_SOT23-3
e e
RA17
te e
SCA00002900 YSLC05CH_SOT23-3
ot t t ot t
RA20 SCA00002900 2.2K_0402_5%
o
ESD@
o NNo NNo
10K_0402_5%
@ESD@ MIC_JD
2
1 2 INT_MIC
Close N
toN
2
RA18
Codec pin12
10U_0603_6.3V6M
CA32
22K_0402_5%
1
2
1
1
GNDA
mm mm mm
COMBO AUDIO JACK
co o co o co o
s.s.c s.s.c s.s.c
MV: change RA21,22,23 to short pad
c c c
RA28
i ic i ic i ic
HPR, HPL, 15mil Keep 30mil
at at at
1 2 short@ JHP CONN@
at at at
0_0402_5% INT_MIC RA23 1 2 0_0402_5% INT_MIC_R 3
1
1 short@
mm mm
HP_OUTL
mm
RA27 RA24 2 0_0402_5% HP_OUTL_R
e e e
1 2
hh e e e PLUG_IN#
ch ch ch
0_0402_5% 5
Sc c ch ch c
kS kS kS
1 2 6
kS kS kS kS
CA40 @EMI@ short@
HP_OUTR RA32 1 2 0_0402_5% HP_OUTR_R 2
o o o
.1U_0402_16V7K
oo o oo o 4
oo o
eb eb eb eb
b
e eb
100P_0402_50V8J
CA474
100P_0402_50V8J
CA475
100P_0402_50V8J
CA35
1 2 1 1 1 7
1
CA38 @EMI@
ot t ot t ot t
A .1U_0402_16V7K RA31 A
@EMI@
@EMI@
22K_0402_5% GNDA YUQIU_PJ733-F07J1BE-A~D
2 2 2 DC23000E800
1 2
2
CA39 @EMI@
.1U_0402_16V7K
1 2
For ESD request
Security Classification Compal Secret Data Compal Electronics, Inc.
mm mm mm
CA30 EMI@ 2013/01/04 2015/01/04 Title
Issued Date Deciphered Date
co o co o co o
.1U_0402_16V7K
AUDIO ALC259-VC2-CG
i
atat atat atat
Date: Thursday, March 09, 2017 Sheet 25 of 48
5 4 3 2 1
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b oo
o o
e eb e eb e eb
ot t ot t ot t
NNo NNo o
UAS1
+5VS
NN+SATA_1V2
LAS1
SSDODD@ VDD_LXI 1 2
1 2 10 12
40mils 40mils
+SATA_3V3 VBUS VCCO 40mils +SATA_3V3
RAS1 4.7K_0402_5% 4.7UH_UHP252012BF-4R7M_20% 1
11 48 VDD_LXI SSDODD@
D 40mils VBUS_LDO LXI D
mm mm mm
1 CAS2
co o co co o
CAS3 0.1U_0402_16V7K
CAS1 2.2U_0603_10V6K
co
1 1 10U_0603_6.3V6M SSDODD@
s.s.c s.s.c
2
s.HDDPC
RAS2
s. 45
ODD_PC
40mils 14 VCCIN
ic i c
+SATA_3V3
ic c
i SRXP 29 i c c
ti
ODD_PC 30
SSDODD@
100K_0402_5% PGND
at
at ASM_RST# atat at
SSDODD@ 2 2 39 VCC_1
a
2
14 VCC_2 30 SATA_CRX_DTX_P2 30
em m 1 em m em m SATA_CRX_DTX_N2 30
18 VCCU_1 SRXN
SSDODD@
h e 34 VCCU_2
h e h e +SATA_3V3
h
CAS4 1U_0402_10V4Z
ch h h
32 near UAS1 Pin1
Sc c c Sc
VCCS STXN 33
c c SATA_CTX_DRX_N2 30
Sc
SSDODD@
27
SS SS
kS
VCCTXL STXP SATA_CTX_DRX_P2 30
CAS5 4.7U_0603_10V6K
ook k k k k
40mils
k
oo o oo 1
bo bo
2
e
43
b0_0201_5% SATA_CRX_R_DTX_P1 28
te e
+SATA_1V2
te te0_0201_5% t2 e
GPIO0 44
ot ot
SATA_CRX_R_DTX_N1 28 SSDODD@
46 VDD_2 GPIO1 9
o ASM_GPIO3 o o o
0_0201_5% 1NSSDODD@2 RAS5
13 VDD_3 GPIO2 8
NN N NN
SATA_CTX_R_DRX_N1 28
N
1NSSDODD@2 RAS6
24 VDDU_1 GPIO3 6 ASM_GPIO4 SATA_CTX_R_DRX_P1 28
28 VDDU_2 GPIO4 5 ASM_GPIO5
VDDS GPIO5 37 ASM_GPIO6
GPIO6 35 ASM_GPIO7 near UAS1
GPIO7
PGND
19 3 ASM_I2C_CLK
mm mm mm
C UTXN I2C_CLK ASM_I2C_DA C
20 2
co o c.o c40o co o
UTXP I2C_DATA
s.s.c .s
sUART_RX s.s.c
22
c 23 URXN
c c
UART_RX +SATA_3V3
i i c i i c T304
i i c
at at at
URXP UART_TX
at at at
41 T305 +SATA_1V2
USB20_P1_C 15 UART_TX
@
em mm mm
USB20_N1_C 16 UDP
em
@
UDM
e e e e1 1 1 1
CAS7
CAS8
CAS9
CAS10
CAS11
CAS12
CAS13
h h ch ch ch
ch 1 h
ASM_REXT
Sc
CAS14
CAS15
CAS16
CAS17
CAS18
CAS19
17
c 26 S S
REXT 1
Sc
1
Sc
kS kS kS
1 1 1 1 1 1
ASM_XO
o kXO
k o k o k
ASM_XI
oXI o 2 2 2 2 2 2 2 o
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_16V6K
25 42
o o TEST_EN
o o o o
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
bb bb eb
te te eb
2 2 2 2 2 2
e e
ot ot otot
21
+SATA_3V3 +SATA_3V3 oASM_RST# GNDA_1 31
o
SSDODD@
SSDODD@
SSDODD@
SSDODD@
SSDODD@
SSDODD@
SSDODD@
38 RAS7
UAS2
N N RST# GNDA_3 47
N N N N
SSDODD@
SSDODD@
SSDODD@
SSDODD@
SSDODD@
40mils 1 short@ 2
ASM_GPIO4 PGND
SSDODD@
1 8 0_0402_5%
ASM_I2C_DA 2 CS# VCC 7
3 SO HOLD# 6 ASM_I2C_CLK
4 WP# SCLK 5 ASM_GPIO5 49
GND SI GND3
ASM_GPIO3 RAS8 1SSDODD@ 2 4.7K_0402_5%
MX25L512EMI-10G_SO8 1 ASM_GPIO7
B
mm CAS20 SSDODD@
mm
ASM1153_QFN48_6X6 RAS9 1
m 2 4.7K_0402_5%
m B
c.o
co c.o
co c.o co
SSDODD@ 0.1U_0402_16V7K SSDODD@
PGND
.s .s .s
SSDODD@ ASM_GPIO6 RAS10 1SSDODD@ 2 4.7K_0402_5%
s 2
s s
icic cic
it itciRAS11
ASM_REXT
c SSDODD@ 2 12.1K_0402_1%
at t t
1
at aa aa
mm em em
e
hh e h em h em
ch
ASM_XI
h h
Sc c
kS
cc Sc c
kS
c
kS kS ASM_XO k
kS kS
LM9 EMI@
o o o
USB20_N1_C
o o o
4 3
o o o
6 USB20_N1
o SSDODD@
o o
e2b eb eb eb eb eb
CAS6 10P_0402_50V8C
ot t ot t ot t
1 USB20_P1_C 1 2
6 USB20_P1
c
i ic c
i ic c
i ic
at
at at
at at
atTitle <Title>
YSLC05CH_SOT23-3
SCA00001L00
e mm e mm e mm
hh e e e
Sc c chch chch
Size Document Number Rev
ch c
kS kSkS kSkS kS kS
B <Doc> <RevCode>
o
oo o o
oo o Date: Thursday, March 09, 2017 Sheet 26 o f o48
oo o
eb eb
b
e eb b
e eb
5 4 3 2 1
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b oo o o
e eb e eb e eb
ot t ot t ot t
+3VALW_EC Analog Board ID definition
2
0_0603_5% 1 1 1 C5254 1 1 2 2 BLM15BD601SN1D_2P 12k ohm 20K ohm 33K ohm 56K ohm
C5251 1 R210 R214
1000P_0402_50V7K
C5255
EMI@ CC217 C5252 C178 C5253 C5249 Ra DIS
+EC_VCC_VL
100P_0402_50V8J
2 2 2 2 2
1000P_0402_50V7K
1 1
0.1U_0402_25V6 100K_0402_1% 160k ohm 240k ohm 330k ohm 560k ohm
R214
1
0.1U_0402_25V6 0.1U_0402_25V6 2 AD_BID0
ECAGND
ECAGND 35
Stoney Ridge FT4 - E2/A6
mm mm m
2
m DB
co o co o co o
UMA@ PX@
111
125
D D
SI PV MV
s.s.c s.s.c s.s.c UMA
FANLESS R214 R214
22
33
96
67
9
UK1 56K_0402_1% 160K_0402_1%
c c c
SD034560280 SD034160380
c c c
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
i i i
1
i i i
15k ohm 27K ohm 43K ohm 75K ohm
atat atat
t t
R214
EC_GA20 VR_ON aa
em em em
1 21
m m m
8 EC_GA20 EC_KBRST# GATEA20/GPIO00 GPIO0F EC_BEEP# VR_ON 42
2 23
ch ch
6,33 SERIRQ LPC_FRAME# SERIRQ GPIO12 EC_CLR_CMOS EC_FAN_PWM1 32
Sc Sc c Sc
4 27
c Sc
6,8,33 LPC_FRAME# LPC_AD3 LPC_FRAME# ACOFF/GPIO13
5 B/I#
SS
kS kS LPC & MISC
6,33 LPC_AD3 LPC_AD2 LPC_AD3 B/I# 36
7
ok k k
PWM Output
k k
6,33 LPC_AD2 LPC_AD1 LPC_AD2
8 63 C184 0.01U_0402_50V7K 2 1 ECAGND
oo oo
6,33 LPC_AD1
o
LPC_AD0 10 LPC_AD1 BATT_TEMP/AD0/GPIO38 64 VGA_AC_BATT R484
o bo bo
6,33 LPC_AD0 LPC_AD0 AD1/GPIO39 ADP_I VGA_AC_BATT 15
o bo bo
65 ADP_I 35,37
1 short@ 2 CLR_CMOS# 7
b
LPC_CLK0_EC LPC_CLK0_EC ADP_I/AD2/GPIO3A AD_BID0
b
1 AD Input 12 66 0_0402_5%
6,8 LPC_CLK0_EC
e e e
CLK_PCI_EC AD3/GPIO3B ADP_ID
te te te
13 75
ot ot ot
6,8,33 LPC_RESET# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 EC_PME# ADP_ID 35
@EMI@ C5268 37 76
EC_SCI# EC_RST# IMON/AD5/GPIO43 EC_PME# 24
o o o
22P_0402_50V8J 20
2 6 EC_SCI# EC_SCII#/GPIO0E EC_CLR_CMOS
NN NN NN
1 @ 2 38
R223 10K_0402_1% GPIO1D EC_ACIN R229 1 short@ 2 0_0402_5%
KBL_ON#_R ACIN 15,37
2
1 @ 2 68
6 LPC_CLKRUN_L DAC_BRIG/GPIO3C
R355 10K_0402_1% DA Output 70 SERR# R483
31 KSI[0..7] EN_DFAN1/GPIO3D TS_GPIO_EC SERR# 8
KSI0 55 71 @ 10K_0402_5% C188 2 1 100P_0402_50V8J
KSI0/GPIO30 IREF/GPIO3E LAN_PWR_EN TS_GPIO_EC 21
KSI1 56 72
KSI1/GPIO31 CHGVADJ/GPIO3F LAN_PWR_EN 24
KSI2 57
1
KSI3 58 KSI2/GPIO32 83
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_SMB_CK3 8
KSI4 59 84
KSI4/GPIO34 USB_EN#/GPIO4B EC_SMB_DA3 8
KSI5 60 85 20mil trace
KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 11/20 add GPU_HOT# for GPU R222
PS2 Interface
mm mm mm
KSI6/GPIO36 EAPD/GPIO4D TP_CLK GPU_PROCHOT# 15,44 +EC_VCC_VL
KSI7 62 87 0_0402_5% 1 short@ 2
co o co o co o
31 KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK 31 +3VL
KSO0 39 88
s.s.c s.s.c
TP_DATA 31
s.s.c
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F
KSO2 41 KSO1/GPIO21
c c c
KSO2/GPIO22 PANEL_BKLEN USB_ON#
c c c
42 97 2 1
i i i
KSO3
i i i
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 WL_PWREN_EC# PANEL_BKLEN 5 +5VALW
at at at
KSO4 43 98 10K_0402_1% R228
at at at
KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 WL_PWREN_EC# 28
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH 2 @ 1
C C
KSO6/GPIO26 Matrix
em em em
VCIN0_PH/GPXIOD00 VCIN0_PH 35 +3VALW
em em em
KSO7 46 SPI Device Interface 10K_0402_1% R362
KSO8 47 KSO7/GPIO27
h h h ch
KSO8/GPIO28 EC_SPI_SO
h h h
KSO9 48 119
Sc Sc Sc
KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_SI EC_SPI_SO 6
c Sc Sc Sc
KSO10 49 120
EC_SPI_R_CLK 1 EC_SPI_SI 6
KSO10/GPIO2A SPIDO/GPIO5C 2 EC_SPI_CLK
kS
50 126 +3VALW_EC
kS
KSO11 SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B EC_SPI_CS0# R252 EC_SPI_CLK 6
ok ok
KSO12 51 128 0_0402_5%
ok ok k
KSO12/GPIO2C SPICS#/GPIO5A short@ EC_SPI_CS0# 6
o
KSO13 52 +3VS RP2
o
KSO13/GPIO2D LID_SW#
o o o
KSO14 53 1 8
o o o
KSO15 54 KSO14/GPIO2E 73 TOUCH_ON 2 7
eb eb eb eb eb eb
KSO15/GPIO2F ENBKL/AD6/GPIO40 TOUCH_ON 21 EC_SMB_DA3 VR_ON
KSO16 81 74 SPOK R5214 1 2 2.2K_0402_5% 3 6
KSO16/GPIO48 PECI_KB930/AD7/GPIO41 EC_MUTE# SPOK 38,41 EC_SMB_CK3
ot t ot t ot t
KSO17 82 89 R5215 1 2 2.2K_0402_5% SYSON 4 5
KSO17/GPIO49 FSTCHG/GPIO50 BAT_CHG_LED EC_MUTE# 25
90
mm mm mm
16 103 H_PROCHOT# is OD, LOW active 4 5
34 0.95VS_PWR_EN# GPIO0A H_PROCHOT#_EC/GPXIOA06 H_PROCHOT# 5,8,42
co co co
41 0.775PW_EN# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON 38
18 GPO BKOFF#/GPXIOA08 105 BKOFF# 2.2K_0804_8P4R_5%
.s .s .s
5 APU_RST#_EC GPIO0C DGPU_PWR_EN BKOFF# 21
19 GPIO 106
s s s
28 WLAN_WAKE# GPIO0D PBTN_OUT#/GPXIOA09 1.8VALW_PWREN DGPU_PWR_EN 8,16,44,46
25 107
at at at
32 FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 USB_ON# 29,32
at at at
29
8,34,42 VGATE EC_PME#/GPIO15
30
28 E51TXD_P80DATA EC_TX/GPIO16 EC_ACIN VGA_AC_BATT
31 110 2 1
mm mm mm
@ +3VALW
APU_FCH_POK 28 E51RXD_P80CLK EC_RX/GPIO17 AC_IN/GPXIOD01 EC_ON
1 short@ 2 GPIO18 32 112 R366 10K_0402_1%
e e e e e e
8 APU_FCH_POK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON 38
R251 0_0402_5% 34 114 ON/OFF# R5206
hh ch ch ch
ch ch
35 AC_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 LID_SW# ON/OFF# 32 KBL_ON#_R
2 1 36 115 Delay SUSP# 10ms 1 short@ 2
Sc
GPI KBL_ON# 31
c c
31 MUTE_LED_OUT NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# 32
R250 @ 10K_0402_1% 116 SUSP#
kS kS kS
SUSP# 34,39 0_0402_5%
kS kS
THERMAL_ALERT#
kS kS
SUSP#/GPXIOD05 117
B GPXIOD06 THERMAL_ALERT# 8 B
118
o o o
PBTN_OUT# 122 PECI_KB9012/GPXIOD07
AGND/AGND
o o o
@
bo bo o
8 PBTN_OUT# XCLKI/GPIO5D
bo bo o
123
GND/GND
GND/GND
GND/GND
GND/GND
124 V18R 2 1
XCLKO/GPIO5E V18R +3VALW_EC
eb
R5208 0_0402_5%
eb
2
e e
GND0
te te
C190 +1.8VALW
ot ot ot t
4.7U_0402_6.3V6M 0_0402_5%
o o NNo
DS9 @ESD@
LPC_RESET# 2 1 1
NN NN
KB9022QC_LQFP128_14X14
11
24
35
94
113
69
CK0402101V05_0402-2
mm ESD@
mm mm
co o co o co o
APU_FCH_POK 1 2 E51TXD_P80DATA 1 R211 2100K_0402_1%
c
i ic c
i ic +3VS_VGA
c
i ic
at at at
DS3 @ESD@
at at at
EC_KBRST# 2 1
e mm CK0402101V05_0402-2
e mm e mm
hh e e e
ch ch ch
DS4 @ESD@
Sc ch ch
SUSP# 2 1 +3VALW_EC
c c
kS kS kS kSkS kSkS
0.95VS_PWR_EN# 2 1
CK0402101V05_0402-2
2
o o o
R230 10K_0402_1%
oo o EC_SMB_DA3 6 1
oo o oo o
eb eb b
VGA_EXT_DA1 15
eb EC Side eb e eb
@PX@ Q4106A GPU External
ot t ot tSensor ot t
5
A ME2N7002D1KW-G 2N_SOT363-6 A
thermal
NNo NNo NNo
ESD@ +3VALW
SPOK C5265 2 1 100P_0402_50V8J EC_SMB_CK3 3 4
VGA_EXT_CK1 15
@PX@ Q4106B TP_CLK 2 1
ME2N7002D1KW-G 2N_SOT363-6 4.7K_0402_5% R244
TP_DATA 2 1
DS8 @ESD@ 4.7K_0402_5% R245
SLP_S3# 2 1
i ci c i ci c i c c
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
i
atat atat atat
Date: Thursday, March 09, 2017 Sheet 27 of 48
5 4 3 2 1
h em
e m
h eme m
h eme m
h
Sc ch Sc ch ScSc
h
ScSc
kS oko kS k
oo k k
oo k
o o bo bo
eb eb e bo e bo
ot t ot te ot te
NNo NN o NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
at
at at
at at
at
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
+3VS_WLAN +3VS_WLAN
1
CONN@ RN3
JWLAN1 4.7K_0402_5% WLAN Power
1 2
USB20_P3
2
3 1 2 4 +3VS_WLAN
6 USB20_P3 USB20_N3 5 3 4 6 WL_PWREN_EC# 27
6 USB20_N3 7 5 6 8
7 8 Active Low
2
9 10
11 9 10 12 RWL1
1
100P_0402_50V8J
11 12
0.1U_0402_25V6
CN4 CN5
0.1U_0402_16V7K
13 14
mm mm mm
200K_0402_5%
13 14 @RF@ @RF@
CN3
15 16
co o co o co o
D 15 16 CWL1 1 1 D
17 18 CN2
1
17 18
2
23 24 2 2
c c c
0.1U_0402_16V4Z
i c i c i c
+3VS_WLAN 23 24
G
25 26
i i i
@ESD@
at at at
25 26
at at at
DS14 SCA00001L00 4 PCIE_PTX_C_DRX_P2
27 28 1 3 +3VALW
27 28 E51TXD_P80DATA
1
USB20_N3
S
2 4 PCIE_PTX_C_DRX_N2
29 30 E51TXD_P80DATA 27
29 30 E51RXD_P80CLK
1 31 32 E51RXD_P80CLK 27 1
em em em
USB20_P3 31 32
m m m
3 RN4 33 34 CWL2 QWL1
4 PCIE_PRX_DTX_P2 33 34
10K_0402_5% 35 36 0.1U_0402_16V4Z S TR LP2301ALT1G 1P SOT-23-3
e e e
4 PCIE_PRX_DTX_N2 35 36
37 38
h h h h
YSLC05CH_SOT23-3
ch ch ch
2
39 37 38 40 2
Sc Sc Sc Sc
Sc
6 CLK_PCIE_WLAN 39 40
41 42 1 @ 2
6 CLK_PCIE_WLAN# 41 42 PLT_RST#_WLAN
kS kS kS
43 44 RWL2 0_0603_5%
ok ok k
43 44
k
0_0201_5% 45 46 APU_BT_ON# 8 WL_OFF#
8 WLAN_CLKREQ# 45 46
oo
1 2 47 48
o o
27 WLAN_WAKE# 47 48
@ 49 50
o o bo
RN5
o o bo
51 49 50 52
Output to EC <OD>
eb eb
51 52
eb eb
53 54
1
1
e
53 54
100P_0402_50V8J
0.1U_0402_25V6
@RF@ @RF@ 55 56
ot t ot t ot te
CN9 CN10 57 55 56 58
59 57 58 60
NNo NNo o
2
2 61 59 60 62
NN
63 61 62 64
65 63 64 66 +3VS_WLAN
67 65 66
67
68
GND 69 RN6
GND short@
WL_OFF#
1
0.1U_0402_25V6
100P_0402_50V8J
@RF@ @RF@ 1 2 APU_WL_OFF# 8
1 short@ 2 PLT_RST#_WLAN LOTES_APCI0019-P003H CN8 CN11
8,14,24 PLT_RST_BUF# SP070010DA0 0_0402_5%
RH21 0_0402_5%
2
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
at
at atat atat
C C
SSD
mm mm mm
c.o
.s co c.o
.s co JPHW5 need to short c.o
.s co
s s JSSD
s
icic icic icic
+3VS +3VS_SSD
at at at
@ JPHW5 JUMP_43X79
at at at
1 2 +3VS_SSD
1 2 3 1_CONFIG_3 3.3V_2 4
1 2 3_GND 3.3V_4
mm mm mm
1 5 6
5_NA NA_6
1
10U_0603_6.3V6M
CS105
e e e
7 8
e e e
CS100 9 7_NA NA_8 10 T161@
hh ch ch ch
ch ch
11 9_NA DAS# _10
0.1U_0201_10V6K
Sc
B B
2
11_NA
c c
2
kS kS kS
12
kS kS kS kS
13 NA_20 14
15 21_CONFIG_0 NA_22 16
o o o o o o
17 23_NA NA_24 18
bo bo o
25_NA NA_26
bo bo o
19 20
27_GND NA_28
eb
21 22
eb
29_NA NA_30
e e
23 24
te te
31_NA NA_32
ot ot ot t
25 26
27 33_GND NA_34 28
o o NNo
29 35_NA NA_36 30 DEVSLP_SSD
DEVSLP_SSD 6
NN NN
31 37_NA DEVSLP_38 32
2 SSDHDD@ 0.01U_0402_16V7K SATA_CRX_C_DTX_P1 39_GND NA_40
6 SATA_CRX_DTX_P1 CS101 1 33 34
SATA_CRX_C_DTX_N1 41_SATA-B+/PETn0 NA_42
1
6 SATA_CRX_DTX_N1 CS102 1 2 SSDHDD@ 0.01U_0402_16V7K 35 36
37 43_SATA-B-/PETp0 NA_44 38 RC379
<SSD> CS104 1 2 SSDHDD@ 0.01U_0402_16V7K SATA_CTX_C_DRX_N1
39 45_GND NA_46 40 10K_0402_5%
6 SATA_CTX_DRX_N1 SATA_CTX_C_DRX_P1 47_SATA-A-/PERn0 NA_48
6 SATA_CTX_DRX_P1 CS103 1 2 SSDHDD@ 0.01U_0402_16V7K 41 42 @
43 49_SATA-A+/PERp0 NA_50 44
2
45 51_GND NA_52 46
47 53_NA NA_54 48
49 55_NA MFG1_56 50
51 57_GND MFG2 _58 52
53 59_Notch M Notch M_60 54
mm mm mm
55 61_Notch M Notch M_62 56
Near CS101-CS104
co o
63_Notch M
co o
Notch M_64
co o
57 58
59 65_Notch M Notch M_66 60
c c c
SATA_CRX_DTX_P1 71_GND 3.3V_72
i ic i ic i ic
0_0201_5% 1 2 R130 65 66
26 SATA_CRX_R_DTX_P1 SATA_CRX_DTX_N1 73_GND 3.3V_74
at at at
0_0201_5% 1 2 R131 67
at at at
26 SATA_CRX_R_DTX_N1 75_CONFIG_2
ODD NSSDODD@
NSSDODD@
SATA_CTX_DRX_N1
mm mm mm
0_0201_5% 1 2 R132 68
26 SATA_CTX_R_DRX_N1 SATA_CTX_DRX_P1 GND
0_0201_5% 1 2 69
e
R133
e e e e e
26 SATA_CTX_R_DRX_P1 GND
NSSDODD@
hh ch ch ch
Sc c ch ch c
LOTES_APCI0103-P002A
kS kS kS
CONN@
kS o o kS o okS o o kS
oo oo oo
A A
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
mm mm mm
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
NFL-C CTL51 LA-E841P
co o co o co o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date : Thursday, March 09, 2017 Sheet 28 of 48
i ci c i ci c i ci c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
A B C D E
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
USB3.0 port x 2
NNo NNo NNo
USB3.0 need support 3.5A
6 USB3_TX1_P 2 1 CS1 USB30_MTX_C_DRX_P1 RS1 1 short@ 2 USB3TXDP1_C_R
change USB PWR SW SA00007AO00
0.1U_0402_16V7K 0_0402_5% low active
+USB_VCCA
+5VALW
mm mm US1 W=100mils
mm
co o co o co o
1 1 1
W=100mils
1000P_0402_50V7K
150U_B2_6.3VM_R45M
OUT
0.1U_0402_16V7K
5
47U_0805_6.3V6M
IN 2
USB30_MTX_C_DRX_N1 USB3TXDN1_C_R GND 1
2 1 CS2 1 short@ 2 4
c c c
6 USB3_TX1_N RS2 1 1 1
c c c
@ +
i i i
EN 3 @
i i
CS4
i
0.1U_0402_16V7K 0_0402_5% CS7
at at at
1 OCB
at at at
CS3 CS5
CS6 SY6288D20AAC_SOT23-5
SA00007AO00 2 2 2 2
em em em
0.1U_0402_16V7K
m m m
USB3RXDP1_C 2
1 short@ 2
e e e
6 USB3_RX1_P RS3
h h h h
0_0402_5%
ch ch ch
SGA00001E10
Sc Sc Sc Sc
Sc
<EC> 27,32 USB_ON# RS4 1 2
kS kS kS
0_0402_5%
ok ok k k
short@
o o o o oo
eb
o
eb
o bobo
USB3RXDN1_C
eb eb
RS5 1 short@ 2
6 USB3_RX1_N
ete
0_0402_5%
ot t ot ot ot
6 USB20_N5
4
LM3 EMI@
3
NNo
USB20_N5_C N N
USB2.0/USB3.0 port 1 NN o
CONN@
1 2 USB20_P5_C +USB_VCCA
6 USB20_P5 JUSB1
MCM1012B900F06BP_4P DM14 ESD@ 1
USB3RXDN1_C USB3RXDN1_C USB20_N5_C VBUS
SM070003Z00 1 9 2
USB20_P5_C 3 D-
USB3RXDP1_C 2 8 USB3RXDP1_C 4 D+
USB3RXDN1_C GND
5
mm mm mm
USB3TXDN1_C_R USB3TXDN1_C_R USB3RXDP1_C SSRX-
4 7 6 10
co o co o co o
7 SSRX+ GND 11
USB3TXDP1_C_R USB3TXDP1_C_R USB3TXDN1_C_R GND GND
c c c c c c
USB20_P5_C
i i i
3
i i i
at at at
ACON_TARAH-9R1491
at at at
3
2 2
YSLC05CH_SOT23-3
SCA00001L00 TVWDF1004AD0_DFN9
mm mm mm
c.o c.o c.o
1 CS8 USB30_MTX_C_DRX_P2 USB3TXDP2_C_R
co co co
6 USB3_TX2_P
2 RS6 1 short@ 2
0.1U_0402_16V7K
.s .s .s
0_0402_5%
s s s
icic icic icic
at
at at
at at
at
e mm 2 1 CS9 USB30_MTX_C_DRX_N2
e mm
e e e
6 USB3_TX2_N
0.1U_0402_16V7K 0_0402_5%
hh ch ch ch
Sc ch ch
3 3
c c
kS kSkS kSkS kSkS
USB3RXDP2_C
USB2.0/USB3.0 port 0
1 short@ 2
o o o
RS8
o o o
6 USB3_RX2_P
0_0402_5% CONN@
bobo bo bo
o o
+USB_VCCA
JUSB2
e e eb eb
DM11 ESD@ 1
te te
USB3RXDN2_C USB3RXDN2_C USB20_N6_C VBUS
ot ot ot t
1 9 2
USB20_P6_C 3 D-
o o NNo
USB3RXDP2_C 2 8 USB3RXDP2_C 4 D+
NN NN
USB3RXDN2_C 5 GND
1 short@ 2 USB3RXDN2_C USB3TXDN2_C_R 4 7 USB3TXDN2_C_R USB3RXDP2_C 6 SSRX- 10
6 USB3_RX2_N RS9
7 SSRX+ GND 11
0_0402_5% USB3TXDP2_C_R USB3TXDP2_C_R USB3TXDN2_C_R
5 6 8 GND GND 12
USB3TXDP2_C_R SSTX- GND
9 13
SSTX+ GND
mm mm mm
6 USB20_P6
co o co o co o
MCM1012B900F06BP_4P
SM070003Z00
mm mm mm
1
USB20_P6_C
3
e
hh e e e e e
chch chch ch
YSLC05CH_SOT23-3
Sc c c
SCA00001L00
oo o oo o oo o 4
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB 3.0/2.0 conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
mm mm mm
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
NFL-C CTL51 LA-E841P
co o co o co o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date : Thursday, March 09, 2017 Sheet 29 of 48
i ci c i ci c i ci c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb te eb
ot t ot t t
CONN@
2.5" SATA HDD connector JHDDo
NNo NNo +5VS_HDD1
1N
2 1 N
o
C155 1 2 0.01U_0402_50V7K SATA_CTX_C_DRX_P0 3 2
+5VS_HDD1 6 SATA_CTX_DRX_P0 SATA_CTX_C_DRX_N0 3
6 SATA_CTX_DRX_N0 C156 1 2 0.01U_0402_50V7K 4
+5VS 5 4
C153 1 2 0.01U_0402_50V7K SATA_CRX_C_DTX_N0 6 5
6 SATA_CRX_DTX_N0 C154 1 2 0.01U_0402_50V7K SATA_CRX_C_DTX_P0 7 6
D 6 SATA_CRX_DTX_P0 7 D
m mm mm
R201 1 short@ 2 0_0603_5% 8
m 8
co o co o co o
9
GND
1U_0402_10V4Z
0.1U_0201_10V6K
2 0_0603_5% R212 1 short@ 1 1 10
GND
C5261
C5262
ici c ici c i ci c ACES_51524-00801-001
hem
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch Sc
Sc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
C C
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
at
at atat at at
h emem h emem h em em
Sc c h
Sc
h cc h ch
Sc kS kS Sc
+5VALW
kS ok ok k S k
+5VS_ODD
ODD Power
o o o o oo o
o o o
1
eb eb eb eb e bb
JODDe
CONN@
ot t ot t ot
1 t
ROD1
NNo NNo N o
100K_0402_5%
N 2 1
2
ODD_PC 26 5
5
1
c.o
2
c.o c.o
8 ODD_PLUG# ODD_DA#_M 9
co co co
1 2 10
.s .s .s
+5VS_ODD 2 @ 1 10
s s s
+3VS
2
11
icic icic icic 1
R958 10K_0402_5%
0.047U_0402_16V7K 12 GND
G
at at at
@
at at at
1 3 GND
+5VS
4.7U_0402_6.3V6M
m m m
ESD@ ACES_51524-0100N-001
m 2 m m
COD4
e
hh e 1 1
hhe e e e
CS17
ch ch ch
0.1U_0402_16V4Z
COD3
10U_0603_6.3V6M
COD2
QOD2 SP01001AI00
Sc Sc c
0.1U_0201_10V6K
c S TR LP2301ALT1G 1P SOT-23-3 +3VS 2
c
kS 1 2 2 k kS
o o kS kS o kS kS
1 2
o o o o o o Place CS17 close to JODD
o o o
eb eb
bb eb eb
2
ROD3 0_0805_5%
e te
ot t ot10K_0402_5% ot t
R954
1
ODD_DA#_M 1 3
8 ODD_DA# D
S
SSM3K7002FU_SC70-3
mm mm mm
co o co o co o
A A
kS SITINC. kS kS
B
k
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION
k
CONTAINS
NFL-C CTL51 LA-E841P
o o k o o k
BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
o f o48
o
oo oo Date: Thursday, March 09, 2017 Sheet 30
oo
eb eb eb eb eb
eb
5 4 3 2 1
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
b oo
o o
+3VALW
b oooo
Keyboard conn b ooo o
eb eb eb
27 KSI[0..7]
e e e
KSI7
ot t ot t ot t
KSI6
NNo o NNo
KSI5
NN KSI4
KSI3 JKB1
KSI2 CONN@
2
KSI1 KSI1 32 34
KSI0 KSI7 31 32 G2 33
R5176 R5177
KSI6 30 31 G1
2.2K_0402_5% 2.2K_0402_5%
KSO9 29 30
29
mmR5178 mm mm
KSI4 28
28
1
co o 1 short@ 2 co o co o
KSI5 27
27 KSO[0..17] 27
at at at
at
0_0402_5% 24
PCH_SMBus a a
KSO14 KSO5 23
@ESD@ KSO13 KSO1 22 23
m m em m mm 22
h8e KSO11e e
KSI0 C193 2 1 100P_0402_50V8J KSO12 KSI0 21
e e
R5179
21
h h h
ch ch KSO10 h
KSO2 20
Sc Sc Sc c Sc
Sc
1 short@ 2 TP_SMBData KSO4 19 20
S kS kSKSO8
APU_SMB_SDATA1 19
ok ok k
KSO9 KSO7 18
k k
0_0402_5% 18
oo
KSO8 17
o o o o
bo
17
o o bo
KSO7 KSO6 16
eb eb
16
eb eb
KSO6 KSO3 15
15
ete
ot t ot t ot
KSO5 KSO12 14
14
NNo NNo o
KSO4 KSO13 13
13
KSO3
KSO2
KSO14
KSO11
12
11 12
11
NN
KSO1 KSO10 10
+5VALW +5VS KSO0 KSO15 9 10
KSO16 8 9
KSO17 7 8
7
1
6
CAP_LOCK# R203 1 +5VS 6
R110 2 3.3K_0402_5% 5
mm Q9 JKBL1
mm mm
27 CAP_LOCK#
R207 1 2 3.3K_0402_5% 4 5
co o co o co o
100K_0402_5% 27 MUTE_LED_OUT 4
+5VS_KBL CONN@ 3
S 6 2
2
c c c
GND 2
i c i c i c
2 5 1
i i i
+5VS
at at at
GND 1
at at at
27 KBL_ON# G
D SP01001RG00
em em em
1
em em em
4 ACES_50690-0320N-P01
3 4
0.047U_0402_16V7K
AO3413L_SOT23-3
h h 2 3 h h h h ch
Sc c Sc Sc
cc
Sc
1
1 2
kS kS S kS
@
k
1
ok k k
C94
o oCVILU_CF61042D0R0-10-NH o o o oo o
2
o o o
eb eb eb
SP01002HP00
eb eb eb
ot t ot t ot t
NNo NNo NNo CAP_LOCK#
MUTE_LED_OUT
1 1
mm mm mmESD@ CC123
c.o co c.o
co c.o co2 100P_0402_50V8J 2
ESD@ CC122
s.s s .s s .s 100P_0402_50V8J
icic +3VALW
icic icic
at at at
at at
at
CONN@
JTP1
e mm e mm e mm
e e e
1
h h 2727 TP_CLK TP_CLK 2 1
ch ch ch
Sc c TP_DATA 3 2
ch ch c
kS kS kS kSkS kSkS
TP_DATA RTS5
4 3
MUTE_LED_OUT
5 4
o o o
TP_SMBCLK 1 2
TP_SMBData 6 5
6oo
o o o o +5VS
o o o
7b
eteG2
b eb eb
100K_0402_5%
eb eb
ot ot t ot
8 G1
SP01001YK00
DM5
YSLC05CH_SOT23-3
SCA00001L00
ESD@
mm mm mm
co o co o co o
s.s.c s.s.c s.s.c Compal Electronics, Inc.
1
e mm e mm SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION e
mm Size DocumentKB/TP
e e e
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
hh hDEPARTMENT hh h
Number Rev
h
AND TRADE OF R&D
Sc c Sc Sc
ScMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.c
Sc c
B 0.1
EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
NFL-C CTL51 LA-E841P
kS o k
o k o k
o k S Date: Thursday, March 09, 2017 Sheet 31 of 48 k
o o kS
b oo b oo b oo
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
A B C D E
b ooo o
b oo
o o
b ooo o
te eb e eb e eb
o t ot t ot t
NNo
Powert Button Connector NNo NNo
+3VL
1 1
0.1U_0201_10V6K
mm mm LID_SW# mm
co C166o
co o co o
1
c s.s.c c s.s.c
1 JIO S/B
c s.s.c
i i c i i c i i c
atat atat at
at
2 CONN@ ESD@ CC124
JPWR 100P_0402_50V8J
em m em m em m
1 2 CONN@
h e 2 1
h e h e h
ch ch c ch+5VALW
JIO1
Sc Sc Sc
27 LID_SW# 2
Sc
3 5 1
S
27 ON/OFF#
kS kS S
4 3 G1 6 2 1
ok k k k k
4 G2 3 2
o o oo oo
bo bo
4 3
SP01000TB10 o
bo bo
E-T_6916K-Q04N-03R
eb
5 4
eb
ON/OFF#
e e 6 5 ete
ot t t
o ot ot
+3VS
+3VL 7 6
NNo o
1 +3VALW
8 7
NN NN
USB20_N7_C
ESD@ CC216 CR USB20_P7_C 9 8
100P_0402_50V8J 10 9
2 R215 1 ON/OFF# 2 USB20_N0_C 11 10
100K_0402_1% USB20_P0_C 12 11
USB20 12
13
27,29 USB_ON# 13
14
15 14
mm mm mm
2 6 SATA_LED# 15 2
16
co o co o co o
27 PWR_LED# 17 16
c c c
18
i i c i i c i i c
at
at at at at
at
19
G1 20
em em mm
G2
h em h em e
he
CVILU_CF31181D0R4-10-NH
Sc c h
Sc
h ch SP011411241
ch
kS Sc kS Sc kS Sc
o okok o o o k
oo o k
bb o o o
e te eb eb eb
eb
ot+3VS ot t ot
ot
+5VS
FAN conn
NNo NNo PV
LM5 SM070003Z00
N N
4 3 USB20_N0_C
+5VS 6 USB20_N0
EMI@
1
omm 40 mil c4 om mm
5
om
3 MCM1012B900F06BP_4P 3
c.o
GND1
1 c co co
10U_0603_10V6M
0.1U_0201_10V6K
EMI@
. 3.c
2
CE22 s. CE25
. 27 FAN_SPEED1 .s
cis s
1
s cs21 32
4
cic
it it icic
at t at at
27 EC_FAN_PWM1
2a 2 aa 1
mm em mm
e e em e e
1 ACES_50271-0040N-001
h h h h ch ch
ch
SP02000TS00
Sc c cc c
CE24
0.01U_0402_50V7KS
kS ok
S kS kS kSkS
ok
PV
o o
2
o o o
o bo o6 USB20_N7 o o
LM6 SM070003Z00
bb b eb
eb
4 3 USB20_N7_C
e e e eCR
ot t t t ot t
EMI@
oo
NNo NNo
CEM2
NN 6 USB20_P7
3.3P_0402_50V8J 1 2 USB20_P7_C
MCM1012B900F06BP_4P
EMI@
mm mm mm
co o co o co o
4 4
Sc c c 0.1 c c
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
S S kS
kS S S kS
B
kk
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION
kk
CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. NFL-C CTL51 LA-E841P
o
oo o oo o o Date: Thursday, March 09, 2017 Sheet 32 o f o48
oo o
eb eb eb eb eb
eb
A B C D E
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
TPM2.0
D D
mm omm mm
co o co o
+3VS
s.s.c +3VS_TPMs s
.c.co s.s.c
ici c R26 1
@
2 0_0402_5%
i c i c i ci c
atat at at at
at
hem
e m
h em e m
h e mm
e h
ch h ch
0.1U_0402_16V4Z
Sc c
@ c Sc Sc
Sc
@ @ @
kS
1 1 1 1
kS kS ok kS k
C35 C36 C37
o0.1U_0402_16V4Z
o
C34
o oo k
o o o o bobo
0.1U_0402_16V4Z
eb eb
2 2 2 2
eb eb ete
ot t ot ot
0.1U_0402_16V4Z
NNo N ot NN o
@
U5
N
26 5
6,27 LPC_AD0 23 LAD0 VDD 10
6,27 LPC_AD1 LAD1 VDD
20 19
6,27 LPC_AD2 LAD2 VDD
17 24
6,27 LPC_AD3 LAD3 VDD
mm mm mm
C C
22
6,8,27o o co o co o
6,8,27 LPC_FRAME# LFRAME#
c LPC_RESET#
16
i ci c
27 1
i ci c i ci c
at at at
SERIRQ NC
a t 6 LPC_CLK1
21
LCLK NC
2
3
at at
m em em
@ NC
m R29 1 2 4.7K_0402_5% 6 8
m em
he
+3VS_TPM
he e
1 @ 2 7 GPIO NC 9 R28 2 @ 1 LPC_RESET#
c
PP
c
NC
h h h h ch
Sc
R27 12 0_0402_5%
SS c S NC c
NC
Sc Sc
S kS
4.7K_0402_5% 4 13
k 11 GND
k
o ok NC okok k
14
18 GND 15 o o
bo o o o o o
25 GND NC
1
eb eb
28
ebSLB9665TT2.0-FW-5.00_TSSOP28 eb eb
GND NC
4.7K_0402_5% te
R31
t ot t ot t
@
oo
NN NNo NNo
2
B
mm mm mm B
.sc.oco c.o
.s co c.o
.s co
s
cic s s
VGAtit icic icic
H8 H10 H11 H12
at at
CPU
at at
H_2P5N H_6P0 H_2P5 H_2P5
aa
e mm H6
e m m HOLEA HOLEA HOLEA HOLEA
e mm
e e e
H7
hh ch hH3 ch ch
ch
H_5P0 H_5P0
Sc c H_5P0 c c
H1 H2 H4
S kS kS
kS S kS kS
@ @ @ @
ok
HOLEA H_5P0 H_5P0 H_5P0
1
HOLEA FD1 FD2
1
k
1
o o
bo oo o o o o o o
HOLEA HOLEA HOLEA HOLEA
b bH17b eb eb
@ @ @ @
e e@ H16 e
t te
1
1
t ot
H14
t ot
H13 H18 H20
o oH_2P8
NNo o
@ @ @ H_2P5 H_2P5 FIDUCIAL_C40M80 FIDUCIAL_C40M80
H_2P5X3P1N H_2P5X3P1N H_2P5X3P1N
1
@ @ @ @ @ @ @ @
1
1
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
mm mm mm
co o co o co o
A A
Sc c Sc IT c 0.1 c c
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
kS kSkS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL kSINC.
NFL-C CTL51 LA-E841P kS kS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
o o k
ELECTRONICS,
o f o48
oo o oo o Date: Thursday, March 09, 2017 Sheet 33
oo o
eb eb eb eb eb
eb
5 4 3 2 1
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
A B C D E
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
+5VS and ot
+3VS t
switch ot t ot t
NNo NNo NNo
+1.8V TO +1.8VS (5A)
+1.8VALW
R233 +1.8VS
short@
+1.8VS_R 1 2
Max:6.0A 1
mm mm omm
C205
+5VALW
10U_0603_6.3V6M
1U_0402_6.3V6K
+5VS 10U_0603_6.3V6M 0_0805_5%
co o co o
1
SHORT Max:4.0A 1 1 1
.c.co
C204
C206
s.s.c s.s.c
@ 2
cis
cs
U17 J509
c c
+5VS_R 2 2
c c
1 14 2 1
i i it
U18
i i
VIN1 VOUT1 2 1
at at t
short@ 2 13
at at
VIN1 VOUT1
aa
10U_0805_10V4Z
1U_0402_10V4Z
R2313 JUMP_43X118 1 1 1 7
5VS_GATE VIN VOUT
C202
C203
SUSP# 2 1 3 12 1 2 2 8
em em mm
ON1 CT1 VIN VOUT
m m
0_0402_5% C207 470P_0402_50V7K @
e e hehe
4 11 SUSP# 0_0201_5%1 2 R141 3 6
VBIAS GND 27,39 SUSP# 1.8VS_PWREN0_0201_5% 1 short@ ON CT
h h h
C209 2 2 2 R142
h ch
3VS_GATE 27 1.8VS_PWREN
Sc Sc c Sc
2 1 5 10 1 2 1000P_0402_50V7K
c
10mil ON2 CT2
c Sc
kS
0_0402_5% 4
kS kS kS
+3VS_R +5VALW VBIAS 1
ok k
R2318 6 9 5
k
1 1 VIN2 VOUT2 GND
short@ C2322 C2309 +3VALW 7 8 1 C216 9 C208
o oooo
oo
VIN2 VOUT2 GND
0.01U_0402_50V7K
0.01U_0402_50V7K
1U_0402_10V4Z
330P_0402_50V7K
o o bobo
15 +3VS 2
eb b
2 2 GPAD
eb b
@ AOZ1336_DFN8_2X2
ee e
2
te
EM5209VF_DFN14_3X2 J511
ot t ot t ot
SA00006U600
SA00007PM00 2 1
2 1
NNo NNo NN o
C2324
10U_0603_6.3V6M
C2323
10U_0603_6.3V6M
JUMP_43X118
+3VALW +5VALW
SHORT 1 1 1
C256
.1U_0402_16V7K
@
2 2 2
C2316
10U_0603_6.3V6M
C2318
10U_0603_6.3V6M
C2306
10U_0603_6.3V6M
C2305
1 1 1 1 10U_0603_6.3V6M
mm mm mm
co o co o co o
2 2 2 2
at at at
h emem h emem h emem
ch
Max:18.0A
h h h
Sc c ScSc ScSc kS Sc
kS
+0.95VALW U19 +0.95VS
okok okok k
AO4354_SO8
o o
8 1
o o o
4.7U_0402_6.3V6M
o o o
7 2
C222
eb eb eb
+0.95VS
1U_0402_6.3V6K
C225
6 3
eb eb eb
C221 2 1
5
ot t ot t ot t
4.7U_0402_6.3V6M
1
1 @2 1
R273 @
470_0603_5%
+5VALW
1 2
1 2 0.95VS_GATE
R270 +5VALW
1
4.7K_0402_5% C16 D Q83 @
0.95VS_PWR_EN# 2
1
.1U_0402_16V7K 2N7002K_SOT23-3
1
D G
2 2 S +APU_CORE_NB
27 0.95VS_PWR_EN#
mm mm mm
G RZ593
3
8
c.o c.o c.o
S Q84 U3A 1K_0402_5%
co co co
2N7002K_SOT23-3 +5VALW 3 LM393DR_SO8
.s .s .s
P
CORE_NB_GATE_BUFF
3
2
+ 1
s s s +0.775MOS 2 O
G
2
at at at
+3VALW +0.775VALW
at at at
R2635
4
100K_0402_5%
+5VALW
mm mm mm
6
e e e
1
e e e
2
D
3 R2634 G
3
hh ch ch ch
1
ch ch
100K_0402_5% Q2516B
Sc
S
c c
SB00000FG10 DMN66D0LDW-7_SOT363-6
1
kS kS kS
3
+0.775MOS
kS
Q135 Q2513
kS kS
RZ592
kS
1
+APU_CORE_NB AO3416L_SOT23-3 AO3416L_SOT23-3 +VDDCR_FCH_ALW S5_MUX_CTRL 5 G
D
1K_0402_5%
8 S5_MUX_CTRL
8
o o o
Q2516A U3B
o o o
S
2
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1 3 3 1 5
S
bo bo o
DMN66D0LDW-7_SOT363-6 R2636 LM393DR_SO8
D
bo bo o
P
4
+ 7 0.775VALW_GATE_BUFF
100K_0402_5%
eb
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2 2
eb
O
1
6
C2621
C2620
e e
C2618 -
te te
G
ot
C432
C431
ot ot t
G
G
2
1
4.7U_0402_6.3V6M CORE_NB_GATE
o o NNo
2
4
1 1 1
+0.775VALW
Q2515
AO3416L_SOT23-3
NN Q2514
AO3416L_SOT23-3
NN
1 3 3 1 +5VALW CORE_NB_GATE_BUFF R919 1 short@ 2 0_0201_5% CORE_NB_GATE
S
D
D
2
.1U_0402_16V7K 1 @ 2 0_0201_5%
G
G
2
2
@
+3VALW R917 100K_0402_5%
mm mm mm
co o co o co o
1
100K_0402_5% @ CORE_NB_GATE_CC
1
2
6
c c c
1
2
D
R916 Q2507B
i ic i ic i ic
G
at at at
@ DMN66D0LDW-7_SOT363-6 D
at at at
S
100K_0402_5% 2
1
0.775VALW_GATE_CC
@ G
1
mm mm mm
3
S Q93 @
S5_MUX_CTRL
e e e
5
D
2N7002K_SOT23-3
e e e
G
3
hh ch ch ch
Q2507A
ch ch
S
Sc
DMN66D0LDW-7_SOT363-6 @
c c
4
kS kSkS kSkS kSkS
VGATE
8,27,42 VGATE
o o o
4 4
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/06/10 Deciphered Date 2015/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. NFL-C CTL51 LA-E841P
mm mm mm
Date: Thursday, March 09, 2017 Sheet 34 of 48
co o co o co o
A B C D E
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
D D
h e h e 5A_Z120_25M_0805_2P +19V_VIN
h e h
Sc ch ScSc
h
ScSc
h
Sc
Sc
1 2
kS k
oo k k
oo k k
oo k
bobo bobo bobo
@ PJP1 EMI@ PL11
e e te
ACES_51483-00801-001 5A_Z120_25M_0805_2P
1 2
1
oto te 1 2
oto te @ PR1
0_0402_5%
o o te
2 3
NN NN 1 2
NN
ACIN_LED
1000P_0402_50V7K
0.022U_0402_25V7K
3 4 27 AC_LED#
1000P_0402_50V7K
100P_0402_50V8J
4 5
5 6
1
ADP_SIGNAL
EMI@ PC2
EMI@ PC3
EMI@ PC4
6 7 Charge_LED
EMI@ PC1
7 8 ACIN_LED PR2
2
9 8 100K_0402_5%
10 GND
mm mm mm
2
GND
co o co o co o
s.s.c s.s.c s.s.c PR4
PR3
c c c
10K_0402_5%
i i c ADP_SIGNAL 1
i i c i i c
at at at
2 2K_0402_5%
at at at
C ADP_ID 27 1 2 Charge_LED C
27 BAT_CHG_LED
3
3
emem em em
mm
1
e
he
LUDZS3.6BT1G_SOD323-2
h h h h ch ch
Sc c Sc Sc Sc Sc
1000P_0402_50V7K
PR6
100P_0402_50V8J
kS kS kS
1
100K_0402_5%
okok k k
1
10K_0402_5%
o o o o
2
o o o
PR5
@ PC5
PC6
ESD@ PD1 b b
o o o
eb eb
PD3
eb eb
2
ee ESD@ PD2
ot t ot t ot t
1
2
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at 27 ADP_I
e mm e mm e mm
hh e e e
chch chch ch
+3VALW_EC
Sc c c
B B
kS o kSkS o kS kS o kSkS
o o o
bo bo o
1
e bo e bPR9o PR10
eb eb
o
ot te ot te otot
16.2K_0402_1% 5.9K_0402_1%
NN o NN o NNVCIN1_PH
2
VCIN0_PH 27 27
1
PH1
100K_0402_1%_B25/50 4250K PR13
10K_0402_1%
2
mm mm mm ECAGND 27
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS okSkS o kSkS
oo o oo o oo o
eb eb b
A A
eb eb e eb
ot t ot t ot t
NNo NNo NNo
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/08/30 Deciphered Date 2019/08/30 Title
DC Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
mm mm DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
m m
0.1
co o co o co o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
i ci c i ci c i ci c
atat atat
t
aa t
em
e m eme m
he
mm
h
ch
h
ch he h
Sc Sc SSc c ScSc
kS oko kS k
oo k oo k k
o o bo bo
eb eb e bo e bo
ot t ot te ot te
NNo NN o NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
D D
em m em m em m
1
h e @ PJPB1 +16.8V_BATT+
h e +16.8V_BATT
h e h
Sc ch Sc ch 5A_Z120_25M_0805_2P Sc ch Sc
OCTEK_BTJ-06LMBRAB
Sc
EMI@ PL14
kS kS kS
8
ok ok k
GND
GND
7
6
o
1 2
o oo k
o o o o bobo
6 5 EC_SMB_DA1_R
eb b eb
eb
5 EC_SMB_CK1_R
e
4
B/I#_Rt te te
ot t ot
4
1
3 EMI@ PC8 EMI@ PC9
o
NNo NNo o
3 2 1000P_0402_50V7K 0.01U_0402_50V7K
2 1
NN
2
1
PR14
100_0402_5%
1 2
mm 20161116
mm EC_SMB_DA1 27,37
mm
co o c.oco co o
PR15
s.s.c .s s.s.c
100_0402_5%
c c sEC_SMB_CK1
1 2
c
i i c i i c 27
i i c
at
at at
at atat
C +3VL C
emem
mm emem
1
e
100K_0402_5%
h h h he h ch
PR16
h
Sc c Sc Sc ScSc kS Sc
kS o k k
PR17
o okok o o k
2
bo o o
100_0402_5%
bo eb
o
eb
o
1 2
e eb eb
B/I# 27
oto te ot t ot t
NN NNo NNo
3
+16.8V_BATT
3
mm mm m
@ PR20m
2
ESD@ PD5
c.o
co c.o
co c.o o
1
2M_0402_5%
L30ESD24VC3-2_SOT23-3 ESD@ PD6 @ PR19
.s .s .s c3.9K_0603_1%
1
PR18
s s s
L30ESD24VC3-2_SOT23-3 3.9K_0603_1%
1
mm mm em
e
hh e e e em
Sc c chch
h
cc h chc
6
B B
eb eb eb eb
L2N7002DW1T1G_SC88-6
ete
ot ot t ot t
3
o NNo NNo
1
NN
1M_0402_5%
5
+3VL
PR21
@ PQ2B
4
L2N7002DW1T1G_SC88-6 @
2
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS okSkS o kSkS
oo o oo o oo o
eb eb b
A A
eb eb e eb
ot t ot t ot t
NNo NNo NNo
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/08/30 Deciphered Date 2019/08/30 Title
BATT Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
mm mm m m LA-D712P Sheet
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
co o co o c.o
co
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
c
5
c
4 3
s
cic
2 1
i i c i i c it
atat atat
t
aa
em
e m eme m
he
mm
h
ch
h
ch he h
Sc Sc SSc c ScSc
kS oko kS k
oo k oo k k
o o bo bo
eb eb e bo e bo
ot t ot te ot te
NNo NN o NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
A B C D
1
D +19VB
2
G @ PQB2
2N7002KW_SOT323-3
CHG_N002
S
3
PRB2 @ @ PRB3
1M_0402_5% 3M_0402_5%
1 2 1 2
mm mm mm
co o co o c.o co
1 1
s.s.c s.s.c .s
+19V_VIN 20161206 change to AON6426 (MDU eop) +19VB_CHG
c P1 AON6366 (AON6426 x1PQB12
c P2
c s
c c c
20170105 change to code)
i i i i i iAON7506_DFN33-8-5
at at at
PQB11 AON7506_DFN33-8-5 PRB1 PQB13
at at at
AON6366E_DFN5X6-8-5 1
0.01_1206_1%
1 2
em em em
@ PJB1
e m 2 3 5 1 4
e m 1
1 2
2
e m 1
h 2 h h h
5 3 2
Sc ch c c h c ch Sc
Sc
3 5 3
S S
JUMP_43X79
0.1U_0402_25V6
kS S S
2200P_0402_50V7K
ok PCB8 @EMI@ k k k
4
1
1
ok k
+19V_VIN
PCB6
PCB7
10U_0805_25V6K
10U_0805_25V6K
0.01U_0402_50V7K
oo oo
4
1
1
PCB4
@0@ PRB4
0_0402_5%
PCB5 bo bo bo bo bobo
PCB9
2200P_0402_50V7K
2
e e ete ete
2
t
o t ot ot
2
2
3
2
NNo NN o NN o
PDB1
ACDRV_CHG_R
BAS40CW_SOT323-3
BATDRV_CHG 1 2 BATDRV_CHG_R
0.1U_0402_25V6
0.1U_0402_25V6
1
1
PCB1
PRB5
PCB11
1 1
1 2 CHG_N003 PCB12 4.12K_0603_1%
0.047U_0402_25V7K PQB1
PRB6 10_1206_1%
2
2
PCB10 1 2 CHG_N001 AON7934_DFN3X3A8-10
10
0.1U_0402_25V6
mm mm PDB2 mm
1
5 4
2.2_0603_5%
co o co o co o
D1
S2 D1
PRB7
s.s.c s.s.c s.s.c
2
RB751V-40_SOD323-2 6 3
S2 D1
i ci c i c i c 7 2 @ PRB8
i ci c
at
at
t t t2 t
VCC_CHG
2
S2 D1
D2/S1
+16.8V_BATT
aPCB13 1 a
0_0402_5%
a 8 1UG_CHG_R
a UG_CHG
4.12K_0603_1%
4.12K_0603_1%
2 2
REGN_CHG
BTST_CHG
PRB9
PRB10
UG_CHG
PRB11
h h h ch
LX_CHG
h h h
9
Sc Sc Sc
4.7UH +-20% 5.5A 7X7X3 MOLDING 0.01_1206_1%
c c c 1 Sc
kS
1U_0603_25V6K 1 2
ACP_CHG
ACN_CHG
kS S S
LX_CHG
k k
2 CHG 1 4
k k k
2
o o o
PCB14
o o o oo o
o o o
1U_0603_25V6K 2 3
20
19
18
17
16
bb bb eb eb
PUB1
e e
SRN_R
e e
SRP_R
t t t t ot t
PHASE
HIDRV
VCC
BTST
REGN
10U_0805_25V6K
10U_0805_25V6K
21
o oo
@EMI@ PRB12
4.7_1206_5%
NNo NNo
PAD
0.1U_0402_25V6
0.1U_0402_25V6
N N
PCB15
PCB16
1
1
1 15 LG_CHG
ACN LODRV
PCB17
PCB18
SNUB_CHG 2
2
2 14
ACP GND PRB13
2
BQ24725ARGRR_QFN20_3P5X3P5 10_0603_1%
CMSRC_CHG 3 13 SRP1 2 SRP_R
CMSRC SRP
1
PRB14
mm mmSRN 12 mm
6.8_0603_1% PCB20
1
ACDRV_CHG 2 SRN_R
co co co
680P_0402_50V7K
.1U_0402_16V7K
@EMI@ PCB19
2
ACDRV
s.s s .s s .s
icic icic icic
2
1 11 BATDRV_CHG
2 5
at at at
+3VL ACOK BATDRV
at at at
PRB15
ACDET
100K_0402_1%
IOUT
SDA
ILIM
SCL
e mm e mm e mm
hh e e e
Sc c
15,27 ACIN
ch ch ch ch chc
6
10
+3VL
kS kS kS kS kS kSkS
3 3
ILIM_CHG 1 2
o o o
IOUT_CHG
o o o
ACDET_CHG
SDA_CHG
SCL_CHG
bobo bo bo
o o
100K_0402_1%
eb
PRB16
eb
1
e e
620K_0402_1%
ot te ot te ot t
PRB20
1
PRB17
NN o +19V_VIN
1
422K_0402_1%
2
NN
PCB21
o
0.01U_0402_50V7K
NNo
2
PRB18
PRB19
2
1
1
0_0402_5%
0_0402_5%
2
mm mm mm
co o co o co o
s.s.c s.s.c s.s.c
EC_SMB_CK1 27
0.22U_0402_16V7K
@
100P_0402_50V8J
1
c
i ic c
i ic c
i ic
66.5K_0402_1%
1
at at at
PCB23
PRB21
at at at
PCB22
EC_SMB_DA1 27,36
mm mm mm
2
e e e
PRB22
e e e
2
hh ch ch ch
0_0402_5%
Sc c ch ch c
1 2
S
ADP_I 27
kS k k S kSkS kSkS
0.1U_0402_25V6
o o o o o o
1
PCB24
Vin Dectector bo bo bo bo b oo
te eMax. e te e eb
2
o ot18.12V ot o ot t
NNo
4
Min. Typ 4
L-->H
H-->L
17.16VN
16.76V N
17.63V
17.22V 17.70V
N N EC chip
Close
VILIM = 20*ILIM*Rsr
ILIM = 3.3*100/(100+620)/20/0.02
= 2.291 A
Security Classification Compal Electronics, Inc.
Compal Secret Data
Issued Date 2016/08/30 Title 2019/08/30
mm mm om
Deciphered Date
m CHARGER
co o co o c o
s.s.c s.s.c s.s.c
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev Size
0.1
c c c
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
i c i c i c LA-D712P
i i i
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
atat atat
t
aa t Date: Thursday, March 09, 2017 Sheet 37 o f 48
A B C D
h em
e m
h eme m emem
Sc ch Sc ch chch Sc
h
kS kS
S S Sc
o oko
k
oo k oo k k
eb
o bobo bo bo
eb ete ete
ot t ot ot
NNo NN o NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo +3VLP
PC303 NNo NNo
1U_0603_10V6K
1 2
@ PC304 @ PC305
D
100P_0402_50V8J 100P_0402_50V8J D
1 2 1 2
mm mm mm
co o co o co o
PR303 PR304
ici c ici c i ci c
atat at at PR305 PR306 atat
em m em m em m
20K_0402_1% 19.1K_0402_1%
e e e
1 2 1 2
h h h h
Sc ch Sc ch c ch
S20161122 Sc
Sc
kS oko kS oko kS +19VB_3/5V
k
oo k
o o o o bobo
PR302 PR301
eb eb eb eb
@ PJ301 71.5K_0402_1% 90.9K_0402_1%
e
1 2 1 2
te
JUMP_43X79 20161122
ot t ot t ot
+19VB +19VB_3/5V
10U_0805_25V6K
NNo NNo o
1 2
1 2
NN
PC321
CS2_3V
CS1_5V
1
FB_3V
FB_5V
10U_0805_25V6K
+3VALW
0.1U_0402_25V6
2200P_0402_50V7K
PC322
2
1
1
@EMI@ PC310
EMI@ PC311
PU301
21
1
1
RT6575DGQW(2)_WQFN20_3X3
10K_0402_1%
2
PR318
GND
CS2
FB2
LDO3
FB1
CS1
C EN_3V EN_5V C
mm mm mm
PQ302 6 20 PQ301
2
EN2 EN1
co o co o co o
AON7934_DFN3X3A8-10 AON7934_DFN3X3A8-10
i c c i c c i c c
4
4
PL301
i i i
at at at
11/15 change footprint L_5X5X3_M_2P LX_3V LX_5V
t at at
12/30 change footprint CYNTE_PCMB053T-3R3MS_2P 8 18 PL302
D1
D1
D1
G1
G1
D1
D1
D1
PHASE2 PHASE1
a
PL301 PC313 PR308 PR307 PC314 4.7UH_5.5A _20%_7X7X3_M
em em em
3.3UH_PCMB053T-3R3MS_5A_20% 0.1U_0402_25V6 2.2_0603_5% 2.2_0603_5% 0.1U_0402_25V6
em em em
1 2 LX_3V 10 9 1 2BST_3V_R 1 2BST_3V 9 17 BST_5V 1 2BST_5V_R 1 2 9 10 LX_5V 1 4
+3VALWP D1 D2/S1 BOOT2 BOOT1 D2/S1 D1 +5VALWP
h h h h h h 2 3
ch
Sc c ScSc ScSc Sc
UG_3V UG_5V
1
10 16
PR310
G2 kS
G2
S2
S2
S2
S2
S2
S2
4.7_1206_5%
4.7_1206_5%
kS
UGATE2 UGATE1
1
ok ok
@EMI@ PR309
ok ok k
LGATE2
LGATE1
o o
5
5
LDO5
BYP1
o o o o o o
VIN
@EMI@
1 1
eb eb eb
2
eb eb eb
2
+ SNB_3V + PC320
ot t ot ot ot t
11
12
13
14
15
PC302 220U_6.3V_ESR15M_6.3X6
NNo NNo
220U_6.3V_ESR15M_6.3X6 SNB_5V
LG_3V LG_5V
N
1
1
2 2
VIN_3/5V
@EMI@ PC315
680P_0603_50V8J
PR311
+5VALWP
680P_0603_50V8J
2.2_1206_1%
@EMI@
PC316
2
2
+19VB_3/5V 1 2
+5VLP
1U_0603_25V6K
1U_0603_10V6K
3VALWP
1
@ PC317
PC318
Vout=2*(1+PR303/PR305)=3.3V
2
mm mm om
B B
om
5VALWP
c.o co c.o
co c
@ PR312 Vout=2*(1+PR304/PR306)=5.14V
.s .s s. .c
0_0402_5%
s s
icics
EN_5V 1 2
icic icic
at
at at
at atat
mm mm em
@ PR313
e e e e
0_0402_5%
m
he
EN_3V
hh ch ch ch
1 2
Sc ch
20170105 change short pad
c c c
kS S kS
@ PR317
kS kS k S kS
0_0402_5%
27 MAINPWON
1 2
o o oo k o o
bobo bo o
eb
o o
e e eb eb
EN_5V3V
te
1 2
ot t t ot t
27 EC_ON
o oo
NNo
2.2K_0402_5% PR314
NN +5VALWP
NN @
1
PJ303
2 +5VALW
@ PJ305
1 2
+5VLP 1 2 1 2
JUMP_43X39
402K_0402_1%
JUMP_43X118
1
4.7U_0805_25V6-K
1
@
PR316
PC319
PJ302
@ PJ304
+3VALWP 1 2 +3VALW 1 2
+3VLP +3VL
2
1 2 1 2
mm mm mm
2
A JUMP_43X39 A
JUMP_43X118
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic ic
i2019/09/01 Compal Electronics, Inc.
Security Classification Compal Secret Data
at
at atat atat
Issued Date 2016/09/01 Title
Deciphered Date
3VALW/5VALW
e mm m m m m THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
e he e he e
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
hh ch
Custom 0.1
h h
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Sc c c c c c c
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kS kS kS
Date: Thursday, March 09, 2017 Sheet 38 of 48
kS o o kS o o kS o o kS
5
b oo b oo 4
b oo 3 2 1
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h em
e m
h eme m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS oko kS oko kS k
oo k
o o o o bo
eb eb eb eb e bo
ot t ot t ot te
NNo NNo NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
mm @ PJM1
mm +19VB_DDR
mm
co o co o co o
1 2 PRM1
+19VB 1 2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
D JUMP_43X79
+1.2VP D
ic c ic c i c c
1
i i i
@EMI@ PCM1
PCM2
PCM3
atat atat atat +0.6VSP
UG_DDR
1
PCM4
2
em m em m em m
0.1U_0603_25V7K
e e e
2
LX_DDR
h h h h
ch ch ch
10U_0603_6.3V6M
10U_0603_6.3V6M
Sc Sc Sc Sc
Sc
1
PCM5
PCM6
kS ok kS ok kS k
16
17
18
19
20
o o oo k
2
o o bo
VLDOIN
PHASE
UGATE
BOOT
VTT
o o bo
21
eb eb
PAD
eb eb e
LG_DDR
te
15 1
ot t ot t ot
LGATE VTTGND
1
NNo NNo NN o
14 2
D1
D1
D1
G1
PLM1 PRM2 PGND VTTSNS
1UH_11A_20%_7X7X3_M 11.5K_0402_1%
1 2 LX_DDR 10 9 1 2 CS_DDR 13 3
+1.2VP D1 D2/S1 PCM7 CS GND
1U_0402_6.3V6K
1 2 12 4 VTTREF_DDR
G2
S2
S2
S2
VDDP VTTREF
1
PRM4
5.1_0603_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
8
VDD_DDR
1
1
@EMI@ PRM3 1 2 11 5
+5VALW VDD VDDQ +1.2VP
1
PGOOD
PCM8
PCM9
4.7_1206_5% PCM15
PCM10
PCM11
PCM12
PCM13
mm mm mm
VDDP_DDR
co o co o co o
TON
2
1 2
SNB_DDR
1
0.033U_0402_16V7K
FB
S5
S3
s.s.c s.s.c s.s.c
2
PCM16
@EMI@ PCM14 1U_0402_6.3V6K
c c c
10
6
i c i c i c
680P_0402_50V7K PQM1 PUM1
i i i
2
at at at
AON7934_DFN3X3A8-10 PRM5 RT8207PGQW_WQFN20_3X3
at at at
5.1_0603_5%
FB_DDR
1 2 PRM6
TON_DDR
emem emem em em
6.04K_0402_1%
S5_DDR
+1.2VP
S3_DDR
PWROK_DDR PRM7 1 2
h h h h h h ch
@ PTPM1 470K_0402_1%
Sc Sc Sc
+19VB_DDR
c c c Sc
1 2
kS S S kS
1
k k
C @ PRM8 C
o ok o ok o k
0_0402_5%
o
PG_+2.5V
bo bo o
1 2 PRM9
o o 10K_0402_1%
o
e eb e eb eb eb
2
t t ot t
1 2
oo t 27 SYSON
oo t
NNo
@0@ PRM10
NN NN 0_0402_5%
1
@ PJM2
PCM17
0.1U_0402_10V7K
JUMP_43X118
+1.2VP 1 2 +1.2V_VDDQ Vout=0.75* (1+PRM6/PRM9)=1.2V
2
1 2 @
@ PJM3
m mm mm
JUMP_43X39 @ PRM12
m
c.o c.o c.o
1 2 0_0402_5%
co co co
+0.6VSP 1 2 +0.6VS_VTT 1 2
1
em mm mm
@ PCM18
em
0.1U_0402_10V7K
e e e e
2
h h ch ch ch
Sc c ch ch c
kS o kSkS o kSkS o kSkS
o o o
bobo bo bo eb
o o
ete e te eb
oto ot o ot t
B NN NN NNo B
@ PJ2502
JUMP_43X39
mm mm PC2501
mm 1 2
co o c.o co o
+2.5VP 1 2 +2.5V
co
22U_0603_6.3V6M
s.s.c .s s.s.c
PU2501
s
1 2 SY8032ABC_SOT23-6
c c c
@ PJ2501 PL2501
i ic i ic i ic
at at at
JUMP_43X39 1UH_2.3A_+-20%_2.5X2X1.2_F
at at at
+3VALW 1 2 IN_2.5V 4 3 LX_2.5V 1 2
1 2 IN LX +2.5VP
mm +3VALW m mm
1 2 5 2
e e e e m PG GND
e e
hh ch ch ch
PR2504 6 1
ch1.2V ch
68P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
1
Sc
100K_0402_5%
c c
PC2504
PC2505
PC2506
1
2
o o o
0_0402_5% 4.7_0402_5% 32.4K_0402_1%
o o o
SYSON 1 2 EN_2.5V
oo oo oo
2
eb eb b
2
eb eb e eb
.1U_0402_16V7K
SNB_2.5V
1
ot t ot t ot t
PC2502
FB_2.5V
1
PR2503
1
2
@EMI@ PC2503
680P_0402_50V7K PRM2507
2
10K_0402_1%
Vout=0.6V *(1+PRM2506/PRM2507)=2.544V
2
mm mm mm
co o co o co o
A A
oo k oo k
1.2VP/0.6VSP/2.5V oo o
Title
Issued Date 2019/09/01
e bobo e bo bo e b bo THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Re v
te te te
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ot ot ot
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
NN o NN o 4
NN o 3 2
Date: Thursday, March 09, 2017
1
Sheet 39 of 48
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
5 4 3 2 1
b oo
o o
b oo
o o
b ooo o
e eb e eb e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
D D
mm mm mm
co o co o co o
PC1801
c c c
2 SNB_1.8V
c c c
1 1 2
i i i i
PU1801
i i +1.8VALWP
C
at
at at
@ PJ1802
at 4 5 PL1801
atat C
em em em
PGND NC
em em em
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
+3VB_1.8V LX_1.8V
+3VALW 1 2 3 6 1 2
h h h ch
1 2 IN LX
h h h
Sc Sc Sc
PG_1.8V EN_1.8V
1
c Sc Sc Sc
2 7
PG EN
1
kS kS
@ PTP1801 PR1803
PC1803
PC1804
PC1805
PC1806
22P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
ok ok
1 8 20.5K_0402_1%
ok ok k
FB SGND
o
9
2
PGND
o o o o o o
2
@
eb eb eb eb eb eb
FB_1.8V SY8003ADFC_DFN8_2X2
ot t ot t ot t
1
NNo 20170105 change short pad
@ PR1801
0_0402_5%
NNo
PR1804
10K_0402_1% NNo
2
1 2
27 1.8VALW_PWREN
+1.8VALWP +1.8VALW
1
PC1807
PR1805
1M_0402_5%
.1U_0402_16V7K
1
@ PJ1801
JUMP_43X79
1 2
2
1 2
2
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
3A continuous
s s s
icic icic icic
3.5A current limit
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS kSkS kSkS kSkS
B B
o o o o o o
bobo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS okSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
A A
co o co o co o
1.8VALWP
s.s.c s.s.c s.s.c
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
c c c LA-D712P
i c i c i c
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
i i i
atat atat atat
Date: Thursday, March 09, 2017 Sheet 40 of 48
5 4 3 2 1
h em
e m
h eme m emem
Sc ch Sc ch chch Sc
h
kS kS
S S Sc
o oko
k
oo k k
oo k
eb
o bobo bobo
eb ete ete
ot t ot ot
NNo NN o NN o
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i i c i i c
atat atat atat
h emem h emem h emem
Sc c h
Sc
h
Sc
h ch
kS Sc Sc kS Sc
o okok ookok o o o k
o o o
eb eb eb eb ebeb
ot t ot t ot t
NNo NNo NNo
mm mm mm
c.o
.s co c.o
.s co c.o
.s co
s s s
icic icic icic
at
at at
at at
at
emm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS okS kS
o o o
bo
bo bo
bo eb
o o
ete ete eb
oto oto ot t
NN NN NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i ic i ic i ic
at
at at
at at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
kS o kSkS o kSkS o kSkS
oo o oo o oo o
eb eb eb eb
b
e eb
ot t ot t ot t
NNo NNo NNo
mm mm mm
co o co o co o
c s.s.c c s.s.c c s.s.c
i i c i ic i i c
atat atat atat
h em
e m
h em
e m
h eme m
h
Sc ch Sc ch Sc ch ScSc
kS okokS oko kS k
oo k
o
b bo o
b bo bo
bo
te
te te
te te
te
kS k kS k kS k kS
A B C D
b oo
o o
b oooo
b ooo o
e eb e eb e eb
@ PJF1
ot t ot t ot t
JUMP_43X79
NNo NN o NNo
@0@ +19VB_0.95V 1 2
PRF1 0_0402_5% 1 2 +19VB
1 2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
27,38 SPOK
PCF1
PCF2
1
1
1M_0402_1%
PCF3
PCF4
1
1
PRF2
PCF14
0.1U_0402_25V7K
2
EMI@
@EMI@
@ PRF4
0_0402_5%
mm mm mm
2
1 2
co o change co o co o
27 0.95VALW_PWREN
2
1 1
ici c i ci c i ci c
atat at at BST_0.95V 12.2_0402_5%2 BST_0.95V_R10.1U_0402_25V6
PRF3 PCF5
atat +0.95VALWP +0.95VALW
em m em m em m
+3VALW 2
h e h e h e @ PJF2
h
Sc ch c c h c c h
Sc
Sc
JUMP_43X118
kS kS
1
kS kS S
1 2
10K_0402_1%
k
PUF1 1 2
ok2 k
PRF9
10
oooo oo oo
1
NB671GQ-Z_QFN16_3X3 PLF2
o bobo
1UH_6.6A_20%_5X5X3_M
b b
VIN
BOOT
b b
EN_0.95V 13 8 LX_0.95V 1
ee ee ete
2
EN SW
ot
27 PGOOD_0.95V t
ot t ot
NNo NNo PRF5 o
4 9
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
PGOOD SW
3
NC SW
15 NN
1
@EMI@
PCF7
PCF8
PCF9
PCF10
PCF15
PCF16
5 16 4.7_1206_5%
NC SW
2
6 7
NC VOUT
1SNUB_0.95V
14 2
VCC
AGND PGND
FB
mm mm mm
co o co o co o
s.s.c s.s.c s.s.c
VCC_0.95V 11
12
PCF11
i ci c i ci c @EMI@
i ci c
at
at at at at at
PCF12 680P_0402_50V7K
2
2
1 2 2
h emem h em em 22P_0402_50V8J
h emem
Sc c h cc h cc h ch
Sc
1
FB_0.95V
kS kS kS
1 2
kS k S 2.2U_0603_10V6K k S k
PCF13
o o
PRF7
o o o o
2
o o o
1
o o o
17.8K +-1% 0402
eb eb eb eb eb
eb
ot t ot t ot t
PRF8
30K_0402_1%
Vout=0.6V* (1+PRF7/PRF8)=0.956V
NNo NNo NNo
2
Current limit = 8A
@ PJC3
1 2
+0.95VALW 1 2 +0.775VALW
mm mm mm
JUMP_43X39
c.o
.s co c.o
.s co c.o
.s co
s s s 20161221
icic cic
it icic
at
at at
a+3VALW at
at
e mm e mm e mm
hh e e e
Sc c chch chch chc
1
3 3
o o o
JUMP_43X39
o o o
bobo bo bo
o o
2
ete e te eb eb
ot o1 t ot t
2
@ PUC1
o o +3VALW
NNo
VIN_0.775VALW 6
NN NN
VIN VCNTL
2 5
2
1
GND NC
1
@ PCC1 3 7 @ PCC2
4.7U_0603_6.3V6M @ PRC2 VREF NC 1U_0402_6.3V6K
1
2
3.24K_0402_1% 4 8
VOUT NC
9
2
VREF_0.775VALW TP
mm mm mm
co o c.o co o
G2992F1U_SO8~N
s.s.c co
s.s@1K_0402_1% s.s.c
1
@ PRC1
.1U_0402_16V7K
1
c
i ic c
i ic c
D