EE-412 VLSI Circuit Design (& Verification)

Assignment 2
Due Date: 8th May, 2024, 11:59 PM (No late submissions, Zero marks for plagiarism)
Max Marks: 50

Note: Assignment must be solved on individual basis. Plagiarism will lead to zero marks. The
design under verification (DUV) can be same for two students but the solution must be unique.

Any information sources or websites used for assistance in assignment must be clearly cited and
acknowledged in comments.

Question 1 (20 marks)

Write and Simulate SystemVerilog constraints to solve a 9x9 Sudoku Puzzle.

The input must be a randomly filled puzzle:

1. With constraints
2. Without any constraints.

The output must be a completely filled puzzle.

You can take inspiration from online resources but must find unique way of implementing the
same logic. There might be an exam question along similar lines.

Question 2 (30 marks: 15 for basic testbench with bfm scoreboard, bfm, 15 for
covergroups)

Develop a SystemVerilog test bench that uses OOP features (classes, bfm, scoreboard etc.) to
verify the functionality of a 16-bit ripple carry adder. The output is registered and changes on
every positive edge of the clock cycle.

Introduce two stuck-at errors at randomly selected carry-out signals. Modify the testbench
to include covergroups and coverpoints that can help you debug the source of the error.

Simulate the testbench and monitor the coverage data OR Questasim coverage window to locate
the source of error.