LB # 820-2828-A Schematic Diagram_S

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
K62 MLB
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2011-02-08
LAST_MODIFIED=Tue Feb 8 15:20:30 2011

( csa) Date ( csa) Date
D Page Contents Sync Page Contents Sync D

1 05/21/2009 52 01/09/2011
1 Table of Contents K60 49 SMBUS CONNECTIONS K62 MARK
2 01/09/2011 53 01/09/2011
2 System Block Diagram K62 SIJI 50 CPU/PCH/GPU POWER SENSE K62 MARK
3 01/09/2011 54 01/09/2011
3 Power Block Diagram K62 JERRY 51 HDD OOB SENSE K62 MARK
4 N/A 55 01/09/2011
4 BOM Configuration K62 AARON 52 TEMP SENSORS K62 MARK
5 07/01/2009 56 01/09/2011
5 DEBUG LEDS K62 AARON 53 HD AND OD FAN K62 JERRY
6 12/30/2010 57 01/09/2011
6 Power Conn / Alias K62 AARON 54 CPU FAN K62 JERRY
7 11/30/2009 61 11/30/2009
7 Holes K62 AARON 55 SPI ROM K62 AARON
8 01/09/2011 62 01/09/2011
8 UNUSED SIGNAL ALIAS K62 SIJI 56 AUDIO: CODEC/REGULATOR K62 DAVID
9 09/11/2010 63 01/09/2011
9 Signal Aliases K62 SIJI 57 AUDIO: FILTER/BUFFER K62 DAVID
10 01/09/2011 64 01/09/2011
10 CPU DMI/PEG/FDI/RSVD K62 ROSITA 58 AUDIO: SPEAKER AMP 1 K62 DAVID
11 01/09/2011 65 01/09/2011
11 CPU CLOCK/MISC/JTAG K62 ROSITA 59 AUDIO: SPEAKER AMP K62 DAVID
12 01/09/2011 66 01/09/2011
12 CPU DDR3 INTERFACES K62 ROSITA 60 Audio: MLB to I/O Conn. K62 DAVID
13 01/09/2011 67 01/09/2011
13 CPU POWER K62 ROSITA 61 AUDIO: Detects/Grounding K62 DAVID
14 01/09/2011 68 01/09/2011
14 CPU GROUNDS K62 ROSITA 62 AUDIO: Mikey K62 DAVID
15 01/09/2011 69 01/09/2011
15 STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU K62 SIJI 63 POWER SEQUENCING ENABLES K62 SIJI
16 N/A 70 01/09/2011
16 CPU NON-GFX DECOUPLING K62 AARON 64 POWER SEQUENCING PGOOD K62 SIJI
17 11/30/2009 71 N/A
17 GFX DECOUPLING & PCH PWR ALIAS 65 VREG: PPVCORE S0 CPU
C 18
18
PCH SATA/PCIE/CLK/LPC/SPI
K62 AARON
K62 SIJI
01/09/2011
66
72
VREG: CPU CORE - PHASES 1-3
K62 AARON
K62 AARON
N/A C
19 01/09/2011 73 N/A
19 PCH DMI/FDI/GRAPHICS K62 SIJI 67 VREG:AXG PHASE/CORE - CAPS K62 AARON
20 01/09/2011 74 12/08/2009
20 PCH PCI/FLASHCACHE/USB K62 SIJI 68 1V05 REGULATOR K62 AARON
21 01/09/2011 75 12/08/2009
21 PCH MISC K62 SIJI 69 CPU VCCSA REGULATOR K62 AARON
22 07/01/2009 76 12/08/2009
22 PCH POWER K60 SIJI 70 CPU 3P/4P BOM OPTIONS K62 AARON
23 07/01/2009 77 12/08/2009
23 PCH GROUNDS K62 AARON 71 5V S3 / 3V3 S5 VREGS K62 AARON
24 07/01/2009 78 11/30/2009
24 PCH DECOUPLING K62 AARON 72 1.5V / 1.8V VREGS K62 AARON
25 01/09/2011 79 N/A
25 CPU & PCH XDP K62 SIJI 73 3.42 G3HOT SUPPLY K62 AARON
26 01/09/2011 80 04/07/2010
26 CLOCK (CK505) K62 ROSITA 74 S3+S0 FETS K62 AARON
28 01/09/2011 81 01/09/2011
27 CHIPSET SUPPORT K62 SIJI 75 12V S0 & 12V S5 switch K62 JERRY
29 01/09/2011 84 N/A
28 DDR3 VREF MARGINING K62 ROSITA 76 MXM PCIe, DP & Power K62 AARON
30 01/09/2011 85 N/A
29 MEMORY CAPS K62 ROSITA 77 MXM I/O K62 AARON
31 01/09/2011 86 N/A
30 DDR3 SO-DIMM 0 & 2 K62 ROSITA 78 MXM PCIE CAPS K62
32 01/09/2011 87 N/A
31 DDR3 SO-DIMM 1 & 3 K62 ROSITA 79 DP ALIAS K62 AARON
33 01/09/2011 88 N/A
32 DDR3 SUPPORT AND BITSWAPS K62 ROSITA 80 GREEN CLOCK K62 AARON
34 07/16/2009 89 (MASTER)
33 PCI-E Wireless Connector K62 AARON 81 T29 POWER K62 AARON
35 11/14/2010 90 N/A
34 USB HUB 1 K62 SIJI 82 Display: Int DP Connector K62 AARON
36 11/14/2010 91 N/A
B 35
38
USB HUB 2 K62 SIJI
01/09/2011
83
92
2V9/3V3/12V POWER SWITCH K62 AARON
N/A
B
36 CAESAR IV SUPPORT K62 MARK 84 Internal DP MUXing K62 AARON
39 01/09/2011 93 (MASTER)
37 ETHERNET PHY (CAESAR IV) K62 MARK 85 DisplayPort/T29 A MUXing (MASTER)
40 01/09/2011 94 (MASTER)
38 Ethernet Connector K62 MARK 86 DisplayPort/T29 A Connector (MASTER)
41 01/09/2011 95 (MASTER)
39 FireWire LLC/PHY (FW643) K62 ROSITA 87 DisplayPort/T29 B MUXing (MASTER)
42 01/09/2011 96 (MASTER)
40 FireWire: 1394B MISC K62 ROSITA 88 DisplayPort/T29 B Connector (MASTER)
43 01/09/2011 97 (MASTER)
41 FIREWIRE CONNECTOR K62 ROSITA 89 T29 Host (1 of 2) (MASTER)
45 01/09/2011 98 (MASTER)
42 SATA Connectors K62 JERRY 90 T29 Host (2 of 2) (MASTER)
46 01/09/2011 100 06/08/2010
43 EXTERNAL USB CONNECTORS K62 JERRY 91 K60/K62 RULE DEFINITIONS K62 AARON
47 01/09/2011 101 01/09/2011
44 Internal USB Connections K62 JERRY 92 Memory Constraints K62 ROSITA
48 01/09/2011 102 01/09/2011
45 SD READER CONNECTOR K62 MARK 93 PCIE/DMI/FDI/SATA CONSTRAINTS K62 ROSITA
49 01/09/2011 103 01/09/2011
46 SMC K62 JERRY 94 IBEX PEAK CONSTRAINTS K62 SIJI
50 01/09/2011 104 01/09/2011
47 SMC Support K62 JERRY 95 USB/ENET/SD/FW/AUD CONSTRAINTS K62 MARK
51 11/30/2009 105 06/11/2010
48 LPC+SPI Debug Connector K62 AARON 96 GRAPHICS CONSTRAINTS K62 AARON
106 01/09/2011
97 SMC Constraints K62 JERRY
107 01/09/2011
98 POWER CONSTRAINTS K62 JERRY
108 06/11/2010
99 T29 CONSTRAINTS K62 AARON
109 01/09/2011
A 100 PM RESETS ENABLES PGOOD CONST

101
110
K60/K62 ICT/FCT
K62 JERRY
K62 AARON
N/A
DRAWING TITLE
A
SCH,K62,MLB
DRAWING NUMBER SIZE
Apple Inc. 051-8442 D

REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING
TITLE=K22
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 110
ABBREV=DRAWING III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
LAST MODIFIED=Tue Feb 8 15 20 30 2011 IV ALL RIGHTS REDRAWING
E VE 1 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
2 SO DIMMS
PG 10
POWER PGSENSE
53
U1000 J3100 J3100
DISPLAY PORT CONN X4 DP
EXTERNAL J8400 DDR3 1333 CHA
SO-DIMMS
J9400 PG 94 X4 DP MXM CONNECTOR PG 31
LOGIC X16 PCI E GEN2
INTEL CPU 2 SO DIMMS
INTERNAL DISP X4 DP X4 DP PG 84
DDR3 1333 CHB
J3200 J3200
J9002 PG 90
X4 DP X4 DP SO-DIMMS POWER SUPPLY
LGA1155 - SANDY BRIDGE PG 32
T29 LANES TEMP, CURRENT SENSE
T29 LANES
DP LANES TO INT MUX
T29 ROUTER J2500
XDP CONN
DISPLAY PORT CONN PG 25
TEMP SENSORS
J9600 PG 96 X4 DMI
D MIDBUS PROBE
MXM - GPU DIE
CPU HEATSINK
D
GPU HEATSINK
AMBIENT INTAKE
PG 13
CPU DIE-PECI
HARD DRIVE (OOB)
LCD TEMP
XDP
FDI INTERFACE DMI INTERFACE U2510 LEFT SKIN TEMP
GPIOs INTERFACE XDP CONN
PG 25 RIGHT SKIN TEMP
OPTICAL DRIVE
PG 19 PG 19 PG 19 PG 55
J4700
25MHZ
ALS
U8800 Misc PG 47
TO ENET 25MHZ GREEN CLK 25MHZ CLK
PG 88 PG 19 U6100 J5600 J5601 J5700
SYNTH
FAN CONN AND CONTROL
SPI PG 56 57
Boot ROM
PG 61
PG 18 SPI J5100
LPC+SPI CONN
SATA-A0
J4510
SATA CONN SATA 3 0 6GHZ Port80,serial
HDD
PG 51
PG 45 PG 18
INTEL U4900
SATA-A1
J4520 B,0 BSB ADC Fan
SATA CONN
SSD
SATA 3 0 6GHZ
SATA COUGAR POINT SMC Ser
6 SATA 2 O PORTS Prt
PG 45 LPC
C J4530
PG 49
C
SATA-A2
SATA CONN
ODD
SATA 2 0 3GHZ
U1800
PG 45
PG 18
PG 18
ANALOG VIDEO OUTPUT

RGB OUT
PWR
(PORT A)
DIGITAL VIDEO OUTPUT

CTRL
HDMI/DVI/DP
(PORT B)
0 1 2 3 4 5 6 7 8 9 10 11 12 13
PG 20
J4700
DIGITAL VIDEO OUTPUT USB CAMERA
PG 47
HDMI/DVI/DP
(PORT C)
DIGITAL VIDEO OUTPUT

HDMI/DVI/DP
J4630
(PORT D)
U3600 EXTD
(UP TO 14 DEVICES)
PG 46
PG 19
J4610
USB HUB2 EXTB
USB 2.0
PG 46
X4 PCIE GEN2 LANES 5GBIT/S
PG 36
J4700
J3900 T3900
BLUETOOTH
PG 47
U3800
UP TO 8 LANES3
PCI-E GEN2
J4620
GB E-NET U3500 EXTC PG 46
E-NET E-NET X1 PCIE GEN1 LANE 2 5GBIT/S
CONTROLLER
CONNECTOR MAGNETICS J4600
EXTA
AND PHY PG 46
USB HUB1 J4780
PG 39 PG 39 PG 38 IR
B PG 35
PG 47
J47XX
SD CONNECTOR
B
X1 PCIE GEN1 LANE 2 5GBIT/S SMB PG 47
DIMM’S, MIKEY, BLC
X1 PCIE GEN1 LANE 2 5GBIT/S
MIKEY
J4800
PG 18
PG 18
SD CARD PCI HDA

(SUPPORTED UPTO 4 REQ/GNT)
PG 20 PG 18
PG 48
U4100
U6201
Audio
FW643 Codec
PG 41
HEADPHONES
INTERNAL/EXTERNAL
MICROPHONES SPEAKER AMPS
LINE INPUT
A U6400 U6500
SYNC MASTER=K62 SIJI SYNC DATE=01/09/2011 A
PAGE TITLE
System Block Diagram

DRAWING NUMBER SIZE

J4300 J3400 Audio REVISION
R
FireWire Mini PCI-E Conns 10.1.0

J6600 J6601 J6602 J6603
Conn AirPort THE INFORMATION CONTAINED HEREIN IS THE
PG 43 PG 34 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
K75F AC/DC POWER SUPPLY (SPEC:310W)
TEMP SENSOR I2C CLK,DATA
12V_G3H EMC1403
INA219
SPEC:22.5A(270W)
12V LED POWER PP12V_S5_LED 7.5A
(PS_ON) SPEC:7.5A (90W)
PP12V_S0:PEAK 26.5A(318W)
LCD PANEL 1.6A
PP12V_S0_FWR 1.2A
PP12V_S0_HDD 1.2A
AUDIO 1.7A
PM_SLP_S3 FANS 0.75A
MXM 7.13A (95W TDP)
C PP12V_G3H: PP3V42_G3H_REG SMC PP3V3_S5_AVREF_SMC SMC VREF
SW LT3470A
C
LDO SN0903048
PAGE 79 PAGE 50 PPVCORE/AXG CORE 112A
.65-1.5V @ 112A/55A VAXG 15A
PM_SMC_G2_EN
PM_EN_USB_PWR SWreg ISL6364
PP12V_S5:PEAK 9.8A(118W) PP5V_USB_PORTx USB EXT PORT 4.7A PAGE 71-73
PP5V_S3_REG TPS2560 PAGE 46
ISL62383 5V@10.3A USB_IR
PAGE 77 USB_CAMERA PP1V05_S0 CPU VCCIO 8.5A (CPU)
1.05V @ 25A 1V05 VCCIO 5A (PCH)
P5VS0_EN PP5V_S0 AUDIO
PCH SWReg ISL9563A 1V05 T29 3A
MXM 2.5A PAGE 76
FET 7A/2.7A HDD 1.8A
SSD 0.8A
PAGE 80 ODD_PWR_EN_L
PP3V3_S5_REG
ISL62383 3.3V@6.2A ODD 1.5A
PCH PPVCCSA 8.8A
PAGE 77 BOOT ROM LDO 0.925V@8.8A
VCCSA
CPU PLL
PP1V8_S0_REG
SWReg ISL8013A 1A PAGE 76
B PAGE 78 B
P3V3S3_EN
SMSC HUB X2, BT PP12V_T29
PP3V3_S3 PP12V_T29 1.1A@12V (1ST PORT)
PM_SLP_S3_L & AP_PWR_EN 12V @ 1.2A
FET 2.9A/1.2A
PP3V3_S3_MINI AIRPORT FET 0.5A@3.3V (2ND PORT#1)
PAGE 80
FET 2.75A/1.1A/0.19A PAGE 91
PAGE 34
ENET_PWR_EN
PP3V3_S3_ENET ETHERNET
FET 0.25A/0.2A/0.06A
P3V3S0_EN
FIREWIRE PAGE 38
PP3V3_S0 LCD PANEL
PCH FW
FET 2.7A/1.76A AUDIO PP1V0_FWPHY
MXM 1A MAX BJT 1.0V @ 0.08A
PAGE 80 PAGE 42
DP_RDRV 0.7/0.02A
PP3V3_S0_SD SDHC(0.25AMP)
PP1V5_S3_REG LAZARUS ( 0.1AMP)
TPS51116, 1.5V 11A/6.7A
PAGE 48
PAGE 78 MAIN MEMORY
A SYNC MASTER=K62 JERRY SYNC DATE=01/09/2011 A
PAGE TITLE
PM_SLP_S3 Power Block Diagram
DRAWING NUMBER SIZE
CPU MEM
PP1V5_S0 AUDIO Apple Inc. 051-8442 D
FET 6.2A/3A REVISION
R
PAGE 78 10.1.0
PP0V75_S0 THE INFORMATION CONTAINED HEREIN IS THE

0.75V @ 0.6A MEM_VTT
PAGE 75
3 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM Variants COMMON

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
BOM NUMBER BOM NAME BOM OPTIONS
337S4088 1 IC COUGAR POINT SLJ4F BD82Z68 PRQ B3 U1800 CRITICAL
D 085-1226 PCBA,MLB,DEV,K62 DEVELOPMENT,DEV_GROUP

353S3055 2 IC PI3VEDP212 X2 DP MUX QFN U9390,U9590 CRITICAL D
639-1769 PCBA,MLB,K62,2.8G,4C,PRQ,P2_ODD K62,2P8GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P2,YES_DBG
338S0753 1 IC,FW643,1394B_PCIE,PHY/LINK U4100 CRITICAL
825-7122 1 MLB LABEL,48.0X4.8 X14 CRITICAL
343S0534 1 IC,BCM57765,ENET&SD,8X8 U3900 CRITICAL
639-2186 PCBA,MLB,K62,2.8G,4C,PRQ,P2_ODD,NO_DBG K62,2P8GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P2,NO_DBG
RAW: 335S0807 341T0184 1 FLASH,EFI BOOTROM,K60/K62 U6100 CRITICAL
RAW: 335S0539 341T0328 1 SFLASH ENET 2MBIT,CIV U3990 CRITICAL
338S0945 1 T29 ROUTER, IC, ASSP U9700 CRITICAL T29
RAW: 335S0550 341T0329 1 IC,T29 SERIAL EEPROM U9790 CRITICAL T29
RAW: 337S3997 341T0327 2 IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25 U9330,U9530 CRITICAL T29
RAW: 338S0878 341T0186 1 IC,SMC,K62 U4900 CRITICAL
BOM GROUPS
BOM GROUP BOM OPTIONS CPUS
BASIC1 COMMON,ALTERNATE,MXM,FCIM,CPU_1V5_SENSE,CPU_VCCSA_SENSE,1V05_PCH_SENSE PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
C BASIC2 HUB_USX2061,AP,BT,IR,T29,VAXG,PRODUCTION 337S4042 1 SNB SR00D PRQ D2 2 8 95W 4+1 6M LGA CPU CRITICAL 2P8GHZ_SNB_CPU
C
DEV_GROUP VREFMRGN_A,VREFMRGN_B,DIMM_1V5_SENSE 337S4040 1 SNB SR00Q PRQ D2 3 1 95W 4+1 6M LGA CPU CRITICAL 3P1GHZ_SNB_CPU
YES_DBG XDP,XDP_CONN,XDP_CPU_BPM,MOJOMUX:YES,LPCPLUS:YES 337S4041 1 SNB SR00B PRQ D2 3 4 95W 4+1 8M LGA CPU CRITICAL 3P4GHZ_SNB_CPU
NO_DBG MOJOMUX:NO,LPCPLUS:NO
K62 PARTS
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
CPU SOCKET & ILM SUB-BOMS 051-8442 1 SCH,MLB,K62 SCH1 K62
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 820-2828 1 PCBF,MLB,K62 MLB1 K62
511S0071 1 SOCKET,LGA1155,CPU-LF U1000 CRITICAL TYCO_SOCKET
604-1474 1 ASSY,PURCHASED,ILM,TYCO ILM CRITICAL TYCO_SOCKET
511S0073 1 SOCKET,LGA1155,CPU-LF U1000 CRITICAL MOLEX_SOCKET
604-1161 1 ASSY,PURCHASED,ILM,MOLEX ILM CRITICAL MOLEX_SOCKET
B K62 ALTERNATE PARTS B

BOM NUMBER BOM NAME BOM OPTIONS
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
085-2451 SUB ASSY,CPU SOCKET,K62,TYCO TYCO_SOCKET PART NUMBER
085-2450 SUB ASSY,CPU SOCKET,K62,MOLEX MOLEX_SOCKET 128S0298 128S0293 ALL 330UF
371S0679 371S0652 ALL PIN DIODE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 377S0107 377S0066 ALL USB DIODE
085-2451 1 TYCO CPU SOCKET AND ILM SKT_ILM CRITICAL 376S0972 376S0612 ALL ROHM TRA-BJT
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
085-2450 085-2451 SKT_ILM MOLEX ALTERNATE
BOARD STACK-UP
TOP SIGNAL
2 GROUND
A 3 SIGNAL SYNC MASTER=K62 AARON SYNC DATE=N/A A
PAGE TITLE
4 POWER BOM Configuration
5 POWER DRAWING NUMBER
051-8442
SIZE
D
Apple Inc.
6 SIGNAL R
REVISION
10.1.0
7 GROUND NOTICE OF PROPRIETARY PROPERTY:
BRANCH

BOTTOM SIGNAL THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
4 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
S5 Led ALL_SYS_PWRGD Led MXM PWR GOOD Led VIDEO ON Led

=PP3V3_S0_LED
D =PP3V3 S3 LED
6 5
6 5 =PP3V3_S0_LED
D
6 5
1
R502
1
R503
1K
R504
1
5% 1K
1K 1/16W 5%
5% MF-LF 1/16W
1/16W MF-LF
MF-LF 2 402 2 402
6 5 =PP3V3_S5_LED 2 402 GPU_PRESENT_R
CORE_VOLTAGES_ON_R LCD_SHOULD_ON_R
1
R501
1K
A
A
LED503
5%
1/16W
LED502
GREEN-3.6MCD
GREEN 3 6MCD
2 0X1 25MM SM
MF-LF K
2.0X1.25MM-SM SILKSCREEN:3 A
2 402 K
SILKSCREEN:2
ITS PLUGGED_IN
CORE_VOLTAGES_ON
GPU_PRESENT_DRAIN
LED504
GREEN-3.6MCD
A
6 K 2.0X1.25MM-SM
SILKSCREEN:4
LED501 3
D
GREEN-3.6MCD
2.0X1.25MM-SM
D Q502
K
SILKSCREEN:1 Q502 2
2N7002DW-X-G VIDEO ON L
2N7002DW-X-G 100 25 21 IN MXM_GOOD G S SOT-363 IN 82
100 64 32 IN ALL SYS PWRGD R 5 G S SOT 363

1
4
C C
PROTO DEBUG LEDS ARE SHOWN BELOW
6 5 =PP3V3_S5_LED
DEVELOPMENT 6 5 =PP3V3_S5_LED 6 5 =PP3V3_S0_LED
6 5 =PP3V3_S0_LED DEVELOPMENT DEVELOPMENT
1
R510 DEVELOPMENT
1
1
R500 1
R549
3.3K R540
5% 3.3K 3.3K
1/16W 3.3K 5% 5%
MF-LF 5% 1/16W 1/16W
2 402 1/16W
MF-LF
MF-LF MF-LF
PM_LED_S3 2 402 2 402
2 402 PM LED S4 PM LED AXG
PM_LED_PCHCORE
A DEVELOPMENT DEVELOPMENT
A A DEVELOPMENT
SILK_PART=SLP_S3 LED510 A DEVELOPMENT
GREEN 3 6MCD SILK_PART=SLP_S4 LED500 SILK_PART=VAXG_PGOOD LED542
2 0X1 25MM SM
SILK_PART=PCHCORE_PGOOD LED540 GREEN 3 6MCD GREEN 3 6MCD
B K
SILKSCREEN:5
PM_LED1_S3
K
GREEN 3 6MCD
2 0X1 25MM SM
SILKSCREEN:6
K 2 0X1 25MM SM
SILKSCREEN:7
K 2 0X1 25MM SM
SILKSCREEN:11 B
PM_LED1_S4 PM_LED1_AXG
PM_LED1_PCHCORE
6
DEVELOPMENT 3
D 6 3 DEVELOPMENT
DEVELOPMENT DEVELOPMENT D
Q500 D D
2N7002DW-X-G Q520
100 63 47 46 36 32 26 19 PM_SLP_S3_L 2 G S SOT 363
Q540 Q500 2N7002DW-X-G
IN 2N7002DW-X-G 2N7002DW-X-G PM_PGOOD_PVAXG 5 G S
100 65 IN SOT 363
100 64 PGOOD_PCH_S0 2 G S SOT 363 100 63 47 46 32 19 PM_SLP_S4_L 5 G S SOT 363
IN IN
1
4
1 4
6 5 =PP3V3 S3_LED
DEVELOPMENT
1
R505
1K
6 5 =PP3V3_S5_LED 6 5 =PP3V3_S5_LED 5%
DEVELOPMENT DEVELOPMENT 1/16W
1 6 5 =PP3V3_S0_LED 1 MF-LF
R560 DEVELOPMENT
1
R530 2 402
3.3K R550 3.3K ITS_ALIVE
5% 5%
1/16W 3.3K 1/16W A
MF-LF 5% MF-LF DEVELOPMENT
2 402 1/16W
MF-LF 2 402 LED505
PM_LED_S5 2 402
PM_LED_DDRREG GREEN 3 6MCD
DEVELOPMENT PM_LED_PVCORE K 2 0X1 25MM SM
A A DEVELOPMENT
A SILKSCREEN:8
SILK_PART=SLP_S5 LED560 DEVELOPMENT LED530 SILK_PART=DDR_PGOOD
GREEN 3 6MCD
SILK_PART=VCORE_PGOOD LED550 GREEN 3 6MCD
A K 2 0X1 25MM SM
SILKSCREEN:12
K
GREEN 3 6MCD
2 0X1 25MM SM
K 2 0X1 25MM SM
SILKSCREEN:10 SYNC MASTER=K62 AARON SYNC DATE=07/01/2009 A
PM_LED1_S5 SILKSCREEN:9 PM_LED1_DDRREG PAGE TITLE
3
PM LED1 PVCORE
6
DEBUG LEDS
DEVELOPMENT DRAWING NUMBER SIZE
3
D
Q530 DEVELOPMENT
D DEVELOPMENT
Q520 Apple Inc. 051-8442 D
D
2N7002DW-X-G 2N7002DW-X-G REVISION
PM_SLP_S5_L 5 G Q540 PM_PGOOD_DDR1V5_S3_REG 2 G R
100 63 47 46 19 IN S SOT 363
5
2N7002DW-X-G
100 72 63 IN S SOT 363
10.1.0
100 65 64 25 IN PM_PGOOD_PVCORE_CPU G S SOT 363
4 1
1 C501 4 THE INFORMATION CONTAINED HEREIN IS THE
0.1UF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
20%
10V
2 CERM
5 OF 110
402 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
98 PP0V75_S0 PPVTT_S0_DDR_LDO 72
MAKE BASE=TRUE
VOLTAGE=0 75V
MIN LINE WIDTH=0 4 mm
=PP0V75_S0_MEM_VTT_S0FET 32 "S5" RAILS
POWER SUPPLY TO MLB PP12V_G3H_ACDC 6
MIN NECK WIDTH=0 2 mm
NET SPACING TYPE=POWER
MAX NECK LENGTH=3 MM
ALWAYS ON WHEN UNIT HAS AC POWER AND IN S5
"S0" RAILS PP3V3_S5 PP3V3_S5_REG

518-0352 1 C614
1UF
10%
98 PPVTT_S0_DDR
MAKE BASE=TRUE
VOLTAGE=0 75V
PPVTT_S0_DDR_FET
=PP0V75_S0_MEM_VTT_B
32
31 ONLY ON IN RUN
98
MAKE BASE=TRUE
VOLTAGE=3 3V
MIN LINE WIDTH=0 4MM
MIN NECK WIDTH=0 2MM
=PP3V3_S5_PCH
=PP3V3_S5_PCH_GPIO
71
18 19 21 24
20
100 84 IN BL_PWM CRITICAL 2 25V
X5R MIN NECK WIDTH=0 2 mm =PP0V75_S0_MEM_VTT_A 30 NET SPACING TYPE=POWER
402 NET SPACING TYPE=POWER MAX NECK LENGTH=3 MM =PP3V3 S5 ROM 48 55
1 C613
J600 =PP3V3_S5_PCH_VCCSUS3_3_USB 22 24
76833-0100 98 PPVCORE_S0_CPU PPVCORE_S0_CPU_REG 66 67 98 PP1V8_S0 PP1V8_S0_REG 72 =PP3V3_S5_PWRCTL 11 63 64
0.001UF M-RT-TH MAKE BASE=TRUE MAKE BASE=TRUE
10% VOLTAGE=1 1V =PPVCORE_S0_CPU 13 16 50 65 VOLTAGE=1 8V =PP3V3R1V8_S0_PCH_VCCDFTERM 22 24 =PP3V3_S5_S3FET 74
50V 1 8
2 X7R MIN LINE WIDTH=0 6MM MIN LINE WIDTH=0 5MM
D 402 2
3
9
10
PP12V S0 PS 6
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V8_S0_CPU_PLL
24 80
13 16
=PP3V3_S5_S0FET
=PP3V3_S5_PCH_STRAPS
74
15
D
98 PPVAXG_S0 PPVAXG_S0_REG 67 =PP1V8_S0_PCH 19 =PP3V3_S5_XDP 25
4 11 MAKE BASE=TRUE
R601 VOLTAGE=1 05V =PPVAXG S0 CPU 13 17 50 65 =PP1V8 S0 PWRCTL 64 =PP3V3 S5 LPCPLUS 48
5 12 BL_EN 82 100 MIN LINE WIDTH=0 6MM
0 IN =PP3V3 S5 PCH VCCDSW
6 MIN NECK WIDTH=0 3MM 22 24
49 =SMB_ACDC_SDA 1 2 SMB_ACDC_SDA_RC 13 NET SPACING TYPE=POWER
BI 1 1
1/16W I2C_GND 7 14 SMB_ACDC_SCL_RC
C611 C612 MAX NECK LENGTH=3 MM 101 98 PP5V S0 PP5V S0 FET 74 =PP3V3 S5 USB HUB 34
10UF 0.001UF MAKE BASE=TRUE
402
10% 10% 98 PP1V05_S0 PP1V05_S0_REG 68 VOLTAGE=5V =PP5V_S0_AUDIO 56 =PP3V3_S5_CPU_VCCSA 69
5% MAKE BASE=TRUE MIN LINE WIDTH=0 5 mm
1 16V 50V
R609 2 X5R-CERM
1210
2 X7R
402
VOLTAGE=1 05V
=PP1V05_S0_PWR 50 MIN NECK WIDTH=0 2 MM
=PP5V_S0_SATA 42 =PP3V3_S5_PCH_VCCSPI 22 24
0 MIN NECK WIDTH=0 25MM =PPVCCIO_S0_XDP 25 MAX NECK LENGTH=3 MM =PP5V_S0_MXM 76 =PP3V3_S5_VRD 71
5% NET SPACING TYPE=POWER
1 C604 1/16W
MF-LF
MAX NECK LENGTH=3 MM =PPVCCIO_S0_CPU 10 11 13 16 65 =PP5V_S0_VRD 65 67 =PP3V3_S5_LED 5
47PF =PPVCCIO_S0_SMC =PP5V_S0_ISENSE =PP3V3_S5_MEMRESET
5% 2 402 46 47 50 32
2 50V
CERM
=PP1V05 S0 PCH PWR 50 =PP5V S0 PCH 24 =PP3V3 S5 RSTBUF 27
402 =PPVCCSA S0 INPUT PWR =PP5V S0 P1V05 VREG =PP3V3 S5 SMCUSBMUX
50 69 68 43
PS ON =PP1V05 S0 CK505 26 =PP5V S0 LPCPLUS 48 =PP3V3 S5 P3V3R2V9 A 83
=PP5V_S0_P1V8_REG 72 =PP3V3_S5_P3V3R2V9_B 83
R611 98 PP1V05_S0_PCH PP1V05_S0_PCH_SNS 50
MAKE BASE=TRUE =PP3V3R1V5_S5_PCH_VCCSUSHDA 24
0 VOLTAGE=1 05V =PP1V05 S0 PCH VCC DMI 22 24
1 2 =SMB_ACDC_SCL IN 49 MIN LINE WIDTH=0 6 mm
3 MIN NECK WIDTH=0 2 mm =PP1V05 S0 PCH VCCADPLL 17
1/16W NET SPACING TYPE=POWER
D 1 C610 402 MAX NECK LENGTH=3 MM =PP1V05_S0_PCH_VCCIO_DMI 22 24
Q610 0.001UF 5%
=PP1V05_S0_PCH_VCCIO_SATA
2N7002 10% 1 C605 18 22 24
98 PP5V_S5 PP5V_S5_LDO 71
PM_EN_P12V_S0_FET 1 G S SOT23-HF1 50V =PP1V05_S0_PCH_VCCIO_PCIE
100 63 IN 2 X7R 47PF 18 19 22 24 MAKE BASE=TRUE
402 5% VOLTAGE=5V =PP5V S5 PCH 24
50V =PP1V05_S0_PCH_VCC_CORE 22 24 MIN LINE WIDTH=0 4 MM
PLACE C610 CLOSE TO CONNECTOR 2 2 CERM MIN NECK WIDTH=0 2 mm
PLACE C613 CLOSE TO CONNECTOR 402
=PP1V05_S0_PCH_VCCIO_USB 22 24 98 PP12V_S0 PP12V_S0_PS 6 NET SPACING TYPE=POWER
PLACE C614 CLOSE TO CONNECTOR =PP1V05_S0_PCH
MAKE BASE=TRUE
=PP12V_S0_AUDIO_SPKRAMP
PLACE C612 CLOSE TO CONNECTOR 18 24 80 VOLTAGE=12V 58 59
MIN LINE WIDTH=1mm
=PP1V05 S0 PCH VCCDIFFCLK 22 24 MIN NECK WIDTH=0 5mm =PP12V S0 VRD 65
NET SPACING TYPE=POWER 98 PP12V_S5 PP12V_S5_FET 75 98
=PP1V05 S0 PCH VCCSSC 22 24 MAX NECK LENGTH=3 MM =PP12V S0 MXM PWR 50 MAKE BASE=TRUE
VOLTAGE=12V =PP12V_S5_DDR_VREG 72
=PP1V05 S0 PCH V PROC IO 22 24 =PP12V S0 LCD 82 MIN LINE WIDTH=0 6 mm
MIN NECK WIDTH=0 2 mm =PP12V_S5_P5VS3_VREG 71
C =PP1V05_S0_PCH_VCCASW
=PP1V05_S0_P1V05T29FET
22 24
81
=PP12V_S0_P1V05_VREG
=PP12V_S0_PWRCTL
68
63 64 81
MAX NECK LENGTH=3 MM =PP12V_S5_PWRCTL
=PP12V S5 T29 A
33 64 74
83
C
=PP12V_S0_SENSE 51
98 PP1V05 S0 INPUT VCCSA PPVCCSA S0 INPUT SNS 50 =PP12V S5 T29 B 83
MAKE BASE=TRUE =PP12V_S0_FW 41
VOLTAGE=1 05V =PPVCCIO_S0_CPU_VCCSA
69
=PP12V_S0_CPU_VCCSA 69 "G3H" RAILS
NET SPACING TYPE=POWER =PP12V_S0_SATA 42 ALWAYS ON WHEN UNIT HAS AC POWER AND IN G3HOT PER SMC
=PP12V S0 FAN 53 54 G3H: ALIASES
MLB TO BLC NOSTUFF
98 PPVCCSA_S0_CPU
MAKE BASE=TRUE
VOLTAGE=0 925V
PPVCCSA_S0_FET
=PPVCCSA_S0_CPU
69
13 50 98 PP3V42_G3H PP3V42_G3H_REG 73
MIN LINE WIDTH=0 6MM MAKE BASE=TRUE
1 C626 MIN NECK WIDTH=0 3MM =PPVCCSA_S0_PWRCTL 64 VOLTAGE=3 42V =PP3V3_G3H_RTC_D 27
NET SPACING TYPE=POWER MIN LINE WIDTH=0 6MM
47PF MAX NECK LENGTH=3 MM MIN NECK WIDTH=0 2MM =PP3V3_G3H_SMC 46 47
5% NET SPACING TYPE=POWER
2 50V 98 PP1V5_S0 PP1V5_S0_FET 74 MAX NECK LENGTH=3 MM =PP3V3_G3H_SMCUSBMUX 43
CERM MAKE BASE=TRUE
402 VOLTAGE=1 5V =PP1V5_S0_AUD_DIG 56 =PP3V3_G3H_LPCPLUS 48
MIN NECK WIDTH=0 2MM =PP1V5_S0_CK505 26 98 PP12V_S0_MXM PP12V_S0_MXM_SNS 50
NET SPACING TYPE=POWER MAKE BASE=TRUE
MAX NECK LENGTH=3 MM =PP1V5_S0_MINI 33 VOLTAGE=12V
MIN LINE WIDTH=0 6MM =PP12V_S0_MXM 76
=PP1V5_S0_PWR 50 MIN NECK WIDTH=0 2MM
R631 =PP1V5_S0_DP
0 84 MAX NECK LENGTH=3 MM
97 82 49 BI SMB_BLC_TCON_SDA R630 1 2 SMB_BLC_TCON_SDA_R
0 98 PP1V5_S0_CPU_MEM PP1V5_S0_CPU_MEM_SNS 50
97 82 49 IN SMB_BLC_TCON_SCL 1 2 1/16W SMB_BLC_TCON_SCL_R MAKE BASE=TRUE 98 PP12V_G3H PP12V_G3H_ACDC 6
402 =PP1V5_S0_CPU_MEM
1/16W 5% VOLTAGE=1 5V 11 13 16 28 29 MAKE BASE=TRUE
402 MIN LINE WIDTH=0 4MM VOLTAGE=12V =PP12V_G3H_S5_FET 75
5% NOSTUFF MIN NECK WIDTH=0 2MM MIN LINE WIDTH=0 6 mm
=PP12V_G3H_3V42
NET SPACING TYPE=POWER MIN NECK WIDTH=0 2 MM 73
1 C616 MAX NECK LENGTH=3 MM
"S3" RAILS NET SPACING TYPE=POWER
47PF PP3V3_S0 PP3V3_S0_FET
5% 98 74 ON IN RUN AND SLEEP
50V MAKE BASE=TRUE
2 CERM VOLTAGE=3 3V =PP3V3_S0_PCH 18 21 24
402 MIN LINE WIDTH=0 4MM
=PP3V3_S0_FAN 53 54 T29 RAILS
=PP3V3_S0_SMBUS MAX NECK LENGTH=3 MM =PP3V3_S0_PCH_VCCADAC 17
49 6 PP1V5_S3 PP1V5_S3_REG
98 72
FET DIODE IS S TO D (FACES BLC WHICH CRITICAL =PPSPD_S0_MEM_A 30 47 MAKE BASE=TRUE
B NOSTUFF
3V3 RISES BEFORE MLB 3V3).
2 J602 =PPSPD_S0_MEM_B 31
VOLTAGE=1 5V
=PP1V5_S3_MEM_PWR
=PP1V5_S3_S0FET
50
B
Q600 53780-8608 =PP3V3 S0 AUDIO 56 58 59 60 61 62 NET SPACING TYPE=POWER
74
1 C607 G 2N7002DW-X-G F-RT-SM

10
=PP3V3R1V5 S0 PCH VCCSUSHDA 24
47PF SOT-363
=PP3V3_S0_SMBUS
5% 1 S D 6 6 49
50V
2 CERM =PP3V3_S0_SMC_LS 47 51 98 PP3V3_S0_T29 PP3V3_T29_FET 81
402 1 98 PP1V5 S3 MEM PP1V5 S3 MEM SNS 50 MAKE BASE=TRUE
NOSTUFF 2
=PP3V3_S0_SMBUS_SMC_0 49 MAKE BASE=TRUE VOLTAGE=3 3V =PP3V3_T29_RTR 80 81 89 90
VOLTAGE=1 5V =PP1V5 S3 MEMRESET 32 MIN LINE WIDTH=0 6MM
NOSTUFF R617 3
=PP3V3_S0_SMBUS_SMC_B 49 MIN LINE WIDTH=0 6 mm MIN NECK WIDTH=0 2MM
MIN NECK WIDTH=0 2 mm =PP1V5 S3 MEM A 28 29 30 NET SPACING TYPE=POWER
R618 0 =PP3V3_S0_SMBUS_SMC_MGMT 49 NET SPACING TYPE=POWER MAX NECK LENGTH=3 MM
49 =SMB_BLC_PCH_SDA 1 2 SMB_BLC_PCH_SDA_R 4 MAX NECK LENGTH=3 MM =PP1V5_S3_MEM_B 28 29 31
BI =PP3V3_S0_MXM
0 5 21 64 76 77
49 IN =SMB_BLC_PCH_SCL 1 2 1/16W SMB_BLC_PCH_SCL_R
402
6
=PP3V3 S0 ODD 42 101 98 PP3V3 S3 PP3V3 S3 FET 74
1/16W 5% MAKE BASE=TRUE 98 PP1V05_S0_T29 PP1V05_T29_FET 81
402
BLC SDA/SCL 7
=PP3V3 S0 SATALED 18 42 VOLTAGE=3 3V =PP3V3 S3 BT 44 MAKE BASE=TRUE
5% MIN LINE WIDTH=0 4MM VOLTAGE=1 05V =PP1V05_T29_RTR 90
ISOLATION CIRCUIT 8
=PP3V3_S0_SENSE 50 52 MIN NECK WIDTH=0 2MM =PP3V3_S3_SMBUS_SMC_A 49 MIN LINE WIDTH=0 6MM
NET SPACING TYPE=POWER MIN NECK WIDTH=0 2MM =PP1V05_T29 81
NOSTUFF =PP3V3_S0_PWRCTL 63 64 74 81 MAX NECK LENGTH=3 MM =PP3V3_S3_MINI 33 NET SPACING TYPE=POWER
1 C606 5
Q600 9
=PP3V3_S0_PCH_VCC3_3_GPIO 22 24 =PP3V3_S3_PWRCTL 64 74 83
47PF G 2N7002DW-X-G =PP3V3_S0_FWPHY 39 40 41 =PP3V3_S3_MEMRESET 32
5%
50V SOT-363
2 CERM 518S0543 =PP3V3_S0_DP 82 =PP3V3_S3_USB_HUB 34 35
402 4 S D 3
=PP3V3_S0_PCH_VCC3_3_PCI 22 24 =PP3V3_S3_ENET_PHY 36
ISOLATED_GND
R619
0
1
R620
=PP3V3 S0 CK505 26 =PP3V3 S3 SDCARD 44 45 GND RAILS
BLC_GPIO 1 2 BLC_GPIO_R =PP3V3 S0 PCH GPIO 20 45 =PP3V3 S3 VREFMRGN 28
94 21 15 IN 0 =PP3V3_S0_PCH_STRAPS =PP3V3_S3_VRD
1/16W 5% 15 72
402 1/16W
5% MF-LF =PP3V3_S0_PCH_VCC3_3_SATA 22 24 =PP3V3_S3_LED 5 GND
2 402 =PP3V3_S0_RSTBUF 11 27 =PP3V3_SW_DPAPWR 79
VOLTAGE=0V
=PP3V3_S0_PCH_PM 27 =PP3V3_SW_DPBPWR 79 NET SPACING TYPE=GND
L602 =PP3V3_S0_SMBUS_SMC_BSA =PP3V3_S3_SYSCLK
MAKE BASE=TRUE
FERR-1000-OHM 49 80 MAX NECK LENGTH=4 1 MM
=PP3V3_S0_SDCARD 45 =PP3V3_S3_P3V3R2V9_REG_A 83
100 82 VSYNC_DP_CONN 1 2 VSYNC_DP_CONN_R
IN =PP3V3 S0 P1V05 VREG =PP3V3 S3 P3V3R2V9 REG B
A 0402
=PP3V3 S0 PCH VCC3V3
68
22 24 =PP3V3 S3 PCH
83
21 SYNC MASTER=K62 AARON SYNC DATE=12/30/2010 A

=PP3V3 S0 VRD 65 68
PAGE TITLE
=PP3V3_S0_LED 5 101 98 PP5V_S3
MAKE BASE=TRUE
PP5V_S3_REG 71 Power Conn / Alias
=PP3V3_S0_P3V3T29FET 81 VOLTAGE=5V =PP5V_S3_USB 43 DRAWING NUMBER SIZE
=PP3V3_S0_DPSDRVA 85
MIN NECK WIDTH=0 2MM =PP5V S3 S0FET 74
=PP3V3_S0_DPSDRVB NET SPACING TYPE=POWER
87 MAX NECK LENGTH=3 MM =PP5V S3 CAMERA 44 REVISION
R
=PP3V3_S0_INTDPMUX 84 =PP5V S3 IR 44 10.1.0
=PP3V3_S0_T29PWRCTL 81 =PP5V_S3_MEMRESET 32 NOTICE OF PROPRIETARY PROPERTY: BRANCH
=PP3V3 S0 T29I2C 49 =PP5V_S3_DDR_VREG 72 THE INFORMATION CONTAINED HEREIN IS THE
=PP3V3_S0_ENET_PHY 36 37 =PP5V_S3_VREFMRGN 28 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
=PP5V_S3_P3V3R2V9_REG_A 83
6 OF 110
=PP5V_S3_P3V3R2V9_REG_B 83 SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU Heatsink DIMM CONNECTOR NUTS

4mm Plated Holes (998-0850) Nuts (805-9582)
OMIT OMIT OMIT OMIT
ZH0700 ZH0701 ZH0702 ZH0703 CRITICAL CRITICAL CRITICAL CRITICAL
4P75R4 4P75R4 4P75R4 4P75R4 NUT0750 NUT0751 NUT0752 NUT0753
1 1 1 1 NUT-4.25OD1.4H-1.40-3.25-TH NUT-4.25OD1.4H-1.40-3.25-TH NUT-4.25OD1.4H-1.40-3.25-TH NUT-4.25OD1.4H-1.40-3.25-TH
D 1 1 1 1 D
PCH HEATSINK MTG HOLES (NON-PLATED HOLE ON PCB ONLY)
Rear Cover
STANDOFFS (WAS 860-1255 BUT NOW REPLACED WITH 860-1430) OMIT_TABLE
OMIT_TABLE CRITICAL OMIT_TABLE OMIT_TABLE OMIT_TABLE CRITICAL
OMIT TABLE
CRITICAL SDF0714 CRITICAL CRITICAL SDF0718 CRITICAL
SDF0713 STDOFF-6.8OD15.0H-1.56-TH SDF0715 STDOFF-6.8OD15.0H-1.56-TH
SDF0717 SDF0719
C STDOFF-6.8OD15.0H-1.56-TH 1 STDOFF-6.8OD15.0H-1.56-TH STDOFF-6.8OD15.0H-1.56-TH 1 STDOFF-6.8OD15.0H-1.56-TH C
1 1 1 1
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
860-1430 6 STANDOFF,MLB,K60/K62 SDF0713 SDF0714 SDF0715 SDF0717 SDF0718 SDF0719 COMMON
Backer Plate
B B
Nuts (835-0269)
CRITICAL CRITICAL CRITICAL CRITICAL
NUT0700 ZH0720 ZH0721 ZH0722
NUT-6.5OD1.4H-1.56-3.8-TH 5R3 5R3 5R3
1 1 1 1
For EMC
EMC Spring (870-1577); Near DIMMs EMC POGO Pins (870-1698); Near DIMMs
NOSTUFF
CRITICAL SC0705 SC0706
2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98
A SC0702
SM SM SYNC MASTER=K62 AARON SYNC DATE=11/30/2009 A
1 EMI-SPRING 1 1 PAGE TITLE
CLIP SM K2
Holes
DRAWING NUMBER SIZE
CRITICAL CRITICAL
NOSTUFF NOSTUFF Apple Inc. 051-8442 D
REVISION
R
10.1.0
7 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
UNUSED CPU SIGNALS NC ON UNUSED PCIE ALIASES NC ON UNUSED DISPLAY ALIASES NC ON UNUSED FDI ALIASES
10 TP_CPU_RSVD<16..1> NC_CPU RSVD<16..1>
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_CRT_IG_DDC_CLK NC CRT_IG_DDC_CLK 10 TP_CPU_FDI_TX_N<7..0> NC_CPU_FDI_TXN<7..0>
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
10 TP_CPU_RSVD<46..19> NC_CPU RSVD<46..19>
MAKE_BASE=TRUE NO_TEST=TRUE 10 TP_CPU_FDI_TX_P<7..0> NC_CPU_FDI_TXP<7..0>
19 TP CRT IG DDC DATA NC CRT IG DDC DATA MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_PCH_FDI_RX_N<7..0> NC_PCH_FDI_RXN<7..0>
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_CRT_IG_RED NC CRT_IG_RED 19 TP_PCH_FDI_RX_P<7..0> NC_PCH FDI_RXP<7..0>
19 TP_CRT_IG_GREEN NC CRT_IG_GREEN
18 TP PCIE CLK100M PE5P NC PCIE CLK100M PE5P
D 18 TP_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5N
19 TP_CRT_IG_BLUE NC_CRT_IG_BLUE
MAKE_BASE=TRUE NO_TEST=TRUE D
19 TP CRT IG HSYNC NC CRT IG HSYNC
21 TP_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE6P
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_CRT_IG_VSYNC NC CRT_IG_VSYNC
21 TP PCIE CLK100M PE6N NC PCIE CLK100M PE6N MAKE_BASE=TRUE NO_TEST=TRUE
21 TP_PCIE_CLK100M_PE7P NC_PCIE_CLK100M_PE7P 19 TP_DP_IG_B_MLN<3..0> NC_DP_IG_B_MLN<3..0>

21 TP PCIE CLK100M PE7N NC PCIE CLK100M PE7N 19 TP_DP_IG_B_MLP<3..0> NC_DP_IG_B_MLP<3..0>
19 TP DP IG B AUX N NC DP IG B AUXN
10 TP PE RX N<3..0> NC PE RXN<3..0> MAKE_BASE=TRUE NO_TEST=TRUE
10 TP_PE_RX_P<3..0>
MAKE_BASE=TRUE
NC_PE_RXP<3..0>
NO_TEST=TRUE 19 TP_DP_IG_B_AUX_P NC_DP_IG_B_AUXP
NC ON UNUSED SATA ALIASES
19 TP DP IG B HPD NC DP IG B HPD 18 TP SATA D D2RN NC SATA D D2RN
NC ON UNUSED PCI ALIASES 10 TP_PE_TX_N<3..0> NC_PE_TXN<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_DP_IG_B_DDC_CLK
NC_DP_IG_B_CTRL_CLK 18 TP_SATA_D_D2RP
MAKE_BASE=TRUE
NC SATA_D_D2RP
NO_TEST=TRUE
10 TP_PE_TX_P<3..0> NC_PE_TXP<3..0> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

20 TP PCI AD<31..0> NC PCI AD<31..0> MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_DP_IG_B_DDC_DATA NC_DP_IG_B_CTRL_DATA
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 18 TP SATA D R2D CN NC SATA D R2D CN
20 TP_PCI_C_BE_L<3..0> NC_PCI_C_BE_L<3..0> MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE TP_SATA_D_R2D_CP NC_SATA_D_R2D_CP
18 TP_PCIE_D2R_PERN4 NC_PCIE_D2R_PERN4 18
20 TP PCI PAR NC PCI PAR 19 TP DP IG C MLN<3..0> NC DP IG C MLN<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCIE_D2R_PERP4 NC_PCIE_D2R_PERP4 MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_SATA_E_D2RN NC SATA_E_D2RN
19 TP_DP_IG_C_MLP<3..0> NC_DP_IG_C_MLP<3..0>
20 TP_PCI_RESET_L NC_PCI RESET_L MAKE_BASE=TRUE NO_TEST=TRUE TP_SATA_E_D2RP NC_SATA_E_D2RP
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCIE_R2D_PETN4 NC_PCIE_R2D_PETN4 18
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_DP_IG_C_AUX_N NC_DP_IG_C_AUXN
18 TP_PCIE_R2D_PETP4 NC_PCIE_R2D_PETP4 TP_SATA_E_R2D_CN NC_SATA_E_R2D_CN
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP DP IG C AUX P NC DP IG C AUXP 18
18 TP_SATA_E_R2D_CP NC SATA_E_R2D_CP
TP_DP_IG_C_HPD NC_DP_IG_C_HPD MAKE_BASE=TRUE NO_TEST=TRUE
C 19
19 TP DP IG C CTRL CLK
NC DP IG C CTRL CLK 18 TP_SATA_F_D2RN NC SATA_F_D2RN
C
19 TP_DP_IG_C_CTRL_DATA NC_DP_IG_C_CTRL DATA 18 TP_SATA_F_D2RP NC_SATA_F_D2RP
18 TP_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE4P 18 TP_SATA_F_R2D_CN NC SATA_F_R2D_CN
18 TP PCIE CLK100M PE4N NC PCIE CLK100M PE4N 19 TP DP IG D MLN<3..0> NC DP IG D MLN<3..0> 18 TP_SATA_F_R2D_CP NC_SATA_F_R2D_CP
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_DP_IG_D_MLP<3..0> NC_DP_IG_D_MLP<3..0>
18 TP_LPC_DREQ0_L NC_LPC DREQ0_L MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_DP_IG_D_AUXN NC_DP_IG_D_AUXN
19 TP_DP_IG_D_AUXP NC_DP_IG_D_AUXP
NC ON UNUSED MEM ALIASES 19 TP_DP_IG_D_HPD NC_DP_IG_D_HPD
TP_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_CLK
12 TP_MEM_A_DQ_CB<7..0> NC_MEM_A DQ_CB<7..0>
NC ON UNUSED USB ALIASES 19
19 TP_DP_IG_D_CTRL_DATA
NC_DP_IG_D_CTRL DATA
20 TP_USB_1N NC_USB_1N
12 TP_MEM_A_DQS_N<8> NC_MEM_A_DQSN<8> 20 TP_USB_1P NC_USB_1P
12 TP_MEM_A_DQS_P<8> NC_MEM_A_DQSP<8> 20 TP_USB_2N NC USB 2N
20 TP_USB_2P NC_USB_2P
12 TP_MEM_B_DQ_CB<7..0> NC_MEM_B_DQ_CB<7..0> 20 TP_USB_3N NC_USB_3N

20 TP_USB_3P NC_USB 3P
TP USB 4N NC USB 4N
B 12 TP_MEM_B_DQS_N<8> NC_MEM_B_DQSN<8>
20
TP_USB_4P
MAKE_BASE=TRUE
NC_USB 4P
NO_TEST=TRUE
19 TP SDVO TVCLKINN NC SDVO TVCLKINN
B
12 TP MEM B DQS P<8> NC MEM B DQSP<8> 20
19 TP_SDVO_TVCLKINP NC_SDVO_TVCLKINP
20 TP USB 5N NC USB 5N MAKE_BASE=TRUE NO_TEST=TRUE
NC ON UNUSED MISC ALIASES 20 TP_USB_5P
MAKE_BASE=TRUE
NC_USB_5P
NO_TEST=TRUE
19 TP_SDVO_STALLN NC_SDVO_STALLN
18 TP_HDA_SDIN1 NC_HDA_SDIN1
20 TP USB 6N NC USB 6N 19 TP_SDVO_STALLP NC_SDVO_STALLP
18 TP HDA SDIN2 NC HDA SDIN2
MAKE_BASE=TRUE NO_TEST=TRUE TP_USB_6P NC_USB_6P
20
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP SDVO INTN NC SDVO INTN
18 TP_HDA_SDIN3 NC_HDA_SDIN3
20 TP_USB_7N NC_USB 7N 19 TP_SDVO_INTP NC SDVO_INTP
20 TP_USB_7P NC_USB 7P
21 TP_PCH_PWM0 NC_PCH_PWM0
21 TP_PCH_PWM1 NC_PCH_PWM1
18 TP PCH L BKLTCTL NC PCH L BKLTCTL
21 TP PCH PWM2 NC PCH PWM2 MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_10N NC_USB_10N 18 TP_PCH_L_BKLTEN NC PCH_L BKLTEN
21 TP_PCH_PWM3 NC_PCH_PWM3 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 20 TP USB 10P NC USB 10P
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCH_L_VDD_EN NC_PCH_L_VDD_EN
21 TP_PCH_SST NC_PCH_SST MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_11N NC_USB 11N
20 TP_USB_11P NC_USB_11P 18 TP_PCH_CLKOUT_DPN NC_PCH_CLKOUT_DPN
A 20 TP_USB_12N NC_USB_12N 18 TP_PCH_CLKOUT_DPP NC_PCH_CLKOUT_DPP

MAKE_BASE=TRUE NO_TEST=TRUE SYNC MASTER=K62 SIJI SYNC DATE=01/09/2011 A
MAKE_BASE=TRUE NO_TEST=TRUE PAGE TITLE
18 TP_PCH_CL_CLK1 NC_PCH_CL_CLK1
20 TP USB 12P NC USB 12P
MAKE_BASE=TRUE NO_TEST=TRUE UNUSED SIGNAL ALIAS
DRAWING NUMBER SIZE
18 TP_PCH_CL_DATA1 NC_PCH_CL_DATA1
MAKE_BASE=TRUE NO_TEST=TRUE 20 TP_USB_13N NC_USB_13N Apple Inc. 051-8442 D
MAKE_BASE=TRUE NO_TEST=TRUE REVISION
18 TP_PCH_CL_RST1 NC_PCH_CL RST1 20 TP_USB_13P NC_USB_13P R
10.1.0
8 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
PEG Slot Support

THIS SIGNAL NAME IS CONNECTED TO MXM
18 IN PEG_CLK100M_P 93 GPU_CLK100M_PCIE_P CLK_100M_MXM_P OUT 76
MAKE_BASE=TRUE
18 IN PEG_CLK100M_N 93 GPU CLK100M_PCIE_N CLK_100M_MXM_N OUT 76
MAKE_BASE=TRUE
10 IN =PEG R2D C P<0..15> PEG R2D C P<0..15> OUT 78 93
MAKE_BASE=TRUE
10 IN =PEG_R2D_C_N<0..15> PEG R2D C_N<0..15> OUT 78 93
MAKE_BASE=TRUE
=PEG_D2R_P<0..15> PEG D2R P<0..15>
C 10
10
OUT
=PEG D2R N<0..15>

MAKE_BASE=TRUE
PEG D2R N<0..15>
IN 78 93
78 93
C
OUT IN
MAKE_BASE=TRUE
21 IN PEG_CLKREQ_L MXM CLKREQ_L OUT 76 100

MAKE_BASE=TRUE
76 MXM_RESET_L PEG_RESET_L 27 100

MAKE_BASE=TRUE
B B
R929
22
100 94 19 IN PM_CLK32K_SUSCLK_R 1 2 PM_CLK32K_SUSCLK OUT 46 94 100
PLACEMENT NOTE=PLACE CLOSE TO U1800 5%

1/16W
MF LF
402
A SYNC MASTER=K62 SIJI SYNC DATE=09/11/2010 A

PAGE TITLE
Signal Aliases
DRAWING NUMBER SIZE

REVISION
R
10.1.0
9 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SHORT B4 & C4 TOGETHER ROUTE AS A SINGLE 4 MIL TRACE TO R1010 1
ROUTE B5 TO R1010 1 AS A SEPERATE 10 MIL TRACE
OMIT
=PPVCCIO S0 CPU
93 19 IN DMI_S2N_N<0> W4 DMI_RX_0* OMIT PEG_COMPI B4
PLACEMENT NOTE=Place within 12 7MM of CPU 6 11 13 16 65
U1000
93 19 IN DMI_S2N_N<1> V4 DMI_RX_1* U1000 PEG_ICOMPO B5 R1010 SANDY_BRIDGE
24.9 2 LGA1155-SKT
93 19 IN DMI_S2N_N<2> Y4 DMI_RX_2* SANDY_BRIDGE PEG_RCOMPO C4 93 CPU_PEG_COMP
1
93 19 DMI S2N N<3> AA5 DMI_RX_3* LGA1155-SKT MIN NECK WIDTH=0 2MM 1% (5 OF 10)
IN
(1 OF 10) NET SPACING TYPE=CPU RCOMP 1/16W
MF-LF 8 TP_CPU_RSVD<1> C38 RSVD_C38 RSVD_P35 P35 TP_CPU_RSVD<20> 8
93 19 DMI_S2N_P<0> W5 DMI_RX_0 PEG_RX_0* B12 =PEG_D2R_N<0> 9 402
IN IN TP_CPU_RSVD<2> C39 P37 TP_CPU_RSVD<21>
V3 D11 8 RSVD_C39 RSVD_P37 8
93 19 IN DMI_S2N_P<1> DMI_RX_1 PEG_RX_1* =PEG_D2R_N<1> IN 9
8 TP_CPU_RSVD<3> D38 RSVD_D38 RSVD_P39 P39 TP_CPU_RSVD<22> 8
93 19 DMI S2N P<2> Y3 DMI_RX_2 PEG_RX_2* C9 =PEG D2R N<2> 9
D 93 19
IN
IN DMI S2N P<3> AA4 DMI_RX_3 PEG_RX_3* E9
B7
=PEG D2R N<3>
IN
IN 9
8
8
TP_CPU_RSVD<4>
TP_CPU_RSVD<5>
H7
H8
RSVD_H7
RSVD_H8
RSVD_R34
RSVD_R36
R34
R36
TP_CPU_RSVD<23>
TP_CPU_RSVD<24>
8
8
D
PEG_RX_4* =PEG_D2R_N<4> IN 9
DMI_N2S_N<0> V6 DMI_TX_0* TP_CPU_RSVD<6> J9 RSVD_J9 RSVD_R38 R38 TP_CPU_RSVD<25>
DMI
93 19 OUT 8 8
PEG_RX_5* C5 =PEG_D2R_N<5> 9
DMI N2S N<1> W8 IN TP CPU RSVD<7> J31 R40 TP CPU RSVD<26>
93 19 OUT DMI_TX_1* A6 8 RSVD_J31 RSVD_R40 8
PEG_RX_6* =PEG_D2R_N<6> IN 9
93 19 DMI N2S N<2> Y7 DMI_TX_2* 8 TP CPU RSVD<8> J33 RSVD_J33 RSVD_AB6 AB6 TP CPU RSVD<27> 8
OUT E1 =PEG_D2R_N<7>
AA8 PEG_RX_7* IN 9
J34 AB7
93 19 OUT DMI N2S N<3> DMI_TX_3* 8 TP CPU RSVD<9> RSVD_J34 RSVD_AB7 TP CPU RSVD<28> 8
PEG_RX_8* F3 =PEG_D2R_N<8> 9
IN TP_CPU_RSVD<10> K9 AD34 TP_CPU_RSVD<29>
V7 G1 8 RSVD_K9 RSVD_AD34 8
93 19 OUT DMI_N2S_P<0> DMI_TX_0 PEG_RX_9* =PEG_D2R_N<9> IN 9
8 TP_CPU_RSVD<11> K31 RSVD_K31 RSVD_AD35 AD35 TP_CPU_RSVD<30> 8
93 19 DMI N2S P<1> W7 DMI_TX_1 PEG_RX_10* H4 =PEG D2R N<10> 9
OUT IN TP_CPU_RSVD<12> K34 AD37 TP_CPU_RSVD<31>
8 RSVD_K34 RSVD_AD37 8
RESERVED
93 19 DMI N2S P<2> Y6 DMI_TX_2 PEG_RX_11* J2 =PEG D2R N<11> 9
OUT IN TP_CPU_RSVD<13> L9 AE6 TP_CPU_RSVD<32>
AA7 K4 8 RSVD_L9 RSVD_AE6 8
93 19 OUT DMI_N2S_P<3> DMI_TX_3 PEG_RX_12* =PEG_D2R_N<12> IN 9
8 TP_CPU_RSVD<14> L31 RSVD_L31 RSVD_AF4 AF4 TP_CPU_RSVD<33> 8
PEG_RX_13* L2 =PEG_D2R_N<13> 9
IN TP CPU RSVD<15> L33 AG4 TP CPU RSVD<34>
AC7 M4 8 RSVD_L33 RSVD_AG4 8
8 TP_CPU_FDI_TX_N<0> FDI_TX_0* PEG_RX_14* =PEG_D2R_N<14> IN 9
8 TP CPU RSVD<16> L34 RSVD_L34 RSVD_AJ11 AJ11 TP CPU RSVD<35> 8
8 TP_CPU_FDI_TX_N<1> AC3 FDI_TX_1* PEG_RX_15* N2 =PEG_D2R_N<15> 9
IN SNS CPU THERMD N M34 AJ29 TP CPU RSVD<36>
AD1 97 52 OUT RSVD_M34 ThermDC RSVD_AJ29 8
8 TP_CPU_FDI_TX_N<2> FDI_TX_2*
PEG_RX_0 B11 =PEG_D2R_P<0> 9 97 52 SNS_CPU_THERMD_P N33 RSVD_N33 ThermDA RSVD_AJ30 AJ30 TP_CPU_RSVD<37> 8
TP_CPU_FDI_TX_N<3> AD3 IN OUT
FDI_TX_3*
FLEXIBLE DISPLAY INTERFACE

8
PEG_RX_1 D12 =PEG_D2R_P<1> 9 8 TP_CPU_RSVD<19> N34 RSVD_N34 RSVD_AJ31 AJ31 TP_CPU_RSVD<38> 8
TP CPU FDI TX N<4> AD6 IN
8 FDI_TX_4* C10 AN20
PEG_RX_2 =PEG_D2R_P<2> IN 9 RSVD_AN20 TP_CPU_RSVD<39> 8
8 TP CPU FDI TX N<5> AE8 FDI_TX_5*
PEG_RX_3 E10 =PEG_D2R_P<3> 9 93 25 15 CPU_CFG<0> H36 CFG_0 RSVD_AP20 AP20 TP_CPU_RSVD<40> 8
TP_CPU_FDI_TX_N<6> AF2 IN IN
8 FDI_TX_6* B8 J36 AT11
PEG_RX_4 =PEG_D2R_P<4> IN 9 93 25 15 IN CPU_CFG<1> CFG_1 RSVD_AT11 TP_CPU_RSVD<41> 8
8 TP_CPU_FDI_TX_N<7> AG1 FDI_TX_7*
PEG_RX_5 C6 =PEG_D2R_P<5> 9 93 25 15 CPU_CFG<2> J37 CFG_2 RSVD_AT14 AT14 TP_CPU_RSVD<42> 8
IN IN
8 TP CPU FDI TX P<0> AC8 FDI_TX_0 PEG_RX_6 A5 =PEG D2R P<6> 9 93 25 15 CPU CFG<3> K36 CFG_3 RSVD_AU10 AU10 TP CPU RSVD<43> 8
IN IN
(Unused)
8 TP CPU FDI TX P<1> AC2 FDI_TX_1 PEG_RX_7 E2 =PEG D2R P<7> 9 93 25 CPU CFG<4> L36 CFG_4 RSVD_AV34 AV34 TP CPU RSVD<44> 8
IN IN
8 TP_CPU_FDI_TX_P<2> AD2 FDI_TX_2 PEG_RX_8 F4 =PEG_D2R_P<8> 9 93 25 15 CPU_CFG<5> N35 CFG_5 RSVD_AW34 AW34 TP_CPU_RSVD<45> 8
IN IN
PCI EXPRESS -- GRAPHICS

8 TP_CPU_FDI_TX_P<3> AD4 FDI_TX_3 PEG_RX_9 G2 =PEG_D2R_P<9> 9 93 25 15 CPU_CFG<6> L37 CFG_6 RSVD_AY10 AY10 TP_CPU_RSVD<46> 8
IN IN
8 TP_CPU_FDI_TX_P<4> AD7 FDI_TX_4 PEG_RX_10 H3 =PEG_D2R_P<10> 9 93 25 CPU_CFG<7> M36 CFG_7
IN IN
AE7 J1 J38 RSVD_NCTF_AV1 AV1 TP CPU RSVD NCTF<1>
8 TP_CPU_FDI_TX_P<5> FDI_TX_5 PEG_RX_11 =PEG_D2R_P<11> IN 9 93 25 IN CPU_CFG<8> CFG_8
AF3 K3 L35 RSVD_NCTF_AW2 AW2 TP CPU RSVD NCTF<2>
8 TP_CPU_FDI_TX_P<6> FDI_TX_6 PEG_RX_12 =PEG_D2R_P<12> IN 9 93 25 IN CPU_CFG<9> CFG_9
RSVD_NCTF_AY3 AY3
C 8 TP_CPU_FDI_TX_P<7> AG2 FDI_TX_7 PEG_RX_13
PEG_RX_14
L1
M3
=PEG_D2R_P<13>
=PEG D2R P<14>
IN 9
9
93 25
93 25
IN CPU_CFG<10>
CPU CFG<11>
M38
N36
CFG_10
CFG_11
RSVD_NCTF_B39 B39
TP_CPU_RSVD_NCTF<3>
TP_CPU_RSVD_NCTF<4> C
CPU_FDI_FSYNC<0> AC5 FDI_FSYNC_0 IN IN
15
PEG_RX_15 N1 =PEG D2R P<15> 9 93 25 CPU CFG<12> N38 CFG_12 NCTF_A38 A38 TP CPU NCTF<1>
CPU_FDI_FSYNC<1> AE5 FDI_FSYNC_1 IN IN
15
93 25 CPU_CFG<13> N39 CFG_13 NCTF_C2 C2 TP_CPU_NCTF<2>
C14 =PEG_R2D_C_N<0> IN
AG3 FDI_INT PEG_TX_0* OUT 9
N37 D1
15 CPU_FDI_INT 93 25 IN CPU_CFG<14> CFG_14 NCTF_D1 TP_CPU_NCTF<3>
PEG_TX_1* E13 =PEG_R2D_C_N<1> 9
OUT CPU_CFG<15> N40 AU40 TP_CPU_NCTF<4>
AC4 FDI_LSYNC_0 G13 93 25 IN CFG_15 NCTF_AU40
15 CPU FDI LSYNC<0> PEG_TX_2* =PEG R2D C N<2> OUT 9
93 25 15 IN CPU_CFG<16> G37 CFG_16 NCTF_AW38 AW38 TP_CPU_NCTF<5>
15 CPU_FDI_LSYNC<1> AE4 FDI_LSYNC_1 PEG_TX_3* F11 =PEG_R2D_C_N<3> 9
OUT CPU_CFG<17> G36
J13 93 25 IN CFG_17
PLACEMENT NOTE=Place within 12 7MM of CPU PEG_TX_4* =PEG_R2D_C_N<4> OUT 9 INTEL SUGGESTS TO KEEP THESE TPS
CPU_FDI_COMPIO AE2 FDI_COMPIO
MIN LINE WIDTH=0 3MM PEG_TX_5* D7 =PEG_R2D_C_N<5> 9
AE1 FDI_ICOMPO OUT
1 MIN NECK WIDTH=0 2MM
C3
R1011 NET SPACING TYPE=CPU RCOMP PEG_TX_6*
E5
=PEG_R2D_C_N<6> OUT 9
0 TP_PE_RX_N<0> P4 PEG_TX_7* =PEG_R2D_C_N<7> OUT 9

5% 8 PE_RX_0* F7
1/16W PEG_TX_8* =PEG_R2D_C_N<8> OUT 9
MF-LF 8 TP_PE_RX_N<1> R1 PE_RX_1*
402 2 PEG_TX_9* G9 =PEG_R2D_C_N<9> OUT 9
(Available for Workstation only)
8 TP_PE_RX_N<2> T3 PE_RX_2*
PEG_TX_10* G6 =PEG_R2D_C_N<10> 9
FOR SANDYBRIDGE PROCESSOR
TP_PE_RX_N<3> U1 OUT
8 PE_RX_3* K8
PEG_TX_11* =PEG_R2D_C_N<11> OUT 9
TP_PE_RX_P<0> P3 J6 =PEG_R2D_C_N<12>
CFG [6:5] :PCIE CONFIGURATION SELECT 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
8 PE_RX_0 PEG_TX_12* OUT 9
CFG [2] :PCIE LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
PCI EXPRESS
8 TP_PE_RX_P<1> R2 PE_RX_1 PEG_TX_13* M7 =PEG_R2D_C_N<13> 9

OUT
8 TP_PE_RX_P<2> T4 PE_RX_2 PEG_TX_14* L5 =PEG_R2D_C_N<14> 9
OUT
8 TP_PE_RX_P<3> U2 PE_RX_3 PEG_TX_15* N6 =PEG_R2D_C_N<15> 9
OUT
8 TP_PE_TX_N<0> P7 PE_TX_0* PEG_TX_0 C13 =PEG_R2D_C_P<0> 9

OUT
8 TP_PE_TX_N<1> T8 PE_TX_1* PEG_TX_1 E14 =PEG_R2D_C_P<1> 9
OUT
8 TP_PE_TX_N<2> R5 PE_TX_2* PEG_TX_2 G14 =PEG_R2D_C_P<2> 9
OUT
8 TP_PE_TX_N<3> U6 PE_TX_3* PEG_TX_3 F12 =PEG_R2D_C_P<3> 9
OUT
PEG_TX_4 J14 =PEG R2D C P<4> OUT 9
8 TP_PE_TX_P<0> P8 PE_TX_0
PEG_TX_5 D8 =PEG_R2D_C_P<5> 9
TP_PE_TX_P<1> T7 OUT
8 PE_TX_1
B 8 TP_PE_TX_P<2> R6
U5
PE_TX_2
PEG_TX_6
PEG_TX_7
D3
E6
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
OUT
OUT
9
9
B
8 TP PE TX P<3> PE_TX_3
PEG_TX_8 F8 =PEG_R2D_C_P<8> OUT 9
PEG_TX_9 G10 =PEG_R2D_C_P<9> OUT 9
PEG_TX_10 G5 =PEG_R2D_C_P<10> 9
OUT
PEG_TX_11 K7 =PEG R2D C P<11> OUT 9
PEG_TX_12 J5 =PEG R2D C P<12> 9

OUT
PEG_TX_13 M8 =PEG R2D C P<13> OUT 9
PEG_TX_14 L6 =PEG_R2D_C_P<14> OUT 9
PEG_TX_15 N5 =PEG_R2D_C_P<15> 9
OUT
A A
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE

REVISION
R
10.1.0
10 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
65 16 13 11 10 6 =PPVCCIO_S0_CPU
D D
1
NOSTUFF 1 1 NOSTUFF NOSTUFF1
R1100 R1101 R1104 R1102
1K 51 51 1K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF LF MF LF MF LF MF LF
402 402 402 402
2 2 2 2
OMIT
U1000
SANDY_BRIDGE
LGA1155-SKT
(2 OF 10)
CLOCKS
BASED ON INTEL MOBILE SOLUTION AJ33 SKTOCC* BCLK_ITP C40 ITPCPU_CLK100M_P IN 18 93
100 63 OUT CPU SKTOCC L
BCLK_ITP* D40 ITPCPU_CLK100M_N IN 18 93
=PPVCCIO S0 CPU 100 19 OUT CPU_PROC_SEL K32 PROC_SEL

65 16 13 11 10 6
BCLK_0 W2 DMI_CLK100M_CPU_P IN 18 93
BCLK_0* W1 DMI_CLK100M_CPU_N IN 18 93
PLACEMENT NOTE=PLACE WITHIN 2 INCHES OF CPU
100 CPU_CATERR_L E37 CATERR*
R11241 PRDY* K38
THERMAL
XDP_CPU_PRDY_L OUT 25
75 J35 PECI
5% 100 46 21 BI CPU_PECI PREQ* K40 XDP_CPU_PREQ_L IN 25
1/16W
MF-LF
402 2
CPU PROCHOT L H34 PROCHOT* TCK M40 XDP CPU TCK
R1125 100 65 47 BI IN 25 93
2
43 1
TMS L38 XDP_CPU_TMS IN 25 93
100 27 IN CPU_RESET_L
100 47 OUT CPU_THRMTRIP_L G35 THERMTRIP* TRST* J39 XDP_CPU_TRST_L IN 25 93
5%
1/16W NOSTUFF
MF-LF
R11261 TDI L40 XDP_CPU_TDI
JTAG & BPM

402
PWR MGMT
IN 25 93
0 100 PLT_RESET_LS1V05_L F36 RESET* TDO L39 XDP_CPU_TDO OUT 25 93
C 5%
1/16W
MF-LF
402 2 100 19 PM SYNC E38 PM_SYNC DBR* E39 XDP DBRESET L 25 100
C
IN OUT
100 25 21 IN CPU_PWRGD J40 UNCOREPWRGOOD

BPM[0]* H40 XDP_BPM_L<0> BI 25 93
BPM[1]* H38 XDP_BPM_L<1> BI 25 93
100 PM_MEM_PWRGD_R AJ19 SM_DRAMPWROK BPM[2]* G38 XDP_BPM_L<2>
DDR3 MISC
29 28 16 13 6 =PP1V5_S0_CPU_MEM BI 25 93
BPM[3]* G40 XDP_BPM_L<3> BI 25 93

100 32 CPU_MEM_RESET_L AW18 SM_DRAMRST*
OUT G39 XDP_BPM_L<4>
BPM[4]*
R11201 CPU_DDR_VREF AJ22 SM_VREF BPM[5]* F38 XDP_BPM_L<5>
BI 25 93
200 92 28 IN BI 25 93
1% BPM[6]* E40 XDP BPM L<6> 25 93
1/16W BI
FROM PCH MF-LF AH1 FC_AH1 F40
R1121 TP_CPU_DIMM_VREF_B BPM[7]* XDP_BPM_L<7> BI 25 93
402 2
121 TP_CPU_DIMM_VREF_A AH4 FC_AH4
100 19 IN PM_MEM_PWRGD 2 1
1%
PM_MEM_PWRGD MUST ASSERT MIN. 100ns AFTER =PP1V5_S0_CPU_MEM IS STABLE 1/16W
MF-LF
402
64 63 6 =PP3V3_S5_PWRCTL
NOSTUFF NOSTUFF
1
27 11 6 =PP3V3_S0_RSTBUF 1
C1110 1 1 C1111 R1111
R1183 0.1UF
10%
0.1UF
10%
1K
5%
4.7K 16V 2 2 16V
1/16W
5% 6 X5R X5R MF LF
1 1/16W 402 402 2 402
R1190 MF-LF
2 402
D Q1180
27 11 6 =PP3V3_S0_RSTBUF 12K
OPEN-DRAIN BUFFER 5% DMB53D0UV
1/16W SOT-563
MF-LF 2 G
PM_MEM_PWRGD_L
2 402
100
B 5 U1190 B
74LVC1G07 3 S
SC70
100 74 64 IN PM_PGOOD_P1V5_S0_FET 2 4 100 PGOOD_P1V5_S0_DLY 5 Q1180 1
DMB53D0UV
NC SOT-563
4
1 3 C1180 1
NC_U1190_P1 0.015UF
NO TEST=TRUE 10%
16V
CAN ADJUST R1190 AND C1180 X7R 2
C1190 1 402
0.1UF
20%
10V
CERM 2
402
A A
PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER SIZE

REVISION
R
10.1.0
11 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1000 U1000
SANDY_BRIDGE SANDY_BRIDGE
LGA1155-SKT LGA1155-SKT
92 32 MEM A DQ<0> AJ3 SA_DQ_0 (3 OF 10) SA_CK_0 AY25 MEM A CLK P<0> 32 92 92 32 MEM B DQ<0> AG7 SB_DQ_0 (4 OF 10) SB_CK_0 AL21 MEM B CLK P<0> 32 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<1> AJ4 SA_DQ_1 SA_CK_0* AW25 MEM_A_CLK_N<0> OUT 32 92 92 32 BI MEM_B_DQ<1> AG8 SB_DQ_1 SB_CK_0* AL22 MEM_B_CLK_N<0> OUT 32 92
92 32 BI MEM_A_DQ<2> AL3 SA_DQ_2 92 32 BI MEM_B_DQ<2> AJ9 SB_DQ_2

AL4 SA_CKE_0 AV19 MEM_A_CKE<0> OUT 30 92
AJ8 SB_CKE_0 AU16 MEM_B_CKE<0> OUT 31 92
92 32 BI MEM_A_DQ<3> SA_DQ_3 92 32 BI MEM_B_DQ<3> SB_DQ_3
D 92 32
92 32
BI
BI
MEM_A_DQ<4>
MEM_A_DQ<5>
AJ2
AJ1
SA_DQ_4
SA_DQ_5
SA_CK_1 AU24
SA_CK_1* AU25
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
OUT
OUT
32 92
32 92
92 32
92 32
BI
BI
MEM_B_DQ<4>
MEM_B_DQ<5>
AG5
AG6
SB_DQ_4
SB_DQ_5
SB_CK_1 AL20
SB_CK_1* AK20
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
OUT
32 92
32 92
D
92 32 BI MEM_A_DQ<6> AL2 SA_DQ_6 92 32 BI MEM_B_DQ<6> AJ6 SB_DQ_6
AL1 SA_CKE_1 AT19 MEM_A_CKE<1> OUT 30 92
AJ7 SB_CKE_1 AY15 MEM_B_CKE<1> OUT 31 92
92 32 BI MEM A DQ<7> SA_DQ_7 92 32 BI MEM B DQ<7> SB_DQ_7
DDR SYSTEM MEMORY A

92 32 BI MEM A DQ<8> AN1 SA_DQ_8 SA_CK_2 AW27 MEM A CLK P<2> OUT 32 92 92 32 BI MEM B DQ<8> AL7 SB_DQ_8 SB_CK_2 AL23 MEM B CLK P<2> OUT 32 92
DDR SYSTEM MEMORY B

92 32 MEM A DQ<9> AN4 SA_DQ_9 SA_CK_2* AY27 MEM A CLK N<2> 32 92 92 32 MEM B DQ<9> AM7 SB_DQ_9 SB_CK_2* AM22 MEM B CLK N<2> 32 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<10> AR3 SA_DQ_10 92 32 BI MEM_B_DQ<10> AM10 SB_DQ_10
AR4 SA_CKE_2 AU18 MEM_A_CKE<2> OUT 30 92
AL10 SB_CKE_2 AW15 MEM_B_CKE<2> OUT 31 92
92 32 BI MEM_A_DQ<12> AN2 SA_DQ_12 SA_CK_3 AV26 MEM_A_CLK_P<3> OUT 32 92 92 32 BI MEM_B_DQ<12> AL6 SB_DQ_12 SB_CK_3 AP21 MEM_B_CLK_P<3> OUT 32 92
92 32 MEM_A_DQ<13> AN3 SA_DQ_13 SA_CK_3* AW26 MEM_A_CLK_N<3> 32 92 92 32 MEM_B_DQ<13> AM6 SB_DQ_13 SB_CK_3* AN21 MEM_B_CLK_N<3> 32 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<14> AR2 SA_DQ_14 92 32 BI MEM_B_DQ<14> AL9 SB_DQ_14
AR1 SA_CKE_3 AV18 MEM_A_CKE<3> OUT 30 92
AM9 SB_CKE_3 AV15 MEM_B_CKE<3> OUT 31 92
92 32 BI MEM A DQ<16> AV2 SA_DQ_16 SA_CS_0* AU29 MEM A CS L<0> OUT 30 92 92 32 BI MEM B DQ<16> AP7 SB_DQ_16 SB_CS_0* AN25 MEM B CS L<0> OUT 31 92
92 32 MEM A DQ<17> AW3 SA_DQ_17 SA_CS_1* AV32 MEM A CS L<1> 30 92 92 32 MEM B DQ<17> AR7 SB_DQ_17 SB_CS_1* AN26 MEM B CS L<1> 31 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<18> AV5 SA_DQ_18 SA_CS_2* AW30 MEM_A_CS_L<2> OUT 30 92 92 32 BI MEM_B_DQ<18> AP10 SB_DQ_18 SB_CS_2* AL25 MEM_B_CS_L<2> OUT 31 92
92 32 BI MEM_A_DQ<19> AW5 SA_DQ_19 SA_CS_3* AU33 MEM_A_CS_L<3> OUT 30 92 92 32 BI MEM_B_DQ<19> AR10 SB_DQ_19 SB_CS_3* AT26 MEM_B_CS_L<3> OUT 31 92
92 32 MEM_A_DQ<20> AU2 SA_DQ_20 92 32 MEM_B_DQ<20> AP6 SB_DQ_20

BI BI
92 32 BI MEM_A_DQ<21> AU3 SA_DQ_21 SA_ODT_0 AV31 MEM_A_ODT<0> OUT 30 92 92 32 BI MEM_B_DQ<21> AR6 SB_DQ_21 SB_ODT_0 AL26 MEM_B_ODT<0> OUT 31 92
92 32 BI MEM_A_DQ<22> AU5 SA_DQ_22 SA_ODT_1 AU32 MEM_A_ODT<1> OUT 30 92 92 32 BI MEM_B_DQ<22> AP9 SB_DQ_22 SB_ODT_1 AP26 MEM_B_ODT<1> OUT 31 92
92 32 BI MEM_A_DQ<23> AY5 SA_DQ_23 SA_ODT_2 AU30 MEM_A_ODT<2> OUT 30 92 92 32 BI MEM_B_DQ<23> AR9 SB_DQ_23 SB_ODT_2 AM26 MEM_B_ODT<2> OUT 31 92
92 32 MEM A DQ<24> AY7 SA_DQ_24 SA_ODT_3 AW33 MEM A ODT<3> 30 92 92 32 MEM B DQ<24> AM12 SB_DQ_24 SB_ODT_3 AK26 MEM B ODT<3> 31 92
BI OUT BI OUT
92 32 BI MEM A DQ<25> AU7 SA_DQ_25 92 32 BI MEM B DQ<25> AM13 SB_DQ_25
92 32 MEM_A_DQ<26> AV9 SA_DQ_26 SA_DQS_0* AK2 MEM_A_DQS_N<0> 32 92 92 32 MEM_B_DQ<26> AR13 SB_DQ_26 SB_DQS_0* AH6 MEM_B_DQS_N<0> 32 92
BI BI BI BI
92 32 MEM_A_DQ<27> AU9 SA_DQ_27 SA_DQS_1* AP2 MEM_A_DQS_N<1> 32 92 92 32 MEM_B_DQ<27> AP13 SB_DQ_27 SB_DQS_1* AL8 MEM_B_DQS_N<1> 32 92
BI BI BI BI
92 32 BI MEM_A_DQ<28> AV7 SA_DQ_28 SA_DQS_2* AV4 MEM_A_DQS_N<2> BI 32 92 92 32 BI MEM_B_DQ<28> AL12 SB_DQ_28 SB_DQS_2* AP8 MEM_B_DQS_N<2> BI 32 92
92 32 MEM_A_DQ<29> AW7 SA_DQ_29 SA_DQS_3* AW8 MEM_A_DQS_N<3> 32 92 92 32 MEM_B_DQ<29> AL13 SB_DQ_29 SB_DQS_3* AN12 MEM_B_DQS_N<3> 32 92
BI BI BI BI
92 32 BI MEM_A_DQ<30> AW9 SA_DQ_30 SA_DQS_4* AV36 MEM_A_DQS_N<4> BI 32 92 92 32 BI MEM_B_DQ<30> AR12 SB_DQ_30 SB_DQS_4* AN28 MEM_B_DQS_N<4> BI 32 92
C 92 32
92 32
BI MEM_A_DQ<31>
MEM A DQ<32>
AY9
AU35
SA_DQ_31
SA_DQ_32
SA_DQS_5*
SA_DQS_6*
AP39
AK39
MEM_A_DQS_N<5>
MEM A DQS N<6>
BI 32 92
32 92
92 32
92 32
BI MEM_B_DQ<31>
MEM B DQ<32>
AP12
AR28
SB_DQ_31
SB_DQ_32
SB_DQS_5*
SB_DQS_6*
AR33
AM33
MEM_B_DQS_N<5>
MEM B DQS N<6>
BI 32 92
32 92
C
BI BI BI BI
92 32 MEM A DQ<33> AW37 SA_DQ_33 SA_DQS_7* AF39 MEM A DQS N<7> 32 92 92 32 MEM B DQ<33> AR29 SB_DQ_33 SB_DQS_7* AG34 MEM B DQS N<7> 32 92
BI BI BI BI
92 32 MEM_A_DQ<34> AU39 SA_DQ_34 SA_DQS_8* AV12 TP_MEM_A_DQS_N<8> 8 92 32 MEM_B_DQ<34> AL28 SB_DQ_34 SB_DQS_8* AN15 TP_MEM_B_DQS_N<8> 8
BI BI
92 32 MEM_A_DQ<35> AU36 SA_DQ_35 92 32 MEM_B_DQ<35> AL29 SB_DQ_35
BI AK3 MEM_A_DQS_P<0> BI AH7 MEM_B_DQS_P<0>
AW35 SA_DQS_0 BI 32 92
AP28 SB_DQS_0 BI 32 92
SA_DQS_1 AP3 MEM A DQS P<1> 32 92 SB_DQS_1 AM8 MEM B DQS P<1> 32 92
MEM_A_DQ<37> AY36 BI MEM_B_DQ<37> AP29 BI
92 32 BI SA_DQ_37 AW4 92 32 BI SB_DQ_37 AR8
SA_DQS_2 MEM_A_DQS_P<2> BI 32 92 SB_DQS_2 MEM_B_DQS_P<2> BI 32 92
92 32 MEM_A_DQ<38> AU38 SA_DQ_38 92 32 MEM_B_DQ<38> AM28 SB_DQ_38
BI AV8 MEM_A_DQS_P<3> BI AN13 MEM_B_DQS_P<3>
AU37 SA_DQS_3 BI 32 92
AM29 SB_DQS_3 BI 32 92
SA_DQS_4 AV37 MEM_A_DQS_P<4> 32 92 SB_DQS_4 AN29 MEM_B_DQS_P<4> 32 92
MEM A DQ<40> AR40 BI MEM B DQ<40> AP32 BI
92 32 BI SA_DQ_40 AP38 92 32 BI SB_DQ_40 AP33
92 32 BI MEM_A_DQ<41> AR37 SA_DQ_41 92 32 BI MEM_B_DQ<41> AP31 SB_DQ_41
SA_DQS_6 AK38 MEM_A_DQS_P<6> 32 92 SB_DQS_6 AL33 MEM_B_DQS_P<6> 32 92
MEM_A_DQ<42> AN38 BI MEM_B_DQ<42> AP35 BI
92 32 BI SA_DQ_42 AF38 92 32 BI SB_DQ_42 AG35
92 32 BI MEM_A_DQ<43> AN37 SA_DQ_43 92 32 BI MEM_B_DQ<43> AP34 SB_DQ_43
SA_DQS_8 AV13 TP_MEM_A_DQS_P<8> 8 SB_DQS_8 AN16 TP_MEM_B_DQS_P<8> 8
92 32 BI MEM_A_DQ<44> AR39 SA_DQ_44 92 32 BI MEM_B_DQ<44> AR32 SB_DQ_44
92 32 MEM_A_DQ<45> AR38 SA_DQ_45 SA_MA_0 AV27 MEM_A_A<0> 30 92 92 32 MEM_B_DQ<45> AR31 SB_DQ_45 SB_MA_0 AK24 MEM_B_A<0> 31 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<46> AN39 SA_DQ_46 SA_MA_1 AY24 MEM_A_A<1> OUT 30 92 92 32 BI MEM_B_DQ<46> AR35 SB_DQ_46 SB_MA_1 AM20 MEM_B_A<1> OUT 31 92
92 32 BI MEM_A_DQ<47> AN40 SA_DQ_47 SA_MA_2 AW24 MEM_A_A<2> OUT 30 92 92 32 BI MEM_B_DQ<47> AR34 SB_DQ_47 SB_MA_2 AM19 MEM_B_A<2> OUT 31 92
92 32 BI MEM_A_DQ<48> AL40 SA_DQ_48 SA_MA_3 AW23 MEM_A_A<3> OUT 30 92 92 32 BI MEM_B_DQ<48> AM32 SB_DQ_48 SB_MA_3 AK18 MEM_B_A<3> OUT 31 92
92 32 BI MEM_A_DQ<49> AL37 SA_DQ_49 SA_MA_4 AV23 MEM_A_A<4> OUT 30 92 92 32 BI MEM_B_DQ<49> AM31 SB_DQ_49 SB_MA_4 AP19 MEM_B_A<4> OUT 31 92
92 32 MEM_A_DQ<50> AJ38 SA_DQ_50 SA_MA_5 AT24 MEM_A_A<5> 30 92 92 32 MEM_B_DQ<50> AL35 SB_DQ_50 SB_MA_5 AP18 MEM_B_A<5> 31 92
BI OUT BI OUT
92 32 MEM_A_DQ<51> AJ37 SA_DQ_51 SA_MA_6 AT23 MEM_A_A<6> 30 92 92 32 MEM_B_DQ<51> AL32 SB_DQ_51 SB_MA_6 AM18 MEM_B_A<6> 31 92
BI OUT BI OUT
92 32 MEM_A_DQ<52> AL39 SA_DQ_52 SA_MA_7 AU22 MEM_A_A<7> 30 92 92 32 MEM_B_DQ<52> AM34 SB_DQ_52 SB_MA_7 AL18 MEM_B_A<7> 31 92
BI OUT BI OUT
92 32 MEM_A_DQ<53> AL38 SA_DQ_53 SA_MA_8 AV22 MEM_A_A<8> 30 92 92 32 MEM_B_DQ<53> AL31 SB_DQ_53 SB_MA_8 AN18 MEM_B_A<8> 31 92
BI OUT BI OUT
92 32 MEM_A_DQ<54> AJ39 SA_DQ_54 SA_MA_9 AT22 MEM_A_A<9> 30 92 92 32 MEM_B_DQ<54> AM35 SB_DQ_54 SB_MA_9 AY17 MEM_B_A<9> 31 92
BI OUT BI OUT
92 32 MEM A DQ<55> AJ40 SA_DQ_55 SA_MA_10 AV28 MEM A A<10> 30 92 92 32 MEM B DQ<55> AL34 SB_DQ_55 SB_MA_10 AN23 MEM B A<10> 31 92
BI OUT BI OUT
92 32 MEM_A_DQ<56> AG40 SA_DQ_56 SA_MA_11 AU21 MEM_A_A<11> 30 92 92 32 MEM_B_DQ<56> AH35 SB_DQ_56 SB_MA_11 AU17 MEM_B_A<11> 31 92
BI OUT BI OUT
B 92 32
92 32
BI
BI
MEM_A_DQ<57>
MEM_A_DQ<58>
AG37
AE38
SA_DQ_57
SA_DQ_58
SA_MA_12
SA_MA_13
AT21
AW32
MEM_A_A<12>
MEM_A_A<13>
OUT
OUT
30 92
30 92
92 32
92 32
BI
BI
MEM_B_DQ<57>
MEM_B_DQ<58>
AH34
AE34
SB_DQ_57
SB_DQ_58
SB_MA_12
SB_MA_13
AT18
AR26
MEM_B_A<12>
MEM_B_A<13>
OUT
OUT
31 92
31 92
B
92 32 MEM_A_DQ<59> AE37 SA_DQ_59 SA_MA_14 AU20 MEM_A_A<14> 30 92 92 32 MEM_B_DQ<59> AE35 SB_DQ_59 SB_MA_14 AY16 MEM_B_A<14> 31 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<60> AG39 SA_DQ_60 SA_MA_15 AT20 MEM_A_A<15> OUT 30 92 92 32 BI MEM_B_DQ<60> AJ35 SB_DQ_60 SB_MA_15 AV16 MEM_B_A<15> OUT 31 92
92 32 MEM_A_DQ<61> AG38 SA_DQ_61 92 32 MEM_B_DQ<61> AJ34 SB_DQ_61

BI AU12 TP_MEM_A_DQ_CB<0> BI AL16 TP_MEM_B_DQ_CB<0>
AE39 SA_ECC_CB_0 8
AF33 SB_ECC_CB_0 8
SA_ECC_CB_1 AU14 TP_MEM_A_DQ_CB<1> 8 SB_ECC_CB_1 AM16 TP_MEM_B_DQ_CB<1> 8
92 32 BI MEM A DQ<63> AE40 SA_DQ_63 92 32 BI MEM B DQ<63> AF35 SB_DQ_63
SA_ECC_CB_2 AW13 TP_MEM_A_DQ_CB<2> 8 SB_ECC_CB_2 AP16 TP_MEM_B_DQ_CB<2> 8
92 30 MEM_A_BA<0> AY29 SA_BS_0 SA_ECC_CB_3 AY13 TP_MEM_A_DQ_CB<3> 8 92 31 MEM_B_BA<0> AP23 SB_BS_0 SB_ECC_CB_3 AR16 TP_MEM_B_DQ_CB<3> 8
OUT OUT
92 30 MEM_A_BA<1> AW28 SA_BS_1 SA_ECC_CB_4 AU13 TP_MEM_A_DQ_CB<4> 8 92 31 MEM_B_BA<1> AM24 SB_BS_1 SB_ECC_CB_4 AL15 TP_MEM_B_DQ_CB<4> 8
OUT OUT
92 30 MEM A BA<2> AV20 SA_BS_2 SA_ECC_CB_5 AU11 TP MEM A DQ CB<5> 8 92 31 MEM B BA<2> AW17 SB_BS_2 SB_ECC_CB_5 AM15 TP MEM B DQ CB<5> 8
OUT OUT
SA_ECC_CB_6 AY12 TP MEM A DQ CB<6> 8 SB_ECC_CB_6 AR15 TP MEM B DQ CB<6> 8
92 30 MEM_A_CAS_L AV30 SA_CAS* 92 31 MEM_B_CAS_L AK25 SB_CAS*
OUT AW12 TP_MEM_A_DQ_CB<7> OUT AP15 TP_MEM_B_DQ_CB<7>
AU28 SA_RAS* SA_ECC_CB_7 8
AP24 SB_RAS* SB_ECC_CB_7 8
92 30 OUT MEM_A_RAS_L 92 31 OUT MEM_B_RAS_L
92 30 OUT MEM A WE L AW29 SA_WE* 92 31 OUT MEM B WE L AR25 SB_WE*
A SYNC DATE=01/09/2011 A
PAGE TITLE
CPU DDR3 INTERFACES

DRAWING NUMBER SIZE

REVISION
R
10.1.0
12 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1000
65 50 16 13 6 =PPVCORE_S0_CPU SANDY_BRIDGE
65 50 16 13 6 =PPVCORE_S0_CPU LGA1155-SKT =PPVCCIO_S0_CPU 6 10 11 13 16 65
D
A12
A13
VCC_001 (6 OF 10) VCCIO_01 A11
A7
(NOT controlled by VCCIO_SEL)
OMIT D
OMIT
A14
VCC_002
VCC_003
VCCIO_02
VCCIO_03 AA3
Fixed at 1.05V U1000
U1000 A15 VCC_004 VCCIO_04 AB8
SANDY_BRIDGE
LGA1155-SKT
SANDY_BRIDGE 65 50 17 6 =PPVAXG S0 CPU
A16 VCC_005 VCCIO_05 AF8 AB33 ( 7 OF 10 )
LGA1155-SKT VCCAXG_01
A18 VCC_006 VCCIO_06 AG33 AB34
F16 VCC_071 (10 OF 10) VCC_131 K22 VCCAXG_02
A24 VCC_007 VCCIO_07 AJ16 AB35
F18 VCC_072 VCC_132 K24 VCCAXG_03
B15 VCC_011 VCCIO_11 AJ32 AB39
B16 VCC_012 VCCIO_12 AK15 AB40
F25 VCC_077 VCC_137 L13 VCCAXG_08
B18 VCC_013 VCCIO_13 AK17 AC33
B24 VCC_014 VCCIO_14 AK19 AC34
B25 VCC_015 VCCIO_15 AK21 AC35 =PP1V5 S0 CPU MEM 6 11 16 28 29
B27 VCC_016 VCCIO_16 AK23
POWER
F31 L18 AC36 VCCAXG_12
VCC_081 VCC_141 B28 AK27
F32 L19 VCC_017 VCCIO_17 AC37 VCCAXG_13
VCC_082 VCC_142 B30 AK29
F33 CPU CORE SUPPLY L21 VCC_018 VCCIO_18 AC38 VCCAXG_14
VCC_083 VCC_143 B31 AK30
F34 L22 VCC_019 VCCIO_19 AC39 VCCAXG_15 VDDQ0 AJ13
IO POWER
VCC_084 VCC_144 B33 B9
G15 L24 VCC_020 VCCIO_20 AC40 VCCAXG_16 VDDQ1 AJ14
POWER
VCC_085 VCC_145 B34 D6
G16 L25 VCC_021 VCCIO_22 T33 VCCAXG_17 VDDQ2 AJ20
VCC_086 VCC_146 C15 D10
VCC_087 VCC_147 C16 E3
VCC_088 VCC_148 C18 E4
G21 L30 VCC_024 VCCIO_24 T36 VCCAXG_20 VDDQ5 AR20
VCC_089 VCC_149 C19 G3
G22 M14 VCC_025 VCCIO_25 T37 AR21
VCC_090 VCC_150 VCCAXG_21 VDDQ6
C21 VCC_026 VCCIO_26 G4
T38 AR22
G24 VCC_091 VCC_151 M15 VCCAXG_22 VDDQ7
DDR3-1.5V RAILS
C22 VCC_027 VCCIO_27 J3 T39 AR23
G25 M16
C
GRAPHICS
VCCAXG_23 VDDQ8
C VCC_092 VCC_152 C24 VCC_028 VCCIO_28 J4 T40 AR24
POWER
C25 VCC_029 VCCIO_29 J7 U33 AU19
C27 VCC_030 VCCIO_30 J8 U34 AU23
CPU CORE SUPPLY

C28 VCC_031 VCCIO_31 L3 U35 AU27
C30 VCC_032 VCCIO_32 L4 U36 AU31
C31 L7
CPU CORE SUPPLY
G33 M25 VCC_033 VCCIO_33 U37 VCCAXG_29 VDDQ14 AV21

VCC_098 VCC_158 C33 M13
H13 M27 VCC_034 VCCIO_34 U38 VCCAXG_30 VDDQ15 AV24
VCC_099 VCC_159 C34 N3
H14 M28 VCC_035 VCCIO_35 U39 VCCAXG_31 VDDQ16 AV25
VCC_100 VCC_160 C36 N4
VCC_036 VCCIO_36 PLACEMENT NOTE: U40 AV29
H15 VCC_101 VCC_161 M30 VCCAXG_32 VDDQ17
D13 VCC_037 VCCIO_37 N7
W33 AV33
H16 VCC_102 VCCAXG_33 VDDQ18
=PPVCCSA_S0_CPU D14 VCC_038 VCCIO_38 R3 PLACE R1300 AND
H18 6 50
R1302 NEAR CPU W34 VCCAXG_34 VDDQ19 AW31
VCC_103 D15 R4
H19 VCC_039 VCCIO_39 W35 AY23
VCC_104 VCCAXG_35 VDDQ20
D16 VCC_040 VCCIO_40 R7 PLACEMENT NOTE=Place close to CPU W36 AY26
H21 VCC_105 VCCSA0 H10 PLACEMENT NOTE=Place close to CPU VCCAXG_36 VDDQ21
D18 VCC_041 VCCIO_41 U3 W37 AY28
H22 VCC_106 VCCSA1 H11 =PPVCCIO_S0_CPU 6 10 11 13 16 65 VCCAXG_37 VDDQ22
D19 VCC_042 VCCIO_42 U4 W38
H24 VCC_107 VCCSA2 H12 VCCAXG_38
D21 VCC_043 VCCIO_43 U7 Y33
H25 VCC_108 VCCSA3 J10 1 1 VCCAXG_39
D22 VCC_044 VCCIO_44 V8 R1300 R1302 Y34
H27 K10 75 110 VCCAXG_40 =PP1V8 S0 CPU PLL
VCCSA
VCC_109 VCCSA4 D24 W3

6 16
H28 K11 VCC_045 VCCIO_45 1% 1% Y35 VCCAXG_41

VCC_110 VCCSA5 D25 1/16W 1/16W
VCC_046 MF LF MF LF Y36 VCCPLL0 AK11
1.8V
H30 VCC_111 VCCSA6 L11 402 402 VCCAXG_42
D27 VCC_047 2 2
H31 L12 Y37 VCCAXG_43 VCCPLL1 AK12
VCC_112 VCCSA7 D28
H32 M10 VCC_048 Y38 VCCAXG_44
VCC_113 VCCSA8 D30
J12 M11 VCC_049
VCC_114 VCCSA9 D31 VCCIO_SEL P33 TP_CPU_VCCIO_SEL
J15 M12 VCC_050
VCC_115 VCCSA10 D33
J16 VCC_051 VCCSA_VID P34 TP_CPU_VCCSA_VID
CPU VIDS
VCC_116 D34 R1310
J18 VCC_052
VCC_117 D35
44.2 2
J19 VCC_053 VIDALERT* A37 98 CPU_VIDALERT_L_R 1% 1 1/16W CPU_VIDALERT_L IN 65 98
VCC_118 402
B J21 VCC_119
D36
E15
VCC_054
VCC_055 VIDSCLK C37 98 CPU_VIDSCLK_R
MF-LF
R1311
B
J22 VCC_120 E16 VCC_056 5% 1
0 2 1/16W CPU_VIDSCLK
J24 VCC_121 VSS_NCTF0 A4 OUT 65 98
E18 VCC_057 VIDSOUT B37 98 CPU_VIDSOUT_R MF-LF 402
J25 VCC_122 VSS_NCTF1 B3
NCTF
E19 VCC_058
J27 VCC_123 VSS_NCTF2 AV39 R1312
E21 VCC_059 0
J28 VCC_124 VSS_NCTF3 AY37 5% 1 2 1/16W CPU_VIDSOUT 65 98
E22 BI
J30 VCC_060 MF-LF 402
VCC_125 E24
K15 VCC_061
VCC_126
SENSE LINES
E25 VCC_062 VCCSA_SENSE T2 CPU_VCCSA_SENSE OUT 69 98

K16 VCC_127 E27 VCC_063
K18 VCC_128 E28 VCC_064 VCC_SENSE A36 CPU_VCC_SENSE_P 65 98
K19 OUT
VCC_129 E30
K21 VCC_065 VSS_SENSE B36 CPU VCC SENSE N OUT 65 98
VCC_130 E31 VCC_066
E33 VCC_067 VCCIO_SENSE AB4 CPU_VCCIO_SENSE_P 68 98
OUT
E34 VCC_068 VSSIO_SENSE AB3 CPU_VCCIO_SENSE_N OUT 68 98
E35 VCC_069
F15 VCC_070 VCCAXG_SENSE L32 CPU_VAXG_SENSE_P OUT 65 98
VSSAXG_SENSE M32 CPU_VAXG_SENSE_N OUT 65 98
A SYNC MASTER=K62 ROSITA SYNC DATE=01/09/2011 A

PAGE TITLE
CPU POWER
DRAWING NUMBER SIZE

REVISION
R
10.1.0
13 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
OMIT
U1000 U1000
SANDY_BRIDGE SANDY_BRIDGE
LGA1155-SKT
LGA1155-SKT
AV11 VSS_181 (9 OF 10) VSS_271 G8
A17 VSS_001 ( 8 OF 10 ) VSS_091 AM27
AV14 VSS_182 VSS_272 H1
A23 VSS_002 VSS_092 AM3
AV17 VSS_183 VSS_273 H17
A26 VSS_003 VSS_093 AM30
AV3 VSS_184 VSS_274 H2
A29 VSS_004 VSS_094 AM36
AV35 VSS_185 VSS_275 H20
A35 VSS_005 VSS_095 AM37
AV38 VSS_186 VSS_276 H23
AA33 VSS_006 VSS_096 AM38
AV6 VSS_187 VSS_277 H26
AA34 VSS_007 VSS_097 AM39
AW10 VSS_188 VSS_278 H29
D
AA35
AA36
VSS_008
VSS_009
VSS_098
VSS_099
AM4
AM40
AW11
AW14
VSS_189 VSS_279 H33
H35
D
AA37 AM5 VSS_190 VSS_280
VSS_010 VSS_100 AW16 H37
AA38 AN10 VSS_191 VSS_281
VSS_011 VSS_101 AW36 H39
AA6 AN11 VSS_192 VSS_282
VSS_012 VSS_102 AW6 H5
AB5 AN14 VSS_193 VSS_283
VSS_013 VSS_103 AY11 H6
AC1 AN17 VSS_194 VSS_284
VSS_014 VSS_104 AY14 H9
AC6 AN19 VSS_195 VSS_285
VSS_015 VSS_105 AY18 J11
AD33 AN22 VSS_196 VSS_286
VSS_016 VSS_106 AY35 J17
VSS_017 VSS_107 AY4 J20
VSS_018 VSS_108
VSS
AY6 VSS_199 VSS_289 J23
AD39 VSS_019 VSS_109 AN30
AY8 VSS_200 VSS_290 J26
VSS
B10 VSS_201 VSS_291 J29
B13 VSS_202 VSS_292 J32
B14 VSS_203 VSS_293 K1
AE3 VSS_023 VSS_113 AN34
B17 VSS_204 VSS_294 K12
B23 VSS_205 VSS_295 K13
B26 VSS_206 VSS_296 K14
AF1 VSS_026 VSS_116 AN5
B29 VSS_207 VSS_297 K17
B32 VSS_208 VSS_298 K2
B35 VSS_209 VSS_299 K20
B38 VSS_210 VSS_300 K23
B6 VSS_211 VSS_301 K26
AF5 VSS_031 VSS_121 AP1
C11 VSS_212 VSS_302 K29
C12 VSS_213 VSS_303 K33
C17 VSS_214 VSS_304 K35
AG36 VSS_034 VSS_124 AP17
C20 K37
C AH2
AH3
VSS_035
VSS_036
VSS_125
VSS_126
AP22
AP25
C23
VSS_215
VSS_216
VSS_305
VSS_306 K39 C
C26 VSS_217 VSS_307 K5
AH33 VSS_037 VSS_127 AP27
C29 VSS_218 VSS_308 K6
C32 VSS_219 VSS_309 L10
C35 VSS_220 VSS_310 L17
C7 VSS_221 VSS_311 L20
C8 VSS_222 VSS_312 L23
D17 VSS_223 VSS_313 L26
D2 VSS_224 VSS_314 L29
AH8 VSS_044 VSS_134 AR11
D20 VSS_225 VSS_315 L8
AJ12 VSS_045 VSS_135 AR14
D23 VSS_226 VSS_316 M1
D26 VSS_227 VSS_317 M17
D29 VSS_228 VSS_318 M2
D32 VSS_229 VSS_319 M20
D37 VSS_230 VSS_320 M23
D39 VSS_231 VSS_321 M26
D4 VSS_232 VSS_322 M29
D5 VSS_233 VSS_323 M33
AK1 VSS_053 VSS_143 AT1
D9 VSS_234 VSS_324 M35
E11 VSS_235 VSS_325 M37
E12 VSS_236 VSS_326 M39
E17 VSS_237 VSS_327 M5
E20 VSS_238 VSS_328 M6
E23 VSS_239 VSS_329 M9
E26 VSS_240 VSS_330 N8
E29 VSS_241 VSS_331 P1
B AK32
AK33
VSS_061
VSS_062
VSS_151
VSS_152
AT25
AT27
E32
E36
VSS_242 VSS_332 P2
P36
B
AK34 AT28 VSS_243 VSS_333
VSS_063 VSS_153 E7 P38
VSS_064 VSS_154 E8 P40
VSS_065 VSS_155 F1 P5
VSS_066 VSS_156 F10 P6
VSS_067 VSS_157 F13 R33
VSS_068 VSS_158 F14 R35
VSS_069 VSS_159 F17 R37
VSS_070 VSS_160 F2 R39
VSS_071 VSS_161 F20 R8
VSS_072 VSS_162 F23 T1
VSS_073 VSS_163 F26 T5
AL11 AT38 VSS_254 VSS_344
VSS_074 VSS_164 F29 T6
VSS_075 VSS_165 F35 U8
VSS_076 VSS_166 F37 V1
VSS_077 VSS_167 F39 V2
VSS_078 VSS_168 F5 V33
VSS_079 VSS_169 F6 V34
VSS_080 VSS_170 F9 V35
VSS_081 VSS_171 G11 V36
VSS_082 VSS_172 G12 V37
AM1 AU1 VSS_263 VSS_353
VSS_083 VSS_173 G17 V38
VSS_084 VSS_174 G20 V39
VSS_085 VSS_175 G23 V40
VSS_086 VSS_176 G26 V5
A AM2
AM21
VSS_087
VSS_088
VSS_177
VSS_178
AU4
AU6
G29
VSS_267
VSS_268
VSS_357
VSS_358 W6 A
G34 VSS_269 VSS_359 Y5 PAGE TITLE
AM23 AU8
AM25
VSS_089
VSS_090
VSS_179
VSS_180 AV10
G7 VSS_270 VSS_360 Y8 CPU GROUNDS
DRAWING NUMBER SIZE
1156
1157 REVISION
SKT_MNT_HOLE R
1158 10.1.0
14 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
15 6 =PP3V3_S0_PCH_STRAPS
15 6 =PP3V3_S0_PCH_STRAPS 15 6 =PP3V3_S0_PCH_STRAPS
NOSTUFF NOSTUFF NOSTUFF

R15221 NOSTUFF R15261 R15271 R15281
1 1 1 1 1 NOSTUFF
1 NOSTUFF
1 1 10K R15231 R15241 R15251 10K 10K 10K
R1519 R1591 R1508 R1507 R1503 R1504 R1506 R1509
D 10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
5%
1/16W
MF LF
10K
5%
1/16W
10K
5%
1/16W
10K
5%
1/16W
5%
1/16W
MF LF
5%
1/16W
MF LF
5%
1/16W
MF LF
D
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 402 MF LF MF LF MF LF 402 402 402
MF LF MF LF MF LF MF LF MF LF MF LF MF LF MF LF
2 402 402 402
2 2 2
402 402 402 402 402 402 402 402
2 2 2
2 2 2 2 2 2 2 2
MINI_CLKREQ_L 15 33 100
PCH_GPIO0_BMBUSY_L 21 25 JTAG_T29_TDO 21 89 99
PCH_GPIO19_SATA1GP 18 25 JTAG_T29_TDI 21 89 99
JTAG_T29_TCK 21 25 89 99 PCH_GPIO36_SATA2GP 21 25
DP_AUXCH_ISOL 18 25 85 87 94
T29_SW_RESET_L 21 81 94
FW_PME_L 21 39 100
PCH_GPIO7_TACH3 21
BLC GPIO 6 21 94
NOSTUFF NOSTUFF PCH_GPIO49_SATA5GP 21 25
FW PWR EN 21 100
R15341 R15551
95 37 18 ENET MEDIA SENSE Multiplux with Mini FW MINI CLKREQ L 15 18 94 10K 10K
5% 5%
100 37 21 ENET_LOW_PWR 1/16W 1/16W
MF LF MF LF
402 402
2 2
1 1
R1510 R1511
10K 10K R15481
5% 5% 10K
1/16W 1/16W 5%
MF LF
402
2
MF LF
402
2
1/16W
MF LF
R1595
402
2 FW_MINI_CLKREQ_L 1
0 2 MINI_CLKREQ_L
94 18 15 15 33 100
5%
1/16W
MF-LF
NOSTUFF 402
R1596
0
C 1
5%
1/16W
2 FW_CLKREQ_L 39 100
C
MF-LF 15 6 =PP3V3_S5_PCH_STRAPS
15 6 =PP3V3 S0 PCH STRAPS 402 15 6 =PP3V3 S5 PCH STRAPS
NOSTUFF 1 NOSTUFF 1 NOSTUFF

NOSTUFF NOSTUFF R1520 R1538 R15351 R15391 R15151
R15761 R15751 R15741 R15731 R15721 R15701 R15431 4.7K 4.7K 10K 10K 10K
10K 10K 10K 10K 10K 10K 4.7K 5% 5% 5% 5% 5%
5% 5% 5% 5% 5% 5% 5% 1/16W 1/16W 1/16W 1/16W 1/16W
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W MF LF MF LF MF LF MF LF MF LF
MF LF MF LF MF LF MF LF MF LF MF LF MF LF 402 402 402 402 402
402 402 402 402 402 402 402
2 2 2 2 2
2 2 2 2 2 2 2
NOSTUFF
R15711 R15301 R15901 R15561
10K 10K 10K 10K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF LF MF LF MF LF MF LF
402 402 402 402 PM_BATLOW_L 19 46 100
PCH_SPKR 18
2 2 2 2
PCH_GPIO30_SUSWARN_L 19
PM_CLKRUN_L 19 46 48 100
ENET_CLKREQ_L 18 36 94
PCH_GPIO15 21 25
SDCARD_RESET 21 44 100 101
T29_CLKREQ_L 21 81 94 PCH_GPIO29_SLP_LAN_L 19
ENET_SW_RESET_L 21 36 94
PCH_GPIO24 21
PCH_GPIO70_TACH6 21 PCH_GPIO8 21
SMC_WAKE_SCI_L 18 21 46 100
PCH_GPIO71_TACH7 21 NOSTUFF
JTAG T29 TMS 18 89 99
HDA_SDOUT 18 56 94 R15171
New SP_DESCRIPTOR_OVERRIDE_L strap 10K
5%
1/16W
MF LF
402
2
93 25 10 CPU CFG<2>
93 25 10 CPU_CFG<16> 93 25 10 CPU_CFG<6> NOSTUFF
1
R1592
B 93 25 10
93 25 10
CPU_CFG<3>
CPU_CFG<1>
93 25 10 CPU_CFG<5>
10K
5%
B
1/16W
93 25 10 CPU_CFG<0> MF LF
402
2
NOSTUFF1 NOSTUFF 1
NOSTUFF1 NOSTUFF 1 NOSTUFF 1 NOSTUFF 1 R1500 1
R1585 R1586 R1587 R1588 R1521 R1541 1K 19 PCH_FDI_FSYNC<0>
1K 1K 1K 1K 1K 1K 5%
5% 5% 5% 5% 5% 5% 1/16W 19 PCH_FDI_FSYNC<1>
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W MF LF
MF LF MF LF MF LF MF LF MF LF MF LF 402
2
19 PCH_FDI_INT
402 402 402 402 402 402
2 2 2 2 2 2 PCH_FDI_LSYNC<1>
19
19 PCH FDI LSYNC<0>
NOSTUFF 1 NOSTUFF 1
These can be Placed close to J2500 and Only for debug access NOSTUFF NOSTUFF NOSTUFF R1568 R1569
R1565 1 R1566 1 R15671 1K 1K
1K 1K 1K 5% 5%
5% 5% 5% 1/16W 1/16W
1/16W 1/16W 1/16W MF LF MF LF
MF LF MF LF MF LF 402 402
402 402 402
2 2
2 2 2
REMOVE THESE PULL DOWN RESISTORS AFTER PROTO
10 CPU_FDI_FSYNC<0>
100 42 21 ODD PWR EN L
10 CPU_FDI_FSYNC<1>
10 CPU_FDI_INT
20 PCH_PCI_GNT3_L
CPU FDI LSYNC<1>
A 20
20
PCH_PCI_GNT2_L
PCH_PCI_GNT1_L
10
10 CPU FDI LSYNC<0> SYNC MASTER=K62 SIJI SYNC DATE=01/09/2011 A

PAGE TITLE
20 PCH_PCI_GNT0_L
PCH_INIT3V3_L
NOSTUFF 1 NOSTUFF 1 STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
21 NOSTUFF NOSTUFF 1 NOSTUFF 1 R1563 R1564
R1560 1 R1561 R1562 1K 1K
DRAWING NUMBER SIZE
NOSTUFF NOSTUFF
1K
5% 5%
1K 1K
5%
5%
1/16W
5%
1/16W Apple Inc. 051-8442 D
NOSTUFF1 NOSTUFF1 NOSTUFF 1 1 1 REVISION
1 R1553 R1554 R1512 1/16W 1/16W 1/16W MF LF MF LF
R1550 R1551 R1552 10K 10K 10K
MF LF
402
MF LF
402
MF LF
402
402
2 402
2 R
10.1.0
1K 10K 10K 5% 5% 5%
2 2 2
5% 5% 5% 1/16W 1/16W 1/16W NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/16W 1/16W 1/16W MF LF MF LF MF LF
MF LF MF LF MF LF 402
2 402
2 402
2 THE INFORMATION CONTAINED HEREIN IS THE
402
2
402
2
402
2 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
REMOVE THESE PULL DOWN RESISTORS AFTER PROTO I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
15 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE DECOUPLING

14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor) 10x 10UF and 10x 1UF CAPACITORS
PLACEMENT_NOTE (C1600-C1613):
65 50 16 13 6
=PPVCORE S0 CPU Place inside socket cavity
16 13 6
65 50
=PPVCORE_S0_CPU Place inside socket cavity
1 C1620 1 C1621 1 C1622 1 C1623 1 C1624 1 C1625 1 C1626 1 C1627 1 C1628 1 C1629 D
D 1 C1600
22UF
1 C1601
22UF
1 C1602
22UF
1 C1603
22UF
1 C1604
22UF
1 C1605
22UF
1 C1606
22UF
1 C1607
22UF
1 C1608
22UF
1 C1609
22UF
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V 603 603 603 603 603 603 603 603 603 603
CERM X5R CERM X5R CERM X5R CERM X5R CERM X5R CERM X5R CERM X5R CERM X5R CERM X5R CERM X5R
805 3 805 3 805 3 805 3 805 3 805 3 805 3 805 3 805 3 805 3
1 C1630 1 C1631 1 C1632 1 C1633 1 C1634 1 C1635 1 C1636 1 C1637 1 C1638 1 C1639
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
1
C1610 1
C1611 1
C1612 1
C1613 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
16V
2 X5R
22UF 22UF 22UF 22UF 402 402 402 402 402 402 402 402 402 402
20% 20% 20% 20%
6 3V 6 3V 6 3V 6 3V
2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R
805 3 805 3 805 3 805 3
BULK CAPS ON CPU VREG PAGE 72
CPU VCCIO DECOUPLING

C 8X 22UF 0805, 6X 10UF 0805 INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders C
13 11 10 6
65
=PPVCCIO_S0_CPU Place under socket cavity on secondary side.
1 C1650 1 C1651 1 C1652 1 C1653 1 C1654 1 C1655 1 C1656 1 C1657

22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20%
6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V
2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R
805 805 805 805 805 805 805 805
Place at edge of socket. BULK CAPS ON CPU VREG PAGE 72
1
C1660 1
C1661 1
C1662 1
C1663 1
C1664 1
C1665
10uF 10uF 10uF 10uF 10uF 10uF
20% 20% 20% 20% 20% 20%
6 3V 6 3V 6 3V 6 3V 6 3V 6 3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603
B 1
C1670
330UF-0.0045OHM B
20%
2 2V
POLY
CASE-D2-SM
Memory (CPU VCCDDR) DECOUPLING

6x 22uF 0805, 5x 1uF 0402. INTEL RECOMMENDATION 9X 22uF 0805
28 13 11 6
29
=PP1V5_S0_CPU_MEM Note: VCCSA decoupling is on regulator page
1 1 1 1 1 1 1 1 1 1 1
C1676 C1677 C1678 C1679 C1680 C1681 C1682 C1683 C1684 C1685 C1686
22uF 22uF 22uF 22uF 22uF 22uF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10%
6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 10V 10V 10V 10V 10V
2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805 402 402 402 402 402
PLL (CPU VCCSFR) DECOUPLING

A 2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 10x 10uF 0805
SYNC MASTER=K62 AARON SYNC DATE=N/A A
13 6 =PP1V8_S0_CPU_PLL PAGE TITLE
CPU NON-GFX DECOUPLING

DRAWING NUMBER SIZE
1 C1693 1 C1694 1 C1692 1 C1691 1 C1695 1 C1690 1 C1696 1 C1697
1UF 1UF 2.2UF 4.7UF 10UF 22uF 47UF 47UF REVISION
10% 10% 10% 10% 20% 20% 20% 20%
R
2
10V
X5R 2
10V
X5R 2
6 3V
X5R 2
6 3V
X5R CERM 2
6 3V
X5R 2
6 3V
CERM X5R 2
6 3V
X5R 2
6 3V
X5R 10.1.0
402 402 402 603 603 805 0805 0805
BULK CAPS ON VTT REG PAGE 78 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
16 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
VAXG DECOUPLING
INTEL RECOMMENDATION 6X22UF 0805,3X 4.7UF
Place inside socket cavity
65 50 13 6 =PPVAXG_S0_CPU
VAXG VAXG VAXG VAXG VAXG VAXG
1
C1704 1
C1705 1
C1706 1
C1707 1
C1708 1
C1709
22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20%
6 3V 6 3V 6 3V 6 3V 6 3V 6 3V
2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R 2 CERM X5R
805 3 805 3 805 3 805 3 805 3 805 3
OMIT VAXG VAXG

1
C1710 1
C1711 1
C1712
4.7UF 4.7UF 4.7UF
10% 10% 10%
6 3V 6 3V 6 3V
2 X5R CERM 2 X5R CERM 2 X5R CERM
603 603 603
C BULK CAPS ON CPU VREG PAGE 73 C
138S0586 1 CAP,4.7UF,10%,6.3V,0603 C1710 VAXG
113S0022 1 RES,0 OHM,5%,0603 C1710 NO_VAXG
R1750
0
6 =PP3V3_S0_PCH_VCCADAC 1 2
PP3V3_S0_PCH_VCCA_DAC_F 22 98
5% MAKE BASE=TRUE
1/16W MIN LINE WIDTH=0 4 MM
MF LF MIN NECK WIDTH=0 2 MM
402 VOLTAGE=3 3V
R1760
0
6 =PP1V05 S0 PCH VCCADPLL 1 2 PP1V05 S0 PCH VCCADPLLA F 22 98
MAKE BASE=TRUE
5% MIN LINE WIDTH=0 4MM
1/16W MIN NECK WIDTH=0 2MM
B MF LF
402
VOLTAGE=1 05V
B
R1765
0
1 2 PP1V05_S0_PCH_VCCADPLLB_F 22 98
MAKE BASE=TRUE
5% MIN LINE WIDTH=0 4MM
1/16W MIN NECK WIDTH=0 2MM
MF LF VOLTAGE=1 05V
402
A SYNC MASTER=K62 AARON SYNC DATE=11/30/2009 A

PAGE TITLE
GFX DECOUPLING & PCH PWR ALIAS

DRAWING NUMBER SIZE

REVISION
R
10.1.0
17 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
24 22 6 =PP1V05_S0_PCH_VCCIO_SATA
24 21 6 =PP3V3_S0_PCH 24 22 19 6 =PP1V05_S0_PCH_VCCIO_PCIE
1
94 LPC_R_AD<0> R1860 1 2 33 LPC_AD<0> PLACE THIS RESISTOR NEAR THE PCH PIN
R1890
R1830 1
BI 46 48 94
5% 1/16W MF LF 402
BR39 OMIT BK15 90.9
PCH_CLK32K_RTCX1 RTCX1 FWH0/LAD0 37.4
94 27 IN
PCH_CLK32K_RTCX2 BN39 RTCX2
U1800 FWH1/LAD1
94
BJ17
LPC_R_AD<1> R1861 1
5% 1/16W
2 33 LPC_AD<1>
MF LF 402
BI 46 48 94
1
1%
MF LF 1%
1/16W
94 27 OUT
COUGAR-POINT R1820 1/16W
OMIT
FWH2/LAD2 BJ20 LPC_R_AD<2> R1862 1 2 33 LPC_AD<2>
BI 46 48 94 10K
MF LF
PCIE_ENET_D2R_N J20 PERN1 SMBALERT*/GPIO11 BN49 PCH_GPIO11_SMBALERT_L
402
2
WLCSP
SYM 1 OF 10 FWH3/LAD3 BG20
5% 1/16W MF LF 402
5%
402
2
95 37 IN
PCIE_ENET_D2R_P L20 PERP1
U1800 18
94 LPC_R_AD<3> R1863 1 2 33 LPC_AD<3>

BI 46 48 94
1/16W
MF LF
95 37 IN
COUGAR-POINT SMBCLK BT47 SMBUS_PCH_CLK 49 97
RTC_RESET_L BT41 RTCRST* 5% 1/16W MF LF 402
PCIE_ENET_R2D_C_N F25 PETN1 OUT
100 27 18
FWH4/LFRAME* BG17 2
402 95 37 OUT WLCSP SMBDATA BR49 SMBUS_PCH_DATA
94 LPC_FRAME_R_L R1864 1 2 33 LPC_FRAME_L
OUT 46 48 94
95 37 PCIE_ENET_R2D_C_P F23 PETP1 BI 49 97
100 18 PCH_SRTCRST_L BN37 SRTCRST* 5% 1/16W MF LF 402 OUT SYM 2 OF 10

LDRQ0* BK17 TP LPC DREQ0 L
RTC
LPC
8
D 18 PCH INTRUDER L BM38 INTRUDER* LDRQ1*/GPIO23 BA20 T29 PWR EN 81 100

93 33
93 33
IN
IN
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
P20
R20
PERN2
PERP2
SML0ALERT*/GPIO60 BU49 SML_PCH_0_ALERT_L 18
D
BN41 SML0CLK BT51 SML_PCH_0_CLK 49 97
100 18 PCH_INTVRMEN_L INTVRMEN SERIRQ AV52 LPC_SERIRQ 46 48 93 33 PCIE_MINI_R2D_C_N C22 PETN2 OUT
BI OUT
A22 SML0DATA BM50 SML_PCH_0_DATA BI 49 97
93 33 OUT PCIE MINI R2D C P PETP2
94 18 HDA_BIT_CLK_R BU22 HDA_BCLK SATA0RXN AC56 SATA_HDD_D2R_N 42 93 93 39 PCIE_FW_D2R_N H17 PERN3 SML1ALERT*/PCHHOT*/GPIO74 BR46 SML_PCH_1_ALERT_L 18
IN IN
SATA0RXP AB55 SATA_HDD_D2R_P PCIE_FW_D2R_P J17 PERP3
SMBUS
IN 42 93 93 39 IN
BP23 AE46 E21 SML1CLK/GPIO58 BJ46 SML_PCH_1_CLK OUT 49 97
94 18 HDA_SYNC_R HDA_SYNC SATA0TXN SATA_HDD_R2D_C_N 42 93 93 39 PCIE_FW_R2D_C_N PETN3
AE44
OUT OUT
B21 SML1DATA/GPIO75 BK46 SML_PCH_1_DATA BI 49 97
SATA0TXP SATA HDD R2D C P OUT 42 93 93 39 OUT PCIE FW R2D C P PETP3
15 PCH SPKR BE56 SPKR
SATA1RXN AA53 SATA_SSD_D2R_N 42 93 8 TP_PCIE_D2R_PERN4 P17 PERN4
IN IN
SATA1RXP AA56 SATA_SSD_D2R_P TP_PCIE_D2R_PERP4 M17 PERP4
IHDA
94 18 HDA_RST_R_L BC22 HDA_RST*
IN 42 93 8 IN
SATA1TXN AG49 SATA SSD R2D C N 42 93 8 TP PCIE R2D PETN4 F18 PETN4
OUT OUT
SATA1TXP AG47 SATA SSD R2D C P 42 93 8 TP PCIE R2D PETP4 E17 PETP4
HDA_SDIN0 BD22 OUT OUT
94 56 IN HDA_SDIN0
8 TP_HDA_SDIN1 BF22 HDA_SDIN1 SATA2RXN AL50 SATA_ODD_D2R_N 42 93 99 89 PCIE_T29_D2R_N<0> N15 PERN5
IN IN
TP_HDA_SDIN2 BK22 HDA_SDIN2 SATA2RXP AL49 SATA_ODD_D2R_P PCIE_T29_D2R_P<0> M15 PERP5
PEG
8 42 93 99 89
BJ22 AL56
IN IN
B17 CLKOUT_PEG_A_N AG8 PEG_CLK100M_N OUT 9
8 TP HDA SDIN3 HDA_SDIN3 SATA2TXN SATA ODD R2D C N 42 93 99 89 PCIE T29 R2D C N<0> PETN5
CLKOUT_PEG_A_P AG9
OUT OUT PEG_CLK100M_P
SATA2TXP AL53 SATA ODD R2D C P 42 93 99 89 PCIE T29 R2D C P<0> C16 PETP5 OUT 9
OUT OUT
94 18 HDA_SDOUT_R BT23 HDA_SDO
SATA3RXN AN46 TP_SATA_D_D2RN 8 99 89 PCIE_T29_D2R_N<1> J15 PERN6
IN
AN44 L15 CLKOUT_DMI_N P31 DMI_CLK100M_CPU_N OUT 11 93
BC25 SATA3RXP TP_SATA_D_D2RP 8 99 89 PCIE_T29_D2R_P<1> PERP6
CLKOUT_DMI_P R31
JTAG_T29_TMS IN DMI_CLK100M_CPU_P
99 89 15 HDA_DOCK_EN*/GPIO33 AN56 A16 OUT 11 93
BA25 SATA3TXN TP SATA D R2D CN 8 99 89 OUT PCIE T29 R2D C N<1> PETN6
SATA
95 37 15 ENET_MEDIA_SENSE HDA_DOCK_RST*/GPIO13 AM55 B15
SATA3TXP TP SATA D R2D CP 8 99 89 OUT PCIE T29 R2D C P<1> PETP6
AN49 J12 CLKOUT_DP_N N56 TP_PCH_CLKOUT_DPN OUT 8
BA43 SATA4RXN TP_SATA_E_D2RN 8 99 89 PCIE_T29_D2R_N<2> PERN7
CLKOUT_DP_P M55
XDP_PCH_TCK IN TP_PCH_CLKOUT_DPP
94 25 JTAG_TCK AN50 H12 OUT 8
TP SATA E D2RP PCIE T29 D2R P<2>
PCI-E*
SATA4RXP 8 99 89 IN PERP7
94 25 XDP PCH TMS BC50 JTAG_TMS JTAG SATA4TXN AT50 TP SATA E R2D CN 8 99 89 PCIE T29 R2D C N<2> F15 PETN7
OUT
FROM CLK BUFFER

SATA4TXP AT49 TP SATA E R2D CP PCIE T29 R2D C P<2> F13 PETP7 CLKIN_DMI_N P33 PCH CLK100M DMI N
94 25 XDP_PCH_TDI BC52 JTAG_TDI
8 99 89 OUT IN 26 93
CLKIN_DMI_P R33
C 94 25 XDP_PCH_TDO BF47 JTAG_TDO
SATA5RXN
SATA5RXP
AT46
AT44
TP_SATA_F_D2RN
TP SATA F D2RP
8
8
99 89
99 89
IN PCIE_T29_D2R_N<3>
PCIE T29 D2R P<3>
H10
J10
PERN8
PERP8
PCH_CLK100M_DMI_P IN 26 93
C
IN
SATA5TXN AV50 TP SATA F R2D CN 8 99 89 PCIE T29 R2D C N<3> B13 PETN8 CLKIN_DOT_96N BD38 PCH CLK96M DOT N 26 93
OUT IN
SATA5TXP AV49 TP_SATA_F_R2D_CP 8 99 89 PCIE_T29_R2D_C_P<3> D13 PETP8 CLKIN_DOT_96P BF38 PCH_CLK96M_DOT_P 26 93
OUT IN
55 48 SPI_CLK_R R1822 1 2 22 94 SPI_CLK_1_R AR54 SPI_CLK TOTAL ETCH LENGTH=5 MM

94 OUT
SATAICOMPO AJ53 94 PCH_SATAICOMP 93 37 PCIE_CLK100M_ENET_N AE6 CLKOUT_PCIE0N
5% 1/16W MF LF 402
AT57 PLACE R1830 AT BALL AJ53 OUT
CLKIN_SATA_N AF55 PCH CLK100M SATA N IN 26 93
SATAICOMPI AJ55 AC6
TIE THEM TOGETHER VERY CLOSE TO PINS PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
94 48 SPI_CS0_R_L SPI_CS0* 93 37 PCIE_CLK100M_ENET_P CLKOUT_PCIE0P
OUT OUT
CLKIN_SATA_P AG56 PCH_CLK100M_SATA_P
SPI
IN 26 93
TP_SPI_CS1_L AR56 SPI_CS1* 93 33 PCIE_CLK100M_MINI_N AA5 CLKOUT_PCIE1N

SATALED* BF57 PCH_SATALED_L OUT
18 42 W5
PCIE_CLK100M_MINI_P CLKOUT_PCIE1P
SPI MOSI R R1823 22 SPI MOSI 1 R AU53 93 33 OUT
55 48 1 2 SPI_MOSI REFCLK14IN AN8 PCH CLK14P3M REFCLK 26 94
SATA0GP/GPIO21 BC54
94 OUT DP_AUXCH_ISOL IN
5% 1/16W MF LF 402 15 25 85 87 94 AB12
AT55 =PP1V05_S0_PCH 6 24 80 93 39 OUT PCIE_CLK100M_FW_N CLKOUT_PCIE2N
94 55 48 IN SPI_MISO SPI_MISO SATA1GP/GPIO19 AY52 PCH_GPIO19_SATA1GP 15 25 AB14
93 39 PCIE_CLK100M_FW_P CLKOUT_PCIE2P
CLKIN_PCILOOPBACK BD15
OUT PCH_CLK33M_PCIIN IN 27 94
1
R1831 94 15 FW_MINI_CLKREQ_L AV43 PCIECLKRQ2*/GPIO20
DOES THIS NEED LENGTH MATCH???
L_BKLTCTL AG12 TP_PCH_L_BKLTCTL 49.9 IN

8
1%
L_BKLTEN AG18 TP_PCH_L_BKLTEN 8 1/16W 99 89 OUT PCIE_CLK100M_T29_N AB9 CLKOUT_PCIE3N XTAL25_IN AJ3 PCH_CLK25M_XTALIN IN 27 80 94
MF LF
L_VDD_EN AG17 TP_PCH_L_VDD_EN 8 402
2 99 89 OUT PCIE_CLK100M_T29_P AB8 CLKOUT_PCIE3P XTAL25_OUT AJ5 PCH_CLK25M_XTALOUT OUT 27 94
SATA3COMPI AE54 8 OUT TP_PCIE_CLK100M_PE4N Y9 CLKOUT_PCIE4N

TOTAL ETCH LENGTH=5 MM TOTAL ETCH LENGTH=5 MM
SATA3RCOMP0 AE52 94 PCH_SATA3COMP 8 OUT TP_PCIE_CLK100M_PE4P Y8 CLKOUT_PCIE4P XCLK_RCOMP AL2 94 PCH_XCLK_RCOMP
PLACE R1831 AT BALL AE52 PLACE R1890 AT BALL AL2
SATA3RBIAS AC52 94 PCH_SATA3RBIAS AF3
8 OUT TP_PCIE_CLK100M_PE5N CLKOUT_PCIE5N
TP_PCIE_CLK100M_PE5P AG2 CLKOUT_PCIE5P CLKOUTFLEX0/GPIO64 AT9 DP_GPU_T29_SEL
CLOCK
8 OUT 61 84 94
FLEX
98 27 22 19 PP3V3_G3H_RTC R18321 94 36 15 ENET_CLKREQ_L BL54 PCIECLKRQ5*/GPIO44
CLKOUTFLEX1/GPIO65 BA5
=PP3V3_S0_SATALED 750 IN TP_PCH_GPIO65_CLKOUTFLEX1
42 6
1% AE12
1/16W TP_DMI_MIDBUS_CLK100M_PEGB1N CLKOUT_PEG_B_N
MF LF AE11
1 1
402
2
TP DMI MIDBUS CLK100M PEGB1P CLKOUT_PEG_B_P CLKOUTFLEX2/GPIO66 AW5 TP PCH GPIO66 CLKOUTFLEX2
R1802 R1803 PLACE R1832 AT BALL AC52
20K 20K
CLKOUTFLEX3/GPIO67 BA2
B 5%
1/16W
MF LF
5%
1/16W
MF LF
R18501
TP_PCH_GPIO67_CLKOUTFLEX3
B
402 402 10K
2 2
5% CLKOUT_ITPXDP_N R52 ITPXDP_CLK100M_N 18 25 93
1/16W
MF LF CLKOUT_ITPXDP_P N52 ITPXDP_CLK100M_P 18 25 93
402
1 1 2
R1800 R1801 CLKIN_GND0_N W53 PCH_CLKIN_GNDN0
390K 1M
5% 5% CLKIN_GND0_P V52 PCH_CLKIN_GNDP0
1/16W 1/16W
MF LF MF LF RTC_RESET_L 18 27 100
402 402 CLKIN_GND1_N R27 PCH CLKIN GNDN1
2 2 PCH_SRTCRST_L 18 100
CLKIN_GND1_P P27 PCH_CLKIN_GNDP1
PCH_INTRUDER_L 18
PCH INTVRMEN L 18 100 CL_CLK1 BA50 TP PCH CL CLK1 8

NOSTUFF
PCH SATALED L 18 42
R1840 CL_DATA1 BF50 TP_PCH_CL_DATA1 8
C1802 1 1
C1803 0
1UF 1UF 93 25 18 ITPXDP CLK100M N 1 2 ITPCPU CLK100M N 11 93
CL_RST1* BF49 TP_PCH_CL_RST1 8
10% 10%
10V 10V 5%
X5R 2 2 X5R 1/16W NOSTUFF
MF LF
402 402
R1841
R18721
402 1
0 R1873
R18701
1
93 25 18 ITPXDP CLK100M P 1 2 ITPCPU CLK100M P 11 93 R1871 10K 10K
5% 10K 10K 5% 5%
1/16W 5% 5% 1/16W 1/16W
MF LF 1/16W 1/16W MF LF MF LF
MF LF MF LF 402
402
402 402
2 2 402
2 2
PLACE THESE 33 OHM RESISTORS CLOSE TO PCH (MIN 500MIL)

24 21 19 6 =PP3V3_S5_PCH
R1810
33
94 18 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK OUT 56 94
A PLACE R1880 CLOSE TO R1813

5%
1/16W
MF LF
402 R1811 SYNC MASTER=K62 SIJI SYNC DATE=01/09/2011 A
33 1 1 1 PAGE TITLE
R1853 R1854 R1855
R1880
0
94 18 HDA_SYNC_R 1
5%
2 HDA_SYNC OUT 56 94
10K
5%
10K
5%
10K
5%
PCH SATA/PCIE/CLK/LPC/SPI
94 18 HDA_SDOUT_R 1 2 SPI_DESCRIPTOR_OVERRIDE_L OUT 46 100 1/16W 1/16W 1/16W 1/16W DRAWING NUMBER SIZE
MF LF
5% R1812 402 NOSTUFF
MF LF MF LF MF LF
051-8442 D
1/16W 33 2 402 2 402 2 402 Apple Inc.
MF LF
402
94 18 HDA_RST_R_L 1 2 HDA_RST_L OUT 56 94
SMC_WAKE_SCI_L
R1895 REVISION
100 46 21 15 R
NOSTUFF
5%
1/16W
1
0
2 PCH_GPIO11_SMBALERT_L
10.1.0
MF LF
402 R1813 5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/16W
33 MF LF THE INFORMATION CONTAINED HEREIN IS THE
94 18 HDA_SDOUT_R 1 2 HDA_SDOUT OUT 15 56 94 402 18 SML_PCH_0_ALERT_L PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
5%
1/16W
MF LF
18 SML_PCH_1_ALERT_L I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
18 OF 110
402 SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_S5_PCH 6 18 19 21 24
=PP1V05_S0_PCH_VCCIO_PCIE 6 18 22 24
1
R1905 1
10K R1900
5% 49.9
1/16W 1%
MF LF 1/16W
402 MF LF
2
2
402 OMIT OMIT
D33 C42 J57 SDVO_TVCLKINN U9
93 10 IN DMI_N2S_N<0>
A36
DMI0RXN U1800 FDI_RXN0
F45
TP_PCH_FDI_RX_N<0> 8 TP_PCH_RESERVE_0
U43
RESERVED_0 U1800 TP_SDVO_TVCLKINN 8
93 10 IN DMI_N2S_N<1> DMI1RXN COUGAR-POINT FDI_RXN1 TP_PCH_FDI_RX_N<1> 8 TP_PCH_RESERVE_1 RESERVED_1 COUGAR-POINT SDVO_TVCLKINP U8 TP_SDVO_TVCLKINP 8
WLCSP
D 93 10
93 10
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
B37
E37
DMI2RXN
DMI3RXN
SYM 3 OF 10
FDI_RXN2
FDI_RXN3
H41
C46
TP_PCH_FDI_RX_N<2>
TP_PCH_FDI_RX_N<3>
8
8
TP_PCH_RESERVE_2
TP_PCH_RESERVE_3
M49
M50
RESERVED_2
RESERVED_3
WLCSP
SYM 4 OF 10 SDVO_STALLN U5 TP SDVO STALLN 8 D
B45 R50 SDVO_STALLP W3 TP_SDVO_STALLP 8
B33 FDI_RXN4 TP_PCH_FDI_RX_N<4> 8 TP_PCH_RESERVE_4 RESERVED_4
93 10 IN DMI_N2S_P<0> DMI0RXP B47 Y41
B35 FDI_RXN5 TP PCH FDI RX N<5> 8 TP PCH RESERVE 5 RESERVED_5 SDVO_INTN T3 TP SDVO INTN 8
93 10 DMI_N2S_P<1> DMI1RXP J43 H50 SDVO_INTP U2
IN TP PCH FDI RX N<6> TP PCH RESERVE 6 TP SDVO INTP
C36 FDI_RXN6 8 RESERVED_6 8
93 10 IN DMI_N2S_P<2> DMI2RXP M43 U44
F38 FDI_RXN7 TP PCH FDI RX N<7> 8 TP PCH RESERVE 7 RESERVED_7
93 10 IN DMI_N2S_P<3> DMI3RXP U46
B43 TP_PCH_RESERVE_8 RESERVED_8 SDVO_CTRLCLK AL15 TP_DP_IG_B_DDC_CLK 8
FDI_RXP0 TP_PCH_FDI_RX_P<0> 8
U50
J36 F43 TP_PCH_RESERVE_9 RESERVED_9 SDVO_CTRLDATA AL17 TP_DP_IG_B_DDC_DATA 8
93 10 OUT DMI S2N N<0> DMI0TXN FDI_RXP1 TP PCH FDI RX P<1> 8 R44
P38 J41 TP_PCH_RESERVE_10 RESERVED_10
93 10 OUT DMI S2N N<1> DMI1TXN FDI_RXP2 TP PCH FDI RX P<2> 8 U49 DDPB_AUXN R9 TP DP IG B AUX N 8
H38 D47 TP_PCH_RESERVE_11 RESERVED_11
93 10 OUT DMI_S2N_N<2> DMI2TXN FDI_RXP3 TP_PCH_FDI_RX_P<3> 8 AB44 DDPB_AUXP R8 TP_DP_IG_B_AUX_P 8
M41 A46 TP_PCH_RESERVE_12 RESERVED_12
93 10 OUT DMI_S2N_N<3> DMI3TXN FDI_RXP4 TP_PCH_FDI_RX_P<4> 8 AB49 DDPB_HPD T1 TP_DP_IG_B_HPD 8
TP PCH RESERVE 13 RESERVED_13
DMI
FDI
C49
DIGITAL DISPLAY INTERFACE

H36 FDI_RXP5 TP_PCH_FDI_RX_P<5> 8 E52 R12
93 10 OUT DMI S2N P<0> DMI0TXP H43 TP PCH RESERVE 14 RESERVED_14 DDPB_0N TP DP IG B MLN<0> 8
R38 FDI_RXP6 TP_PCH_FDI_RX_P<6> 8 H52 R14 EXTERNAL DP
93 10 OUT DMI S2N P<1> DMI1TXP P43 TP PCH RESERVE 15 RESERVED_15 DDPB_0P TP DP IG B MLP<0> 8
J38 FDI_RXP7 TP_PCH_FDI_RX_P<7> 8 F53 M12
93 10 OUT DMI_S2N_P<2> DMI2TXP TP_PCH_RESERVE_16 RESERVED_16 DDPB_1N TP_DP_IG_B_MLN<1> 8
93 10 DMI_S2N_P<3> P41 DMI3TXP TP_PCH_RESERVE_17 J55 RESERVED_17 DDPB_1P M11 TP_DP_IG_B_MLP<1> 8

OUT
FDI_INT H46 PCH FDI INT OUT 15
L56 K8
TP_PCH_RESERVE_18 RESERVED_18 DDPB_2N TP_DP_IG_B_MLN<2> 8
A32 H8
PCH_DMI2RBIAS
94 DMI2RBIAS FDI_FSYNC0 B51 PCH_FDI_FSYNC<0> OUT 15 TP_PCH_RESERVE_19 K46 RESERVED_19 DDPB_2P TP_DP_IG_B_MLP<2> 8
PLACE R1920 AT BALL A32
FDI_FSYNC1 C52 PCH_FDI_FSYNC<1> OUT 15 TP_PCH_RESERVE_20 Y50 RESERVED_20 DDPB_3N M3 TP_DP_IG_B_MLN<3> 8
1 TP_PCH_RESERVE_21 AB50 RESERVED_21 DDPB_3P L5 TP_DP_IG_B_MLP<3>
R1920 94 PCH_DMI_COMP E31 DMI_ZCOMP FDI_LSYNC0 E49 PCH_FDI_LSYNC<0> 15
8
750 SHORT THESE TWO PINS VERY NEAR THE PINS

OUT TP PCH RESERVE 22 L53 RESERVED_22
1% PLACE THE RESISTOR VERY CLOSE TO COMMON POINT
B31 DMI_IRCOMP FDI_LSYNC1 D51 PCH_FDI_LSYNC<1> 15
1/16W PLACE R1900 AT BALL E31 OUT TP PCH RESERVE 23 Y44 RESERVED_23 DDPC_CTRLCLK AL12 TP DP IG C CTRL CLK 8
MF LF TOTAL ETCH LENGTH=5 MM G56
2 402 TP_PCH_RESERVE_24 RESERVED_24 DDPC_CTRLDATA AL14 TP_DP_IG_C_CTRL_DATA 8
SYSTEM POWER
100 46 27 25 PM_SYSRST_L BE52 SYS_RESET* WAKE* BC44 PCIE_WAKE_L 19 33 36 79 100 TP_PCH_RESERVE_25 AB46 RESERVED_25
IN IN
DDPC_AUXN U12 TP DP IG C AUX N 8
MANAGEMENT
TP_PCH_RESERVE_26 K49 RESERVED_26
100 64 32 PM SYS PWRGD BJ53 SYS_PWROK CLKRUN*/GPIO32 BC56 PM CLKRUN L 15 46 48 100 DDPC_AUXP U14 TP DP IG C AUX P 8
IN BI TP_PCH_RESERVE_27 K50 RESERVED_27
BJ38 M48 DDPC_HPD N2 TP DP IG C HPD 8
100 64 21 IN PM_PCH_PWRGD PWROK TP_PCH_RESERVE_28 RESERVED_28
C 100 11 OUT PM_MEM_PWRGD BG46 DRAMPWROK SUS_STAT*/GPIO61 BN54 LPC_PWRDWN_L OUT 46 48 100
DDPC_0N
DDPC_0P
J3
L2
TP_DP_IG_C_MLN<0>
TP DP IG C MLP<0>
8
8
C
BT37 INTERNAL DP
100 19 IN PM DSW PWRGD DPWROK SUSCLK/GPIO62 BA47 PM CLK32K SUSCLK R OUT 9 94 100 DDPC_1N G4 TP DP IG C MLN<1> 8
DDPC_1P G2 TP_DP_IG_C_MLP<1> 8
100 64 PM_ASW_PWRGD BC46 APWROK SLP_S5*/GPIO63 BH50 PM_SLP_S5_L 5 46 47 63 100
IN OUT
DDPC_2N F5 TP_DP_IG_C_MLN<2> 8
100 27 19 PM_RSMRST_PCH_L BK38 RSMRST* SLP_S4* BN52 PM_SLP_S4_L 5 32 46 47 63 100 DDPC_2P F3 TP_DP_IG_C_MLP<2> 8
IN OUT
DDPC_3N E2 TP_DP_IG_C_MLN<3> 8
15 PCH_GPIO30_SUSWARN_L BU46 SUSWARN*/SUSPWRDNACK/GPIO30 SLP_S3* BM53 PM_SLP_S3_L 5 26 32 36 46 47 63 100
OUT
DDPC_3P E4 TP_DP_IG_C_MLP<3> 8
100 46 25 PM_PWRBTN_L BT43 PWRBTN* SLP_A* BC41 TP_PM_SLP_A_L

IN
KEEPING TP IF NEED TO USE IT LATER
BG43 DDPD_CTRLCLK AL9 TP DP IG D CTRL CLK 8
19 PCH_GPIO31_ACPRESENT GPIO31 TP23 J25 TP_PCH_TP23
IN
DDPD_CTRLDATA AL8 TP_DP_IG_D_CTRL_DATA 8
100 46 15 PM_BATLOW_L AV46 BATLOW*/GPIO72 PMSYNCH F55 PM_SYNC 11 100 8 TP_CRT_IG_BLUE AM1 CRT_BLUE
IN OUT
AN2 DDPD_AUXN R6 TP_DP_IG_D_AUXN 8
BJ48 8 TP_CRT_IG_GREEN CRT_GREEN
PCH_RI_L RI* SLP_LAN*/GPIO29 BH49 PCH_GPIO29_SLP_LAN_L 15
AN6 DDPD_AUXP N6 TP_DP_IG_D_AUXP 8
8 TP_CRT_IG_RED CRT_RED
DDPD_HPD M1 TP_DP_IG_D_HPD 8
CRT
1 DF_TVS R47 PCH_DF_TVS 19 100 AW3 B5
R1909 8 TP_CRT_IG_DDC_CLK CRT_DDC_CLK DDPD_0N TP_DP_IG_D_MLN<0> 8
10K 8 TP_CRT_IG_DDC_DATA AW1 CRT_DDC_DATA DDPD_0P D5 TP_DP_IG_D_MLP<0> 8
5%
1/16W
DDPD_1N D7 TP_DP_IG_D_MLN<1> 8
MF LF
DSWVRMEN BR42 PCH_DSWVRMEN 19 100 AR4 C6
402
2 8 TP_CRT_IG_HSYNC CRT_HSYNC DDPD_1P TP_DP_IG_D_MLP<1> 8
BD43 AR2 C9
SLP_SUS* TP_PCH_SLP_SUS_L 8 TP_CRT_IG_VSYNC CRT_VSYNC DDPD_2N TP_DP_IG_D_MLN<2> 8
DDPD_2P B7 TP_DP_IG_D_MLP<2> 8
SUSACK* BP45 TP PCH SUSACK L AT3 B11
PCH_DAC_IREF DAC_IREF DDPD_3N TP_DP_IG_D_MLN<3> 8
AM6 CRT_IRTN DDPD_3P E11 TP_DP_IG_D_MLP<3> 8
1
R1951
1K
5%
1/16W
MF LF
B 2 402
PLACE CLOSE TO U1800 PIN
B
PP3V3_G3H_RTC 18 22 27 98
1
R1915 R1990
0
390K 100 27 19 PM_RSMRST_PCH_L 2 1 PM_DSW_PWRGD 19 100
5%
1/16W 5%
MF LF 1/16W =PP1V8 S0 PCH 6
402 MF-LF
2 402
=PP3V3 S5 PCH 6 18 19 21 24
1
R1981
=PP3V3 S5 PCH 6 18 19 21 24
1
2.2K
PCH_DSWVRMEN 19 100 R1925 5%
1/16W
1K MF LF
1% 402
1/16W 2
1
R1961 MF LF
402
10K 2
5% R1980
1/16W 4.7K
MF LF 100 19 PCH_DF_TVS 2 1 CPU_PROC_SEL 11 100
402
2 5%
NOSTUFF 1/16W
MF LF
R1960 402
2
0 1
PCIE_WAKE_L 19 33 36 79 100
100 47 46 SMC_ADAPTER_EN PCH_GPIO31_ACPRESENT 19
5%
A 1/16W
MF-LF
402
A
PAGE TITLE
PCH DMI/FDI/GRAPHICS
DRAWING NUMBER SIZE

REVISION
R
10.1.0
19 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
BF15 USBP0N BF36
8 TP_PCI_AD<0>
BF17
AD0 U1800 USB_HUB1_UP_N BI 34 95
8 TP_PCI_AD<1> AD1 COUGAR-POINT USBP0P BD36 USB_HUB1_UP_P BI 34 95

USB HUB 1
8 TP_PCI_AD<2> BT7 AD2 WLCSP
BT13 SYM 5 OF 10 USBP1N BC33 TP_USB_1N BI 8
8 TP PCI AD<3> AD3
BG12 USBP1P BA33 TP_USB_1P BI 8
Unused
8 TP_PCI_AD<4> AD4
8 TP_PCI_AD<5> BN11 AD5 USBP2N BM33 TP_USB_2N 8
BI
8 TP_PCI_AD<6> BJ12 AD6 USBP2P BM35 TP_USB_2P 8
Unused
BI
D 8
8
TP_PCI_AD<7>
TP_PCI_AD<8>
BU9
BR12
AD7
AD8
USBP3N BT33 TP USB 3N BI 8 D
BJ3 USBP3P BU32 TP_USB_3P BI 8
Unused
8 TP_PCI_AD<9> AD9
8 TP PCI AD<10> BR9 AD10 USBP4N BR32 TP USB 4N 8
BI Unused
8 TP PCI AD<11> BJ10 AD11 USBP4P BT31 TP USB 4P 8
BI
8 TP PCI AD<12> BM8 AD12
BF3 USBP5N BN29 TP_USB_5N BI 8
8 TP_PCI_AD<13> AD13 Unused
BN2 USBP5P BM30 TP_USB_5P BI 8
8 TP_PCI_AD<14> AD14
8 TP_PCI_AD<15> BE4 AD15 USBP6N BK33 TP_USB_6N 8
BI
BE6 Unused
8 TP_PCI_AD<16> AD16 USBP6P BJ33 TP_USB_6P BI 8
8 TP_PCI_AD<17> BG15 AD17

BC6 USBP7N BF31 TP_USB_7N BI 8
8 TP PCI AD<18> AD18 Unused
BT11 USBP7P BD31 TP_USB_7P BI 8
8 TP PCI AD<19> AD19
8 TP PCI AD<20> BA14 AD20 USBP8N BN27 USB HUB2 UP N 35 95
BI
BL2 USB HUB 2
8 TP_PCI_AD<21> AD21 USBP8P BR29 USB_HUB2_UP_P BI 35 95
8 TP_PCI_AD<22> BC4 AD22

BL4 USBP9N BR26 USB CAMERA N BI 44 95
BC2 USBP9P BT27 USB CAMERA P BI 44 95
USB CAMERA
8 TP_PCI_AD<25> BM13 AD25 USBP10N BK25 TP_USB_10N 8
BI
BA9 Unused
8 TP_PCI_AD<26> AD26 USBP10P BJ25 TP_USB_10P BI 8
8 TP PCI AD<27> BF9 AD27 =PP3V3 S5 PCH GPIO 6

BA8 USBP11N BJ31 TP_USB_11N BI 8
8 TP PCI AD<28> AD28 Unused
USBP11P BK31 TP_USB_11P
USB
BI 8
TP_PCI_AD<29> BF8 AD29 1 1
8
R2061 1 1PRODUCTION R2068
8 TP_PCI_AD<30> AV17 AD30 USBP12N BF27 TP_USB_12N 8 10K R2063 R2065 10K
BI
BK12 Unused 5% 10K 10K 5%
8 TP_PCI_AD<31> AD31 USBP12P BD27 TP_USB_12P BI 8 1/16W 5% 5% 1/16W
MF LF 1/16W 1/16W MF LF
402 MF LF MF LF
8 TP PCI C BE L<0> BN4 C/BE0* USBP13N BJ27 TP USB 13N 8
2
402 402
2 402
BI 2 2
BP7 Unused
USBP13P BK27 R20601
C 8
8
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2> BG2
C/BE1*
C/BE2*
TP_USB_13P BI 8
10K
5%
R2062 1
10K
5%
R2064 1
R2066
10K
1
C
45 20 6 =PP3V3_S0_PCH_GPIO 8 TP_PCI_C_BE_L<3> BP13 C/BE3* USBRBIAS* BP25 94 PCH_USB_RBIAS 1/16W 1/16W 10K 5%
TIE TRACES TOGETHER CLOSE TO PINS MF LF MF LF 5% 1/16W
BK10 USBRBIAS BM25 402 402 1/16W MF LF
R2010 10K 1 2 PCI_INTA_L PIRQA* PLACE THE RESISTOR CLOSE TO COMMON POINT
2 2
MF LF 402
2
5% 1/16W MF LF 402 BJ5 402
R2011 10K 1 2 PCI_INTB_L PIRQB* 2
5% 1/16W MF LF 402 BM15 BM43
R2012 10K PCI_INTC_L AP_PWR_EN
PCI
1 2 PIRQC* OC0*/GPIO59 25 33 100
5% 1/16W MF LF 402 BP5 BD41
R2013 10K 1 2 PCI_INTD_L PIRQD* OC1*/GPIO40 USB_HUB_SOFT_RESET_L 25 34 100
5% 1/16W MF LF 402 BG41
BG5 OC2*/GPIO41 T29_DP_PORTA_PWR_EN 25 83 94 100
R2015 10K 1 2 94 PCI_REQ0_L REQ0* BK43
5% 1/16W MF LF 402 BT5 OC3*/GPIO42 ENET_PWR_EN 25 36 100
R2016 10K 1 2 94 PCI_REQ1_L REQ1*/GPIO50 BP43
5% 1/16W MF LF 402 BK8 OC4*/GPIO43 T29 DP PORTB PWR EN 25 83 94
94 20 PCI_REQ2_L REQ2*/GPIO52 BJ41
AV11 OC5*/GPIO9 SDCONN_STATE_CHANGE 25 45 100
R2018 10K 1 2 PCI_REQ3_L REQ3*/GPIO54 BT45
5% 1/16W MF LF 402 OC6*/GPIO10 PCH_GPIO10_OC6_L 25
15 PCH_PCI_GNT0_L BA15 GNT0* OC7*/GPIO14 BM45 PCH_GPIO14_OC7_L 25
15 PCH_PCI_GNT1_L AV8 GNT1*/GPIO51

15 PCH_PCI_GNT2_L BU12 GNT2*/GPIO53
15 PCH_PCI_GNT3_L BE2 GNT3*/GPIO55 1
R2070
R2030 10K 1 2 100 51 USE_HDD_OOB_L BN9 PIRQE*/GPIO2 22.6
5% 1/16W MF LF 402 AV9 1%
100 61 AUD_IP_PERIPHERAL_DET PIRQF*/GPIO3 1/16W
BT15 MF LF
R2031 10K 1 2 94 87 85 T29_MCU_INT_L PIRQG*/GPIO4 402
2
5% 1/16W MF LF 402 BR4
100 62 AUD_I2C_INT_L PIRQH*/GPIO5
8 TP_PCI_RESET_L AV14 PCIRST*

PLACE R2070 AT BALL BM25
R2020 10K 1 2 PCI_SERR_L BR6 SERR*
5% 1/16W MF LF 402 BM3
R2021 10K 1 2 PCI_PERR_L PERR*
5% 1/16W MF LF 402
R2022 10K 1 2 PCI_IRDY_L BF11 IRDY*
5% 1/16W MF LF 402 BH8
B R2023 10K 1 2
8 TP_PCI_PAR
PCI_DEVSEL_L BH9
PAR
DEVSEL*
B
5% 1/16W MF LF 402 BC11
R2024 10K 1 2 PCI_FRAME_L FRAME*
5% 1/16W MF LF 402
R2027 10K 1 2 PCI_PLOCK_L BA17 PLOCK*
5% 1/16W MF LF 402
R2025 10K 1 2 PCI STOP L BC12 STOP*
5% 1/16W MF LF 402 BC8
R2026 10K 1 2 PCI TRDY L TRDY*
5% 1/16W MF LF 402
TP_PCI_PME_L AV15 PME*
100 27 PLT_RESET_L BK48 PLTRST*

OUT
PCH SATA PORT 1 OPTION SELECT IS ODD OR SSD
94 27 LPC CLK33M SMC R AT11 CLKOUT_PCI0
OUT
LPC_CLK33M_LPCPLUS_R AN14
20 PCI_REQ2_L R2017 10K ODD_SATA:P2
1 2 =PP3V3_S0_PCH_GPIO 6 20 45
94 27 OUT CLKOUT_PCI1
94 5% 1/16W MF LF 402 TP_PCI_CLK33M_OUT2 AT12 CLKOUT_PCI2
TP_PCI_CLK33M_OUT3 AT17
R2098 10K ODD_SATA:P1
1 2
CLKOUT_PCI3
5% 1/16W MF LF 402 94 27 PCH_CLK33M_PCIOUT AT14 CLKOUT_PCI4
OUT

PAGE TITLE
PCH PCI/FLASHCACHE/USB
DRAWING NUMBER SIZE

REVISION
R
10.1.0
20 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
24 21 18 6 =PP3V3 S0 PCH
OMIT
AW55 =PP3V3_S0_PCH 6 18 21 24
25 15 PCH_GPIO0_BMBUSY_L BMBUSY*/GPIO0 U1800 CLKOUT_PCIE6N AB3 TP_PCIE_CLK100M_PE6N 8
D R2190
1 100 39 15 FW PME L BR19 TACH1/GPIO1 COUGAR-POINT
WLCSP
CLKOUT_PCIE6P AA2 TP_PCIE_CLK100M_PE6P 8
D
47K BLC_GPIO BA22 TACH2/GPIO6 SYM 6 OF 10 CLKOUT_PCIE7N AE2 TP_PCIE_CLK100M_PE7N R2150 1
5%
R2134 94 15 6 OUT 8
10K
1/16W
1
0
2 BR16 CLKOUT_PCIE7P AF1 TP PCIE CLK100M PE7P 8 5%
1
MF LF 100 47 46 SMC_RUNTIME_SCI_L 15 PCH_GPIO7_TACH3 TACH3/GPIO7 1/16W R2155
402 1/16W MF LF MF LF
2 5% 402 10K
402 15 PCH GPIO8 BP51 GPIO8 MISC A20GATE BB57 PCH A20GATE
NOSTUFF
2
5%
1/16W
100 37 15 ENET_LOW_PWR BK50 LAN_PHY_PWR_CTRL/GPIO12 R2170 MF LF

402
0 2
BM55 PECI H48 PCH PECI 1 2 CPU PECI 11 46 100

25 15 PCH_GPIO15 GPIO15 1/16W MF LF
5% Place this near the T point
402
CPU
94 25 21 AUD_IPHS_SWITCH_EN_PCH AU56 SATA4GP/GPIO16 RCIN* BG56 PCH_RCIN_L
BT17
R2140
48 LPCPLUS GPIO TACH0/GPIO17 0
IN
PROCPWRGD D53 100 PCH_PROCPWRGD 1 2 CPU_PWRGD OUT 11 25 100
1/16W MF LF
100 42 15 ODD_PWR_EN_L BA53 SCLOCK/GPIO22 5%
402
BP53 THRMTRIP* E56 PM_THRMTRIP_L IN 47 100
15 IN PCH_GPIO24 GPIO24/MEM_LED
100 46 18 15 SMC WAKE SCI L BJ43 GPIO27

TP1 P22 TP_PCH_TP1
100 32 25 ISOLATE_CPU_MEM_L BJ55 GPIO28
OUT
TP2 L31 TP_PCH_TP2
GPIO
94 81 15 T29_SW_RESET_L BL56 STP_PCI*/GPIO34
TP3 L33 TP_PCH_TP3
100 25 5 MXM GOOD BJ57 GPIO35
TP4 M38 TP_PCH_TP4
25 15 PCH_GPIO36_SATA2GP BB55 SATA2GP/GPIO36
TP5 L36 TP_PCH_TP5
99 89 25 15 JTAG_T29_TCK BG53 SATA3GP/GPIO37
TP6 Y18 TP PCH TP6
99 89 15 JTAG T29 TDO BE54 SLOAD/GPIO38
TP7 Y17 TP_PCH_TP7
99 89 15 JTAG_T29_TDI BF55 SDATAOUT0/GPIO39
TP8 AB18
C 94 21 PCH_PEG_CLKREQ_L AV44 PCIECLKRQ6*/GPIO45
TP9 AB17
TP_PCH_TP8
TP PCH TP9
C
94 81 15 T29 CLKREQ L BP55 PCIECLKRQ7*/GPIO46
TP10 BM46 TP_PCH_TP10
100 15 FW_PWR_EN AW53 SDATAOUT1/GPIO48
TP11 BA27 TP_PCH_TP11
25 15 PCH_GPIO49_SATA5GP BA56 SATA5GP/GPIO49
TP12 BC49 TP PCH TP12
94 48 SPIROM_USE_MLB BT53 GPIO57
TP13 AE49 TP_PCH_TP13
101 100 44 15 SDCARD_RESET BU16 TACH4/GPIO68
94 36 15 ENET_SW_RESET_L BM18 TACH5/GPIO69
15 PCH_GPIO70_TACH6 BN17 TACH6/GPIO70 6 =PP3V3_S3_PCH
15 PCH_GPIO71_TACH7 BP15 TACH7/GPIO71
TP17 BA36 TP_PCH_TP17
5
AUD IPHS SWITCH EN PCH 1 MC74VHC1G08
SOT23-5-HF
TP18 AY36
RSVD
94 25 21
BN21 TP_PCH_TP18
TP_PCH_PWM0 AUD IPHS SWITCH EN
8
BT21
PWM0
U2100 4 62 100
8 TP_PCH_PWM1 PWM1 TP19 Y14 TP_PCH_TP19 100 64 19 PM_PCH_PWRGD 2

8 TP_PCH_PWM2 BM20 PWM2
BN19 TP20 Y12 TP_PCH_TP20 3
8 TP_PCH_PWM3 PWM3
TP21 H31 TP_PCH_TP21
8 TP_PCH_SST BC43 SST
C2110 1
TP22 J27 TP PCH TP22 0.1UF
20%
10V
2
TP24 L22
CERM
TP_PCH_TP24 402
TP25 J31 TP_PCH_TP25

A4 VSS_NCTF_0
A6 TP26 L27 TP_PCH_TP26
VSS_NCTF_1
B B2
BM1
VSS_NCTF_2 TP27 L25 TP_PCH_TP27 B
VSS_NCTF_3
BM57 TP28 J22 TP_PCH_TP28
VSS_NCTF_4
NCTF
BP1 VSS_NCTF_5 TP29 C29 TP_PCH_TP29
BP57 VSS_NCTF_6
BT2 TP30 F28 TP PCH TP30
VSS_NCTF_7
BU4 VSS_NCTF_8 TP31 C26 TP_PCH_TP31
BU52 VSS_NCTF_9
BU54 TP32 B25 TP_PCH_TP32
VSS_NCTF_10
BU6 VSS_NCTF_11 TP33 E29 TP PCH TP33
D1 VSS_NCTF_12
F1 TP34 E27 TP_PCH_TP34
VSS_NCTF_13
A54 TP35 B27 TP_PCH_TP35
TS_VSS1
A52 TS_VSS2 TP36 D25 TP PCH TP36
F57 TS_VSS3
D57 NC_1 AY20 TP_PCH_NC
TS_VSS4
=PP3V3 S0 MXM 6 64 76 77
AU2 VSSADAC INIT3_3V* BN56 PCH INIT3V3 L 15
24 19 18 6 =PP3V3_S5_PCH
THIS SIGNAL IS INTEDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
This has internal pull up and should not pulled low.
1
R2161
10K Q2100
5%
G 1
1/16W SSM3K15FV
MF-LF
2 402 SOD-VESM-HF
PCH_PEG_CLKREQ_L PEG_CLKREQ_L
D
A 94 21 9
A
3
SYNC MASTER=K62 SIJI SYNC DATE=01/09/2011

2
PAGE TITLE
NOSTUFF
PCH MISC
R2160 DRAWING NUMBER SIZE
1
0
2 Apple Inc. 051-8442 D
1/16W MF LF REVISION
5% R
402 10.1.0
MXM CLKREQ ISOLATION I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

21 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1800 OMIT
COUGAR-POINT
WLCSP U1800
SYM 10 OF 10 COUGAR-POINT
TP_1V05_S0_PCH_VCCA_CLK AL5 VCCACLK WLCSP
VCCIO_2 AY25 =PP1V05 S0 PCH VCCIO USB 6 24
AV41 AY27 SMY 7 OF 10
TP_PPVOUT_PCH_DCPSUSBYP DCPSUSBYP VCCIO_3
PP3V3_S0_PCH_VCCA_DAC_F
CRT
PCH output, for decoupling only VCCIO_0 AV24 98 17
98 PPVOUT_G3_PCH_DCPRTC BR54 DCPRTC Max and Idle = 1 MA AT1 VCCADAC VCCCORE_0 AC24 =PP1V05_S0_PCH_VCC_CORE 6 24
PLACE C2210 AT BR54 VCCIO_1 AV26
CLOCK AND MISCELLANEOUS

MIN NECK WIDTH=0 2 mm AC26
MIN LINE WIDTH=0 2 mm VCCCORE_1 1.44 A Max, 474mA Idle
D 1
C2210
0.1UF
VOLTAGE=3 3V
BT56
R54
DCPRTC_NCTF
VCCSUS3_3_0 U31 =PP3V3_S5_PCH_VCCSUS3_3_USB 6 24
98 24 22 PP1V8R1V5 S0 PCH VCCVRM F
159mA Max, 114mA Idle R56
VCCCORE_2 AC28
AC30
D
PP1V8R1V5_S0_PCH_VCCVRM_F
DMI
20%
98 24 22 VCCVRM_2 AV30 97mA Max, 15mA Idle (VCCVRM 4 total) VCCVRM_1 VCCCORE_3
10V VCCSUS3_3_1 AC32
2 CERM AB1 AV32 (VCCSUS3_3 - 11 TOTAL) E41 VCCCORE_4
PP1V05 S0 PCH VCCADPLLA F VCCADPLLA VCCSUS3_3_2 =PP1V05 S0 PCH VCC DMI VCCDMI_0
USB
VCC CORE
98 17 24 6
402
40mA Max, 5mA Idle VCCCORE_5 AE24
VCCSUS3_3_3 AY31 57 mA Max, 30mA Idle B41 VCCDMI_1
98 17 PP1V05_S0_PCH_VCCADPLLB_F AC2 VCCADPLLB VCCCORE_6 AE28
40mA Max, 10mA Idle VCCSUS3_3_4 AY33
VCCCORE_7 AE30
VCCIO_DMI/CLK
VCCSUS3_3_5 BJ36
24 6 =PP1V05_S0_PCH_VCCIO_DMI Y30 VCCIO_26 VCCCORE_8 AE32
VCCSUS3_3_6 BK36
Y32 VCCIO_27 VCCCORE_9 AE34
VCCSUS3_3_7 BM36
AA34 VCCIO_16 VCCCORE_10 AE36
VCCSUS3_3_8 AT40
Y34 VCCIO_28 VCCCORE_11 AG32
VCCSUS3_3_9 AU38
AA36 VCCIO_17 VCCCORE_12 AG34
VCCSUS3_3_10 BT35
Y36 VCCIO_9 VCCCORE_13 AJ32
PCH output, for decoupling only V33 VCCIO_23 VCCCORE_14 AJ34
PLACE CAP AT BALL BA46 BA46
98 PPVOUT_S0_PCH_DCPSST DCPSST V5REF_SUS BT25 =PP5V_S5_PCH_V5REFSUS 24
V36 VCCIO_10 VCCCORE_15 AJ36
MIN LINE WIDTH=0 2 mm MIN NECK WIDTH=0 2 mm VOLTAGE=3 3V Max and Idle = 1mA V31 AL32
AA32 VCCIO_22 VCCCORE_16
TP_DCPSUS_0 DCPSUS_0
PCI/GPIO/LPC
1
C2222 F30 VCCIO_19 VCCCORE_17 AL34
TP_DCPSUS_1 AT41 DCPSUS_1
0.1UF
20% A39 V5REF BF1 =PP5V S0 PCH V5REF 24 VCCCORE_18 AN32
10V
98 PPVOUT_S5_PCH_DCPSUS DCPSUS_2 Max and Idle = 1mA AN34
2 MIN LINE WIDTH=0 2 mm VCCCORE_19
CERM
MIN NECK WIDTH=0 2 mm VCC3_3_7 A12 =PP3V3_S0_PCH_VCC3_3_PCI 6 24
CPU PCI/GPIO/LPC
402
VOLTAGE=1 05V 24 6 =PP3V3_S0_PCH_VCC3V3 AF57 VCC3_3_0 VCCCORE_20 AR32
VCC3_3_8 AU20 409 mA Max, 42mA Idle B53 AR34
1
C2230 PLACE C2230 AT BALL A39 (VCC3_3[1-9] total) PP1V05_S0_PCH_VCCAPLL_EXP_F VCCAPLLEXP VCCCORE_21
VCC3_3_9 AV20
98 24
0.1UF 24 6 =PP3V3_S0_PCH_VCC3_3_GPIO
AL38 VCC3_3_4
HVCMOS
FDI
20% PP1V8R1V5 S0 PCH VCCVRM F AJ1 =PP3V3 S0 PCH VCC3 3 SATA
10V NOSTUFF AN38 98 24 22 VCCVRM_0 6 24
2 VCC3_3_5
CERM
402 Need to check layout decoupling AU22 VCC3_3_1 BC17
VCC3_3_6
VCC3_3_2 BD17
VCCIO_8 AJ38 =PP1V05_S0_PCH_VCCIO_SATA 6 18 24 VCC3_3_3 BD20
24 6 =PP1V05 S0 PCH VCCASW AU32 VCCASW_0
VCCIO_12 AE40
1.61A Max, 433mA Idle AV36 VCCASW_1
VCCIO_15 AG40
AU34
C AG38 VCCASW_2
C
SATA
VCCIO_14 AG24
D55 AG41 VCCASW_3 VCCAFDIPLL C54 TP_1V05_S0_PCH_FDIPLL
24 6 =PP1V05 S0 PCH V PROC IO V_PROC_IO VCCIO_4 AG26
Max and Idle = 1mA B56 BA38 VCCASW_4
V_PROC_IO_NCTF VCCIO_13 AG28 VCCAPLLDMI2 A19 PP1V05 S0 PCH VCCAPLLDMI2 F 24 98
AN40 VCCASW_5
VCCASW
VCCIO_6 AJ24 VCCASW_6 VCCCLKDMI AJ20 PP1V05_S0_PCH_VCCCLKDMI_F
BU42 RTC VCCIO_7 AN41
AJ26 20mA Max, 10mA Idle
24 98
98 27 19 18 PP3V3_G3H_RTC VCCRTC AL40 VCCASW_7

PLACE C2231 AT BALL BU42 VCCIO_5 AJ28
PLACE C2232 AT BALL BU42 VCCASW_8 Y20 =PP1V05_S0_PCH_VCCIO_PCIE
VCCIO_PCIE
T55 AL24 VCCIO_30 6 18 19 24
24 6 =PP3V3R1V8_S0_PCH_VCCDFTERM VCCDFTERM_0 VCCASW_9 Y22 3.456A Max 426mA Idle
200 mA Max, 2mA Idle T57 AL28 VCCIO_31 (VCCIO[1-31] total)
VCCDFTERM_1 VCCASW_10 Y24
1
C2231 1
C2232 VCCIO_24
VCCAPLLSATA U56 PP1V05_S0_PCH_VCCAPLL_SATA_F 24 98
AN22 VCCASW_11
1UF
10%
0.1UF
20%
24 6 =PP1V05 S0 PCH VCCDIFFCLK AE15 VCCDIFFCLKN_0 AN24 VCCIO_25 Y26
6 3V 10V 55mA Max, 5mA Idle AE17 VCCASW_12 Y28
2 CERM 2 CERM VCCDIFFCLKN_1 AN26 VCCIO_11
402 402 AG15 VCCASW_13 V22
VCCDIFFCLKN_2 VCCIO_29
VCCVRM_3 R2 PP1V8R1V5_S0_PCH_VCCVRM_F 22 24 98
AN28 VCCASW_14 V25
AV40 AR24 VCCIO_20
24 6 =PP3V3_S5_PCH_VCCDSW VCCDSW3_3 VCCASW_15 V27
3mA Max, 1mA Idle AR26 VCCIO_21
AN52 VCCASW_16 F20
24 6 =PP3V3_S5_PCH_VCCSPI VCCSPI VCCIO_18
20mA Max, 1mA Idle VCCSUSHDA AV28 PP3V3R1V5_PCH_VCCSUSHDA 24 98
AR28 VCCASW_17
HDA
AC20 10 mA Max, 1mA Idle AR30

24 6 =PP1V05_S0_PCH_VCCSSC VCCSSC_0 VCCASW_18
105mA Max, 90mA Idle AE20 AR36
VCCSSC_1 VCCASW_19
AR38 VCCASW_20
AU30 VCCASW_21
AU36 VCCASW_22
B B
A A
PAGE TITLE
PCH POWER
DRAWING NUMBER SIZE

REVISION
R
10.1.0
22 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
OMIT
AE56 AN12
BG38 J46
BR36 U1800 AN15
BH52
U1800 J48
C12 COUGAR-POINT AN17
BH6
COUGAR-POINT J5
AY22 WLCSP AN18 WLCSP
SYM 8 OF 10 BJ1 SYM 9 OF 10 J53
A26 AN20
D A29
A42
AN30
AN36
BJ15
BK20
K52
K6 D
BK41 K9
A49 AN4
BK52 L12
A9 AN43
BK6 L17
AA20 AN47
BM10 L38
AA22 AN54
BM12 L41
AA24 AN9
BM16 L43
AA26 AR20
BM22 M20
AA28 AR22
BM23 M22
AA30 AR52
BM26 M25
AA38 AR6
BM28 M27
AB11 AT15
BM32 M31
AB15 AT18
BM40 M33
AB40 AT43
BM42 M36
AB41 AT47
BM48 M46
AB43 AT52
BM5 M52
AB47 AT6
BN31 M57
AB52 AT8
BN47 M6
AB57 AU24
BN6 M8
AB6 AU26
BP3 M9
AC22 AU28
BP33 N4
AC34 AU5
BP35 N54
AC36 AV12
BR22 R11
AC38 AV18
BR52 R15
AC4 AV22
BU19 R17
AC54 AV34
BU26 R22
AE14 AV38
C AE18 AV47
BU29
BU36
R4
R41
C
AE22 AV6
BU39 R43
AE26 AW57
C19 R46
AE38 AY38
C32 R49
AE4 AY6
C39 T52
AE47 B23
C4 T6
AE8 BA11
VSS VSS D15 U11
AE9 BA12 VSS VSS
D23 U15
AF52 BA31
D3 U17
AF6 BA41
D35 U20
AG11 BA44
D43 U22
AG14 BA49
D45 U25
AG20 BB1
E19 U27
AG22 BB3
E39 U33
AG30 BB52
E54 U36
AG36 BB6
E6 U38
AG43 BC14
E9 U41
AG44 BC15
F10 U47
AG46 BC20
F12 U53
AG5 BC27
F16 V20
AG50 BC31
F22 V38
AG53 BC36
F26 V6
AH52 BC38
F32 W1
AH6 BC47
F33 W55
AJ22 BC9
F35 W57
AJ30 BD25
B AJ57
AK52
BD33
BF12
F36
F40
Y11
Y15 B
F42 Y38
AK6 BF20
F46 Y40
AL11 BF25
F48 Y43
AL18 BF33
F50 Y46
AL20 BF41
F8 Y47
AL22 BF43
G54 Y49
AL26 BF46
H15 Y52
AL30 BF52
H20 Y6
AL36 BF6
H22 AL43
AL41 BG22
H25 AL44
AL46 BG25
H27 R36
AL47 BG27
H33 P36
AM3 BG31
H6 R25
AM52 BG33
J1 P25
AM57 BG36
J33
AN11

PAGE TITLE
PCH GROUNDS
DRAWING NUMBER SIZE

REVISION
R
10.1.0
23 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH VCCSUS3_3 BYPASS
22 18 6 =PP1V05_S0_PCH VCCIO_SATA
22 6 =PP3V3R1V8_S0_PCH_VCCDFTERM
R2400 (PCH SUSPEND USB 3.3V PWR)
80 6 =PP1V8R1V5_S0_PCH_VCCVRM
0 22 6 =PP3V3_S5_PCH_VCCSUS3_3_USB 1
1
C2444 1
C2452 1
C2453
1 2 98 22 PP1V8R1V5 S0 PCH VCCVRM F C2440 1UF 1UF 1UF
MIN LINE WIDTH=0 5MM 0.1UF
5% MIN NECK WIDTH=0 25MM
1 1 1
1 C2412 20%
10%
6 3V
10%
6 3V
10%
6 3V
1/16W VOLTAGE=1 8V
1 C2484 C2455 C2413 2.2UF 10V 2 CERM 2 CERM 2 CERM
MF LF MAKE BASE=TRUE 1 C2436 1 C2443 C2445 0.1UF 2.2UF 0.1UF 2 CERM 402 402 402
402 1
C2447 1UF 1UF 10UF 10% 10% 10%
10%
6 3V PLACEMENT_NOTE: 402
2
0.1UF 10% 10% 20%
2
16V
2
16V
2
16V X5R
PLACE C2440 AT BALL T55
10% 6 3V 6 3V 6 3V X5R X5R X5R 402
16V 2 CERM 2 CERM CERM 2 402 603 402
2 X5R 402 402 805 1 PLACEMENT_NOTEs:
402
PLACEMENT_NOTEs: PLACE C2452 AT BALL AG38
PLACE C2453 AT BALL AJ38
PLACE C2484 AT BALL U31 PCH VCCSUSHDA BYPASS PLACE C2444 AT BALL BA38
PLACEMENT_NOTEs: PLACE C2455 AT BALL AV30
D PLACE C2447 AT BALL
PLACE C2436 AT BALL
PLACE C2443 AT BALL
R56
R54
AJ1
PLACE C2413 AT BALL
PLACE C2415 AT BALL
BT35
AT40
(PCH HD Audio 3.3V/1.5V PWR)
D
PLACE C2445 AT BALL R2 98 24 22 PP3V3R1V5_PCH_VCCSUSHDA
80 18 6 =PP1V05 S0 PCH
NOSTUFF
L2401
1
C2441 22 6 =PP1V05 S0 PCH VCCSSC
0.1UF
1.0UH-0.5A PLACEMENT_NOTE: 20%
2
10V 1
C2475 C2480 1
1 2 PP1V05_S0_PCH_VCCAPLL_EXP_F 22 98 22 6 =PP1V05_S0_PCH_V_PROC_IO PLACE C2441 AT BALL AV28 CERM
402 1UF 10UF
10% 20%
6 3V 6 3V
VOLTAGE=1 05V 2 CERM CERM 2
MAKE BASE=TRUE 402 805 1
NOSTUFF
NOSTUFF C2416 1 1
C2417 1
C2430
1
C2489 4.7UF 0.1UF 0.1UF
C2400 1
1UF 20% 10% 10%
10UF 10%
PLACE C2489 AT BALL B53 6 3V 16V 16V
10% 6 3V X5R 2 2 X5R 2 X5R PLACEMENT_NOTEs:
16V 2 CERM 402 402 402
X5R CERM 2 402
0805 PLACE C2475 AT BALL AE20
22 6 =PP3V3_S5_PCH_VCCSPI PLACE C2480 AT BALL AC20
PLACEMENT_NOTEs (all 3):
PLACE C2416 AT BALL D55 1 C2442
PLACE C2417 AT BALL D55 1UF
PLACE C2430 AT BALL B56 10%
6 3V
PLACEMENT_NOTE: 2 CERM
PCH VCCIO BYPASS 402 22 6 =PP1V05_S0_PCH_VCCDIFFCLK
NOSTUFF PLACE C2442 AT BALL AN52
(PCH DMI 1.05V PWR)
L2404 1 C2434 1 C2435 C2437 1
1.0UH-0.5A
1UF 1UF 10UF
1 2 22 6 =PP1V05 S0 PCH VCC DMI 10% 10% 20%
6 3V 6 3V 6 3V
2 CERM 2 CERM CERM 2
1210
PP1V05_S0_PCH_VCCAPLLDMI2_F 402 402 805 1
22 98
MIN LINE WIDTH=0 5MM PLACEMENT_NOTE: 1
C2419 1
C2487
NOSTUFF MIN NECK WIDTH=0 25MM 1UF 1UF
NOSTUFF VOLTAGE=1 05V PLACE C2419 AT BALL B41 PLACEMENT_NOTEs:
1
C2488 MAKE BASE=TRUE PLACE C2487 AT BALL E41 10%
6 3V
10%
6 3V
C2406 1
1UF 2 CERM 2 CERM 22 6 =PP3V3_S5_PCH_VCCDSW
10UF 10% 402 402 PLACE C2434 AT BALL AE15
6 3V PLACE C2435 AT BALL AE17
C
10%
16V
X5R CERM
0805
2
2 CERM
402
PLACE C2488 AT BALL A19
C2499
0.1UF
1 PLACE C2437 AT BALL AE15
C
PCH VCC3_3 BYPASS 20%
10V
CERM 2
(PCH PCI 3.3V PWR) PLACEMENT_NOTE: 402
PLACE C2499 AT BALL AV40 PCH VCCIO BYPASS

NOSTUFF
PCH VCCSATAPLL Filter (PCH USB 1.05V PWR)
L2405 (PCH SATA PLL PWR)
10UH-0.45A 22 6 =PP1V05_S0_PCH VCCIO_USB
1 2 PP1V05_S0_PCH_VCCAPLL_SATA_F 22 98
1210 MIN NECK WIDTH=0 25MM 22 19 18 6 =PP1V05_S0_PCH_VCCIO_PCIE 1
C2446 1
C2449 1
C2450
VOLTAGE=1 05V
NOSTUFF MAKE BASE=TRUE 22 6 =PP3V3_S0_PCH_VCC3V3 1UF 1UF 1UF
NOSTUFF 10% 10% 10%
6 3V 6 3V 6 3V
C2408 1
1
2 CERM 2 CERM 2 CERM
10UF C2409 402 402 402
10% 1UF 1
C2423
16V
2
10% 1
C2429 1
C2414 1
C2407 1
C2463 C2401 1 C2410 1 C2415 1
X5R CERM
2
16V 0.1UF PLACEMENT_NOTEs:
0805 X5R
PLACEMENT_NOTE: PLACEMENT_NOTEs: 10% 1UF 1UF 1UF 1UF 10UF 10UF 10UF
402 16V 10% 10% 10% 10% 20% 20% 20%
2 X5R 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V
PLACE C2409 AT BALL U56 402 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 CERM 2 CERM 2 PLACE C2446 AT BALL AY25
PLACE C2423 AT BALL AF57 402 402 402 402 805 805 1 805 1 PLACE C2449 AT BALL AY27
PLACE C2450 AT BALL AV26
L2406
10UH-0.45A R2415
1 2 1
PP1V05_S0_PCH_VCCCLKDMI_L 1 2 PP1V05_S0_PCH_VCCCLKDMI_F 22 98 PCH VCCCORE BYPASS
1210-HF
MIN LINE WIDTH=0 5MM MIN LINE WIDTH=0 5MM (PCH 1.05V CORE PWR)
MIN NECK WIDTH=0 25MM 5% MIN NECK WIDTH=0 25MM PLACEMENT_NOTEs: 22 6 =PP1V05_S0_PCH_VCC_CORE
VOLTAGE=1 05V 1/16W VOLTAGE=1 05V
MF LF MAKE BASE=TRUE
402 C2448 1
22 6 =PP3V3_S0_PCH_VCC3_3_GPIO PLACE C2410 AT BALL Y20 1 1 1 1 1
10UF 1 PLACE C2415 AT BALL F20 C2481 C2482 C2483 C2460 C2461
10%
C2411 PLACE C2429 AT BALL Y24 1UF 1UF 1UF 10UF 10UF
16V 1UF PLACE C2414 AT BALL Y26
X5R CERM 2
10%
1
C2486 1
C2485 PLACE C2407 AT BALL Y28 10%
6 3V
10%
6 3V
10%
6 3V
20%
6 3V
20%
6 3V
0805 16V PLACE C2411 AT BALL AJ20 0.1UF 0.1UF PLACE C2401 AT BALL V22 2 CERM 2 CERM 2 CERM CERM 2 CERM 2
2 X5R 10% 10%
PLACE C2463 AT BALL V25 402 402 402 805 1 805 1
402 25V 25V
2 2
B X5R
402
X5R
402 B
PLACEMENT_NOTE:
PLACE C2485 AT BALL AL38 PLACEMENT_NOTEs:
21 18 6 =PP3V3_S0_PCH PLACE C2486 AT BALL AU22
PLACE C2482 AT BALL AC24
6 =PP5V_S0_PCH PCH V5REF Filter & Follower 22 6 =PP1V05_S0_PCH_VCCASW PLACE C2461 AT BALL AR32
PLACE C2481 AT BALL AC32
1 mA (PCH Reference for 5V Tolerance on PCI) PLACE C2460 AT BALL AJ34
1 PLACE C2483 AT BALL AL34
R2405 2 5 D2400 22 6 =PP3V3_S0_PCH_VCC3_3_PCI
100 NC
5% BAT54DW-X-G
NC
1/16W
1
C2426 1
C2456 1
C2496 1
C2498 C2418 1 C2420 1 C2428 1
SOT 363 1
MF LF 6 C2421 1
C2422 1UF 1UF 1UF 1UF 10UF 10UF 10UF
402
1 0.1UF 1UF 10% 10% 10% 10% 20% 20% 20%
10% 10% 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V =PP1V05_S0_PCH_VCCIO_DMI
PLACEMENT_NOTEs: 16V 6 3V 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 CERM 2 CERM 2 22 6
PP5V S0 PCH V5REF 98 2 X5R 2 CERM 402 402 402 402 805 1 805 1 805 1
MIN LINE WIDTH=0 3MM 402 402
MIN NECK WIDTH=0 25MM <1 MA PLACE C2421 AT BALL A12 1 1 1
VOLTAGE=5V PLACE C2422 AT BALL AU20 1
C2470 1
C2469 C2473 C2472 C2471
C2439 1 MAKE BASE=TRUE
1UF 1UF 10UF 10UF 10UF
1UF =PP5V S0 PCH V5REF 10% 10% 20% 20% 20%
10% 22 6 3V 6 3V 6 3V 6 3V 6 3V
10V 2 CERM 2 CERM CERM 2 CERM 2 CERM 2
X5R 2 402 402 805 1 805 1 805 1
402
PLACEMENT_NOTE: PLACEMENT_NOTEs:
PLACE C2439 AT BALL BF1
PLACE C2420 AT BALL AU32
PLACE C2428 AT BALL AJ24
PLACE C2426 AT BALL AU30
PLACE C2456 AT BALL AG28 PLACEMENT_NOTEs:
PLACE C2496 AT BALL AR36
PLACE C2418 AT BALL AN32 PLACE C2469 AT BALL V36
PLACE C2498 AT BALL AR24 PLACE C2471 AT BALL AA34
PLACE C2470 AT BALL Y32
PLACE C2472 AT BALL V31
21 19 18 6 =PP3V3_S5_PCH PLACE C2473 AT BALL F30
6 =PP5V_S5_PCH PCH V5REF_SUS Filter & Follower
NOSTUFF
1 mA S0-S5 (PCH Reference for 5V Tolerance on USB) R2406
2 4 0
R2404 2 D2400 6
=PP3V3R1V5 S0 PCH VCCSUSHDA 1 2 PP3V3R1V5 PCH VCCSUSHDA 22 24 98
10
A 5%
NC BAT54DW-X-G 5%
VOLTAGE=3 3V
A
NC
1/16W SOT 363 1/16W

MF LF
MIN NECK WIDTH=0 2MM SYNC MASTER=K62 AARON SYNC DATE=07/01/2009
MF LF 3
402 402 PAGE TITLE
=PP3V3_S0_PCH_VCC3_3_SATA
1
PP5V_S5_PCH_V5REFSUS 98
22 6
PCH DECOUPLING
MIN LINE WIDTH=0 3MM 1 DRAWING NUMBER SIZE
MIN NECK WIDTH=0 25MM <1 MA S0-S5 C2424 1
C2425 1
C2427
C2438 1
VOLTAGE=5V 0.1UF 1UF 1UF Apple Inc. 051-8442 D
R2407 PLACEMENT_NOTEs: 10% 10% 10%
REVISION
0.1UF 0 16V 6 3V 6 3V
=PP5V_S5_PCH_V5REFSUS =PP3V3R1V5 S5 PCH VCCSUSHDA 2 2 2 R
20%
10V
2
22 6 1 2
PLACE C2424 AT BALL BC17
X5R
402
CERM
402
CERM
402 10.1.0
CERM 5%
402 1/16W
PLACE C2425 AT BALL BD20
PLACE C2427 AT BALL BD17
PLACEMENT_NOTE: MF LF
PLACE C2438 AT BALL BT25 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
24 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROCESSOR MINI XDP DESIGN NOTE:
ODT AVAILABLE ON JTAG

=PPVCCIO_S0_XDP 6 25
25 6 =PPVCCIO_S0_XDP
PLACEMENT NOTE:
PLACEMENT NOTE=Place close to CPU
CRITICAL PLACE TDO TERM NEAR PLACEMENT NOTE=Place close to CPU
SNB XDP CONN
XDP_CONN XDP XDP XDP
R25101 R25111 R25121
J2500 51 51 51
DF40C-60DS-0.4V 5% 5% 5%
F-ST-SM-HF 1/16W 1/16W 1/16W
MF LF MF LF MF LF
D 1
3
2
4
402
PLACEMENT NOTE=Place close to J2500

2 402
2 402
2 D
11 BI XDP_CPU_PREQ_L OBSFN_A0 OBSFN_C0 CPU_CFG<16> IN 10 15 93
11 XDP_CPU_PRDY_L OBSFN_A1 5 6 OBSFN_C1 CPU_CFG<17> 10 93 93 25 11 XDP_CPU_TDO

IN IN
PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs 7 8 93 25 11 XDP_CPU_TDI
XDP_CPU_BPM 93 11 XDP_BPM_L<0> OBSDATA_A0 9 10 OBSDATA_C0 CPU_CFG<0> 10 15 25 93 93 25 11 XDP_CPU_TMS
IN IN
RP2500 93 11 IN XDP_BPM_L<1> OBSDATA_A1 11 12 OBSDATA_C1 CPU_CFG<1> IN 10 15 93 93 25 11 XDP_CPU_TCK
93 11 XDP_BPM_L<4> 1 8 13 14 93 25 11 XDP_CPU_TRST_L
IN
93 11 XDP BPM L<5> 2
0
7
93 11 XDP BPM L<2> OBSDATA_A2 15 16 OBSDATA_C2 CPU CFG<2> 10 15 93 PLACEMENT NOTE=Place close to CPU PLACEMENT NOTE=Place close to CPU
IN IN IN
5%
93 11 XDP BPM L<6> 3
1/16W
6
93 11 XDP BPM L<3> OBSDATA_A3 17 18 OBSDATA_C3 CPU CFG<3> 10 15 93
IN IN IN
SM LF
19 20 XDP1 XDP
93 11 IN XDP_BPM_L<7> 4 5
R2513 R25141
93 10 CPU_CFG<10> OBSFN_B0 21 22 OBSFN_D0 CPU_CFG<8> 10 93 51 51
IN IN
5% 5%
XDP_CPU_CFG 93 10 CPU_CFG<11> OBSFN_B1 23 24 OBSFN_D1 CPU_CFG<9> 10 93 1/16W 1/16W
IN IN
MF LF MF LF
RP2501 25 26 402
2 402
2
27 28 PLACEMENT NOTE:
93 10 IN CPU_CFG<12> 1 8 93 XDP_OBSDATA_B<0> OBSDATA_B0 OBSDATA_D0 CPU_CFG<4> IN 10 93
2 7 29 30 XDP PLACE TCK/TDI/TMS/TRST*
93 10 IN CPU_CFG<13> 0 93 XDP_OBSDATA_B<1> OBSDATA_B1 OBSDATA_D1 CPU_CFG<5> IN 10 15 93
R2515 PLACEMENT NOTE=Place close to R1841 TERM NEAR CPU
5%
93 10 CPU CFG<14> 3
1/16W
6 31 32 0
IN 5% 1 2 1/16W ITPXDP_CLK100M_P
SM LF IN 18 93
93 10 CPU CFG<15> 4 5 93 XDP OBSDATA B<2> OBSDATA_B2 33 34 OBSDATA_D2 CPU CFG<6> 10 15 93
IN IN MF LF
93 XDP_OBSDATA_B<3> OBSDATA_B3 35 36 OBSDATA_D3 CPU_CFG<7> 10 93 402
IN
37 38 XDP
XDP 39 40 R2516 PLACEMENT NOTE=Place close to R1840
PLACEMENT NOTE=Place close to CPU
R2500 XDP_CPU_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 93 XDP_CPU_CLK100M_P
41 42 0
1K XDP_CPU_PWRBTN_L HOOK1 ITPCLK#/HOOK5 93 XDP_CPU_CLK100M_N 5% 1 2 1/16W ITPXDP_CLK100M_N 18 93
CPU PWRGD 5% 1 2 1/16W
IN
100 21 11 IN
VCC_OBS_AB 43 44 VCC_OBS_CD MF LF
MF LF 402
402 XDP 93 XDP_CPU_CFG<0> HOOK2 45 46 RESET#/HOOK6 XDPCPU_PLTRST_L 27 94
IN
PLACEMENT NOTE=Place close to SMC R2502 47 48 <- 1K SERIES R ON PCH SUPPORT P. 28
XDP VR READY HOOK3 DBR#/HOOK7 XDP DBRESET L OUT 11 25 100
0 49 50
100 46 25 19 OUT PM PWRBTN L 5% 1 2 1/16W NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28
MF LF 49 25 =SMBUS XDP SDA SDA 51 52 TDO XDP CPU TDO 11 25 93
402
BI IN
53 54
C PLACEMENT NOTE=Place close to CPU
XDP
R2501
1K
49 25 IN =SMBUS_XDP_SCL SCL
TCK1 NC
55 56
TRSTn
TDI
XDP_CPU_TRST_L
XDP_CPU_TDI
OUT
OUT
11 25 93
11 25 93
C
93 25 15 10 CPU_CFG<0> 5% 1 2 1/16W 93 25 11 XDP_CPU_TCK TCK0 57 58 TMS XDP_CPU_TMS 11 25 93
OUT OUT OUT =PP3V3 S5 XDP 6 25
MF LF 59 60 XDP_PRESENT#
402 XDP
R2504 XDP XDP PLACEMENT NOTE:
PLACEMENT NOTE=Place close to PCH
0 C2500 1 1
C2501 PLACE TDO TERM NEAR PLACEMENT NOTE=Place close to PCH
100 65 64 5 OUT PM_PGOOD_PVCORE_CPU 5% 1 2 1/16W
0.1uF 518S0774 0.1uF PCH XDP CONN
XDP1 XDP XDP
R25511 R25521
MF LF 10% 10%
402 16V
2 2
16V R2550
X5R X5R
402 402
200 200 200
5% 5% 5%
1/16W 1/16W 1/16W
MF LF MF LF MF LF
402 402 402
2 2 2
XDP 94 25 18 XDP_PCH_TDO
PLACEMENT NOTE=Place close to SW2800
R2506 To Reset Button 94 25 18 XDP_PCH_TDI
XDP_DBRESET_L 1
0 2 PM_SYSRST_L
94 25 18 XDP_PCH_TMS
100 25 11 IN OUT 19 27 46 100
94 25 18 XDP_PCH_TCK
5%
1/16W PLACEMENT NOTE=Place close to PCH PLACEMENT NOTE=Place close to PCH
PCH MINI XDP MF-LF

402
PLACEMENT NOTE=Place close to PCH PLACEMENT NOTE=Place close to PCH
XDP XDP XDP XDP

25 6 =PP3V3_S5_XDP R25531 R25541 R25551 R25561
100 100 100 51
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
CRITICAL MF LF MF LF MF LF MF LF
XDP 402
2 402
2 402
2 402
2
R2582 XDP_CONN
OC0#/GPIO59
100 33 20 IN AP_PWR_EN 5% 1
0
2 1/16W J2550
MF-LF 402 DF40C-60DS-0.4V
XDP F-ST-SM-HF XDP
OC1#/GPIO40 R2580 1 2 R2578 PLACEMENT NOTE=Place close to PCH
GPIO15
B 100 34 20 IN USB_HUB_SOFT_RESET_L 5% 1
MF-LF
0
2 1/16W
402
TP_XDP_PCH_OBSFN_A<0> OBSFN_A0 3
5
4
6
OBSFN_C0 XDP_PCH_GPIO15 5% 1
MF-LF
0
2 1/16W
402
PCH_GPIO15 IN 15 21
This is to derive 1.05V SUS RAIL
B
TP XDP PCH OBSFN A<1> OBSFN_A1 OBSFN_C1 PCH GPIO0 BMBUSY L IN 15 21 XDP PLACEMENT NOTE:
XDP 7 8 R2576 PLACEMENT NOTE=Place close to PCH
R2583 MGPIO7/GPIO28 PLACE TCK/TDI/TMS/TRST*
OC2#/GPIO41 9 10 0 TERM NEAR PCH
0 XDP_PCH_AP_PWR_EN OBSDATA_A0 OBSDATA_C0 XDP_PCH_ISOLATE_CPU_MEM_L 5% 1 2 1/16W ISOLATE_CPU_MEM_L IN 21 32 100
100 94 83 20 IN T29_DP_PORTA_PWR_EN 5% 1 2 1/16W MF-LF 402
MF-LF 402 XDP_PCH_USB_HUB_SOFT_RST_L OBSDATA_A1 11 12 OBSDATA_C1 XDP_PCH_MXM_GOOD XDP
XDP 13 14 R2577 PLACEMENT NOTE=Place close to PCH
GPIO35
PLACEMENT NOTE=Place close to PCH R2587 15 16
0
OC3#/GPIO42 XDP_PCH_T29_DP_PORTA_PWR_EN OBSDATA_A2 OBSDATA_C2 XDP_PCH_DP_AUXCH_ISOL 5% 1 2 1/16W MXM_GOOD IN 5 21 100
0 17 18
MF-LF 402
100 36 20 IN ENET_PWR_EN 5% 1 2 1/16W XDP_PCH_ENET_PWR_EN OBSDATA_A3 OBSDATA_C3 PCH_GPIO19_SATA1GP IN 15 18 XDP
MF-LF 402
19 20 R2575 PLACEMENT NOTE=Place close to PCH
SATA0GP/GPIO21
XDP 21 22
0
R2586 TP XDP PCH OBSFN B<0> OBSFN_B0 OBSFN_D0 TP XDP PCH OBSFN D<0> 5% 1 2 1/16W DP AUXCH ISOL IN 15 18 85 87 94
OC4#/GPIO43 MF-LF 402
0 TP XDP PCH OBSFN B<1> OBSFN_B1 23 24 OBSFN_D1 TP XDP PCH OBSFN D<1>
94 83 20 IN T29_DP_PORTB_PWR_EN 5% 1 2 1/16W
25 26
MF-LF 402 SATA2GP/GPIO36
XDP_PCH_T29_DP_PORTB_PWR_EN OBSDATA_B0 27 28 OBSDATA_D0 PCH_GPIO36_SATA2GP 15 21
IN
XDP 29 30
XDP_PCH_SDCONN_CHANGE OBSDATA_B1 OBSDATA_D1 XDP_PCH_JTAG_T29_TCK XDP
OC5#/GPIO9 R2581 31 32 R2573 PLACEMENT NOTE=Place close to PCH
0 SATA3GP/GPIO37
100 45 20 IN SDCONN STATE CHANGE 5% 1 2 1/16W 0
MF-LF 402 20 PCH_GPIO10_OC6_L OBSDATA_B2 33 34 OBSDATA_D2 XDP_PCH_AUD_IPHS_SWITCH_EN 5% 1 2 1/16W JTAG T29 TCK 15 21 89 99
IN MF-LF 402 IN
XDP 20 PCH_GPIO14_OC7_L OBSDATA_B3 35 36 OBSDATA_D3 PCH_GPIO49_SATA5GP 15 21 XDP
IN IN
R2584 37 38 R2579 PLACEMENT NOTE=Place close to PCH
SATA4GP/GPIO16
1K 39 40
0
25 6 IN =PP3V3 S5 XDP 5% 1 2 1/16W XDP PCH S5 PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 TP XDP PCH HOOK4 5% 1 2 1/16W AUD IPHS SWITCH EN PCH IN 21 94
MF-LF 402 MF-LF 402
XDP_PCH_PWRBTN_L HOOK1 41 42 ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5
XDP 43 44
PLACEMENT NOTE=Place close to SMC
R2585 VCC_OBS_AB VCC_OBS_CD
0 TP_XDPPCH_HOOK2 HOOK2 45 46 RESET#/HOOK6 XDPPCH_PLTRST_L 27 100 <- 1K SERIES R ON PCH SUPPORT P. 28
PM PWRBTN L 5% 1 2 1/16W IN
100 46 25 19 OUT MF-LF 402 TP_XDPPCH_HOOK3 HOOK3 47 48 DBR#/HOOK7 XDP_DBRESET_L 11 25 100
OUT
49 50 NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28
49 25 =SMBUS_XDP_SDA SDA 51 52 TDO XDP_PCH_TDO 18 25 94
BI IN
=SMBUS XDP SCL 53 54 TP XDP PCH TRST L
A 49 25 IN SCL
TCK1 NC
55 56
TRSTn
TDI XDP PCH TDI OUT 18 25 94 SYNC MASTER=K62 SIJI SYNC DATE=01/09/2011 A
94 25 18 XDP PCH TCK TCK0 57 58 TMS XDP PCH TMS 18 25 94
PAGE TITLE
OUT OUT
59 60 XDP_PRESENT# CPU & PCH XDP
XDP XDP DRAWING NUMBER SIZE
C2580 1
518S0774
1 C2581 Apple Inc. 051-8442 D
0.1uF 0.1uF REVISION
10% 10% R
16V
X5R 2 2
16V
X5R
10.1.0
402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
25 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BUF_CLK BUF_CLK
BUF_CLK
L2600 L2650
FERR-120-OHM-1.5A FERR-120-OHM-1.5A R2650
1 2 1 2 1
2.2 2
6 =PP1V05_S0_CK505 98 PP1V05_S0_CK505_F 6 =PP1V5_S0_CK505 98 PP1V5_S0_CK505_F 98 PP1V5_S0_CK505_R
MIN LINE WIDTH=0 5mm MIN LINE WIDTH=0 5mm
0402 MIN NECK WIDTH=0 2mm BUF_CLK BUF_CLK BUF_CLK BUF_CLK BUF_CLK 0402 MIN NECK WIDTH=0 2mm 5% BUF_CLK
VOLTAGE=1 05V VOLTAGE=1 5V 1/16W BUF_CLK BUF_CLK
C2600 1 1
C2602 1
C2603 1
C2604 1
C2605 MF-LF
402
C2650 1
1 C2651 1 C2652
D
10UF
20%
6 3V
X5R 2 2
0.1UF
10%
16V
X5R 2
0.1UF
10%
16V
X5R 2
0.1UF
10%
16V
X5R 2
0.1UF
10%
16V
X5R
10UF
20%
6 3V
X5R 2
2
0.1UF
10%
16V
2
0.1UF
10%
16V
D
603 X5R X5R
402 402 402 402 603 402 402
PLACE IT CLOSE TO L2650
BUF_CLK PLACE IT CLOSE TO POWER PINS PLACE IT CLOSE TO POWER PINS
L2610
FERR-120-OHM-1.5A
6 =PP3V3_S0_CK505 1 2 98 PP3V3_S0_CK505_F
MIN LINE WIDTH=0 5mm
0402 MIN NECK WIDTH=0 2mm BUF_CLK BUF_CLK BUF_CLK
VOLTAGE=3 3V
C2610 1 1 C2615 1 C2616
10UF 0.1UF 0.1UF
20% 10% 10%
6 3V 16V 16V
X5R 2 2 X5R 2 X5R
603 402 402
PLACE IT CLOSE TO POWER PINS
CRITICAL
Y2620
17
16
31
25
22
9
4
14.31818
C 94 CK505_XTAL_OUT_R 1 2
C
VDD_CPU_IO
VDD_SRC_IO
VDD_SATA_IO
VDD_27
VDD_96_IO
VDD_REF
BUF_CLK BUF_CLK
VDD_CORE
5X3 2 SM
C2620 1
BUF_CLK 1
C2621 1 NOSTUFF
R2616
18pF 18pF 10M
5% 5%
50V 50V 5%
CERM 2 2 CERM 1/16W PLACE R2699 NEAR PIN 26
402 402 MF LF
2 402 CRITICAL BUF_CLK
BUF_CLK U2600 R2699

R2615 94 CK505_XTAL_IN 24 X1
SLG2AP108
QFN REF 26 PCH_CLK14P3M_REFCLK_R 5% 1
33 2 402 PCH_CLK14P3M_REFCLK 18 26 94
0 1/16W MF-LF OUT
5% 1 2 1/16W 94 CK505_XTAL_OUT 23 X2 OMIT
CPU* 18 TP CLK133M PCH N 93
R2605 OR R2606 CAN BE CHANGED TO "BUF_CLK" OPTION LATER MF LF 402
WHEN FCIM IS FULLY VALIDATED -> 49 IN =SMBUS_CK505_SCL 3 SCL CPU 19 TP_CLK133M_PCH_P 93 PCH BCLK 133MHZ
NOSTUFF
R2605 49 BI =SMBUS_CK505_SDA 2 SDA SRC_2* 11 PCH_CLK100M_DMI_N OUT 18 26 93
0 SRC_2 10 PCH_CLK100M_DMI_P OUT 18 26 93

100 63 47 46 36 32 19 5 IN PM_SLP_S3_L 5% 1 2 1/16W CK505_CKPWRGD_PD_L 1 CKPWRGD/PD* PCH DMI/PCIe 100MHz
MF LF 402 SATA* 15 PCH_CLK100M_SATA_N OUT 18 26 93
100 CK505_27MHZ_EN 32 27MHZ_EN
NOSTUFF SATA 14 PCH_CLK100M_SATA_P OUT 18 26 93
R2606 PCH SATA 100MHZ
0 27MHZ 29 CK505_CLK27M
64 IN PM_PGOOD_CK505 5% 1 2 1/16W BUF_CLK BUF_CLK
MF LF 402
R26201 1
R2600 27MHZ_SS 30 TP_CK505_CLK27M_SS
10K 10K
5% 5% DOT_96* 7 PCH_CLK96M_DOT_N 18 26 93
VSS_SATA
VSS_CORE
OUT
STUFF THIS TO POWER DOWN CK505 -> 1/16W 1/16W
VSS_REF
VSS_CPU
VSS_SRC
MF-LF MF-LF DOT_96 6 PCH CLK96M DOT P
VSS_27
VSS_96
OUT 18 26 93
402 2 2 402 PCH USB Clock 96MHz
THRM
PAD BUF_CLK
1
R2690
20
12
13
28
27
21
33
10K
5%
B 1/16W
MF-LF
2 402
B
UNUSED clock terminations for FCIM MODE
94 26 18 PCH_CLK14P3M_REFCLK
93 26 18 PCH CLK100M DMI N
93 26 18 PCH_CLK100M_DMI_P
93 26 18 PCH_CLK100M_SATA_N
93 26 18 PCH CLK100M SATA P
93 26 18 PCH_CLK96M_DOT_N
A 93 26 18 PCH_CLK96M_DOT_P
SYNC MASTER=K62 ROSITA SYNC DATE=01/09/2011 A
PAGE TITLE
CLOCK (CK505)
FCIM FCIM FCIM FCIM FCIM FCIM FCIM DRAWING NUMBER SIZE
1
R2657 1
R2651 1R2652 1R2653 1R2654 1
R2655 1
R2656 Apple Inc. 051-8442 D
10K 10K 10K 10K 10K 10K 10K REVISION
5% 5% 5% 5% 5% 5% 5% R
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
10.1.0
2 402 2 402 2 402 2 402 2 402 2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
26 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RTC Power Sources Platform Reset Connections

D2800
BAT54DW-X-G
SOT 363
=PP3V3_G3H_RTC_D PP3V3_G3H_RTC RTC_RESET_L
6
1 6
18 19 22 98 100 18
Unbuffered R2881
Coin-Cell Holder R2800 VOLTAGE=3 3V
PLT_RESET_L 1
33
2 DEBUG_RESET_L
OMIT 100 20 IN OUT 48 100
1K MAKE BASE=TRUE
98 PPVBATT_G3_RTC 2 1 98 PPVBATT_G3_RTC_R 4 3 1 C2899 5%
1/16W
MIN NECK WIDTH=0 2 mm 5%
MIN NECK WIDTH=0 2 mm NOSTUFF MF LF
VOLTAGE=3 3V 1/16W VOLTAGE=3 3V NONE 402
NONE
MF LF
NC
5 NC NC 2 NC 2 NONE
D 1
J2800
402
603
PLACE THIS ON THE BOTTOM SIDE
R2882
33
D
BB10201-C1403-7H 1 2 ENET_RESET_L OUT 36 100
2 SM 5%
1/16W
511-0054 MF LF
NOTE: R2800 and D2800 form the double- 402
fault protection for RTC battery. R2892

33
1 2 FW_RESET_L OUT 39 100
5%
1/16W
MF LF
PCH RTC Crystal 402

T29
R2855
33
1 2 T29_RESET_L OUT 81 100
5%
1/16W
PLACE C2810 CLOSE TO Y2810 MF LF
402
C2810
R2810 12pF XDP
0 1 2 R2899
94 18 PCH_CLK32K_RTCX2 1 2 94 PCH_CLK32K_RTCX2_R
IN 1K
5% 1 2 XDPPCH_PLTRST_L OUT 25 100
1/16W 5%
1 MF LF CRITICAL 50V 5%
R2811 CERM
3
402 1/16W
402
4
10M Y2810 NC MF LF
5% 402
2
1/16W 32.768K NC
MF LF SM 2
C2811 XDP
1
R2870 402 2
12pF R2898
0 1 2
1K
94 18 PCH_CLK32K_RTCX1 1 2 94 PCH_CLK32K_RTCX1_R 1 2 XDPCPU_PLTRST_L 25 94
OUT OUT
5% PLACE Y2810 CLOSE TO U1800 5%
5%
1/16W 27 11 6 =PP3V3_S0_RSTBUF 1/16W
50V
MF LF MF LF MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
402 CERM
402
Buffered 402
PLACE C2811 CLOSE TO Y2810

C PCH 25MHZ CRYSTAL 1
5 MC74VHC1G08
SOT23-5-HF R2890
C
4
33
PLACE C2815 CLOSE TO Y2815 94 PLT RST BUF L 1 2 PEG RESET L
NOSTUFF C2815 DEVELOPMENT 2
U2880 OUT 9 100
5%
R2815 22pF 1/16W
0 1 MF LF
94 18 PCH_CLK25M_XTALOUT 1 2 94 PCH_CLK25M_XTALOUT_R 1 2 3 R2880 402
IN
C2880 1 100K
DEVELOPMENT 1 5%
5% 0.1UF 5%
R2883
25.0000M
1/16W
R2816 1/16W
8X4.5MM-SM3
50V 20% 33
Y2815
MF LF MF LF
CERM 10V SMC_LRESET_L
1M 402 1 2
2
2
2 402
CERM OUT 46 100
402
5% DEVELOPMENT 402
1/16W CRITICAL 5%
MF LF 1/16W
NOSTUFF 402 2
C2816 MF LF
1
402
R2872 22pF
0 1 2 R2888
94 80 18 PCH_CLK25M_XTALIN 1 2 94 PCH_CLK25M_XTALIN_R
OUT 33
5% PLACE Y2815 CLOSE TO U1800 DEVELOPMENT 5% 1 2 MINI_RESET_L OUT 33 100
1/16W
MF LF 50V 5%
402 CERM 1/16W
402 27 11 6 =PP3V3_S0_RSTBUF MF LF
PLACE C2816 CLOSE TO Y2815 402
OPEN-DRAIN BUFFER R2884

33
1 2 SDCARD_PLT_RST_L OUT 44 100
5 U2890 5%
74LVC1G07 1/16W
MF LF
SC70
402
6 =PP3V3_S0_PCH_PM 2 4 CPU_RESET_L 11 100
OUT
NC VTT VOLTAGE DIVIDER AND PU ON CPU PAGE
1
R2897 1 3
4.7K 1
5% C2890 NC_U2890_P1
1/16W
MF LF 0.1UF NO TEST=TRUE
20%
2 402 10V
CERM 2
B 402
B
Reset Button
PM_SYSRST_L OUT 19 25 46 100
DEVELOPMENT
SW2800 6 =PP3V3 S5 RSTBUF
NTC020-CC1J-B260T
1 SM 2
C2870 1
0.1UF
20%
10V
CERM 2
402
3 4
5 MC74VHC1G08
100 71 64 PM PGOOD P3V3 S5 REG 1 SOT23-5-HF
4 PM_RSMRST_PCH_L
SILK_PART=SYS RESET 2
U2870 19 100
R2825
PLACEMENT NOTE=Place close to U1800 33 R2850
94 20 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 46 94 0
100 46 PM_RSMRST_L 1 2
5%
A 1/16W
MF LF
402
PLACEMENT NOTE=Place close to U1800
R2826
33
5%
1/16W
MF LF
402
SYNC MASTER=K62 SIJI SYNC DATE=01/09/2011 A
94 20 LPC CLK33M LPCPLUS R 1 2 LPC CLK33M LPCPLUS 48 94
PAGE TITLE
IN OUT
5%
1/16W
NOSTUFF
CHIPSET SUPPORT
MF LF DRAWING NUMBER SIZE
R2827 402 SMC PROVIDES RSMRST_L DE-ASSERTION DELAY UPON ENTRY TO S5
94 20 PCH CLK33M PCIOUT
PLACEMENT NOTE=Place close to U1800
1
33
2 PCH CLK33M PCIIN 18 94 SMC PROVIDES RSMRST_L ASSERTION TIMING REQUIREMENTS UPON EXPECTED EXIT FROM S5 Apple Inc. 051-8442 D
IN OUT
REVISION
5% SMC MAY FORCE A RSMRST_L ASSERTION WITHOUT AN S5 POWER TRANSITION IN SOME ERROR CASES R
1/16W
MF LF PGOOD PROVIDES RSMRST_L ASSERTION TIMING REQUIREMENTS UPON AN UN-EXPECTED EXIT FROM S5 (POWER LOSS)
10.1.0
402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
28 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
30 29 28 6
=PP1V5 S3 MEM A
=PP3V3 S3 VREFMRGN PLACEMENT NOTE:

28 6
VREFMRGN_A PLACE R2970, R2971 and C2950 close to DIMM PIN

R2909
=PP5V S3 VREFMRGN 1
10 2 98 PP5V S3 VREFMRGN_A
28 6
30 29 28 6 =PP1V5 S3 MEM_A
1% VREFMRGN_A
VREFMRGN_A 1/16W
1 C2900 MF-LF
1 C2901
D VREFMRGN_A 0.1UF
10% 353S2369
402 0.1UF
10%
2 16V
1
R2970 D
R2900 2 16V
X5R
1 VREFMRGN_A VREFMRGN_A X5R
402
1K
=I2C VREFMRGN A SCL 0 VDD R2902 1%
49 IN 1 2 402
U2900 12.1K2 U2901 VREFMRGN_A VREFMRGN_A
1/16W
MF-LF
5% 1 1 5 LM321 2 402
1/16W ISL90727WIE627ZTK SOT23-5 R2904 R2958
MF-LF SC-70 1%
4 1
2.2 2 VREFMARGIN DIMMA DQ 1
0 2 PP0V75_S3_MEM_VREFDQ_A
402 1/16W 92
97 I2C VREFMRGN DIMMA SCL 3 SCL VREFMRGN_A RH 6 MF-LF OUT 28 30 98
402 5% 5%
VREFMRGN_A 3 353S1961 1/16W 1/16W 1 NOSTUFF
R2901 97 I2C VREFMRGN DIMMA SDA 4 SDA RW 5 92 VREFMARGIN DIMMA DACOUT 2
VREFMRGN_A
1
MF-LF
VREFMRGN_A
MF-LF R2971 1 C2950
=I2C VREFMRGN A SDA 1
0 2 GND
VREFMRGN_A
R2905 402
1 C2902
402
1K 0.1UF
49 BI 1K 1UF
1% 10%
2
1 1/16W
5%
1/16W
R2903 1%
1/16W 10%
6.3V
MF-LF 2 16V
X5R
MF-LF I2C ADDR = 0X5C (WRITE) 12.1K MF-LF 2 CERM 2 402 402
402 1% 2 402 402
I2C ADDR = 0X5D (READ) 1/16W 92 VREFMARGIN DIMMA OPFB
MF-LF
2 402
31 29 28 6
=PP1V5 S3 MEM B
PLACEMENT NOTE:
28 6 =PP3V3 S3 VREFMRGN
PLACE R2975, R2976 and C2951 close to DIMM PIN
VREFMRGN_B
R2919
=PP5V S3 VREFMRGN 1
10 2 98 PP5V S3 VREFMRGN_B
C VREFMRGN_B
28 6
1%
1/16W
VREFMRGN_B VREFMARGIN DIMMB DQ
31 29 28 6 =PP1V5 S3 MEM_B C
1 C2910 MF-LF
1 C2911 OUT 28 92
402 0.1UF 1
VREFMRGN_B 0.1UF 353S2370 10% R2975
R2910 10%
16V 1 2 16V
X5R R2956 change to NOSTUFF if use VREFMARGIN_DIMMB_DQ 1K
2 X5R VREFMRGN_B VREFMRGN_B 402 1%
=I2C_VREFMRGN_B_SCL 0 VDD R2912 to drive both VREFCA_A and VREFCA_B
49 IN
1 2 402
U2910 12.1K2 U2911 VREFMRGN_B VREFMRGN_B
1/16W
MF-LF
5%
ISL90728WIE627ZTK
1 1 5 LM321 R2914 R2956 2 402
1/16W SOT23-5
MF-LF SC-70 1%
4 1
2.2 2 1
0 2 PP0V75_S3_MEM_VREFDQ_B
402 1/16W
97 I2C VREFMRGN DIMMB SCL 3 SCL VREFMRGN_B RH 6 MF-LF OUT 28 31 98
402 5% 5%
VREFMRGN_B 3 353S1961 1/16W 1/16W 1 NOSTUFF
R2911 97 I2C VREFMRGN DIMMB SDA 4 SDA RW 5 92 VREFMARGIN DIMMB DACOUT 2 1
VREFMRGN_B MF-LF
VREFMRGN_B MF-LF R2976 1 C2951
=I2C VREFMRGN B SDA 1
0 2
GND
VREFMRGN_B
R2915 402
1 C2912
402
1%
1K 0.1UF
49 BI 1K 1UF 10%
2
1 1/16W
5%
1/16W
R2913 1%
1/16W 10%
6.3V
MF-LF
16V
2 X5R
MF-LF I2C ADDR = 0X7C (WRITE) 12.1K MF-LF 2 CERM 2 402 402
402 1% 2 402 402
I2C ADDR = 0X7D (READ) 1/16W 92 VREFMARGIN DIMMB OPFB PLACE IT CLOSE TO DIMM CONNECTOR PIN
MF-LF
2 402
DIMM VREFDQ
B B
DIMM VREFCA
30 29 28 6 =PP1V5 S3 MEM A
1
R2988 PLACEMENT NOTE:
1K PLACE R2988, R2989 and C2921 close to DIMM PIN
1%
1/16W
MF-LF
NOSTUFF 2 402
R2995
0
VREFMARGIN_DIMMB_DQ PP0V75_S3_MEM_VREFCA_A
92 28 IN
1
5%
1/16W
2
1 NOSTUFF
OUT 30 98
CPU VREF
MF-LF
402 R2989 1 C2921
1K 0.1UF
1% 10% NOSTUFF
1/16W
MF-LF 16V
2 X5R PLACEMENT NOTE: R2960
2 402 402 PP0V75_S3_MEM_VREFDQ_A 1
0 2 PP0V75_S3_MEM_VREFDQ_B
98 30 28 28 31 98
PLACE R2968, R2969 and C2961 near CPU
5%
1/16W
MF-LF
29 16 13 11 6 =PP1V5 S0 CPU MEM 402
31 29 28 6 =PP1V5_S3_MEM_B EMPTY ONE SET OF OP-AMP & POT WHEN R2960 IS STUFF
1
R2968
100
1%
1
R2978 PLACEMENT NOTE: 1/16W
MF-LF
1K 2 402
A NOSTUFF
1%
1/16W
MF-LF
PLACE R2978, R2979 and C2991 close to DIMM PIN
CPU_DDR_VREF SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A

R2996 2 402 OUT 11 92
PAGE TITLE
0
92 28 IN VREFMARGIN DIMMB DQ 1 2 PP0V75 S3 MEM VREFCA B OUT 31 98 1
R2969
DDR3 VREF MARGINING
5%
1/16W NOSTUFF 100
1 C2961 DRAWING NUMBER SIZE
1 0.1UF 051-8442 D
MF-LF
402 R2979 1 C2991 1%
1/16W 10%
16V Apple Inc.
1K 0.1UF MF-LF 2 X5R REVISION
1% 10% 2 402 402 R
10.1.0
1/16W 16V
MF-LF 2 X5R
2 402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
29 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DIMM A (CLOSER TO CPU) CAPS TO STITCH 1V5_CPU_MEM TO GND NEAR DIMM DIMM B (FURTHER FROM CPU)
29 28 16 13 11 6 =PP1V5 S0 CPU MEM
D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D
C3015 C3016 C3017 C3018 C3019 C3010 C3025 C3026 C3027 C3028 C3029 C3020 C3021 C3022 C3023 C3014 C3030 C3031 C3032 C3033 C3034 C3035 C3036 C3037 C3038 C3039
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
EXTRA DECOUPLING CAPS FOR 1V5_CPU_MEM RAIL
29 28 16 13 11 6 =PP1V5 S0 CPU MEM
1 C3040 1 C3041 1 C3042 1 C3043 1 C3044 1 C3045 1 C3046 1 C3047 1 C3048 1 C3049 1 C3090 1 C3091 1 C3092 1 C3093 1 C3094 1 C3095 1 C3096
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
C C
29 28 16 13 11 6 =PP1V5_S0_CPU_MEM
1 C30A0 1 C30A1 1 C30A2 1 C30A3 1 C30A4 1 C30A5 1 C30A6 1 C30A7 1 C30A8 1 C30A9 1 C30AA 1 C30AB 1 C30AC 1 C30AD 1 C30AE 1 C30AF 1 C30AG
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
DECOUPLING CAPS FOR 1V5_S3_MEM AT CHANNEL A DIMM CONNECTOR
30 28 6 =PP1V5_S3_MEM_A
B 1
C3050
10UF
1
C3051
10UF
1 C3052
1UF
1 C3053
1UF
1 C3054
1UF
1 C3055
1UF
1 C3056
1UF
1 C3057
1UF
1 C3058
1UF
1 C3059
1UF
1 C3060
1UF
1 C3061
1UF
1 C3062
1UF
1 C3063
1UF
1 C3064
1UF
1 C3065
1UF
1 C3066
1UF
1 C3067
1UF
1 C3068
1UF
1 C3069
1UF
B
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6 3V 6 3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
603 603 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
DECOUPLING CAPS FOR 1V5_S3_MEM AT CHANNEL B DIMM CONNECTOR
31 28 6 =PP1V5_S3_MEM_B
1
C3070 1
C3071 1 C3072 1 C3073 1 C3074 1 C3075 1 C3076 1 C3077 1 C3078 1 C3079 1 C3080 1 C3081 1 C3082 1 C3083 1 C3084 1 C3085 1 C3086 1 C3087 1 C3088 1 C3089
10UF 10UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2
6 3V
X5R 2
6 3V
X5R 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
603 603 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

PAGE TITLE
MEMORY CAPS
DRAWING NUMBER SIZE

REVISION
R
10.1.0
30 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP0V75_S3_MEM_VREFDQ_A 1A 2A PP0V75_S3_MEM_VREFDQ_A 1B 2B
98 30 28 VREFDQ
CRITICALVSS_0
98 30 28 VREFDQCRITICAL VSS_0
3A 4A =MEM_A_DQ<4> 3B 4B =MEM_A_DQ<4>
VSS_1 DQ4 VSS_1 DQ4
32 30 =MEM_A_DQ<0> 5A
DQ0 J3100 DQ5
6A =MEM_A_DQ<5>
30 32
30 32 32 30 =MEM_A_DQ<0> 5B
DQ0
J3100 DQ5
6B =MEM_A_DQ<5>
30 32
30 32
DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD) DIMM2 SPD ADDR=0XA2(WR)/0XA3(RD)
7A F-RT-TH 8A 7B F-RT-TH 8B
32 30 =MEM_A_DQ<1> DQ1 VSS_2 32 30 =MEM_A_DQ<1> DQ1 VSS_2 30 MEM_DIMM0_SA<1> 47 30 6 =PPSPD_S0_MEM_A
9A (1 OF 2) 10A =MEM A DQS N<0> 9B (2 OF 2) 10B =MEM A DQS N<0>
DDR3-SODIMM-DUAL
VSS_3 DQS0* 30 32 VSS_3 DQS0* 30 32
DDR3-SODIMM-DUAL
11A 12A 11B 12B 30 MEM_DIMM0_SA<0>
DM0 DQS0 =MEM_A_DQS_P<0> 30 32 DM0 DQS0 =MEM_A_DQS_P<0> 30 32
1
13A 14A 13B 14B R3142
VSS_4 VSS_5 VSS_4 VSS_5 1 1 10K
32 30 =MEM_A_DQ<2> 15A
DQ2 DQ6
16A =MEM_A_DQ<6> 30 32 32 30 =MEM_A_DQ<2> 15B
DQ2 DQ6
16B =MEM_A_DQ<6> 30 32
R3140 R3141 5%
17A 18A 17B 18B 10K 10K 1/16W
32 30 =MEM_A_DQ<3> DQ3 DQ7 =MEM_A_DQ<7> 30 32 32 30 =MEM_A_DQ<3> DQ3 DQ7 =MEM_A_DQ<7> 30 32 5% 5% MF LF
19A 20A 19B 20B 1/16W 1/16W 402
2
VSS_6 VSS_7 VSS_6 VSS_7 MF LF MF LF
21A 22A 21B 22B 402 402
=MEM_A_DQ<8> =MEM_A_DQ<12> =MEM_A_DQ<8> =MEM_A_DQ<12> 2 2
32 30 DQ8 DQ12 30 32 32 30 DQ8 DQ12 30 32
MEM_DIMM2_SA<0>
=MEM A DQ<9> 23A 24A =MEM A DQ<13> =MEM A DQ<9> 23B 24B =MEM A DQ<13>
30
32 30 DQ9 DQ13 30 32 32 30 DQ9 DQ13 30 32
D 25A
27A
VSS_8 VSS_9
26A
28A
25B
27B
VSS_8 VSS_9
26B
28B
30 MEM DIMM2 SA<1> D
32 30 =MEM_A_DQS_N<1> DQS1* DM1 32 30 =MEM_A_DQS_N<1> DQS1* DM1
=MEM_A_DQS_P<1> 29A 30A MEM_RESET_L =MEM_A_DQS_P<1> 29B 30B MEM_RESET_L
32 30 DQS1 RESET* 30 31 32 92 100 32 30 DQS1 RESET* 30 31 32 92 100
31A 32A 31B 32B 1
VSS_10 VSS_11 VSS_10 VSS_11 R3143
=MEM_A_DQ<10> 33A 34A =MEM_A_DQ<14> =MEM_A_DQ<10> 33B 34B =MEM_A_DQ<14> 10K
32 30 DQ10 DQ14 30 32 32 30 DQ10 DQ14 30 32
35A 36A 35B 36B 5%
32 30 =MEM_A_DQ<11> DQ11 DQ15 =MEM_A_DQ<15> 30 32 32 30 =MEM_A_DQ<11> DQ11 DQ15 =MEM_A_DQ<15> 30 32 1/16W
37A 38A 37B 38B MF LF
VSS_12 VSS_13 VSS_12 VSS_13 2
402
32 30 DQ16 DQ20 30 32 32 30 DQ16 DQ20 30 32
32 30 DQ17 DQ21 30 32 32 30 DQ17 DQ21 30 32
=PPSPD_S0_MEM_A
43A 44A 43B 44B 47 30 6
VSS_14 VSS_15 VSS_14 VSS_15
=MEM_A_DQS_N<2> 45A 46A =MEM_A_DQS_N<2> 45B 46B
32 30 DQS2* DM2 32 30 DQS2* DM2
=MEM_A_DQS_P<2> 47A 48A =MEM_A_DQS_P<2> 47B 48B 1
C3140
32 30 DQS2 VSS_16 32 30 DQS2 VSS_16
49A 50A =MEM_A_DQ<22> 49B 50B =MEM_A_DQ<22> 2.2UF
VSS_17 DQ22 30 32 VSS_17 DQ22 30 32
20%
=MEM_A_DQ<18> 51A 52A =MEM_A_DQ<23> =MEM_A_DQ<18> 51B 52B =MEM_A_DQ<23> 6 3V
32 30 DQ18 DQ23 30 32 32 30 DQ18 DQ23 30 32 2 CERM
=MEM_A_DQ<19> 53A 54A =MEM_A_DQ<19> 53B 54B 402 LF
32 30 DQ19 VSS_18 32 30 DQ19 VSS_18
55A 56A =MEM A DQ<28> 55B 56B =MEM A DQ<28>
VSS_19 DQ28 30 32 VSS_19 DQ28 30 32
32 30 DQ24 DQ29 30 32 32 30 DQ24 DQ29 30 32
=MEM_A_DQ<25> 59A 60A =MEM_A_DQ<25> 59B 60B

32 30 DQ25 VSS_20 32 30 DQ25 VSS_20
61A 62A =MEM_A_DQS_N<3> 61B 62B =MEM_A_DQS_N<3>
VSS_21 DQS3* 30 32 VSS_21 DQS3* 30 32
63A 64A =MEM_A_DQS_P<3> 63B 64B =MEM_A_DQS_P<3>
DM3 DQS3 30 32 DM3 DQS3 30 32
PP0V75 S3 MEM VREFCA A
98 30 28
65A 66A 65B 66B
=MEM_A_DQ<26> 67A 68A =MEM_A_DQ<30> =MEM_A_DQ<26> 67B 68B =MEM_A_DQ<30>
32 30 DQ26 DQ30 30 32 32 30 DQ26 DQ30 30 32

32 30 DQ27 DQ31 30 32 32 30 DQ27 DQ31 30 32
71A 72A 71B 72B
KEY KEY
1
C3135 1
C3136
MEM_A_CKE<2> 73A 74A MEM_A_CKE<3> MEM_A_CKE<0> 73B 74B MEM_A_CKE<1> 2.2UF 0.1UF
92 12 CKE0 CKE1 12 92 92 12 CKE0 CKE1 12 92
20% 20%
=PP1V5_S3_MEM_A 75A 76A =PP1V5_S3_MEM_A =PP1V5_S3_MEM_A 75B 76B =PP1V5_S3_MEM_A 6 3V 10V
30 29 28 6 VDD_0 VDD_1 6 28 29 30 30 29 28 6 VDD_0 VDD_1 6 28 29 30 2 2
C MEM A BA<2>
77A
79A
NC_0 A15
78A
80A
MEM_A_A<15>
MEM A A<14>
12 30 92
MEM A BA<2>
77B
79B
NC_0 A15
78B
80B
MEM_A_A<15>
MEM A A<14>
12 30 92
CERM
402 LF
CERM
402
C
92 30 12 BA2 A14 12 30 92 92 30 12 BA2 A14 12 30 92
81A 82A 81B 82B
VDD_2 VDD_3 VDD_2 VDD_3
MEM_A_A<12> 83A 84A MEM_A_A<11> MEM_A_A<12> 83B 84B MEM_A_A<11>
92 30 12 A12/BC* A11 12 30 92 92 30 12 A12/BC* A11 12 30 92
MEM_A_A<9> 85A 86A MEM_A_A<7> MEM_A_A<9> 85B 86B MEM_A_A<7> PP0V75_S3_MEM_VREFDQ_A

92 30 12 A9 A7 12 30 92 92 30 12 A9 A7 12 30 92 98 30 28
87A 88A 87B 88B
DIMM 2
DIMM 0
92 30 12 A8 A6 12 30 92 92 30 12 A8 A6 12 30 92

92 30 12 A5 A4 12 30 92 92 30 12 A5 A4 12 30 92
1
C3130 1
C3131
93A 94A 93B 94B
VDD_6 VDD_7 VDD_6 VDD_7 2.2UF 0.1UF
MEM A A<3> 95A 96A MEM A A<2> MEM A A<3> 95B 96B MEM A A<2> 20% 20%
92 30 12 A3 A2 12 30 92 92 30 12 A3 A2 12 30 92 6 3V 10V
97A 98A 97B 98B 2 CERM 2 CERM
92 30 12 MEM_A_A<1> A1 A0 MEM_A_A<0> 12 30 92 92 30 12 MEM_A_A<1> A1 A0 MEM_A_A<0> 12 30 92 402 LF 402
99A 100A 99B 100B
=MEM_A_CLK_P<2> 101A 102A =MEM_A_CLK_P<3> =MEM_A_CLK_P<0> 101B 102B =MEM_A_CLK_P<1>
32 CK0 CK1 32 32 CK0 CK1 32
=MEM_A_CLK_N<2> 103A 104A =MEM_A_CLK_N<3> =MEM_A_CLK_N<0> 103B 104B =MEM_A_CLK_N<1>

32 CK0* CK1* 32 32 CK0* CK1* 32
105A 106A 105B 106B
VDD_10 VDD_11 VDD_10 VDD_11 =PP0V75_S0_MEM_VTT_A
MEM_A_A<10> 107A 108A MEM_A_BA<1> MEM_A_A<10> 107B 108B MEM_A_BA<1>
30 6
92 30 12 A10_AP BA1 12 30 92 92 30 12 A10_AP BA1 12 30 92
MEM_A_BA<0> 109A 110A MEM_A_RAS_L MEM_A_BA<0> 109B 110B MEM_A_RAS_L

92 30 12 BA0 RAS* 12 30 92 92 30 12 BA0 RAS* 12 30 92
111A 112A 111B 112B
MEM_A_WE_L 113A 114A MEM_A_CS_L<2> MEM_A_WE_L 113B 114B MEM_A_CS_L<0> 1
C3150 1
C3151
92 30 12 WE* S0* 12 92 92 30 12 WE* S0* 12 92
MEM_A_CAS_L 115A 116A MEM_A_ODT<2> MEM_A_CAS_L 115B 116B MEM_A_ODT<0> 2.2UF 2.2UF
92 30 12 CAS* ODT0 12 92 92 30 12 CAS* ODT0 12 92
20% 20%
117A 118A 117B 118B 6 3V 6 3V
VDD_14 VDD_15 VDD_14 VDD_15 2 CERM 2 CERM
MEM_A_A<13> 119A 120A MEM_A_ODT<3> MEM_A_A<13> 119B 120B MEM_A_ODT<1> 402 LF 402 LF
92 30 12 A13 ODT1 12 92 92 30 12 A13 ODT1 12 92
MEM_A_CS_L<3> 121A 122A MEM_A_CS_L<1> 121B 122B

92 12 S1* NC_1 92 12 S1* NC_1
123A 124A 123B 124B
125A 126A PP0V75 S3 MEM VREFCA A 125B 126B PP0V75 S3 MEM VREFCA A
TEST VREFCA 28 30 98 TEST VREFCA 28 30 98
127A 128A 127B 128B STACKED SO-DIMM CONN.
129A 130A 129B 130B
B 32 30
32 30
=MEM_A_DQ<32>
=MEM_A_DQ<33> 131A
DQ32
DQ33
DQ36
DQ37
132A
=MEM_A_DQ<36>
=MEM_A_DQ<37>
30 32
30 32
32 30
32 30
=MEM_A_DQ<32>
=MEM_A_DQ<33> 131B
DQ32
DQ33
DQ36
DQ37
132B
=MEM_A_DQ<36>
=MEM_A_DQ<37>
30 32
30 32
DIMM2 B
133A 134A 133B 134B (Section A)
=MEM_A_DQS_N<4> 135A 136A =MEM_A_DQS_N<4> 135B 136B DIMM0
32 30 DQS4* DM4 32 30 DQS4* DM4
=MEM_A_DQS_P<4> 137A 138A =MEM_A_DQS_P<4> 137B 138B (Section B)
32 30 DQS4 VSS_30 32 30 DQS4 VSS_30
VSS_31 DQ38 30 32 VSS_31 DQ38 30 32
32 30 DQ34 DQ39 30 32 32 30 DQ34 DQ39 30 32
=MEM A DQ<35> 143A 144A =MEM A DQ<35> 143B 144B

32 30 DQ35 VSS_32 32 30 DQ35 VSS_32
145A 146A 145B 146B CPU - MEM Ch. A
VSS_33 DQ44 =MEM_A_DQ<44> 30 32 VSS_33 DQ44 =MEM_A_DQ<44> 30 32

32 30 DQ40 DQ45 30 32 32 30 DQ40 DQ45 30 32
=MEM_A_DQ<41> 149A 150A =MEM_A_DQ<41> 149B 150B

32 30 DQ41 VSS_34 32 30 DQ41 VSS_34
151A 152A =MEM_A_DQS_N<5> 151B 152B =MEM_A_DQS_N<5>
153A
VSS_35
DM5
DQS5*
DQS5
154A =MEM_A_DQS_P<5>
30 32
30 32
153B
VSS_35
DM5
DQS5*
DQS5
154B =MEM_A_DQS_P<5>
30 32
30 32
Page Notes
155A 156A 155B 156B
157A 158A 157B 158B Power aliases required by this page
32 30 =MEM A DQ<42> DQ42 DQ46 =MEM A DQ<46> 30 32 32 30 =MEM A DQ<42> DQ42 DQ46 =MEM A DQ<46> 30 32
159A 160A 159B 160B =PP1V5 S0 MEM A
161A 162A 161B 162B =PP1V5 S3 MEM A
163A 164A 163B 164B =PP0V75 S0 MEM VTT A
32 30 =MEM_A_DQ<48> DQ48 DQ52 =MEM_A_DQ<52> 30 32 32 30 =MEM_A_DQ<48> DQ48 DQ52 =MEM_A_DQ<52> 30 32
165A 166A 165B 166B =PPSPD S0 MEM A (2 5 3 3V)
32 30 =MEM_A_DQ<49> DQ49 DQ53 =MEM_A_DQ<53> 30 32 32 30 =MEM_A_DQ<49> DQ49 DQ53 =MEM_A_DQ<53> 30 32
167A 168A 167B 168B Signal aliases required by this page
=MEM_A_DQS_N<6> 169A 170A =MEM_A_DQS_N<6> 169B 170B =I2C SODIMMA SCL ALL DQ DQS DM SIGNALS
32 30 DQS6* DM6 32 30 DQS6* DM6 TO FACILITATE BITSWAPS WITH ALIASES
=MEM_A_DQS_P<6> 171A 172A =MEM_A_DQS_P<6> 171B 172B =I2C SODIMMA SDA
32 30 DQS6 VSS_42 32 30 DQS6 VSS_42
VSS_43 DQ54 30 32 VSS_43 DQ54 30 32
175A 176A 175B 176B BOM options provided by this page
177A 178A 177B 178B (NONE)
32 30 =MEM_A_DQ<51> DQ51 VSS_44 32 30 =MEM_A_DQ<51> DQ51 VSS_44
179A 180A =MEM_A_DQ<60> 179B 180B =MEM_A_DQ<60>
VSS_45 DQ60 30 32 VSS_45 DQ60 30 32
A 32 30 =MEM_A_DQ<56>
=MEM_A_DQ<57>
181A
183A
DQ56 DQ61
182A
184A
=MEM_A_DQ<61> 30 32 32 30 =MEM_A_DQ<56>
=MEM_A_DQ<57>
181B
183B
DQ56 DQ61
182B
184B
=MEM_A_DQ<61> 30 32
32 30 DQ57 VSS_46 32 30 DQ57 VSS_46 PAGE TITLE
185A 186A 185B 186B
187A
VSS_47
DM7
DQS7*
DQS7
188A
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
30 32
30 32
187B
VSS_47
DM7
DQS7*
DQS7
188B
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
30 32
30 32
DDR3 SO-DIMM 0 & 2
189A 190A 189B 190B DRAWING NUMBER SIZE
VSS_48 VSS_49 VSS_48 VSS_49 051-8442 D
32 30 =MEM A DQ<58> 191A
DQ58 DQ62
192A =MEM A DQ<62> 30 32 32 30 =MEM A DQ<58> 191B
DQ58 DQ62
192B =MEM A DQ<62> 30 32 Apple Inc. REVISION
32 30 DQ59 DQ63 30 32 32 30 DQ59 DQ63 30 32 R
195A 196A 195B 196B 10.1.0
VSS_50 VSS_51 VSS_50 VSS_51 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MEM_DIMM2_SA<0> 197A 198A MEM_EVENT_L MEM_DIMM0_SA<0> 197B 198B MEM_EVENT_L
30 SA0 EVENT* 30 31 47 30 SA0 EVENT* 30 31 47
199A 200A 199B 200B THE INFORMATION CONTAINED HEREIN IS THE
47 30 6 =PPSPD_S0_MEM_A VDDSPD SDA =I2C_SODIMMA_SDA 30 49 47 30 6 =PPSPD_S0_MEM_A VDDSPD SDA =I2C_SODIMMA_SDA 30 49 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
201A 202A 201B 202B THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MEM_DIMM2_SA<1> SA1 SCL =I2C_SODIMMA_SCL MEM_DIMM0_SA<1> SA1 SCL =I2C_SODIMMA_SCL
30
=PP0V75_S0_MEM_VTT_A 203A 204A =PP0V75_S0_MEM_VTT_A

30 49 30
=PP0V75_S0_MEM_VTT_A 203B 204B =PP0V75_S0_MEM_VTT_A

30 49
31 OF 110
30 6 VTT_0 VTT_1 6 30 30 6 VTT_0 VTT_1 6 30
409
MTG PIN MTG PIN
410 IV ALL RIGHTS RESERVED 30 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP0V75_S3_MEM_VREFDQ_B 1A 2A PP0V75_S3_MEM_VREFDQ_B 1B 2B
98 31 28 VREFDQ
CRITICALVSS_0
98 31 28 VREFDQ
CRITICALVSS_0
3A 4A =MEM_B_DQ<4> 3B 4B =MEM_B_DQ<4>
VSS_1 DQ4 VSS_1 DQ4
32 31 =MEM_B_DQ<0> 5A
DQ0 J3200 DQ5
6A =MEM_B_DQ<5>
31 32
31 32 32 31 =MEM_B_DQ<0> 5B
DQ0
J3200 DQ5
6B =MEM_B_DQ<5>
31 32
31 32
DIMM1 SPD ADDR=0XA4(WR)/0XA5(RD) DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)
7A F-RT-TH 8A 7B F-RT-TH 8B
32 31 =MEM_B_DQ<1> DQ1 VSS_2 32 31 =MEM_B_DQ<1> DQ1 VSS_2 31 6 =PPSPD_S0_MEM_B 31 6 =PPSPD_S0_MEM_B
9A (1 OF 2) 10A =MEM B DQS N<0> 9B (2 OF 2) 10B =MEM B DQS N<0>
DDR3-SODIMM-DUAL
VSS_3 DQS0* 31 32 VSS_3 DQS0* 31 32
DDR3-SODIMM-DUAL
11A 12A =MEM_B_DQS_P<0> 11B 12B =MEM_B_DQS_P<0>
DM0 DQS0 31 32 DM0 DQS0 31 32
1 1 1
13A 14A 13B 14B R3240 R3242 R3243
VSS_4 VSS_5 VSS_4 VSS_5 10K 10K 10K
=MEM_B_DQ<2> 15A 16A =MEM_B_DQ<6> =MEM_B_DQ<2> 15B 16B =MEM_B_DQ<6>
32 31 DQ2 DQ6 31 32 32 31 DQ2 DQ6 31 32 5% 5% 5%
17A 18A 17B 18B 1/16W 1/16W 1/16W
32 31 =MEM_B_DQ<3> DQ3 DQ7 =MEM_B_DQ<7> 31 32 32 31 =MEM_B_DQ<3> DQ3 DQ7 =MEM_B_DQ<7> 31 32 MF LF MF LF MF LF
19A 20A 19B 20B 402 402 402
2 2 2
32 31 DQ8 DQ12 31 32 32 31 DQ8 DQ12 31 32
MEM_DIMM3_SA<1>
=MEM B DQ<9> 23A 24A =MEM B DQ<13> =MEM B DQ<9> 23B 24B =MEM B DQ<13> MEM DIMM1 SA<1>
31
32 31 DQ9 DQ13 31 32 32 31 DQ9 DQ13 31 32 31
D 25A
27A
VSS_8 VSS_9
26A
28A
25B
27B
VSS_8 VSS_9
26B
28B
31 MEM DIMM1 SA<0> 31 MEM DIMM3 SA<0> D
32 31 =MEM_B_DQS_N<1> DQS1* DM1 32 31 =MEM_B_DQS_N<1> DQS1* DM1
=MEM_B_DQS_P<1> 29A 30A MEM_RESET_L =MEM_B_DQS_P<1> 29B 30B MEM_RESET_L
32 31 DQS1 RESET* 30 31 32 92 100 32 31 DQS1 RESET* 30 31 32 92 100
1
31A
VSS_10 VSS_11
32A 31B
VSS_10 VSS_11
32B R3241
33A 34A 33B 34B 10K
32 31 =MEM_B_DQ<10> DQ10 DQ14 =MEM_B_DQ<14> 31 32 32 31 =MEM_B_DQ<10> DQ10 DQ14 =MEM_B_DQ<14> 31 32 5%
35A 36A 35B 36B 1/16W
32 31 =MEM_B_DQ<11> DQ11 DQ15 =MEM_B_DQ<15> 31 32 32 31 =MEM_B_DQ<11> DQ11 DQ15 =MEM_B_DQ<15> 31 32 MF LF
37A 38A 37B 38B 402
2
=MEM B DQ<16> 39A 40A =MEM B DQ<20> =MEM B DQ<16> 39B 40B =MEM B DQ<20>
32 31 DQ16 DQ20 31 32 32 31 DQ16 DQ20 31 32
32 31 DQ17 DQ21 31 32 32 31 DQ17 DQ21 31 32
43A 44A 43B 44B
VSS_14 VSS_15 VSS_14 VSS_15 =PPSPD_S0_MEM_B
=MEM_B_DQS_N<2> 45A 46A =MEM_B_DQS_N<2> 45B 46B 31 6
32 31 DQS2* DM2 32 31 DQS2* DM2
=MEM_B_DQS_P<2> 47A 48A =MEM_B_DQS_P<2> 47B 48B
32 31 DQS2 VSS_16 32 31 DQS2 VSS_16
VSS_17 DQ22 31 32 VSS_17 DQ22 31 32

1
C3240
32 31 DQ18 DQ23 31 32 32 31 DQ18 DQ23 31 32
2.2UF
=MEM_B_DQ<19> 53A 54A =MEM_B_DQ<19> 53B 54B 20%
32 31 DQ19 VSS_18 32 31 DQ19 VSS_18 6 3V
55A 56A 55B 56B 2 CERM
VSS_19 DQ28 =MEM B DQ<28> 31 32 VSS_19 DQ28 =MEM B DQ<28> 31 32 402 LF
32 31 DQ24 DQ29 31 32 32 31 DQ24 DQ29 31 32
=MEM_B_DQ<25> 59A 60A =MEM_B_DQ<25> 59B 60B

32 31 DQ25 VSS_20 32 31 DQ25 VSS_20
61A 62A =MEM_B_DQS_N<3> 61B 62B =MEM_B_DQS_N<3>
VSS_21 DQS3* 31 32 VSS_21 DQS3* 31 32
63A 64A =MEM_B_DQS_P<3> 63B 64B =MEM_B_DQS_P<3>
DM3 DQS3 31 32 DM3 DQS3 31 32
65A 66A 65B 66B
VSS_22 VSS_23 VSS_22 VSS_23 PP0V75 S3 MEM VREFCA B
98 31 28
32 31 DQ26 DQ30 31 32 32 31 DQ26 DQ30 31 32

32 31 DQ27 DQ31 31 32 32 31 DQ27 DQ31 31 32
71A 72A 71B 72B
73A KEY 74A 73B KEY 74B
92 12 MEM_B_CKE<2> CKE0 CKE1 MEM_B_CKE<3> 12 92 92 12 MEM_B_CKE<0> CKE0 CKE1 MEM_B_CKE<1> 12 92
1
C3235 1
C3236
=PP1V5_S3_MEM_B 75A 76A =PP1V5_S3_MEM_B =PP1V5_S3_MEM_B 75B 76B =PP1V5_S3_MEM_B 2.2UF 0.1UF
31 29 28 6 VDD_0 VDD_1 6 28 29 31 31 29 28 6 VDD_0 VDD_1 6 28 29 31
C MEM B BA<2>
77A
79A
NC_0 A15
78A
80A
MEM_B_A<15>
MEM B A<14>
12 31 92
MEM B BA<2>
77B
79B
NC_0 A15
78B
80B
MEM_B_A<15>
MEM B A<14>
12 31 92 2
20%
6 3V
CERM
402 LF
2
20%
10V
CERM
402
C
92 31 12 BA2 A14 12 31 92 92 31 12 BA2 A14 12 31 92
81A 82A 81B 82B
MEM_B_A<12> 83A 84A MEM_B_A<11> MEM_B_A<12> 83B 84B MEM_B_A<11>
92 31 12 A12/BC* A11 12 31 92 92 31 12 A12/BC* A11 12 31 92

92 31 12 A9 A7 12 31 92 92 31 12 A9 A7 12 31 92
87A 88A 87B 88B
DIMM 3
DIMM 1
VDD_4 VDD_5 VDD_4 VDD_5 98 31 28 PP0V75_S3_MEM_VREFDQ_B
92 31 12 A8 A6 12 31 92 92 31 12 A8 A6 12 31 92

92 31 12 A5 A4 12 31 92 92 31 12 A5 A4 12 31 92
93A 94A 93B 94B
MEM B A<3> 95A 96A MEM B A<2> MEM B A<3> 95B 96B MEM B A<2>
1
C3230 1
C3231
92 31 12 A3 A2 12 31 92 92 31 12 A3 A2 12 31 92
2.2UF 0.1UF
MEM_B_A<1> 97A 98A MEM_B_A<0> MEM_B_A<1> 97B 98B MEM_B_A<0> 20% 20%
92 31 12 A1 A0 12 31 92 92 31 12 A1 A0 12 31 92
2
6 3V
2
10V
99A 100A 99B 100B CERM CERM
VDD_8 VDD_9 VDD_8 VDD_9 402 LF 402
=MEM_B_CLK_P<2> 101A 102A =MEM_B_CLK_P<3> =MEM_B_CLK_P<0> 101B 102B =MEM_B_CLK_P<1>
32 CK0 CK1 32 32 CK0 CK1 32
=MEM_B_CLK_N<2> 103A 104A =MEM_B_CLK_N<3> =MEM_B_CLK_N<0> 103B 104B =MEM_B_CLK_N<1>

32 CK0* CK1* 32 32 CK0* CK1* 32
105A 106A 105B 106B
MEM_B_A<10> 107A 108A MEM_B_BA<1> MEM_B_A<10> 107B 108B MEM_B_BA<1>
92 31 12 A10_AP BA1 12 31 92 92 31 12 A10_AP BA1 12 31 92
31 6 =PP0V75_S0_MEM_VTT_B
MEM_B_BA<0> 109A 110A MEM_B_RAS_L MEM_B_BA<0> 109B 110B MEM_B_RAS_L
92 31 12 BA0 RAS* 12 31 92 92 31 12 BA0 RAS* 12 31 92
111A 112A 111B 112B
MEM_B_WE_L 113A 114A MEM_B_CS_L<2> MEM_B_WE_L 113B 114B MEM_B_CS_L<0>
92 31 12 WE* S0* 12 92 92 31 12 WE* S0* 12 92
MEM_B_CAS_L 115A 116A MEM_B_ODT<2> MEM_B_CAS_L 115B 116B MEM_B_ODT<0> 1

C3250 1
C3251
92 31 12 CAS* ODT0 12 92 92 31 12 CAS* ODT0 12 92
117A 118A 117B 118B 2.2UF 2.2UF
VDD_14 VDD_15 VDD_14 VDD_15 20% 20%
MEM_B_A<13> 119A 120A MEM_B_ODT<3> MEM_B_A<13> 119B 120B MEM_B_ODT<1> 6 3V 6 3V
92 31 12 A13 ODT1 12 92 92 31 12 A13 ODT1 12 92 2 CERM 2 CERM
MEM_B_CS_L<3> 121A 122A MEM_B_CS_L<1> 121B 122B 402 LF 402 LF
92 12 S1* NC_1 92 12 S1* NC_1
123A 124A 123B 124B
125A 126A PP0V75 S3 MEM VREFCA B 125B 126B PP0V75 S3 MEM VREFCA B
TEST VREFCA 28 31 98 TEST VREFCA 28 31 98
127A 128A 127B 128B STACKED SO-DIMM CONN.
129A 130A 129B 130B
B 32 31
32 31
=MEM_B_DQ<32>
=MEM_B_DQ<33> 131A
DQ32
DQ33
DQ36
DQ37
132A
=MEM_B_DQ<36>
=MEM_B_DQ<37>
31 32
31 32
32 31
32 31
=MEM_B_DQ<32>
=MEM_B_DQ<33> 131B
DQ32
DQ33
DQ36
DQ37
132B
=MEM_B_DQ<36>
=MEM_B_DQ<37>
31 32
31 32
DIMM3 B
133A 134A 133B 134B (Section A)
=MEM_B_DQS_N<4> 135A 136A =MEM_B_DQS_N<4> 135B 136B DIMM1
32 31 DQS4* DM4 32 31 DQS4* DM4
=MEM_B_DQS_P<4> 137A 138A =MEM_B_DQS_P<4> 137B 138B (Section B)
32 31 DQS4 VSS_30 32 31 DQS4 VSS_30
139A 140A =MEM B DQ<38> 139B 140B =MEM B DQ<38>
VSS_31 DQ38 31 32 VSS_31 DQ38 31 32
32 31 DQ34 DQ39 31 32 32 31 DQ34 DQ39 31 32
=MEM B DQ<35> 143A 144A =MEM B DQ<35> 143B 144B

32 31 DQ35 VSS_32 32 31 DQ35 VSS_32
145A 146A 145B 146B CPU - MEM Ch. B
VSS_33 DQ44 =MEM_B_DQ<44> 31 32 VSS_33 DQ44 =MEM_B_DQ<44> 31 32

32 31 DQ40 DQ45 31 32 32 31 DQ40 DQ45 31 32
=MEM_B_DQ<41> 149A 150A =MEM_B_DQ<41> 149B 150B

32 31 DQ41 VSS_34 32 31 DQ41 VSS_34
151A 152A =MEM_B_DQS_N<5> 151B 152B =MEM_B_DQS_N<5>
153A
VSS_35
DM5
DQS5*
DQS5
154A =MEM_B_DQS_P<5>
31 32
31 32
153B
VSS_35
DM5
DQS5*
DQS5
154B =MEM_B_DQS_P<5>
31 32
31 32
Page Notes
155A 156A 155B 156B
157A 158A 157B 158B Power aliases required by this page
32 31 =MEM B DQ<42> DQ42 DQ46 =MEM B DQ<46> 31 32 32 31 =MEM B DQ<42> DQ42 DQ46 =MEM B DQ<46> 31 32
159A 160A 159B 160B =PP1V5 S0 MEM B
161A 162A 161B 162B =PP1V5 S3 MEM B
163A 164A 163B 164B =PP0V75 S0 MEM VTT B
32 31 =MEM_B_DQ<48> DQ48 DQ52 =MEM_B_DQ<52> 31 32 32 31 =MEM_B_DQ<48> DQ48 DQ52 =MEM_B_DQ<52> 31 32
165A 166A 165B 166B =PPSPD S0 MEM B (2 5 3 3V)
32 31 =MEM_B_DQ<49> DQ49 DQ53 =MEM_B_DQ<53> 31 32 32 31 =MEM_B_DQ<49> DQ49 DQ53 =MEM_B_DQ<53> 31 32
167A 168A 167B 168B Signal aliases required by this page
=MEM_B_DQS_N<6> 169A 170A =MEM_B_DQS_N<6> 169B 170B =I2C SODIMMB SCL ALL DQ DQS DM SIGNALS
32 31 DQS6* DM6 32 31 DQS6* DM6 TO FACILITATE BITSWAPS WITH ALIASES
=MEM_B_DQS_P<6> 171A 172A =MEM_B_DQS_P<6> 171B 172B =I2C SODIMMB SDA
32 31 DQS6 VSS_42 32 31 DQS6 VSS_42
173A 174A =MEM B DQ<54> 173B 174B =MEM B DQ<54>
VSS_43 DQ54 31 32 VSS_43 DQ54 31 32
175A 176A 175B 176B BOM options provided by this page
177A 178A 177B 178B (NONE)
32 31 =MEM_B_DQ<51> DQ51 VSS_44 32 31 =MEM_B_DQ<51> DQ51 VSS_44
VSS_45 DQ60 31 32 VSS_45 DQ60 31 32
A 32 31 =MEM_B_DQ<56>
=MEM_B_DQ<57>
181A
183A
DQ56 DQ61
182A
184A
=MEM_B_DQ<61> 31 32 32 31 =MEM_B_DQ<56>
=MEM_B_DQ<57>
181B
183B
DQ56 DQ61
182B
184B
=MEM_B_DQ<61> 31 32
32 31 DQ57 VSS_46 32 31 DQ57 VSS_46 PAGE TITLE
185A 186A 185B 186B
187A
VSS_47
DM7
DQS7*
DQS7
188A
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
31 32
31 32
187B
VSS_47
DM7
DQS7*
DQS7
188B
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
31 32
31 32
DDR3 SO-DIMM 1 & 3
189A 190A 189B 190B DRAWING NUMBER SIZE
VSS_48 VSS_49 VSS_48 VSS_49 051-8442 D
32 31 =MEM B DQ<58> 191A
DQ58 DQ62
192A =MEM B DQ<62> 31 32 32 31 =MEM B DQ<58> 191B
DQ58 DQ62
192B =MEM B DQ<62> 31 32 Apple Inc. REVISION
32 31 DQ59 DQ63 31 32 32 31 DQ59 DQ63 31 32 R
195A 196A 195B 196B 10.1.0
VSS_50 VSS_51 VSS_50 VSS_51 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MEM_DIMM3_SA<0> 197A 198A MEM_EVENT_L MEM_DIMM1_SA<0> 197B 198B MEM_EVENT_L
31 SA0 EVENT* 30 31 47 31 SA0 EVENT* 30 31 47
199A 200A 199B 200B THE INFORMATION CONTAINED HEREIN IS THE
31 6 =PPSPD_S0_MEM_B VDDSPD SDA =I2C_SODIMMB_SDA 31 49 31 6 =PPSPD_S0_MEM_B VDDSPD SDA =I2C_SODIMMB_SDA 31 49 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
201A 202A 201B 202B THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MEM_DIMM3_SA<1> SA1 SCL =I2C_SODIMMB_SCL MEM_DIMM1_SA<1> SA1 SCL =I2C_SODIMMB_SCL
31
=PP0V75_S0_MEM_VTT_B 203A 204A =PP0V75_S0_MEM_VTT_B

31 49 31
=PP0V75_S0_MEM_VTT_B 203B 204B =PP0V75_S0_MEM_VTT_B

31 49
32 OF 110
31 6 VTT_0 VTT_1 6 31 31 6 VTT_0 VTT_1 6 31
409
MTG PIN MTG PIN
410 IV ALL RIGHTS RESERVED 31 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU CHANNEL A DQS 0 -> DIMM A DQS 7 CPU CHANNEL B DQS 0 -> DIMM B DQS 7
DDR3 RESET SUPPORT S5
CPU_RESET_L
0
ISOLATE_L
3.3V
MEM_RESET_L
0
SNB? CANNOT CONTROL THIS SIGNAL DIRECTLY SINCE IT MUST BE HIGH IN SLEEP AND CPU MEM RAILS ARE NOT POWERED IN SLEEP.
92 12 MEM_A_DQS_N<0> =MEM_A_DQS_N<7> 30 92 12 MEM_B_DQS_N<0> =MEM_B_DQS_N<7> 31
S0 0 3.3V 0
92 12 MEM_A_DQS_P<0> =MEM_A_DQS_P<7> 30 92 12 MEM_B_DQS_P<0> =MEM_B_DQS_P<7> 31
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE S0 1.5V 3.3V 1.5V
92 12 MEM_A_DQ<7> =MEM_A_DQ<57> MEM_B_DQ<7> =MEM_B_DQ<61> 32 6 =PP3V3_S3_MEMRESET 32 6 =PP5V_S3_MEMRESET 6 =PP1V5_S3_MEMRESET
30 92 12 31
MAKE_BASE=TRUE MAKE_BASE=TRUE S3 0 0 1.5V
92 12 MEM A DQ<6> =MEM A DQ<56> 30 92 12 MEM B DQ<6> =MEM B DQ<60> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
R33501
1
92 12 MEM_A_DQ<5> =MEM_A_DQ<58> 30 92 12 MEM_B_DQ<5> =MEM_B_DQ<62> 31 R3351 R33521 NOSTUFF 1
S0 1.5V 3.3V 1.5V
MAKE_BASE=TRUE MAKE_BASE=TRUE R3353
92 12 MEM_A_DQ<4>
MAKE_BASE=TRUE
=MEM_A_DQ<59> 30 92 12 MEM_B_DQ<4>
MAKE_BASE=TRUE
=MEM_B_DQ<63> 31
20K
5%
20K
5%
20K
5%
R3355 C3353 1
20K S5 0 3.3V 0
92 12 MEM_A_DQ<3> =MEM_A_DQ<60> 30 92 12 MEM_B_DQ<3> =MEM_B_DQ<56> 31
1/16W 1/16W 1/16W
CPU_MEM_RESET_L 1
0 2
0.0022UF 5%
MAKE_BASE=TRUE MAKE_BASE=TRUE MF LF MF LF MF LF 100 32 11 10% 1/16W
D 92 12
92 12
MEM_A_DQ<2>
MEM_A_DQ<1>
MAKE_BASE=TRUE
=MEM_A_DQ<61>
=MEM_A_DQ<62>
30
30
92 12
92 12
MEM_B_DQ<2>
MEM_B_DQ<1>
MAKE_BASE=TRUE
=MEM_B_DQ<57>
=MEM_B_DQ<58>
31
31
402
2 2 402
ISOLATE CPU MEM

402
2 5%
1/16W
MF-LF
50V
CERM 2
402 2
MF LF
402 D
MAKE_BASE=TRUE MAKE_BASE=TRUE 402
6
CPU CHANNEL A DQS 1 -> DIMM A DQS 6 CPU CHANNEL B DQS 1 -> DIMM B DQS 6 3 2 3 MEM_RESET_L 30 31 92 100
MEM_A_DQS_N<1> =MEM_A_DQS_N<6> MEM_B_DQS_N<1> =MEM_B_DQS_N<6> D S D
92 12
MEM_A_DQS_P<1>
=MEM_A_DQS_P<6>
30 92 12
MEM_B_DQS_P<1>
=MEM_B_DQS_P<6>
31
Q3306 D
Q3306
Q3304
92 12
30 92 12
31
2
2N7002DW-X-G 2N7002 G
32 ISOLATE_CPU_MEM_L_R1 G S SOT 363 2N7002DW-X-G SOT23-HF1
5 G S SOT 363 S R CLK D Q QB
1 L H X X H L
4 ISOLATE CPU MEM 5V L H L X X L H
92 12 MEM_A_DQ<13> =MEM_A_DQ<51> 30 92 12 MEM_B_DQ<13> =MEM_B_DQ<53> 31 L L X X H H
MAKE_BASE=TRUE MAKE_BASE=TRUE H H POSEDGE L L H
92 12 MEM_A_DQ<10> =MEM_A_DQ<53> 30 92 12 MEM_B_DQ<10> =MEM_B_DQ<49> 31 H H POSEDGE H H L
MEM_A_DQ<9> =MEM_A_DQ<55> MEM_B_DQ<9> =MEM_B_DQ<50> =PP3V3_S5_MEMRESET
92 12
MAKE_BASE=TRUE
30 92 12
MAKE_BASE=TRUE
31 32 6
R3385
92 12 MEM_A_DQ<8> =MEM_A_DQ<54> 30 92 12 MEM_B_DQ<8> =MEM_B_DQ<55> 31 0
MAKE_BASE=TRUE MAKE_BASE=TRUE MEM_RESET_HW 100 25 21 ISOLATE_CPU_MEM_L 1 2
CPU CHANNEL A DQS 2 -> DIMM A DQS 5 CPU CHANNEL B DQS 2 -> DIMM B DQS 5 C3300 1 5%
14
MEM_RESET_HW 1/16W
92 12 MEM_A_DQS_N<2> =MEM_A_DQS_N<5> 30 92 12 MEM_B_DQS_N<2> =MEM_B_DQS_N<5> 31
0.1UF MF-LF
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 20% 402 =PP3V3_S5_MEMRESET
MEM_A_DQS_P<2> =MEM_A_DQS_P<5> MEM_B_DQS_P<2> =MEM_B_DQS_P<5> 10V VCC 32 6
CERM 2
92 12
30 92 12
31
402 U3300
MEM A DQ<23> =MEM A DQ<40> MEM B DQ<23> =MEM B DQ<45>
74LVC74ABQ MEM_RESET_HW
1
MEM_RESET_HW
1
92 12
MAKE_BASE=TRUE
30 92 12
MAKE_BASE=TRUE
31
DHVQFN R3381 R3382
4 1SD* 1Q 5 PM SLP S4 D L 32 100 10K 10K
MAKE_BASE=TRUE MAKE_BASE=TRUE 2 1D NOSTUFF 5% 5%
92 12 MEM_A_DQ<21> =MEM_A_DQ<46> 30 92 12 MEM_B_DQ<21> =MEM_B_DQ<42> 31 100 63 47 46 19 5 PM_SLP_S4_L 1Q* 6 TP_PM_SLP_S4_D
R3383 1/16W 1/16W
MAKE_BASE=TRUE MAKE_BASE=TRUE 3 1CP MF LF MF LF
92 12 MEM_A_DQ<20> =MEM_A_DQ<47> 30 92 12 MEM_B_DQ<20> =MEM_B_DQ<47> 31 100 64 19 PM_SYS_PWRGD
ISOLATE CPU MEMHW L 1
0 2 ISOLATE CPU MEM L R1 2 402
2 402
MAKE_BASE=TRUE MAKE_BASE=TRUE 1 1RD* 32
92 12 MEM_A_DQ<19> =MEM_A_DQ<41> 30 92 12 MEM_B_DQ<19> =MEM_B_DQ<44> 31 32 6 =PP3V3_S3_MEMRESET
MAKE_BASE=TRUE MAKE_BASE=TRUE 5%
92 12 MEM_A_DQ<18> =MEM_A_DQ<44> 30 92 12 MEM_B_DQ<18> =MEM_B_DQ<41> 31 10 2SD* 1/16W CPU_MEM_RESET3V3_L
MAKE_BASE=TRUE MAKE_BASE=TRUE 100 32 PM SLP S4 D L 2Q 9 MF-LF 32
92 12 MEM_A_DQ<17> =MEM_A_DQ<43> 30 92 12 MEM_B_DQ<17> =MEM_B_DQ<46> 31 12 2D 402 CPU_MEM_RESET3V3
2Q* 8
C 92 12 MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<42> 30 92 12 MEM_B_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<43> 31
32 6
32
=PP3V3_S3_MEMRESET
CPU_MEM_RESET3V3_L 11 2CP
TP_ISOLATE_CPU
3 MEM_RESET_HW
C
CPU CHANNEL A DQS 3 -> DIMM A DQS 4 CPU CHANNEL B DQS 3 -> DIMM B DQS 4 PM_SLP_S3_L 13 2RD* MEM_RESET_HW
MEM_A_DQS_N<3> =MEM_A_DQS_N<4> MEM_B_DQS_N<3> =MEM_B_DQS_N<4>
100 63 47 46 36 32 26 19 5
THRM R3380 3
MEM_RESET_HW
D Q3350
92 12
30 92 12
31
GND PAD 10K 2N7002
92 12 MEM_A_DQS_P<3> =MEM_A_DQS_P<4> 30 92 12 MEM_B_DQS_P<3> =MEM_B_DQS_P<4> 31 100 32 11 CPU_MEM_RESET_L 1 2 CPU_MEM_RESET_R_L 1 Q3360 1 G S
SOT23-HF1
15
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 2N3904
5%
1/16W SOT23-HF
92 12 MEM A DQ<31> =MEM A DQ<37> 30 92 12 MEM B DQ<31> =MEM B DQ<32> 31 MF-LF 2 2
92 12 MEM_A_DQ<27> =MEM_A_DQ<36> 30 92 12 MEM_B_DQ<27> =MEM_B_DQ<35> 31 =PP3V3 S5 MEMRESET
MAKE_BASE=TRUE MAKE_BASE=TRUE NOSTUFF 32 6
R3390
MAKE_BASE=TRUE MAKE_BASE=TRUE NOSTUFF
ALL_SYS_PWRGD_R
0 1
MEM_A_DQ<24>
MAKE_BASE=TRUE
=MEM_A_DQ<39> MEM_B_DQ<24>
MAKE_BASE=TRUE
=MEM_B_DQ<33>
100 64 5 1 2 C3390
92 12 30 92 12 31
MAKE_BASE=TRUE MAKE_BASE=TRUE 5% 0.1UF
1/16W 20% 32 6 =PP5V_S3_MEMRESET
10V
CPU CHANNEL A DQS 4 -> DIMM A DQS 3 CPU CHANNEL B DQS 4 -> DIMM B DQS 3 MF-LF
402 CERM 2
MEM_A_DQS_N<4> =MEM_A_DQS_N<3> MEM_B_DQS_N<4> =MEM_B_DQS_N<3> 402 1 1
92 12
30 92 12
31
NOSTUFF R3387 R3384
92 12 MEM_A_DQS_P<4> =MEM_A_DQS_P<3> 30 92 12 MEM_B_DQS_P<4> =MEM_B_DQS_P<3> 31
R3391 NOSTUFF 20K 20K
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 5 NOSTUFF 5% 5%
PM_EN_DDRVTT_S0_REG 1
0 2 DDRSYS_EN 1 MC74VHC1G08 R3393 1/16W 1/16W
100 72 63 SOT23-5-HF MF LF MF LF
5% 4 SLP_S3_CTL_L 1
0 2 2 402
2 402
MAKE_BASE=TRUE MAKE_BASE=TRUE U3390
92 12 MEM_A_DQ<38> =MEM_A_DQ<29> 30 92 12 MEM_B_DQ<38> =MEM_B_DQ<24> 31 1/16W PM_SLP_S3_5V 32 100
MAKE_BASE=TRUE MAKE_BASE=TRUE MF-LF 2 5% PM_SLP_S3_5V_L 32 100
92 12 MEM_A_DQ<37> =MEM_A_DQ<27> 30 92 12 MEM_B_DQ<37> =MEM_B_DQ<31> 31 402 1/16W
MAKE_BASE=TRUE MAKE_BASE=TRUE MF-LF 6
3 402 3
MAKE_BASE=TRUE MAKE_BASE=TRUE D
MEM_A_DQ<35> =MEM_A_DQ<25> MEM_B_DQ<35> =MEM_B_DQ<29> D
92 12
MEM_A_DQ<34>
MAKE_BASE=TRUE
=MEM_A_DQ<24>
30 92 12
MEM_B_DQ<34>
MAKE_BASE=TRUE
=MEM_B_DQ<25>
31
R3394 Q3370 Q3370
92 12
MAKE_BASE=TRUE
30 92 12
MAKE_BASE=TRUE
31
1
0 2 100 PM_SLP_S3_5V_R2 2 G
2N7002DW-X-G 2N7002DW-X-G
MEM A DQ<33> =MEM A DQ<26> MEM B DQ<33> =MEM B DQ<27> 100 63 47 46 36 32 26 19 5 PM_SLP_S3_L S SOT 363 5 G S SOT 363
92 12 30 92 12 31
MAKE_BASE=TRUE MAKE_BASE=TRUE 5%
92 12 MEM_A_DQ<32> =MEM_A_DQ<30> 30 92 12 MEM_B_DQ<32> =MEM_B_DQ<26> 31 1/16W 1
B CPU CHANNEL A DQS 5 -> DIMM A DQS 2 CPU CHANNEL B DQS 5 -> DIMM B DQS 2
NOSTUFF
MF-LF
402 B
92 12 MEM A DQS N<5> =MEM A DQS N<2> 30 92 12 MEM B DQS N<5> =MEM B DQS N<2> 31
R3386
92 12 MEM A DQS P<5> =MEM A DQS P<2> 30 92 12 MEM B DQS P<5> =MEM B DQS P<2> 31
1
0 2
5%
92 12 MEM_A_DQ<47> =MEM_A_DQ<17> 30 92 12 MEM_B_DQ<47> =MEM_B_DQ<18> 31 1/16W
MAKE_BASE=TRUE MAKE_BASE=TRUE MF LF
92 12 MEM_A_DQ<46> =MEM_A_DQ<16> 30 92 12 MEM_B_DQ<46> =MEM_B_DQ<20> 31 402
92 12 MEM_A_DQ<44>
MAKE_BASE=TRUE
=MEM_A_DQ<23> 30 92 12 MEM_B_DQ<44>
MAKE_BASE=TRUE
=MEM_B_DQ<22> 31
Q3375
92 12 MEM_A_DQ<43>
MAKE_BASE=TRUE
=MEM_A_DQ<21> 30 92 12 MEM_B_DQ<43>
MAKE_BASE=TRUE
=MEM_B_DQ<19> 31
FDMC8296
POWER33 3
2
5 1
MAKE_BASE=TRUE MAKE_BASE=TRUE 6 =PP0V75_S0_MEM_VTT_S0FET PPVTT_S0_DDR_FET 6
92 12 MEM_A_DQ<40> =MEM_A_DQ<19> 30 92 12 MEM_B_DQ<40> =MEM_B_DQ<16> 31 D S
CPU CHANNEL A DQS 6 -> DIMM A DQS 1 CPU CHANNEL B DQS 6 -> DIMM B DQS 1 R33401 1
100K G R3388
92 12 MEM A DQS N<6> =MEM A DQS N<1> 30 92 12 MEM B DQS N<6> =MEM B DQS N<1> 31 5% 10
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 1/16W
4 5%
92 12 MEM A DQS P<6> =MEM A DQS P<1> 30 92 12 MEM B DQS P<6> =MEM B DQS P<1> 31 MF LF 1/16W
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 402
2 MF LF
100 32 PM_SLP_S3_5V_L 2 402

MAKE_BASE=TRUE MAKE_BASE=TRUE VTT R
92 12 MEM_A_DQ<52>
MAKE_BASE=TRUE
=MEM_A_DQ<15> 30 92 12 MEM_B_DQ<52>
MAKE_BASE=TRUE
=MEM_B_DQ<11> 31
MEMORY CLOCK ALIASING 3
MAKE_BASE=TRUE MAKE_BASE=TRUE MEM_A_CLK_P<0> =MEM_A_CLK_P<0> D

92 12 MEM_A_DQ<51>
MAKE_BASE=TRUE
=MEM_A_DQ<8> 30 92 12 MEM_B_DQ<51>
MAKE_BASE=TRUE
=MEM_B_DQ<9> 31
92 12
MEM_A_CLK_N<0>
=MEM_A_CLK_N<0>
30
Q3380
92 12
30
2N7002
MAKE_BASE=TRUE MAKE_BASE=TRUE 92 12 MEM_A_CLK_P<1> =MEM_A_CLK_P<1> 30 100 32 PM_SLP_S3_5V 1 G S SOT23-HF1
92 12 MEM A DQ<49> =MEM A DQ<11> 30 92 12 MEM B DQ<49> =MEM B DQ<12> 31 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE 92 12 MEM_A_CLK_N<1> =MEM_A_CLK_N<1> 30
92 12 MEM_A_DQ<48> =MEM_A_DQ<14> 30 92 12 MEM_B_DQ<48> =MEM_B_DQ<13> 31 MAKE_BASE=TRUE NO_TEST=TRUE 2
MAKE_BASE=TRUE MAKE_BASE=TRUE 92 12 MEM_A_CLK_P<2> =MEM_A_CLK_P<2> 30
CPU CHANNEL A DQS 7 -> DIMM A DQS 0 CPU CHANNEL B DQS 7 -> DIMM B DQS 0 MEM A CLK N<2> =MEM A CLK N<2>
A 92 12 MEM A DQS N<7>
MAKE_BASE=TRUE
=MEM A DQS N<0>
NO_TEST=TRUE
30 92 12 MEM B DQS N<7>
MAKE_BASE=TRUE
=MEM B DQS N<0>
NO_TEST=TRUE
31
92 12
92 12 MEM A CLK P<3>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
=MEM A CLK P<3>
NO_TEST=TRUE
30
30 SYNC MASTER=K62 ROSITA SYNC DATE=01/09/2011 A

92 12 MEM A DQS P<7> =MEM A DQS P<0> 30 92 12 MEM B DQS P<7> =MEM B DQS P<0> 31 92 12 MEM A CLK N<3> =MEM A CLK N<3> 30
PAGE TITLE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
DDR3 SUPPORT AND BITSWAPS
92 12 MEM_A_DQ<63> =MEM_A_DQ<5> 30 92 12 MEM_B_DQ<63> =MEM_B_DQ<2> 31 92 12 MEM_B_CLK_P<0> =MEM_B_CLK_P<0> 31 DRAWING NUMBER SIZE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
92 12 MEM_A_DQ<62>
MAKE_BASE=TRUE
=MEM_A_DQ<4> 30 92 12 MEM_B_DQ<62>
MAKE_BASE=TRUE
=MEM_B_DQ<1> 31 92 12 MEM_B_CLK_N<0>
MAKE_BASE=TRUE
=MEM_B_CLK_N<0>
NO_TEST=TRUE
31
92 12 MEM_A_DQ<61> =MEM_A_DQ<3> 30 92 12 MEM_B_DQ<61> =MEM_B_DQ<3> 31 92 12 MEM_B_CLK_P<1> =MEM_B_CLK_P<1> 31 REVISION
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE R
92 12 MEM_A_DQ<60>
MAKE_BASE=TRUE
=MEM_A_DQ<2> 30 92 12 MEM_B_DQ<60>
MAKE_BASE=TRUE
=MEM_B_DQ<7> 31 92 12 MEM_B_CLK_N<1>
MAKE_BASE=TRUE
=MEM_B_CLK_N<1>
NO_TEST=TRUE
31 10.1.0
92 12 MEM_A_DQ<59> =MEM_A_DQ<1> 30 92 12 MEM_B_DQ<59> =MEM_B_DQ<4> 31 92 12 MEM_B_CLK_P<2> =MEM_B_CLK_P<2> 31 NOTICE OF PROPRIETARY PROPERTY: BRANCH
92 12 MEM A DQ<58> =MEM A DQ<0> 30 92 12 MEM B DQ<58> =MEM B DQ<5> 31 92 12 MEM B CLK N<2> =MEM B CLK N<2> 31 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
92 12 MEM_A_DQ<57> =MEM_A_DQ<7> 30 92 12 MEM_B_DQ<57> =MEM_B_DQ<6> 31 92 12 MEM_B_CLK_P<3> =MEM_B_CLK_P<3> 31 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
92 12 MEM_A_DQ<56>
MAKE_BASE=TRUE
=MEM_A_DQ<6> 30 92 12 MEM_B_DQ<56>
MAKE_BASE=TRUE
=MEM_B_DQ<0> 31 92 12 MEM_B_CLK_N<3>
MAKE_BASE=TRUE
=MEM_B_CLK_N<3>
NO_TEST=TRUE
31
33 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOSTUFF =PP3V3_S3_MINI_CONN 33
R3400 -----------------------------------------
1
0 2
| 3.3V S3 CURRENT D0-D2,D3HOT D3COLD |
| MAX CONT. 1100MA 190MA |
5%
| MAX PEAK
|
2750MA 2750MA |
|
C3410 1 C3420 1 C3421 1
1/16W | 1.5V CURRENT | 0.1uF 0.1uF 10uF
MF-LF | MAX CONT. N/U N/U | 20% 20% 20%
402 | MAX PEAK N/U N/U | 10V 10V 6.3V 2
----------------------------------------- CERM 2 CERM 2 X5R
NOSTUFF NOTE: CURRENT DATA PER APR 5,2010 PCIE MINI CEM ECN 402 402 603
=PP3V3_S3_MINI_CONN 33
R3401
0
1 2 CRITICAL
AP WAKE# ISOLATION
D 1
R3470
5%
1/16W
MF-LF J3400 D
Q3470 10K 402 AS0B226-S40N-7F
5% F-RT-SM
G 1
SSM3K15FV 1/16W 54
MF-LF
SOD-VESM-HF 2 402
AP_WAKE_L
S
100 79 36 19 OUT PCIE_WAKE_L 1 2
2
RSVD_MINI_WLAN_ACTIVE 3 4 =PP1V5_S0_MINI 6
RSVD MINI BT ACTIVE 5 6
33 OUT AP MINI CLKREQ L 7 8 NC NOSTUFF NOSTUFF

9 10 NC C3400 1 C3401 1
93 18 IN PCIE_CLK100M_MINI_N 11 12 NC 0.1uF 10uF
20% 20%
PCIE_CLK100M_MINI_P 13 14 NC 10V 6.3V 2
93 18 IN CERM 2 X5R
15 16 NC 402 603
RESERVED NC 17 KEY 18
93 18 OUT PCIE_MINI_D2R_N 19 20
RESERVED NC NC
93 18 OUT PCIE MINI D2R P 21 22 AP MINI RESET L IN 33 100
23 24
NOSTUFF
PLACEMENT_NOTE=PLACE CLOSE TO U1800. 25 26
R3490 0
C3431 27 28 1 2 =SMB_MINI_SCL 49
0.1uF 29 30 SMB_MINI_SCL R3491 5%

0 NOSTUFF 1/16W
93 18 IN PCIE_MINI_R2D_C_N 1 2 93 PCIE_MINI_R2D_N 31 32 SMB_MINI_SDA 1 2 MF-LF =SMB_MINI_SDA 49
402
10%
93 PCIE_MINI_R2D_P 33 34 5%
1/16W
16V
X5R
35 36 TP_USB_MININ MF-LF
402
402 37 38 TP USB MINIP
PLACEMENT_NOTE=PLACE CLOSE TO U1800. 39 40 NO AVAILALBLE USB ON THIS PLATFORM
C3430 41 42 NC TARGET CARDS DO NOT USE IT
0.1uF 43 44 NC
C 93 18 IN PCIE_MINI_R2D_C_P 1 2
NC 45 46 NC C
10% NC 47 48
16V
X5R NC 49 50
402
NC 51 52
53
516S0457
=PP3V3_S3_MINI 6 33
=PP12V_S5_PWRCTL
C3408 1 74 64 6
0.1UF CRITICAL 1 C3461

10%
16V 2 Q3403 0.1UF
1
1 X5R 10%
R3412 VDD
402 IRFH3702TRPBF 2 16V
X5R
100K PQFN 402
1%
1/16W Q3406 PP3V3_S3_MINI_CONN 98
MF-LF
2 402
SLG4AP016V VOLTAGE=3 3V
TDFN
S
1
100 33 PM_PGOOD_MINI 2 SENSE
+ =PP3V3_S3_MINI
B 0.7V - 33 6
B
G
DLY RESET HAS 100MS DELAY ONCE ENABLE IS HIGH
P3V3_S0_MINI_EN_G 4
100 33 OUT AP_MINI_RESET_L 4 RESET*
MR* 3 MINI_RESET_L IN 27 100 =PP3V3_S3_MINI
33 6
AP_PWR_EN_FET
1
EN 6 IN 33
OUT 8 MINI CLKREQ L VCC

OUT 15 100
AP_MINI_CLKREQ_L 7 IN (OD) 1
R3410
33 IN
THRM 10K U3404
PAD GND 5% SLG5AP001
1/16W TDFN
9
MF-LF 5D ON 2
2 402
7G CRITICAL S6
100 33 PM_PGOOD_MINI 8 PG NC 3
THRM
PAD GND
4
33 AP_PWR_EN_FET
=PP3V3_S3_MINI 6 33
AP PWR EN ISOLATION
1
R3471
AP 10K
Q3471 5%
G 1
SSM3K15FV 1/16W
A SOD-VESM-HF
MF-LF
2 402 SYNC MASTER=K62 AARON SYNC DATE=07/16/2009 A
PAGE TITLE
PCI-E Wireless Connector

D
100 25 20 AP PWR EN
3
DRAWING NUMBER SIZE

REVISION
R
10.1.0
34 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_S3_USB_HUB
6 =PP3V3 S5 USB HUB 6 34 35
D D
USB HUB-1 1
R3740
20K
5%
1
R3741
10K
5%
L3558 1/16W
MF LF
1/16W
MF LF
FERR-120-OHM-1.5A 2 402
2 402
NOSTUFF
=PP3V3_S3_USB_HUB 1 2 98 USB_HUB1_VDDPLL3V3
35 34 6
0402
C3741 1
100PF
5%
1 C3536 1 C3537 1 C3538 1 C3539 50V
CERM 2 USB_PON_RESET
0.01UF 100PF 10UF 0.1UF 402 USB_PON_RESET_L
10% 5% 20% 10%
16V 50V 6.3V 16V
2 CERM 2 CERM 2 X5R 2 X7R-CERM Q3740 R3755
1 C3518 402 402 603 402 2N7002DW-X-G
6 3
0
10UF SOT 363 D D 1 2 USB_HUB_RESET_L 34
20% 35
2 6.3V Q3740 5%
X5R 2N7002DW-X-G 1/16W
603 PM_PGOOD_P3V3_S3_FET 2 G S 5 G S SOT 363 MF-LF
100 74
402
L3559 NOSTUFF 1 4
FERR-120-OHM-1.5A 1 C3740
1 2
MIN NECK WIDTH=0 25MM 98 USB_HUB1_VDDA3V3 =PP3V3_S3_USB_HUB 6 34 35 0.47UF
10%
0402 6.3V
2 CERM-X5R
1 C3523 1 C3525 1 C3526 1 C3529 402
1 C3542 1 C3543 1 C3544 1 C3545 1 C3546 1 C3547 0.1UF
10%
0.1UF
10%
0.01UF
10% 10%
0.01UF
0.01UF 100PF 10UF 0.1UF 0.1UF 0.1UF 16V 16V 16V 16V
10% 5% 20% 10% 10% 10% 2 X7R-CERM 2 X7R-CERM 2 CERM 2 CERM
16V 50V 6.3V 16V 16V 16V 402 402 402 402
2 CERM 2 CERM 2 X5R 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM
402 402 603 402 402 402 R3745
0
100 25 20 USB_HUB_SOFT_RESET_L 1 2
5%
1/16W
C MF-LF
402 C
35 34 6
=PP3V3_S3_USB_HUB
10
15
23
29
36
5
NOSTUFF NOSTUFF
CRITICAL R35971 R35991 VDD33
Y3500 10K 100K
5% 5%
24.000M-60PPM-16PF 1/16W 1/16W
1 2 MF-LF MF-LF
USB_HUB1_TEST
402 2 402 2 OMIT
5X3.2X1.4-SM
1 C3519 R3591
1 C3520 U3500
5%
18PF 1M 5%
18PF USB2514-AEZG
1 2
50V 50V
2 CERM
402
5%
2 CERM
402
11 TEST QFN USBDM_DN1/PRT_DIS_M1 1 USB_SDCARD_N 44 95
1/16W
MF-LF USBDP_DN1/PRT_DIS_P1 2 USB_SDCARD_P
402 USB HUB RESET L 26 RESET*
44 95
35 34 IN
USBDM_DN2/PRT_DIS_M2 3 USB_IR_N 44 95
94 USB_HUB1_XTAL1 33 XTALIN/CLKIN
USBDP_DN2/PRT_DIS_P2 4 USB_IR_P 44 95
94 USB_HUB1_XTAL2 32 XTALOUT
USBDM_DN3/PRT_DIS_M3 6 USB_EXTA_N
USB_HUB1_LOCAL_PWR 28 43 95
SUSP_IND/LOCAL_PWR/NON_REM0 7
USBDP_DN3/PRT_DIS_P3 USB_EXTA_P 43 95
22 SDA/SMBDATA/NON_REM1
USB_HUB1_SMBDATA 8 USB_EXTC_N
USBDM_DN4/PRT_DIS_M4 43 95
USB_HUB1_SMBCLK 24 SCL/SMBCLK/CFG_SEL0 USBDP_DN4/PRT_DIS_P4 9 USB EXTC P 43 95
=PP3V3_S3_USB_HUB
35 34 6
=PP3V3_S3_USB_HUB USB_HUB1_CFG_SEL1 25 12
6 34 35
HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* TP_USB_HUB1_PRTPWR1
PRTPWR2/BC_EN2* 16 TP_USB_HUB1_PRTPWR2
14 CRFILT 1
1 18 TP USB HUB1 PRTPWR3 1 R3581 1
1
R3504 1 NOSTUFF R3598 PRTPWR3/BC_EN3* R3580 R3550
10K
R35921 R3594 10K 34 PLLFILT PRTPWR4/BC_EN4* 20 TP_USB_HUB1_PRTPWR4 10K 10K 10K
8
10K 10K 5%
NOSTUFF 5% 5% 5%
B 5%
1/16W
MF LF
VCC
5%
1/16W
5%
1/16W
1/16W
MF-LF
2 402
OCS1* 13 TP_USB_HUB1_OCS1_L
1/16W
MF LF
1/16W
MF LF
2 402
1/16W
MF LF B
2 402 U3514 MF LF
402 2
MF LF
2 402 OCS2* 17 TP USB HUB1 OCS2 L 2 402
2 402
M24C02 OSC3* 19 USB EXTA OC L 43
WP_HUB1 7 WC* MLP8 SDA 5 21
OSC4* USB_EXTC_OC_L 43
1 C3534
0.1UF 6 SCL CRITICAL 1 RBIAS 35 USB HUB1 RBIAS
10%
R3501 94
16V
2 X5R
10K 27 USB_HUB1_VBUS_DET
5% VBUS_DET
402 1 E0 NOSTUFF 1/16W CKPLUS WAIVE=NDIFPR BADTERM MIN NECK WIDTH=0 25MM
1 MF-LF 30 MIN LINE WIDTH=0 5MM
2 E1 R3566 1
R3565 1
R3567 402 2 USBDM_UP USB_HUB1_UP_N IN 20 95
3 E2 10K 10K 10K USBDP_UP 31 USB_HUB1_UP_P 20 95

5% IN
1/16W 5% 5%
VSS THRM_PAD 1/16W 1/16W THRM_PAD
MF-LF MF-LF MF-LF
2 402
4
2 402 2 402
37
R3500
1
12K 2
1%
1/16W
BOM TABLE
MF
402 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
SEL1 SEL0 DESCRIPTION 338S0721 2 SMSC USX2061-AEZG U3500,U3600 CRITICAL HUB_USX2061
DEFAULT K23F ==> 0 0 Internal Default with Self powered Operation 338S0824 2 SMSC USB2514B U3500,U3600 CRITICAL HUB_USB2514B
0 1 SMBUS Slave Config 98 USB_HUB1_VDD1V8

1 0 Internal Default with Bus powered Operation
98 USB_HUB1_VDD1V8PLL
1 1 EEPROM Supported MIN NECK WIDTH=0 25MM
MIN LINE WIDTH=0 5MM 1 C3524 1 C3527 1 C3528 1 C3530
0.1UF 1UF 0.1UF 1UF
A 10%
16V
2 X7R-CERM
10%
16V
2 X5R
10%
16V
2 X7R-CERM
10%
16V
2 X5R SYNC MASTER=K62 SIJI SYNC DATE=11/14/2010 A
402 402 402 402 PAGE TITLE
NON_REM1 NON_REM0 DESCRIPTION
0 0 All ports are Non removable USB HUB 1
0 1 Port1 is non removable DRAWING NUMBER SIZE
DEFAULT K23F ==> 1 0 Port 1 and 2 are non removable Apple Inc. 051-8442 D
1 1 Port1,2 and 3 are non Removable REVISION
R
10.1.0
35 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
USB HUB-2 D
L3658
FERR-120-OHM-1.5A
35 34 6 =PP3V3_S3_USB_HUB 1 2 98 USB_HUB2_VDDPLL3V3
1 C3636 1 C3637 1 C3638 1 C3639
0.01UF 100PF 10UF 0.1UF
10% 5% 20% 10%
2 16V
CERM 2 50V
CERM
6.3V
2 X5R 2 16V
X7R-CERM
402 402 603 402
1 C3618
10UF
20%
6.3V
2 X5R
603
L3629
FERR-120-OHM-1.5A
1 2
MIN NECK WIDTH=0 25MM 98 USB_HUB2_VDDA3V3 =PP3V3_S3_USB_HUB 6 34 35
0402
1 C3623 1 C3625 1 C3626 1 C3629
1 C3642 1 C3643 1 C3644 1 C3645 1 C3646 1 C3647 0.1UF
10%
0.1UF
10%
0.01UF
10% 10%
0.01UF
0.01UF 100PF 10UF 0.1UF 0.1UF 0.1UF
10% 5% 20% 10% 10% 10% 2 16V
X7R-CERM
16V
2 X7R-CERM 2 16V
CERM
16V
2 CERM
16V 50V 6.3V 16V 16V 16V 402 402 402 402
2 CERM 2 CERM 2 X5R 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM
402 402 603 402 402 402
35 34 6
=PP3V3_S3_USB_HUB
C C
10
15
23
29
36
5
1 NOSTUFF
CRITICAL NOSTUFF
R36971 R36991 VDD33 =PP3V3_S3_USB_HUB
Y3600 10K 100K 35 34 6
5% 5%
24.000M-60PPM-16PF 1/16W 1/16W
1 2 MF-LF MF-LF
402 2 402 2 OMIT
5X3.2X1.4-SM R36601 R36611
1 C3619 R3691 1 C3620 U3600 10K 10K
5%
18PF 1M 5%
18PF USB2514-AEZG 5%
1/16W
5%
1/16W
1 2 MF LF MF LF
50V 50V
2 CERM
402
5%
2 CERM
402
USB_HUB2_TEST 11 TEST QFN USBDM_DN1/PRT_DIS_M1 1 USB_BT_N 44 95
402 2 402 2
1/16W
MF-LF USBDP_DN1/PRT_DIS_P1 2 USB_BT_P 44 95
402 34 USB_HUB_RESET_L 26 RESET*
IN
USBDM_DN2/PRT_DIS_M2 3 USB_HUB2UNUSED_N 95
94 USB_HUB2_XTAL1 33 XTALIN/CLKIN
USBDP_DN2/PRT_DIS_P2 4 USB_HUB2UNUSED_P 95
94 USB_HUB2_XTAL2 32 XTALOUT
USBDM_DN3/PRT_DIS_M3 6 USB_EXTB_N 43 95
USB_HUB2_LOCAL_PWR 28 SUSP_IND/LOCAL_PWR/NON_REM0
USBDP_DN3/PRT_DIS_P3 7 USB_EXTB_P 43 95
USB_HUB2_SMBDATA 22 SDA/SMBDATA/NON_REM1
USBDM_DN4/PRT_DIS_M4 8 USB_EXTD_N 43 95
USB HUB2 SMBCLK 24 SCL/SMBCLK/CFG_SEL0 USBDP_DN4/PRT_DIS_P4 9 USB_EXTD_P 43 95
35 34 6
=PP3V3_S3_USB_HUB USB_HUB2_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* 12 TP_USB_HUB2_PRTPWR1
PRTPWR2/BC_EN2* 16 TP_USB_HUB2_PRTPWR2 =PP3V3_S3_USB_HUB 6 34 35
14 CRFILT
NOSTUFF 1 PRTPWR3/BC_EN3* 18 TP USB HUB2 PRTPWR3 1
1
R3604 R3692 1 1
R3694 R3698 34 PLLFILT PRTPWR4/BC_EN4* 20 TP_USB_HUB2_PRTPWR4 R3680 1 R3681 R36821
10K 10K 10K 10K 10K 10K 10K
8
5%
NOSTUFF 5% 5%
5% 5%
5%
5%
1/16W OCS1* 13 TP_USB_HUB2_OCS1 1/16W
1/16W VCC 1/16W 1/16W
MF-LF 1/16W
MF LF
1/16W
MF LF MF LF MF LF MF LF MF LF
2 402 17
2 402 U3614 402 2
2 402 OCS2*
19
TP USB HUB2 OCS2 402 2 402 2 402 2
USB_EXTB_OC_L
7 WC*
M24C02 OSC3* 43
SDA 5
B 1
WP_HUB2
C3634
MLP8 OSC4* 21
35
USB_EXTD_OC_L 43
B
0.1UF 1 RBIAS USB HUB2 RBIAS 94
10%
6 SCL CRITICAL R3601
16V
2 X5R
10K VBUS_DET 27 USB_HUB2_VBUS_DET
5%
402 1 E0 1/16W CKPLUS WAIVE=NDIFPR BADTERM
NOSTUFF MF-LF USBDM_UP 30 USB_HUB2_UP_N 20 95
2 E1 402 2 IN
1
3 E2 R3665 1R3666 1R3667 USBDP_UP 31 USB_HUB2_UP_P IN 20 95
10K 10K 10K THRM_PAD
VSS THRM_PAD 5% 5% 5%
1/16W 1/16W 1/16W
4
MF-LF MF-LF MF-LF
37
2 402 2 402 2 402
R3600
1
12K 2
1%
1/16W
MF
402
98 USB_HUB2_VDD1V8
98 USB_HUB2_VDD1V8PLL
1 C3624 1 C3627 1 C3628 1 C3630
0.1UF 1UF 0.1UF 1UF
10% 10% 10% 10%
16V 16V 16V 16V
2 X7R-CERM 2 X5R 2 X7R-CERM 2 X5R
402 402 402 402

PAGE TITLE
USB HUB 2
DRAWING NUMBER SIZE

REVISION
R
10.1.0
36 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CAESAR IV 1.2V INT.VR CMPTS CAESAR IV POWER ENABLE CIRCUIT CAESAR IV ACTIVITY LED
3V3_ENET_PHY_FET = S0 || (S3 POWER && ENET_PWR_EN)
PLACEMENT_NOTE=PLACE L3800 CLOSE TO U3900 =PP3V3_S3_ENET_PHY_FET
80 37 36
L3800
4.7UH-0.8A
=PP3V3_S3_ENET_PHY_FET 36 37 80
D
1
PCAA031B-SM
2 ENET_SR_LX
MIN_LINE_WIDTH=1.0MM
37 98 NOSTUFF
R3856 DEVELOPMENT
1
D
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V =PP3V3_S3_ENET_PHY 1
0
2 PP3V3_S3 ENET_PHY_FET R3815
6
MAKE_BASE=TRUE
98
330
SWITCH NODE=TRUE 5% MIN_LINE_WIDTH=1.0 MM 5%
DIDT=TRUE NOSTUFF 1/8W MIN NECK_WIDTH=0.2 MM 1/16W
1 MF LF VOLTAGE=3.3V MF-LF
R3853 Q3850 805 NET_SPACING_TYPE=SWITCHNODE 2 402
10K FDC606P_G ENET_ACT
5%
ENET_SR_VFB SOT-6
6
37 98 1/16W A
MIN_LINE_WIDTH=1.0MM MF-LF DEVELOPMENT
5
VOLTAGE=1.2V 2 402 LED3800
D
4
2
GREEN 3 6MCD
2 0X1 25MM SM
1
K
=PP1V2 S3 ENET PHY 37
1 SILKSCREEN:ENET ACT
R3855
G
10K 1
C3853
5%
3
1/16W 0.1UF
PP1V2 S3 ENET INTREG MF-LF 10%
MAKE_BASE=TRUE
98
2 402 2
16V
X7R CERM C3852
MIN_NECK_WIDTH=0.2MM R3852 402 0.1UF 37 IN ENET_TRAFFICLED_L ENET_LED_ACT_L
1 C3825 1 C3827 1 C3828 1 C3829 1 C3830 1 C3831 1 C3826 VOLTAGE=1.2V 1
100K
2 ENET_PWR_ENABLE_L 1 2
MAKE_BASE=TRUE
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10% 10% 10% 10% 5%
6.3V 16V 16V 16V 16V 16V 16V 1/16W 10%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R MF LF X5R
603-2 402 402 402 402 402 402 402 16V
ENET_PWR_EN_L 402
PLACEMENT_NOTE=PLACE CLOSE TO L3800

PLACEMENT_NOTE=PLACE CLOSE TO L3800
3
D
R3802 Q3852
100
47 46 0 5
2N7002DW-X-G
CAESAR IV WAKE# ISOLATION 19 5
32 26
63
PM_SLP_S3_L 1
5%
2 PM_SLP_S3_R3802_L G S SOT 363
6
C 1/16W
MF LF
402
R3801
4
D
Q3852
C
=PP3V3_S3_ENET_PHY_FET 36 0 2N7002DW-X-G
37 80
100 25 20 IN ENET_PWR_EN 1 2 ENET_PWR_EN_R 2 G S SOT 363
FROM PCH GPIO ->
5%
1/16W 1
1
R3870 MF LF
402
Q3870 10K
5%
G 1
SSM3K15FV 1/16W
SOD-VESM-HF
MF-LF
2 402
CAESAR IV 25MHZ XTAL
NOSTUFF
D
100 79 33 19 OUT PCIE_WAKE_L ENET_WAKE_L =ENET_WAKE_L IN 37

MAKE_BASE=TRUE NOSTUFF C3850
3
R3850 27pF
200 1 2
95 37 IN ENET_CLK25M_XTALO 1 2 95 ENET_CLK25M_XTALO_R
NOSTUFF 1% NOSTUFF 5%
CAESAR IV SW RESET GATING R38511
1/16W
MF-LF CRITICAL 50V
CERM
3
402 402
10M
2 4
5% Y3850 NOSTUFF
=PP3V3 S0 ENET PHY NOSTUFF 1/16W 25.0000M
37 6 MF-LF SM-3.2X2.5MM C3851
1
R3854 402 2 197S0177 27pF
0 1 2
95 37 OUT ENET_CLK25M_XTALI 1 2 ENET_CLK25M_XTALI_R
5 MC74VHC1G08 5%
100 27 IN ENET_RESET_L 1 SOT23-5-HF 1/16W 5%
MF LF 50V
4 ENET_RESET_LOGIC_L CERM
U3880 OUT 36 94 402
402
94 21 15 IN ENET_SW_RESET_L 2
PLACEMENT_NOTE=PLACE CLOSE TO U3900
3 R3857
0
99 80 ENET_CLK25M_XTALI_OSC 1 2
C3880 1 IN
5%
0.1UF
B 20%
10V
CERM 2
1/16W
MF LF
402
B
402
CAESAR IV RESET CONNECTION CAESAR IV STRAPS (NONE)

R3829
0 ENET RESET LOGIC R L
94 36 IN ENET_RESET_LOGIC_L 1 2 OUT 37
5%
1/16W
MF LF
402
CAESAR IV CLKREQ ISOLATION

A =PP3V3 S3 ENET PHY FET 36 37 80
SYNC MASTER=K62 MARK SYNC DATE=01/09/2011 A
PAGE TITLE
CAESAR IV SUPPORT
1
R3872 DRAWING NUMBER SIZE
Q3872 10K
5%
G 1
SSM3K15FV 1/16W REVISION

MF-LF R
SOD-VESM-HF 2 402
10.1.0
ENET CLKREQ FET L
D
94 18 15 OUT ENET_CLKREQ_L IN 37 94 THE INFORMATION CONTAINED HEREIN IS THE

3

38 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
=PP1V2_S3_ENET_PHY 36
281mA (1000base-T max power, Caesar IV) R3901
0 396mA (1000base-T, Caesar II)
80 37 36 =PP3V3_S3_ENET_PHY_FET 1 2 98 ENET_3V3_S3_SR_IN
SWITCH NODE=TRUE
5%
1/16W
DIDT=TRUE
NET SPACING TYPE=SWITCHNODE
1 C3980 1 C3981
MF LF
402
MIN LINE WIDTH 0 4 MM
MIN NECK WIDTH 0 2 MM
0.1UF 0.1UF
VOLTAGE 3 3V 10% 10%
16V 16V ENET_SR_LX
CRITICAL 2 X5R 2 X5R 36 98
1 C3979 402 402 VDD for Card Reader I/O Internal 1.2V Switching Regulator pins.
4.7UF L3900 =PP3V3R1V8_ENET_LR_OUT CRITICAL
20% FERR-600-OHM-0.5A R3900
37 ENET_SR_VFB 36 98
6.3V L3920
2 CERM 0
1 2 98 PP3V3_S3_ENET_PHY_XTALVDDH ENET_XTALVDDH FERR-600-OHM-0.5A
D
603
SM
VOLTAGE=3 3V C3900 1
1
5%
1/16W
2 98
VOLTAGE=3 3V
98 PP1V2_S3_ENET_PHY_AVDDL 1 2
D
MF LF MIN LINE WIDTH=0 4 mm
0.1UF MIN NECK WIDTH=0 2 mm SM
402
10% VOLTAGE=1 2V
16V
2 1 1
X7R CERM
402
C3921 C3920
CRITICAL 0.1UF 4.7UF
10% 10%
L3905 16V
2 2
6 3V
CRITICAL
FERR-600-OHM-0.5A X7R CERM X5R CERM
402 603
L3925
1 2 98 PP3V3_S3_ENET_PHY_BIASVDDH FERR-600-OHM-0.5A
SM MIN NECK WIDTH=0 2 mm 1 2
VOLTAGE=3 3V 1 C3905 98 PP1V2 S3 ENET PHY PCIEPLL
0.1UF MIN NECK WIDTH=0 2 mm SM
10% VOLTAGE=1 2V
16V
2 X7R CERM
402
C3926 1 1
C3925
10% 10%
L3910 16V
2 2
6 3V
CRITICAL
FERR-600-OHM-0.5A X7R CERM X5R CERM
402 603
L3930
1 2 98 PP3V3 S3 ENET PHY AVDDH FERR-600-OHM-0.5A
SM MIN NECK WIDTH=0 2 mm 1 2
1 C3910 1 C3911 98 PP1V2_S3_ENET_PHY_GPHYPLL
VOLTAGE=3 3V R3910 1 MIN LINE WIDTH=0 4 mm
SM
4.7K 0.1UF 0.1UF MIN NECK WIDTH=0 2 mm
10% 10% VOLTAGE=1 2V
5% 16V 16V
1/16W
MF LF
2 X7R CERM 2 X7R CERM C3931 1 1 C3930
402 402
402
2
0.1UF 4.7UF
10% 10%
16V 6 3V
X7R CERM 2 2 X5R CERM
402 603
R3940 1
1
R3941 1
C3917 1
C3918 C3915 1 1
C3916
4.7K 4.7K 0.1UF 0.1UF 4.7UF 0.1UF
42
48
BIASVDDH 37
XTALVDDH 17
20
56
62
SR_VDD 14
SR_VDDP 15
SR_LX 16
SR_VFB 13
39
45
51
29
32
GPHY_PLLVDDL 36
35
61
1 1
10% 10% 10% 10% C3936 C3935
7
5% 5%
16V 16V 6 3V 16V
36 6 =PP3V3_S0_ENET_PHY 1/16W 1/16W 2 2 2 2 0.1UF 10UF
C MF LF MF LF
X7R CERM
402
X7R CERM
402
X5R CERM
603
X7R CERM
402 10% 10%
C
PCIE_PLLVDDL
402
2 2
402 AVDDH VDDO AVDDL VDDC 16V 6 3V
X7R CERM 2 2 X5R LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
402 805
1
the card reader on-chip I/O.
R3942 Connect only to U3900 pin 20.
C3950 1K
0.1uF 5% Current =PP3V3R1V8 ENET LR OUT 37
1 2
1/16W
Limiting OMIT
95 18 OUT PCIE_ENET_D2R_N MF LF
402 Resistor
10%
2
U3900
16V C3951 ENET_VMAIN_PRSNT 58 VMAIN_PRSNT (IPD ENET) BCM57765 TRD0_P 40 ENETCONN_MDI_P<0> BI 38 95 PP3V3R1V8_ENET_LR_OUT_REG
X5R 98
0.1uF QFN-8X8 41 MIN LINE WIDTH=0 3 mm
402
1 2
TRD0_N ENETCONN_MDI_N<0> BI 38 95 DEVELOPMENT DEVELOPMENT MIN NECK WIDTH=0 2 mm
95 18 OUT PCIE_ENET_D2R_P
95 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N TRD1_P 44 ENETCONN_MDI_P<1> 38 95
VOLTAGE=1 8V
BI
10% 95 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 ENETCONN_MDI_N<1> 38 95 NOSTUFF
BI
16V
X5R 46 ENETCONN_MDI_P<2>
1
C3970 1
C3971 1
C3972 1 NOSTUFF
C3955 402 95 PCIE_ENET_R2D_P 33 PCIE_RXD_P TRD2_P BI 38 95
4.7UF 0.1UF 0.1UF R3959 1 C3959
0.1uF TRD2_N 47 ENETCONN_MDI_N<2> BI 38 95
10% 10% 10% 150
95 PCIE_ENET_R2D_N 34 PCIE_RXD_N 2
6 3V
2
16V
2
16V 5% 10PF
95 18 IN PCIE_ENET_R2D_C_P 1 2
TRD3_P 50 ENETCONN_MDI_P<3> BI 38 95
X5R CERM X7R CERM X7R CERM 1/16W 5%
603 402 402 MF LF 50V
31 PCIE_REFCLK_P 49 2 CERM
10%
93 18 IN PCIE_CLK100M_ENET_P TRD3_N ENETCONN_MDI_N<3> BI 38 95 DEVELOPMENT 2 402
402
16V C3956 93 18 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
X5R
402
0.1uF 5
11 PERST* GPIO_0 NC
(IPD
95 18 IN PCIE_ENET_R2D_C_N 1 2
36 IN ENET_RESET_LOGIC_R_L (IPD)
8
10% ENET_CLKREQ_FET_L 12 CLKREQ*
GPIO_1/CR_BUS_PWR
9 ENET_MEDIA_SENSE
MUST DO: REMOVE C/R3959 AFTER PROTO 2
R3943 16V
94 36 OUT (OD) RE*/GPIO_2 OUT 15 18 95
0 X5R
=ENET_WAKE_L 1 2 402 ENET_WAKE_R_L 3 WAKE* NOTE "IPx" == Programmable pull up/down DEVELOPMENT
36 IN (OD)
SD_DETECT/WE*
(IPx ENET)
o1 95 ENET_SD_DETECT_L R3960 0 1 2 SDCONN_DETECT_L IN 45
(See note) 5%
SD DETECT can only be used active low due to errata
5% 1/16W MF LF 402
1/16W
ENET_LOW_PWR 4 LOW_PWR 26 ENET_SD_CMD R3961 33 DEVELOPMENT
1 2 SDCONN_CMD
MF LF 100 21 15 IN (IPD) (IPU ENET) CR_CMD/CLE 95
IN 45 95
WAKE# 402 PLACEMENT NOTE=PLACE NEAR U3900 5% 1/16W MF LF 402
DEVELOPMENT
6 SMB_CLK CR_CLK/RY_BY* 21 95 ENET_SD_CLK R3979 33 1 2 SDCONN_CLK OUT 45 95
Must isolate from PCIe WAKE# if PHY ENET_SMB_CLK PLACEMENT NOTE=PLACE NEAR U3900 5% 1/16W MF LF 402
ENET SMB DATA 10 SMD_DATA 25 ENET CR DATA<0> R3971 33 DEVELOPMENT
1 2 SDCONN DATA<0>
is powered-down in S3/S5. Standard (IPD ENETM) CR_DATA0 95
BI 45 95
DEVELOPMENT5% 1/16W MF LF 402
N-channel FET isolation suggested. CR_DATA1 24 95 ENET_CR_DATA<1> R3972 33 1 2 SDCONN_DATA<1> BI 45 95
37 ENET_SCLK 66 SCLK DEVELOPMENT5% 1/16W MF LF 402
B If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.
37
BI
IN ENET_MISO 64 SI/LINKLED*
CR_DATA2
CR_DATA3
23
22
95 ENET_CR_DATA<2>
ENET_CR_DATA<3>
R3973
R3974
33
33
1 2
DEVELOPMENT
1 2
5% 1/16W MF LF 402
SDCONN_DATA<2>
SDCONN_DATA<3>
BI 45 95
B
(IPU
95 45 95
ENET MOSI 65 BI
37 BI SO DEVELOPMENT5% 1/16W MF LF 402
52 R3975 33
(IPU-ENET
CR_DATA4 95 ENET_CR_DATA<4> 1 2 SDCONN_DATA<4> BI 45 95
37 ENET CS L 63 CS* 5% 1/16W MF LF 402
BI
CR_DATA5 53 95 ENET_CR_DATA<5> R3976 33 DEVELOPMENT
1 2 SDCONN_DATA<5> 45 95
BI
TP_ENET_SPD100LED_L 2 SPD100LED*/SERIAL_DO (OD) CR_DATA6 54 95 ENET_CR_DATA<6> R3977 33 1 2 SDCONN_DATA<6> BI 45 95
36 OUT ENET TRAFFICLED L 67 TRAFFICLED*/SERIAL_DI (OD) CR_DATA7 55 95 ENET CR DATA<7> R3978 33 1 2 SDCONN DATA<7> BI 45 95
5% 1/16W MF LF 402
(IPU ENET)
CE*/MS_INS* 59 NC_ENET_CE_L_MS_INS_L NO_TEST=TRUE
95 36 ENET CLK25M XTALI 18 XTALI No MS (Memory Stick) Insert feature needed.
IN (IPU ENET) 60 ENET_CR_PWREN
19 XTALO CR_LED/ALE OUT 45 Control signal to light LED or control SD bus power.
95 36 OUT ENET_CLK25M_XTALO (IPU ENET)
CR_WP*/XD_WP* 57 SDCONN_WP IN 45
95 ENET RDAC 38 RDAC (NO IPU OR IPD ENET) XD_DETECT 68 ENET SR DISABLE R3980 1K 1 2 NOSTUFF =PP3V3 S3 ENET PHY FET 36 37 80
THRM_PAD 5% 1/16W MF LF 402
(See note)
PHY Non-Volatile Memory
69
1
R3965 ENET 1.2V SR IS ENABLED IF FLOATING. R3981 1K 1 2
ENET supports both active-levels for WP.
5% 1/16W MF LF 402
ROM contains MAC address, PCIe config 1.24K PLACEMENT NOTE=PLACE R3971 NEAR U3900
1% PLACEMENT NOTE=PLACE R3972 NEAR U3900
1/16W ENET_CR Signals PLACEMENT NOTE=PLACE R3973 NEAR U3900
info as well as code for Bonjour proxy. MF LF PLACEMENT NOTE=PLACE R3974 NEAR U3900
Avoids need for EFI to program at startup. 2 402 PLACEMENT NOTE=PLACE R3975 NEAR U3900
BCM requests SD CR[0:7], CMD, CLK termination. PLACEMENT NOTE=PLACE R3976 NEAR U3900
(Required ROM size 1 Mbit) PLACEMENT NOTE=PLACE R3977 NEAR U3900
PLACEMENT NOTE=PLACE R3978 NEAR U3900
ENET_SR_DISABLE PLACEMENT NOTE=PLACE R3961 NEAR U3900
80 37 36 =PP3V3_S3_ENET_PHY_FET PLACEMENT NOTE=PLACE R3979 NEAR U3900
If ENET switching regulator is

used, this pin can float (alias to
R3993 1 R3992 1 TP_). If not used, must be pulled
6
4.7K 4.7K 1
C3990
5% 5% VCC 0.1UF to 3.3V ENET via 1K resistor (not
1/16W 1/16W 10%
MF LF MF LF 16V provided on this page).
402
2 402
2 U3990 2 X7R CERM
R3904 AT45DB021D 402

SOIC-8S1
0
37 ENET_SCLK 1 2 ENET_SCLK R 2 SCK SI 1 ENET_MOSI 37
IN IN
A 37 ENET_CS_L
5% 402
1/16W
MF LF 4 CS*
OMIT_TABLE
SYNC_MASTER=K62_MARK SYNC_DATE=01/09/2011 A
IN PAGE TITLE
SO 8 ENET_MISO OUT
ENET_SWP_L 5 WP*
NOSTUFF
37
ETHERNET PHY (CAESAR IV)
DRAWING NUMBER SIZE
ENET SRESET L 3 RESET* 1
R3990
1
R3997
GND 4.7K 4.7K Apple Inc. 051-8442 D
5% 5% REVISION
7
NOTE: Pull-down on SO plus internal pull-ups on 1/16W 1/16W R

MF LF MF LF 10.1.0
other 3 SPI pins configures ENET for the 2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Atmel AT45DB011D (1Mbit) ROM. If a different THE INFORMATION CONTAINED HEREIN IS THE
ROM is used then the straps must change. PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
NOTE: ENETM requires SI pull-down instead of SO. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 39 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
THIS PAGE IS DIFFERENT BETWEEN K60 AND K62.
CRITICAL
T4000
LFE9249APF
SOI
1 TCT1 MCT1 24 ENETCONN_MCT0
2 TD1+ 1CT:1CT MX1+ 23

C 95 37 BI ENETCONN_MDI_P<0> ENETCONN_MDI_T_P<0> BI 38 95
NOTE PAIR AND PIN POLARITY SWAPS CRITICAL

C
95 37 BI ENETCONN_MDI_N<0> 3 TD1- MX1- 22 ENETCONN_MDI_T_N<0> BI 38 95
J4000
4 TCT2 MCT2 21 ENETCONN_MCT1
RJ45-K60K62
F-ANG-TH
ENET_MDI
95 37 BI ENETCONN_MDI_N<1> 5 TD2+ 1CT:1CT MX2+ 20 ENETCONN_MDI_T_N<1> BI 38 95 95 38 BI ENETCONN_MDI_T_P<1> 1
TRAN_P0
CKPLUS WAIVE NDIFPR BADTERM CKPLUS WAIVE NDIFPR BADTERM
95 38 BI ENETCONN_MDI_T_N<1> 2
TRAN_N0
95 37 BI ENETCONN_MDI_P<1> 6 TD2- MX2- 19 ENETCONN_MDI_T_P<1> BI 38 95 CKPLUS WAIVE NDIFPR BADTERM 95 38 BI ENETCONN_MDI_T_N<0> 3
TRAN_P1
95 38 ENETCONN_MDI_T_P<2> 4
BI TRAN_P2
7 TCT3 MCT3 18 ENETCONN MCT2 95 38 BI ENETCONN MDI T N<2> 5
TRAN_N2
CKPLUS WAIVE PDIFPR BADTERM 95 38 BI ENETCONN_MDI_T_P<0> 6
TRAN_N1
95 37 BI ENETCONN_MDI_P<2> 8 TD3+ 1CT:1CT MX3+ 17 ENETCONN_MDI_T_P<2> BI 38 95
95 38 ENETCONN_MDI_T_P<3> 7
BI TRAN_P3
95 38 BI ENETCONN_MDI_T_N<3> 8
TRAN_N3
95 37 BI ENETCONN_MDI_N<2> 9 TD3- MX3- 16 ENETCONN_MDI_T_N<2> BI 38 95
9
10 TCT4 MCT4 15 ENETCONN_MCT3 SHIELD
10 PINS
95 37 BI ENETCONN_MDI_N<3> 11 TD4+ 1CT:1CT MX4+ 14 ENETCONN_MDI_T_N<3> BI 38 95
CKPLUS WAIVE NDIFPR BADTERM CKPLUS WAIVE NDIFPR BADTERM 514-0733
95 37 BI ENETCONN_MDI_P<3> 12 TD4- MX4- 13 ENETCONN_MDI_T_P<3> BI 38 95
157S0071
B B
1 1 1 1
ENETCONN_TCT R4000 R4001 R4002 R4003
75 75 75 75
5% 5% 5% 5%
1 C4001 1 C4002 1 C4003 1 C4004 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 2 402 2 402 2 402 2 402
2 10V
CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
402 402 402 402
ENETCONN_MCT_BS
MIN LINE WIDTH=0 4 MM
NOSTUFF
PLACE ONE CAP PER TCT PIN 1 C4000
NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps. 1000PF
10%
2 2KV
CERM
1206
NOTE: BOB SMITH TERMINATION FOR EMC.
A SYNC MASTER=K62 MARK SYNC DATE=01/09/2011 A

PAGE TITLE
Ethernet Connector
DRAWING NUMBER SIZE

REVISION
R
10.1.0
40 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_S0_FWPHY 6 39 40 41
7 mA I/O
138 mA
1 1 1 1 1
C4120 C4121 C4122 C4123 C4124
1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
6 3V 6 3V 6 3V 6 3V 6 3V
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
402 402 402 402 402
L4130
120-OHM-0.3A-EMI
D 114 mA FireWire PHY
98 PP3V3_FW_FWPHY_VDDA 1 2
D
MIN NECK WIDTH=0 2 MM 0402 LF
VOLTAGE=3 3V
C4130 1
C4131 1
C4132 1
1UF 1UF 1UF

10% 10% 10%
6 3V 6 3V 6 3V
CERM 2 CERM 2 CERM 2
402 402 402
K18 has 0.475-ohm upstream of L4110
L4110 L4135
40 =PP1V0_S0_FWPHY 120-OHM-0.3A-EMI 120-OHM-0.3A-EMI
1 2 98 PP1V0_FW_FWPHY_AVDD
25 mA PCIe SerDes 17 mA PCIe SerDes 1 2
135 mA 98 PP3V3_FW_FWPHY_VP25
MIN LINE WIDTH=0 4 MM MIN LINE WIDTH=0 4 MM
0402 LF MIN NECK WIDTH=0 2 MM MIN NECK WIDTH=0 2 MM 0402 LF
VOLTAGE=1 0V VOLTAGE=3 3V
1
C4110 1
C4111 C4135 1
C4136 1
1UF 1UF 1UF 1UF

10% 10% 10% 10%
6 3V 6 3V 6 3V 6 3V
2 CERM 2 CERM CERM 2 CERM 2
402 402 402 402
110 mA Digital Core 0 mA VReg PWR
1
C4100 1
C4101 1
C4102 1
C4103 1
C4104 1
C4105 1
C4106 C4141 1 1
C4140
1UF 1UF 1UF 1UF 1UF 1UF 1UF 0.1UF 1UF
10% 10% 10% 10% 10% 10% 10% 20% 10%
6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 10V 6 3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 2 CERM
402 402 402 402 402 402 402 402 402
C PLACEMENT NOTE=Place C4170 close to U1800

PLACEMENT NOTE=Place C4171 close to U1800
C
C4170
B12
C13
E10
H12
M12
N11
C12
G12
L11
A12
L10
K12
APN: 338S0753 -> 1 2 16V PCIE_FW_R2D_C_N
A1
B1
E2
H2
K2
L1
N3
C1
F1
J1
L3
M2
D5
D6
D8
L5
L6
L9
IN 18 93
0.1UF10% X5R 402
VDD10 VDD33 VDDH VP VP25 VREG_PWR C4171 1 2 16V PCIE_FW_R2D_C_P IN 18 93
OMIT 0.1UF10% X5R 402
NC
B13 ATBUSB PCIE_RXD0N N8 93 PCIE FW R2D N
CRITICAL
NC
A13 ATBUSH PCIE_RXD0P N7 93 PCIE_FW_R2D_P
U4100 C4175 1 2 16V
NC A11 ATBUSN PCIE_TXD0N N5 93 PCIE_FW_D2R_C_N PCIE_FW_D2R_N OUT 18 93
0.1UF10% X5R 402
FW643 PCIE_TXD0P N6 93 PCIE_FW_D2R_C_P
40 IN FW PHY DS0 F12 DS0 (IPD) NT-19 C4176 1 2 16V
BGA
PCIE_FW_D2R_P OUT 18 93
40 IN FW_PHY_DS1 E12 DS1 (IPD) NT-20 0.1UF10% X5R 402
REFCLKN N9 PCIE_CLK100M_FW_N IN 18 93
40 IN FW_PHY_DS2 E13 DS2 (IPD) NT-21 PCI EXPRESS PHY PLACEMENT NOTE=PLACE C4175 CLOSE TO U4100
REFCLKP N10 PCIE_CLK100M_FW_P IN 18 93 PLACEMENT NOTE=PLACE C4176 CLOSE TO U4100
40 BI FW_P0_TPA_N B8 TPA0N
40 BI FW_P0_TPA_P A8 TPA0P
NT-4 (IPU) TCK M4 TP_FW643_TCK
95 40 BI FW_P1_TPA_N B5 TPA1N
NT-3 (IPU) TDI N2 TP_FW643_TDI
95 40 BI FW_P1_TPA_P A5 TPA1P TEST CONTROLLER =PP3V3_S0_FWPHY 6 39 40 41
(IPU) TDO M1 TP_FW643_TDO
95 40 BI FW_P2_TPA_N B3 TPA2N
NT-1 (IPU) TMS M3 TP_FW643_TMS
95 40 BI FW_P2_TPA_P A3 TPA2P 1394 PHY NOSTUFF
R4165 1
FW_P0_TPB_N B9 N1 FW643_TRST_L 1
40 BI TPB0N NT-2 (IPU) TRST* R4166
40 BI FW_P0_TPB_P A9 TPB0P 10K 10K
5% 5%
95 40 BI FW P1 TPB N B6 TPB1N 1/16W 1/16W
MF LF MF LF
FW_P1_TPB_P A6 TPB1P NT-10 (IPD) 402 2
2 402
95 40 BI
WAKE* C2 FW_PME_L OUT 15 21 100
95 40 BI FW_P2_TPB_N B4 TPB2N NT-12 (IPD)
98 41 PPVP_FW_PHY_CPS FIXME!!! TYPO IN SYMBOL REGCTL REGCLT D13 FW643_REGCTL
95 40 BI FW_P2_TPB_P A4 TPB2P
PLACEMENT NOTE=Place close to U4100 B10 POWER MANAGEMENT VAUX_DETECT E1 FW643 VAUX DETECT
R4160 1 40 BI FW_P0_TPBIAS B7 TPBIAS0 FIXME!!! TYPO IN SYMBOL VAUX ENABLE VAUX_DISABLE D2 TP_FW643_VAUX_ENABLE
B 200K
1%
1/16W
40
40
BI
BI
FW_P1_TPBIAS
FW_P2_TPBIAS
C3
A2
TPBIAS1
TPBIAS2
NT-13 (OD) CLKREQN L2 FW_CLKREQ_L OUT 15 100
1
R4164
10K
B
MF LF 5%
402 1/16W
2 FW643 R0 B11 R0 MF LF
FW643_TPCPS B10 TPCPS 2 402
NT-16 (IPD) SCIFCLK G2 TP_FW643_SCIFCLK
SCIF NT-14 (IPD) SCIFDAIN G1 TP FW643 SCIFDAIN
C4150 TP_FW643_NAND_TREE K1 NAND_TREE NT-OUT
R4150 NT-17 SCIFDOUT H1 TP FW643 SCIFDOUT
22PF FW643_REXT L8 REXT
1 2
412 NOTE: NT-xx notes show NT-15 (IPD) SCIFMC F2 TP FW643 SCIFMC
95 FW_CLK24P576M_XO 1 2 95 FW_CLK24P576M_XO_R F13 XO
NAND tree order.
5%
1% 95 FW_CLK24P576M_XI G13 XI NT-9
50V
CRITICAL 1/16W
1 MF LF
CERM
402
Y4150 402 TP_FW643_SE M13 SE (IPD)
24.576M
HC49 USMD
R4161 1 1
R4170 TP_FW643_SM N13 SM (IPD)
SERIAL EEPROM NT-7 SCL N12 FW643 SCL
2 2.94K 191 CONTROLLER NT-6 SDA M11 TP_FW643_SDA
C4151 1% 1% TP_FW643_MODE_A J2 MODE_A (IPD) NT-18
22PF 1/16W 1/16W
MF LF MF LF TP FW643 CE L13 CE (IPD)
1 2
402 402
2 2 TP FW643 FW620 L D12 FW620* (IPU) MISCELLANEOUS
5% TP FW643 JASI EN D1
50V K18 has a different crystal JASI_EN (IPD) NT-11
CERM TP_FW643_AVREG A10 AVREG CHIP RESET NT-5 PERST* N4 FW_RESET_L 27 100
402 IN
TP_FW643_VBUF H13 VBUF
FW643_PU_RST_L K13 1
FW_RESET* (IPU) NT-8 R4163
10K
40 FW643_OCR10_CTL J12 OCR_CTL_V10 5%
R4162 1 1
C4162 J13 OCR_CTL_V12 (Reserved)
1/16W
MF LF
External power-on reset (IPU 100K): 470K NC 402
5%
0.33UF 2
Per LSI, R4162 and C4162 can be NOSTUFF -> 1/16W 10% VSS VREG_VSS
6 3V
MF LF 2
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
L12
CERM X5R
402 402
2

PAGE TITLE
FireWire LLC/PHY (FW643)

DRAWING NUMBER SIZE

REVISION
R
10.1.0
41 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Termination
Place close to FireWire PHY
FW643 1.0V GENERATION
39 FW_P0 TPBIAS
VOLTAGE=1.86V
CRITICAL
Q4200 1 C4250 R42501 1
R4251
BCP6916DG 0.33UF 56.2 56.2
10% 1% 1%
SOT223-4 6.3V
2 CERM-X5R 1/16W 1/16W
402 MF-LF MF-LF
2 PP1V0 S0 FW VDD =PP1V0 S0 FWPHY 39 402 2 2 402
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3MM
MAKE_BASE=TRUE
41 40 39 6 =PP3V3_S0_FWPHY 3 4 1 C4210 1 C4211 1 C4212 1 C4213 MIN_LINE_WIDTH=0.6MM
MIN NECK_WIDTH=0.1MM
0.1UF 0.1UF 10UF 10UF VOLTAGE=1.0V
20% 20% 20% 20%
1 2 10V 2 10V 2 6.3V 2 6.3V
CERM CERM CERM CERM
1 C4200 1 C4201 402 402 805-1 805-1
2.2UF 2.2UF 39 FW_P0_TPA_P FW_PORT0_TPA_P 41 95
20% 20% NOTE: MULTIPLE VIAS TO DGND MAKE BASE=TRUE
6.3V 6.3V FW P0 TPA N FW_PORT0_TPA_N
2 CERM 2 CERM NOTE: Q4200 COLLECTOR CONNECT TO CAPS WITH 0.4 SQ-IN HEAT SINK 39 41 95
402-LF 402-LF MAKE BASE=TRUE
39 FW P0 TPB P FW_PORT0_TPB_P 41 95
MAKE BASE=TRUE
39 FW_P0_TPB_N FW_PORT0_TPB_N 41 95
MAKE BASE=TRUE
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY 1
R42521 R4253
C 56.2
1%
1%
56.2
1/16W
C
1/16W MF-LF
R4200 MF-LF
402 2 2 402
1
75 2
39 FW643_OCR10_CTL FW OCR10_CTL_R
NET_SPACING_TYPE=SWITCHNODE NET_SPACING_TYPE=SWITCHNODE
MIN_LINE_WIDTH=0.25MM 5% MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM 1/16W MIN_NECK_WIDTH=0.2MM
DIDT=TRUE MF-LF DIDT=TRUE FW P0 TPA C
402
1
R4254
C4254 1 1%
4.99K
220PF 1/16W
5% MF-LF
25V
CERM 2 2 402
402
1394 PHY DATA/STROBE OPTIONS

41 40 39 6 =PP3V3_S0_FWPHY 2ND & 3RD TPA/TPB PAIR UNUSED
39 FW_P1_TPBIAS NC_FW_PORT1_TPBIAS
MAKE BASE=TRUE
NOSTUFF NO TEST=TRUE
B 1
R4255 1R4256 1R4257 95 39 FW_P1_TPA_P NC_FW_PORT1_TPA_P
B
10K 10K 10K MAKE BASE=TRUE
5% 5% 5% NO TEST=TRUE
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 95 39 FW_P1_TPA_N NC_FW_PORT1_TPA_N
2 402 2 402 2 402 MAKE BASE=TRUE
NO TEST=TRUE
39 FW_PHY_DS0 95 39 FW_P1_TPB_P NC_FW_PORT1_TPB_P

MAKE BASE=TRUE
NO TEST=TRUE
39 FW PHY DS1
THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT 95 39 FW_P1_TPB_N NC_FW_PORT1_TPB_N
MAKE BASE=TRUE
39 FW_PHY_DS2 IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE, FW643 NO TEST=TRUE
HAS INTERNAL 100K PULL-DOWNS, ONLY PULL-UPS NECESSARY.
39 FW P2 TPBIAS NC FW PORT2 TPBIAS
1 MAKE BASE=TRUE
R4258 NO TEST=TRUE
10K FW P2 TPA P NC FW PORT2 TPA P
5% 95 39
1/16W MAKE BASE=TRUE
MF-LF NO TEST=TRUE
2 402 95 39 FW P2 TPA N NC FW PORT2 TPA N
MAKE BASE=TRUE
NO TEST=TRUE
95 39 FW P2 TPB P NC FW PORT2 TPB P

MAKE BASE=TRUE
NO TEST=TRUE
95 39 FW_P2_TPB_N NC_FW_PORT2_TPB_N
MAKE BASE=TRUE
NO TEST=TRUE
NOTE: AGERE’S RECOMMENDATION FOR UNUSED PORTS

PAGE TITLE
FireWire: 1394B MISC

DRAWING NUMBER SIZE

REVISION
R
10.1.0
42 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
INRUSH RESETABLE PTC

CRITICAL PLACEMENT NOTE=PLACE CLOSE TO F4300
POUR COPPER TO SINK HEAT
CRITICAL
F4301 XW4300
1 2 PPVP_FW_PHY_CPS
0.3AMP-60V OUT 39 98
12 VOLTS Q4350 1 2 SM
FDC610PZ VOLTAGE=12V
14 WATTS MAX PER PORT SSOT6 SMD030F-SM

POUR COPPER TO SINK HEAT
6
R4300 CRITICAL CRITICAL
CRITICAL CRITICAL
L4300
5
0.33 2 Q4300 F4300
=PP12V_S0_FW PP12V_S0_VG_OK P12V_FW_R D4300 D
4
1
98 98
FERR-250-OHM
D 41 6
1 2
5%
MIN LINE WIDTH=1 7MM FDC610PZ SM 3AMP-32V
MIN NECK WIDTH=0 5MM MIN NECK WIDTH=0 5MM
VOLTAGE=12V 1W VOLTAGE=12V SSOT6 98 P12V_FW_CL 1 2 98 P12V_FW_D 1 2 98 FW_PORT0_VP_F 1 2 98 FW_PORT0_VP
MF MIN LINE WIDTH=1 7MM MIN LINE WIDTH=1 7MM MIN LINE WIDTH=1 7MM MIN LINE WIDTH=1 7MM
2512 MIN NECK WIDTH=0 5MM MIN NECK WIDTH=0 5MM MIN NECK WIDTH=0 5MM SM MIN NECK WIDTH=0 5MM
6
VOLTAGE=12V CRS08-1.5A-30V VOLTAGE=12V 603 VOLTAGE=12V VOLTAGE=12V
5
1 FAST NON-RESETABLE FUSE
4
R4351 NOSTUFF
C4300
2
1 1
1K C4351 THIS FUSE WILL NOT BLOW
0.01UF
1
5%
1/16W
0.001UF 3
NOSTUFF IT IS HERE FOR SAFETY ONLY 10%
MF LF
20% 50V SHOULD BE DONE AS A POWER STRIP(SUBPLANE)
50V
2 402 CERM 2
402
Q4301 5.1V 3 D4305 2 X7R
603-1
3
MMBT2907AXG D4301 1 MMBD914XG
60V-600MA SOT23
FWPWR_ON_L SOT23 MMBZ5231BXG 1
SOT23
3
1
R4355
1K R4352
5% 51.1K2
1/16W 1 41 FW CURRENT LIMIT
MF LF
402 1%
2 1
1/16W R4301 PORT 0
FWPWR_EN_L
MF-LF 10K FW_TURN_ON_V

402
5%
1/16W 1
1394B
MF-LF
2 402
R4302 1R4303
15K 20K CRITICAL
5% 5%
FW_CURRENT_LIMIT_Q 1/10W
MF-LF
1/16W
MF-LF
J4300
2 603 2 402
FWB-PL-K60-K62
3 3 F-ANG-TH
D Q4302 1 FW_FET_LINEAR_LIMIT_OUT FW_PORT0_TPB_N 1 TPB TPB(R)
Q4351 MMBT2222A7F IN 41
95 41 40 BI
NO_TEST=TRUE 9
2N7002 SOT23 FW FET LINEAR LIMIT IN OUT 41
1 G S SOT23-HF1 2 PLACE CLOSE TO COMPARATOR 95 41 40 BI FW_PORT0_TPB_P 2 TPB+ VP
1 NO_TEST=TRUE 8
2 1 C4302 R4307 7
20K
C 0.01UF
20%
16V
5%
1/16W
NC
6
SC/NC
C
2 CERM MF-LF 95 41 40 BI FW_PORT0_TPA_N 3 TPA VG
402 2 402 NO_TEST=TRUE FW_PORT0_TPA_R 5
95 41 40 BI FW_PORT0_TPA_P 4 TPA+ TPA(R)

NO_TEST=TRUE
10
SHIELD
NOSTUFF 11 PINS
R4304 D4302 C4332 1

100K 2 BAS40XG 514-0769
1 FW_FET_LINEAR_LIMIT_FB 1 3 0.001UF
10%
50V
5% AREF needs to be isolated from all CERM 2
1/16W SOT23 402
MF-LF 41 6 =PP12V_S0_FW local grounds per 1394b spec
402
When a billingual device is connected to a
beta-only device, there is no DC path
1 C4304 between them (to avoid ground offset issue)
8 0.1UF
10% R43351 1 C4335
V+ 2 16V
X7R-CERM BREF should be hard-connected to logic 1M 0.1UF
10%
U4300 402
ground for speed signaling and connection 1%
1/16W 2 50V
LM393 X7R
MF-LF 603-1
5.1V 6 SOI-HF 402 2
7 NC
R4305
D4303
SOT23
5
FW_CURRENT_LIMIT 100K 2 3 1 2
41 IN 1 FW_CURRENT_LIMIT_R FW_CURRENT_LIMIT_RD 1
3
FW_FET_LINEAR_LIMIT_OUT OUT 41
5% 41 IN FW FET LINEAR LIMIT IN
1/16W
MF-LF MMBZ5231BXG
402 GND
4
B PLACE CLOSE TO COMPARATOR
C4305 1
1
R4306 B
200K
2.2UF 5%
10% 1/16W
16V 2 MF-LF
X5R 2 402
603
ACTIVE "LATE VG" + ESD PROTECTION

40 39 6
=PP3V3_S0_FWPHY
C4350 1
0.1UF
10%
16V
PLACEMENT NOTE=PLACE U4350 CLOSE TO J4300 X7R-CERM 2
402
1
VCC
U4350
TPD4S1394
TP_FW_LATEVG_VCLMP 3 VCLMP LLP 8
CRITICAL D1+ FW_PORT0_TPB_P BI 40 41 95
FWPWR_EN D1- 7 FW_PORT0_TPB_N BI 40 41 95
A NOSTUFF
4 FWPWR_EN
D2+ 6 FW_PORT0_TPA_P BI 40 41 95
PAGE TITLE
1 D2- 5 FW_PORT0_TPA_N
R4350
100K
GND BI 40 41 95
FIREWIRE CONNECTOR
2
5% DRAWING NUMBER SIZE

1/16W
MF-LF
2 402 REVISION
R
10.1.0
43 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D SILKSCREEN:HDD PWR HDD Power D

SILKSCREEN:SATA0
SATA PORT A0 FOR HDD J4511
50293-00771-H01 =PP12V_S0_SATA 6 42
12V 2A/0.8A
M-ST-SM
J4510 1
EP00-081-91
M-ST-SM 2 =PP5V_S0_SATA 6 42 5V 1.2A/0.34A
1 3
C4510 1 2 SATA HDD R2D C P
2 0.01UF 10% CERM 4
93 SATA HDD R2D P 16V 402
3 93 SATA HDD R2D N IN 18 93 5 L4511
4 C4511 1 2 SATA HDD R2D C N IN 18 93
6 FERR-220-OHM
5
0.01UF 10% CERM
16V 402 7 97 HDD_OOB_TEMP_FB 1 2 HDD_OOB_TEMP_FILT
93 SATA_HDD_D2R_C_N 51 97 101
6 CRITICAL 0402
93 SATA_HDD_D2R_C_P C4515 1 2 SATA HDD D2R N
7
0.01UF 10% CERM
16V 402
OUT 18 93
518S0813 C4518 1 1 C4517
CRITICAL OUT 18 93
10UF 10UF
10% 20%
C4516 SATA HDD D2R P 25V 2 10V
518S0251 0.01UF
1 2
10% CERM
X5R 2
1206-1
X5R
603
16V 402
BOMOPTION OPTIONS FOR SATA PORT A1 AND A2

SATA PORT A1 FOR SSD/ODD SATA PORT A2 FOR ODD
A1 A2 ODD SATA:P1 ODD SATA:P2
SSD ODD X SILKSCREEN:SATA2
C ODD X SILKSCREEN:SATA1 ODD_SATA:P2
J4520 6
=PP3V3 S0_ODD C
J4530 1735574 R45201
1735574 M-ST-TH
USE OF PORT A2 FOR SSD IS NOT INTENDED VIA BOMOPTION THOUGH MLB SUPPORTS IT. M-ST-TH
C4530 1 2 SATA SSD R2D C P 14 33K
14 5% ODD_SATA:P2
0.01UF 10% CERM 1/16W
16V 402 IN 18 93
MF-LF C4520 1 2 SATA_ODD_R2D_C_P
5V (SSD) 1.4A/0.8A/0.03A S1
C4531 1 2 SATA_SSD_R2D_C_N IN 18 93
GND
S1 402 2 0.01UF 10% CERM
16V 402 IN 18 93
GND 0.01UF 10% CERM

S2 C4521 1 2 SATA_ODD_R2D_C_N IN 18 93
5V (ODD) 1.5A/1A/0.14A S2 93 SATA_SSD_R2D_P
16V 402
A+ 93 SATA_ODD_R2D_P
10% CERM
A+ S3 93 SATA ODD R2D N 0.01UF 16V 402
S3 93 SATA_SSD_R2D_N A- ODD_SATA:P2
A- S4 ODD_SATA:P2
S4 C4532 1 2 SATA SSD D2R N GND C4522 1 2 SATA_ODD_D2R_N
GND 0.01UF 10% CERM S5 SATA_ODD_D2R_C_N 10% CERM
S5 SATA SSD D2R C N 16V 402 OUT 18 93 B- 93 0.01UF 16V 402 18 93
B- 93 OUT
OUT 18 93 S6 93 SATA_ODD_D2R_C_P
S6 SATA_SSD_D2R_C_P B+ C4523 1 2 SATA_ODD_D2R_P OUT 18 93
B+ 93
C4533 1 2 SATA SSD D2R P S7
S7 GND 0.01UF 10% CERM
16V 402
0.01UF 10% CERM
GND 16V 402 KEY ODD_SATA:P2
KEY P1
P1 DP NC
DP NC P2 ODD_SATA:P2
P2 ODD_SATA:P1 +5V
+5V
P3 R4531 +5V P3 R4521
+5V P4 0 SMC ODD DETECT
P4 SATA1 SMC ODD DETECT 2
0 1 SMC ODD DETECT MD SATA2 SMC ODD DETECT 2 1 42 46 101
42 46 101
MD P5 5%
P5 5% GND 1/16W
GND 1/16W ODD_SATA:P1 P6 MF-LF ODD_SATA:P2
P6 MF-LF GND 402
GND 402 R4532 R4522
PP5V_S0_SATA_PORTA1 0 15 PP5V_S0_SATA_PORTA2 0 PP5V_S0_SATA_FET
15
98 2 1 PP5V S0 SATA FET 42 CRITICAL
98 2 1 42 98
98
NET_PHYSICAL_TYPE=POWER NET_PHYSICAL_TYPE=POWER 5%
CRITICAL VOLTAGE=5V 5%
1/8W 518-0361 ODD_SATA:P2 ODD_SATA:P2 VOLTAGE=5V 1/8W
518-0361 ODD_SATA:P1 MF-LF
805 1 C4527 1 C4525 MF-LF
805
1 C4537 1 C4535 ODD_SATA:P2 10UF 1UF
10% NOSTUFF
10UF 1UF 20%
20%
10V
10%
10V
R4533 10V
2 X5R
10V
2 X5R R4523
2 X5R 2 X5R 0 603 402 0 =PP5V S0 SATA
603 402 2 1 =PP5V S0 SATA 2 1 6 42
B 5%
1/8W
6 42
5%
1/8W
MF-LF
B
MF-LF 805
805
SATA Activity LED

18 6 =PP3V3 S0 SATALED CRITICAL NOSTUFF
DEVELOPMENT R4550
Q4500
R4599 1
42 6
=PP5V_S0_SATA FDMC8298 1
0 2 PP5V S0 SATA FET 42 98
330 MLP3.3X3.3
5% 5% VOLTAGE=5V
1/10W 1/8W NET_PHYSICAL_TYPE=POWER
MF LF MF-LF
1 2 3
603
2
805
SATALED_R_L
S
D
DEVELOPMENT R45031
5
A
DS4599 100K
GREEN-3.6MCD 5%
G
2 0X1 25MM SM 1/16W
MF-LF
K 402 2
PCH_SATALED_L SILK_PART=SATA ACTIVE
4
18 SATALED_L
MAKE BASE=TRUE
42 6
=PP12V_S0_SATA
C4500
1
1 CRITICAL
0.1UF ODD_PWR_GATE VCC
10%
16V
2 X5R
U4501
402 SLG5AP001
5D TDFN On= 2-5V
ON 2
A R4501
0
7 G S6 SYNC_MASTER=K62_JERRY SYNC DATE=01/09/2011 A
ODD PWR EN L 1 2 ODD PWR EN L_R 8 PG PAGE TITLE
100 21 15 3
NC NC 3 NC
5%
1/16W
MF-LF
D
Q4502
353S2499
THRM
SATA Connectors
PAD GND DRAWING NUMBER SIZE
402 2N7002
051-8442 D
4
1 G S SOT23-HF1
Apple Inc. REVISION
R
2
10.1.0
ODD PWR EN LD NOTICE OF PROPRIETARY PROPERTY: BRANCH
45 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
USB/SMC DEBUG MUX ADDED AT EVT & SWITCH TO S5 RAIL

NOSTUFF
R4653
0
6 =PP3V3 G3H SMCUSBMUX 1 2
5%
R4654 1/16W
MF-LF
=PP3V3_S5_SMCUSBMUX 1 0 402
155S0329 6 2
5% MOJOMUX:YES
L4630 1/16W
MF-LF
FERR-220-OHM-2.5A 402
Current Limit at 2.1Amp (@ S3 & S0) 98 PP5V USB PORT3 1 2 98 PP5V USB PORT3 F
CRITICAL
U4600
VOLTAGE=5V
0603
MIN_NECK_WIDTH=0.2MM CRITICAL 155S0329 98 PP3V3_SMCUSBMUX
VOLTAGE=5V
PORT 3
TPS2561DR L4660 C4650 1
SON
FERR-220-OHM-2.5A 0.1UF
MOJOMUX:YES J4630
=PP5V S3 USB PP5V_USB_PORT2 20%
CRITICAL USB-K60K62
9
2 IN_0 CRITICAL
OUT1 9 1 2 10V
43 6 98
CERM 2 F-ANG-TH
3 IN_1 OUT2 8 VOLTAGE=5V 0603 402 VCC L4631
120-OHM-90MA
5
MIN_LINE_WIDTH=0.6MM CRITICAL
MIN_NECK_WIDTH=0.2MM DLP0NS
10 FAULT1* SMC_RX_L 5 M+ MOJOMUX:YES Y+ 1
ILIM 7 ILIM IN1
SYM_VER 1
34 USB EXTC OC L
48 47 46
1
C 35 USB EXTD OC L
6 FAULT2*
R46001 C4603
0.1UF
1 1 C4630
0.01uF
C4661
0.1UF
1 1 C4660
0.01uF
48 47 46 SMC_TX_L 4 M-
U4650
PI3USB102ZLE
Y- 2 95 USB D MUXED N 4 3
95 USB_PORT3_N 2
VBUS
DATA-
C
4 EN1 23.2K 20% 20% 20% 20% 7 D+ TQFN 95 USB_PORT3_P 3
1% 10V 16V 10V 16V 95 35 USB_EXTD_P DATA+
CRITICAL 5 EN2 95 USB_D_MUXED_P 1 2
C4601 1 1 THRM 1/16W CERM 2 2 CERM CERM 2 2 CERM 95 35 USB EXTD N
6 D- 4
GND
C4602 PAD MF-LF 402 402 402 402
0.1UF 330UF GND 402 2
20% 20% 6
2 5 3 4
11
10V
CERM 2 2 6.3V (PUT CAP ON CONNECTOR SIDE) 8 OE* SEL 10
NC
IO
NC
IO
POLY TANT
402 CASE D3L SM
Place R4600 very close to ILIM pin
98 PP5V USB PORT2 F
GND 6 VBUS
514-0768
3
1 GND
155S0329 MIN_NECK_WIDTH=0.2MM
94 63 PM EN USB PWR VOLTAGE=5V R4651
CRITICAL
1
0 2 D4630
L4600 5% RCLAMP0502N
CRITICAL FERR-220-OHM-2.5A
1/16W SLP1210N6
U4620 98 PP5V USB PORT0 155S0329 1 2 98 PP5V USB PORT0 F MF-LF
402 R4652 CRITICAL
VOLTAGE=5V 0603
VOLTAGE=5V MOJOMUX:NO 1 0
TPS2561DR MIN_LINE_WIDTH=0.6MM 2
SON
MIN LINE WIDTH=0 6MM L4620 C46331 1 C4600 MIN_NECK_WIDTH=0.2MM
5%
2 IN_0 FERR-220-OHM-2.5A 0.1UF 0.01uF 1/16W
43 6 =PP5V_S3_USB OUT1 9 20% 20% MF-LF
10V 16V
3 IN_1 OUT2 8 98 PP5V USB PORT1 1 2 CERM 2 2 CERM 402
VOLTAGE=5V 402 402 MOJOMUX:NO
MIN LINE WIDTH=0 6MM 0603
USB_EXTA_OC_L 10 FAULT1* ILIM 7 ILIM_IN2 MIN NECK WIDTH=0 2MM CRITICAL
34
35 USB_EXTB_OC_L
C4621 1 1
CRITICAL
6 FAULT2*
4 EN1
R46201
23.2K
C4623 1
0.1UF
1 C4624
0.01uF
20%
47 46
USB DEBUGPRT EN L
SEL=1: CHOOSE USB
SEL=0: CHOOSE SMC
PORT 2
0.1UF
C4622 1%
20%
10V
CERM 2 2
16V 98 PP5V_USB_PORT1_F
20%
330UF 5 EN2
THRM
1/16W
MF-LF 402
CERM
402 VOLTAGE=5V J4620
10V 20% MIN_LINE_WIDTH=0.6MM CRITICAL
2 6.3V GND PAD 402 2 USB-K60K62
CERM 2 POLY-TANT MIN_NECK_WIDTH=0.2MM
402 CASE-D3L-SM L4621 F-ANG-TH
1
11
(PUT CAP ON CONNECTOR SIDE) 120-OHM-90MA 5

Place R4620 very close to ILIM pin DLP0NS
SYM_VER 1
B J4610
USB-MG6-K60-K62 95 34 USB EXTC N
4 3
95 USB PORT2 N
1
2
VBUS
DATA-
B
CRITICAL F-ANG-TH 95 34 USB EXTC P 3
USB_PORT2_P
L4611 95
120-OHM-90MA
DLP0NS
SYM_VER 1
5
1
PORT 1 1 2
4
DATA+
GND
4 3 VBUS 2 5 3 4 6
95 USB_PORT1_N 2
NC
IO
NC
IO
95 35 USB EXTB N DATA-
95 35 USB_EXTB_P
1 2
95 USB_PORT1_P 3
4
DATA+
6 VBUS 514-0768
GND 1 GND
2 5 3 4 6
NC
IO
NC
IO
6 VBUS D4620
514-0770 RCLAMP0502N
1 GND SLP1210N6
CRITICAL
D4610
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
J4600
USB-MG6-K60-K62
USB PORT POWER: L4601 F-ANG-TH
5
120-OHM-90MA
EACH PORT IS HARDWARE Capable of : DLP0NS
STATE
S0, S3
MAX
2.7A
MIN ( WITHIN THE TOLERANCE)
2.1A -- PER PORT
95 34 USB_EXTA_N
4
SYM_VER 1
3
95 USB PORT0 N
1
2
VBUS
DATA-
PORT 0
WHEN CURRENT HITS LIMIT, TPS2561 BECOME CONSTANT CURRENT MODE 95 34 USB_EXTA_P 95 USB PORT0 P 3
AND STAY AT THE LIMIT LEVEL UNTIL THERMAL SHUTDOWN WHEN JUNCTION REACH 130C 1 2
DATA+
4
A SOFTWARE WILL ALOW 500MA/PORT, PLUS 2700MA EXTRA POWER TO BE
distributed to approved devices on a 1st-come, 1st-served basis.
2 5 3 4
GND
SYNC MASTER=K62 JERRY SYNC DATE=01/09/2011 A
6 PAGE TITLE
NC
IO
NC
IO
6 VBUS
514-0770 EXTERNAL USB CONNECTORS
1 GND DRAWING NUMBER SIZE
EXAMPLE: Port 1 - iPad fast charging = 2100mA
Port 2 - Wired Keyboard = 1100mA Apple Inc. 051-8442 D
REVISION
Port 3 - iPhone fast charging = 1000mA R
PORT 4 - USB 2.0 500MA = 500MA

D4600 10.1.0
RCLAMP0502N NOTICE OF PROPRIETARY PROPERTY: BRANCH
TOTAL: 4700MA SLP1210N6
CRITICAL PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
46 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
IR RECEIVER CONNECTOR CAMERA/ALS & BLUETOOTH (K37A) CONNECTOR

IR
IR CRITICAL CRITICAL
L4700
CRITICAL
L4702
J4780
53261-8604 =PP5V_S3_CAMERA
220-OHM-1.4A
120-OHM-90MA M-RT-SM 6
1 2 98 PP5V_S3_CAMERA_FLT
DLP0NS NET_PHYSICAL_TYPE=POWER 0603
SYM_VER 1 5 VOLTAGE=5V CRITICAL
C4701 1 MIN_LINE_WIDTH=0.6MM
4 3 C4700 1 MIN_NECK_WIDTH=0.2MM
95 34 USB_IR_N 101 95 USB_IR_L_N
95 USB_IR_L_P
1 10UF
20%
10V
0.1UF
20%
10V
J4700
95 34 USB IR P 101 2
X5R 2 CERM 2 50224-01311-001
C 1 2
101 98 PP5V_S3_IR_FLT 3
4
805
120-OHM-90MA
402 M-RT-SM
14
C
VOLTAGE=5V DLP0NS
L4703 MIN_LINE_WIDTH=0.6MM
IR MIN_NECK_WIDTH=0.2MM
SYM_VER 1
220-OHM-1.4A L4701 4 3 CRITICAL 1
6
=PP5V_S3_IR 1 2
1 C4781 6
95 20 USB CAMERA N 101 95 USB CAMERA L N 2
1UF USB_CAMERA_P 95 USB_CAMERA_L_P 3
NET_PHYSICAL_TYPE=POWER 0603 10% 95 20 101
CRITICAL 16V 1 2
2 X5R 4
IR
603
518S0667 BT 120-OHM-90MA
49 =SMB_ALS_SCL 5
6
DLP0NS
SYM_VER 1
49 =SMB_ALS_SDA
CRITICAL
L4720 4 3
7
USB_BT_L_N 8
95 35 USB BT N 101 95
101 95 USB_BT_L_P 9
95 35 USB_BT_P
1 2 10
101 97 52 SNS_SKIN_LEFT_P 11
101 97 52 SNS_SKIN_LEFT_N 12
CRITICAL 13
BT
L4721 220-OHM-1.4A
SD Card Reader Board ( Lazarus ) 6 =PP3V3_S3_BT

NET_PHYSICAL_TYPE=POWER
1
0603
2 98
VOLTAGE=3.3V
PP3V3_S3_BT_FLT
BT BT
15
MIN_NECK_WIDTH=0.2MM 1 C4720
10UF
1 C4721
0.1UF
518S0785
CRITICAL 20% 20%
6.3V 10V
CRITICAL 2 CERM 2 CERM
L4750 J4750
SM06B-SRKS-G-TB-HF
805-1 402
120-OHM-90MA
DLP0NS F-RT-SM
SYM_VER 1 7
4 3
USB SDCARD N Skin Temp sense at upper Left Screen corner
B 95 34
95 34 USB_SDCARD_P
95
95
USB_SDCARD_L_N
USB_SDCARD_L_P
1
2
B
1 2
3
CRITICAL 4
L4751 5
FERR-250-OHM 6
=PP3V3 S3 SDCARD
45 6
1 2 PP3V3_S3_SDCARD_FLT 98
NET_PHYSICAL_TYPE=POWER SM
VOLTAGE=3.3V 8
100 SDCARD_RESET_L 518S0751
R4750 C4750 1
10K 1UF
1 2 10%
6 3V
CERM 2
1% 6
1/16W 402
MF-LF
402
D
Q4710
2N7002DW-X-G
101 100 21 15
SDCARD_RESET 2 G S
SOT-363
1
R4751 1
10K
1%
1/16W
SDCARD_PLT_RST_R_L
MF-LF
2 402 3
D Q4710
2N7002DW-X-G
SOT-363
100 27 SDCARD PLT RST L 5 G S
A 4
PAGE TITLE
Internal USB Connections

DRAWING NUMBER SIZE

REVISION
R
10.1.0
47 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SD CARD 3.3V OVERCURRENT PROTECTION CHIP WITH ACTIVE LOAD DISCHARGE
TPS2065-1 (1.0A LIMIT) HAS ACTIVE LOAD DISCHARGE SO R4800 IS NOSTUFF.
DEVELOPMENT
CRITICAL
U4800 =PP3V3 S0 SW SD PWR 45

TPS2065-1
2 IN0 DGN OUT0 6
6 =PP3V3 S0 SDCARD 3 IN1 OUT1 7
PP3V3_S0_SW_SD_PWR 98
OUT2 8 MAKE BASE=TRUE
353S0004 MIN LINE WIDTH=0 4 mm
37 ENET CR PWREN 4 EN NOSTUFF MIN NECK WIDTH=0 2 mm
OC* 5 DEVELOPMENT DEVELOPMENT
1
VOLTAGE=3 3V
THRM
1 C4802 1 C4803 R4800
DEVELOPMENT DEVELOPMENT DEVELOPMENT
GND PAD 10UF 0.1UF 47K
5% =PP3V3 S0 PCH GPIO
1 C4805 1 C4800 1 C4801 20%
2 6.3V
10%
2 16V
1/16W 6 20
9
22UF 10UF 0.1UF X5R X7R-CERM MF-LF DEVELOPMENT
20% 20% 10% 603 402 2 402
2
6 3V
CERM X5R 2 6.3V
X5R 2 16V
X7R-CERM R48011
805 3 603 402 10K
5%
1/16W
MF-LF
DEVELOPMENT 402 2
SD SPEC REQUIRES 47 UF R4802

CAPACITANCE ON 3.3V INPUT.
SDCONN OC L R 1
0 2
22 + 10 + 10 + 2.2 (FLEX) TP_SDCONN_OC_L
5%
1/16W
MF-LF
C 402
C
SDCONN DETECT DEBOUNCE, INVERSION, AND DETECT-CHANGED PCH GPIO CIRCUIT SD CARD CONNECTOR
DEVELOPMENT
CRITICAL
998-3513
J4800
44 6 =PP3V3_S3_SDCARD SDCONN_DETECT_L OUT 37 -> TO ENET CHIP 50671-02641
F-RT-SM
28
DEVELOPMENT
1
R4810 1
10K 3 45 SDCONN_DETECT 2
5% NOSTUFF
1/16W 3
MF-LF
D Q4810 (CARD INSERTED = OPEN)
402 2 2N7002 DEVELOPMENT 37 OUT SDCONN_WP 4 CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG
SOT23-HF1
1 G S 95 37 SDCONN_DATA<7> 5 MAKES THE ACTIVE-HIGH CASE UNUSABLE.
BI
SDCONN_DATA<6> 6
2 C4812 1 95 37 BI
7
0.1UF
DEVELOPMENT 20%
10V GENERATE A 1 PULSE ON 95 37 SDCONN_DATA<1> 8
B R4811
33K
CERM
402
2
CARD INSERT OR REMOVAL
DEVELOPMENT
BI
9 B
1 2 SDCONN DETECT SHORT DLY DEVELOPMENT L4800 95 37 BI SDCONN DATA<0> 10
6
74LVC1G86GF FERR-10-OHM-500MA 11
5%
1/16W 1
SOT891
R4814 1 2 12
MF-LF Vih = 2.0V 4 1
0 2
95 37 IN SDCONN_CLK SDCONN_CLK_L
SDCONN_DETECT 402 SDCONN_DETECT_PULSE SDCONN_STATE_CHANGE OUT
45 IN
Vil = 0.8V 2
U4810 20 25 100
SM 13
R4812 NC
DEVELOPMENT
5%
1/16W
-> TO PCH GPIO 14
-> FROM SD CONN 33K 5 MF-LF
15
1
5%
2 SDCONN_DETECT_LONG_DLY 3
X 402 45 =PP3V3_S0_SW_SD_PWR
SDCONN_CMD 16
NC 95 37 OUT
1/16W
MF-LF
402
C4810 1 C4811 1 17
1UF 0.1UF 95 37 SDCONN DATA<3> 18
DEVELOPMENT 10% 20% BI
10V 10V DEVELOPMENT 19
X5R 2 CERM 2
402 1 402
95 37 SDCONN_DATA<5> 20
BI
DEVELOPMENT 21
BI
23
BI
25
26
27

PAGE TITLE
SD READER CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
10.1.0
48 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
338S0878 PP3V3_G3H_AVREF_SMC Peak/Ave/Standby = 2mA/1mA/5uA
98 47 46
SMC EXCARD PWR EN B12 P10

U4900 P60 L13 SMC PM G2 EN
47 46 6 =PP3V3 G3H_SMC Peak/Ave/Sleep/Standby = 40mA/25mA/20mA/50uA
47 OUT H8S2117 OUT 75 100
47 OUT SMC_RSTGATE_L C13 P11 LFBGA P61 L14 NC 1

C4904 1
C4905 1
C4906
ALL_SYS_PWRGD_SMC A15 L15
C4902 1 1
C4903
100 64 IN P12 (1 OF 4) P62 NC 22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20%
RSMRST_PWRGD B14 K12 20% 20%
100 64 IN P13 OMIT P63 NC 6 3V 10V 2
10V
2
10V
2
10V
2 2 CERM CERM CERM
B15 K13 SMC_ADAPTER_EN CERM CERM
NC P14 P64 OUT 19 47 100 805 402 402 402 402
PM_RSMRST_L C14 P15 P65 K14
100 27 OUT NC PLACEMENT NOTE=Place C4907 close to U4900 pin 13
47 OUT CPUIMVP_VR_ON D12 P16 P66 J12 SMC_PROCHOT_3_3_L IN 47 100
100 25 19 OUT PM PWRBTN L C15 P17 P67 J13 SMC BIL BUTTON L IN 47
R4999 Peak/Ave/Standby= 2mA/1mA/5uA SMC VCL
4.7
K62 NEW:NOT USE NC D13 P20 P70 N12 SMC_VCORE_ISENSE IN 50 97 (IMON) 1 2 98 46 PP3V3_G3H_SMC_AVCC
MIN LINE WIDTH=0 25 MM C4907 1
N14
J15
M14
NC D14 P21 P71 R13 SMC_VCORE_VSENSE IN 50 97 (IMON) 5% MIN NECK WIDTH=0 20 MM
0.47UF
A1
P1
F1
1/16W VOLTAGE=3 4V
D15 P22 P72 P13 SMC CPU 1V5 ISENSE 50 97 MF LF 10%
NC IN 402 6 3V
E12 P23 P73 R14 SMC CPU 1V5 VSENSE C4920 1 CERM X5R 2
NC IN 50 97
0.1UF AVCC VCC VCL AVREF
402
NC E14 P24 P74 P14 SMC VCCSA ISENSE IN 50 97 20%

K62 NEW:NOT USE
R4909 1
1
10V R4901
NC E15 P25 P75 R15 SMC_VCCSA_VSENSE IN 50 97 CERM
402
2
U4900 10K 10K
K62 NEW:NOT USE NC E13 P26 P76 N13 SMC_VAXG_ISENSE IN 50 97 (IMON)
PLACEMENT NOTE=Place R4999 close to U4900 pin 76
H8S2117 5%
1/16W
5%
1/16W
F14 P27 P77 P15 SMC_VAXG_VSENSE (IMON) PLACEMENT NOTE=Place C4920 close to U4900 pin 76
LFBGA MF LF MF LF
NC IN 50 97
402 2
(3 OF 4) 2 402
94 48 18 BI LPC AD<0> D9 P30 P80 C7 SMC WAKE SCI L OUT 15 18 PROTO-3, Change back to WAKE_SCI_L OMIT
21 100 MD1 E2 SMC_MD1 IN 48
C 94 48 18
94 48 18
BI
BI
LPC_AD<1>
LPC_AD<2>
C9
A9
P31
P32
P81
P82
A7
B7
NC
PM_CLKRUN_L OUT 15 19 48 100 100 48 47 IN SMC_RESET_L E3 RES*
MD2 K1
SMC_KBC_MDE C
94 48 18 BI LPC_AD<3> B9 P33 P83 D6 LPC_PWRDWN_L IN 19 48 100
97 47 SMC XTAL A2 XTAL
94 48 18 IN LPC_FRAME_L D8 P34 P84 C6 SMC_TX_L OUT 43 46 47 48 SMC_NMI
97 47 SMC_EXTAL B2 EXTAL NMI F4 IN 48
100 27 IN SMC_LRESET_L C8 P35 P85 A6 SMC_RX_L IN 43 46 47 48
94 27 IN LPC_CLK33M_SMC A8 P36 P86 B6 (OC) SMB_MGMT_CLK BI 49
48 18 BI LPC SERIRQ D7 P37

P90 K4 SMC_ONOFF_L IN 47 100 SMC TRST L
ETRST* L1 IN 48
NC A5 P40 P91 J2 SMC_BC_ACOK IN 47
B5 P41 P92 J1 AVSS R12 NOSTUFF

K62 P1 NOT USED, WAS OOB_TEMP NC NC 1
49 BI SMB MGMT DATA D5 P42 (OC) P93 J3 PM SLP S3 L IN 5 19 26 32 36 47 63 100 VSS R4902 1
R4998
1
R4903
10K 10K 0
47 OUT SMS_ONOFF_L C3 P43 P94 J4 PM_SLP_S4_L IN 5 19 32 47 K60 New Change 5%
5% 5%
63 100 1/16W
D2
P4
F12
B13
A4
NC B1 P44 P95 H2 PM_SLP_S5_L IN 5 19 47 63
100
K60 New Change XW4900 MF LF
1/16W
MF LF
1/16W
MF LF
SM
2 402
C2 P45 P96 H1 PM_CLK32K_SUSCLK 2 402 2 402
NC IN 9 94 100
2 1
47 OUT SMC_GFX_THROTTLE_L D3 P46 P97 G2 (OC) SMB_0_S0_DATA BI 49
NC C1 P47
48 47 46 43 OUT SMC_TX_L G1 P50

48 47 46 43 IN SMC_RX_L G4 P51
PP3V3_G3H_AVREF_SMC GND_SMC_AVSS 46 47 50 97
49 BI SMB_0_S0_CLK F2 P52 (OC) 98 47 46
47 46 6 =PP3V3_G3H_SMC
98 46 PP3V3_G3H_SMC_AVCC
AVCC1 N15
AVREF1 M15
VCC3 P2
SMC_PA0 R3 PA0
U4900 PE0 M3 SMC PE0
K62 NEW:NOT USE,PULLED UP 47 IN
H8S2117 IN 47 K62 NEW:NOT USE,PULLED UP
100 18 OUT SPI DESCRIPTOR OVERRIDE L (OC) P3 PA1 LFBGA PE1* M2 SMC TCK IN 47 48
100 27 25 19 OUT PM_SYSRST_L (OC) R2 PA2 (2 OF 4) PE2* M1 SMC_TDI IN 47 48
B 47 43
47
OUT
IN
USB_DEBUGPRT_EN_L
MEM_EVENT_A_L
(OC)
(OC)
N3
R1
PA3
PA4 OMIT
PE3*
PE4*
L4
L2
SMC_TDO
SMC_TMS
OUT 47 48
IN 47 48
E4 U4900 B
N4
H8S2117 PJ0 C5 NC
47 IN MEM_EVENT_B_L (OC) N2 PA5 PF0 M7 G3_POWERON_L IN 47 LFBGA
M9 (4 OF 4) PJ1 B8 NC
47 BI SYS_ONEWIRE (OC) M4 PA6
PF1 P6 SMC_SYS_LED OUT 47
M12 PJ2 C10 NC
100 19 15 OUT PM_BATLOW_L (OC) N1 PA7 NC OMIT
PF2 R6 SMC_LID 47
M13 PJ3 C12 NC
NC B10 PB0 PF3 N6 NC L12 PJ4 A14 NC
SMC RUNTIME SCI L A10 PB1 PF4 M6 PJ5 F15
PROTO-3:back to K75F 100 47 21 OUT NC A3 NC
101 42 IN
SMC ODD DETECT D10 PB2 PF5 R5 BDV_BKL_PWM OUT 84 100 K62 PROTO-2:NEW PJ6 J14 NC
K62 NEW:NOT USE,PULLED UP 47 IN
(See below) SMC PB3 A11 PB3 PF6 P5 NC PJ7 K15 NC
97 51 IN SMC HDD OOB TEMP B11 PB4 PF7 N5 NC PI0 N8 NC
NC C11 PB5
PG0 P9 NC PI1 N7 NC
K62 NEW:NOT USE,PULLED UP IN
SMC_PB6 A12 PB6
PG1 R9 SMC_SMS_INT IN 47 PI2 M5 NC
47 IN SMC_GFX_OVERTEMP_L D11 PB7
PG2 N9 (OC) SMB BSA DATA BI 49 PI3 L3 NC
53 OUT SMC FAN 0 CTL G14 PC0 PG3 P8 (OC) SMB BSA CLK BI 49 PI4 K3 NC
53 OUT
SMC FAN 1 CTL G15 PC1 PG4 R8 (OC) SMB A S3 DATA BI 49 PI5 H3 NC
G13 PC2 PG5 M8 (OC) SMB_A_S3_CLK PI6 H4
P12 AVSS1
NC BI 49
NC
VSS
54 OUT SMC_FAN_3_CTL G12 PC3 PG6 P7 (OC) SMB_B_S0_DATA BI 49 PI7 G3 NC
53 IN SMC_FAN_0_TACH H14 PC4 PG7 R7 (OC) SMB_B_S0_CLK BI 49
SMC_FAN_1_TACH
R4
F13
A13
B4
D1
53 IN H15 PC5
PH0 E1 SMC_PROCHOT OUT 47 100
NC H13 PC6 R4910
PH1 F3 SMC_THRMTRIP OUT 47
54 IN SMC_FAN_3_TACH H12 PC7 1 2 0 CPU_PECI 11 21 100
PH2 K2 NC MF-LF 5% 402 1/16W 97 50 47 46 GND_SMC_AVSS
(IMON) 97 50 IN SMC_1V05_ISENSE M11 PD0 PECI PH3 C4 100 CPU_PECI_R R4911
(IMON) 97 50 IN SMC_1V05_VSENSE P11 PD1 PEVref PH4 D4 PVCCIO S0 SMC R 1 2 0 =PPVCCIO_S0_SMC 6 47
MF-LF 5% 402 1/16W
97 50 IN SMC_PCH_1V05_ISENSE R11 PD2 PEVSTP PH5 B3 100 PM_PECI_PWRGD_R
SMC PCH 1V05 VSENSE N11 R4912 0
A 97 50
97 50
IN
IN SMC GPU ISENSE P10
PD3
PD4 1 C4910 MF-LF 5%
1 2
402 1/16W
PM PECI PWRGD 64 100
97 50 SMC GPU VSENSE R10 PD5 0.1UF PAGE TITLE
IN
97 50 IN
SMC_DIMM_ISENSE N10 PD6 2
20%
10V
CERM
402
SMC
97 50 IN SMC_DIMM_VSENSE M10 PD7 DRAWING NUMBER SIZE

REVISION
SMC PB3: SMC_IG_THROTTLE_L for MG systems. R
Otherwise, TP/NC okay (was ISENSE_CAL_EN) 10.1.0
SMC PG1: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail. PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
49 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3 G3H SMC D

D SMC Reset "Button", Supervisor & AVREF Supply MISC. SIGNAL ALIASES
47 46 6
100 47 46 SMC_ONOFF_L R5020 10K 1 2

SMC_GFX_OVERTEMP_L MXM_ALERT_L 5% 1/16W MF LF 402
47 46 77
48 46 43 SMC_TX_L R5021 10K 1 2
47 46 6
=PP3V3_G3H_SMC MAKE BASE=TRUE
SMC_RX_L R5022 100K 1 2
5% 1/16W MF LF 402
48 46 43
SMC_GFX_THROTTLE_L MXM_PWR_LEVEL 5% 1/16W MF LF 402
46 77 46 SYS_ONEWIRE R5023 2.0K 1 2
MAKE BASE=TRUE 5% 1/16W MF LF 402
CPUIMVP VR ON SMC DELAYED PWRGD 48 46 SMC_TMS R5024 10K 1 2
46 64 100 5% 1/16W MF LF 402
1 MAKE BASE=TRUE 48 46 SMC_TDO R5025 10K 1 2
3
C5010 1 R5010 SMC_TDI R5026 10K 1 2
5% 1/16W MF LF 402
48 46
0.47UF V+ VIN 1K 5% 1/16W MF LF 402
10% 5%
48 46 SMC_TCK R5027 10K 1 2
6 3V U5010 1/16W
5% 1/16W MF LF 402
SILK PART=SMC RESET CERM X5R 2
VREF-3.3V-VDET-3.0V
MF LF
46 SMC_BIL_BUTTON_L R5028 10K 1 2
402 2 402 5% 1/16W MF LF 402
46 SMC_BC_ACOK R5029 10K 1 2
DEVELOPMENT
NC 6
DFN
5 SMC_RESET_L 5% 1/16W MF LF 402
MR1* (IPU)SN0903048 RESET* 46 48 100 R5030 10K
S5000 NC 7
MR2* (IPU)
OUT 100 46 19 SMC_ADAPTER_EN
USB DEBUGPRT EN L R5031 10K
1
1
2
2
5% 1/16W MF LF 402
46 43
5% 1/16W MF LF 402
1 SM 2 100 SMC_MANUAL_RST_L 4 8 PP3V3 G3H AVREF SMC G3_POWERON_L R5034 10K 1 2
DELAY REFOUT 46 98 46
MIN LINE WIDTH=0 4 mm 5% 1/16W MF LF 402
THRM MIN NECK WIDTH=0 1 mm
GND PAD VOLTAGE=3 3V UNUSED PORT 7 ANALOG SENSORS 46 SMC_SMS_INT R5032 10K 1 2
C5011 1
9
5% 1/16W MF LF 402
0.01UF C5012 1 1
C5013 46 SMC_LID R5033 10K 1 2
10% 5% 1/16W MF LF 402
3 4 16V 10uF 0.01UF
CERM 2 20% 10%
6 3V 16V
402
X5R 2 2 CERM 46 SMC_PA0 R5037 100K 1 2
603 402 5% 1/16W MF LF 402
GND SMC AVSS 46 50 97 46 SMC_PB6 R5038 100K 1 2
NTC020-CC1J-B260T MIN NECK WIDTH=0 1 mm 46 SMC PE0 R5036 100K 1 2
5% 1/16W MF LF 402
VOLTAGE=0V 5% 1/16W MF LF 402
MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
51 47 6
=PP3V3_S0_SMC_LS
NOTE: Internal pull-ups are to VIN, not V+.
R5035
C 47 46 SMC_GFX_OVERTEMP_L
R5044
10K
10K
1 2
5% 1/16W MF LF 402 C
UNUSED TP/NC ALIASES 100 46 21 SMC RUNTIME SCI L 1 2
5% 1/16W MF LF 402
46 SMC_EXCARD_PWR_EN TP_SMC_EXCARD_PWR_EN
POWER BUTTON 46 SMS ONOFF L
MAKE BASE=TRUE
TP SMS ONOFF L
J5010 SILK_PART=PWR BTN MAKE BASE=TRUE
SMC_RSTGATE_L TP_SMC_RSTGATE_L 100 63 46 36 32 26 19 5 PM_SLP_S3_L R5041 100K 1 2
53261-8602 46
5% 1/16W MF LF 402
R5042 100K
SMC Crystal Circuit M-RT-SM
3 518S0665
MAKE BASE=TRUE
100 63 46 19 5
100 63 46 32 19 5
PM_SLP_S5_L
PM_SLP_S4_L R5043 100K
1
1
2
2
5% 1/16W MF LF 402
CRITICAL 5% 1/16W MF LF 402

C5020 100 POWER BUTTON L 1
46 SMC_SYS_LED TP_SMC_SYS_LED
15PF MAKE BASE=TRUE
97 46 SMC_XTAL 1 2 2 46 SMC_PB3 TP_SMC_PB3

MAKE BASE=TRUE
5%
CRITICAL 50V 4
1 CERM
Y5020 402
20.00MHZ
5X3.2-SM
2 C5021
DEVELOPMENT
S5010 SMC PROCHOT 3.3V LEVEL SHIFTING
15PF R5012
1 2
NTC020-CC1J-B260T
97 46 SMC_EXTAL 1 SM 2 1
1K
2
SMC_ONOFF_L 46 47 100 =PP3V3_S0_SMC_LS
OUT 51 47 6
5% 5%
50V 1/16W
CERM MF LF
402 402
1
C5014 R5077 1 R5078 1
0.1UF 3.3K 470
20% 5%
10V 5%
3 4 2 CERM R5094 1/16W 1/16W
MF LF MF LF
402
CPU_PROCHOT_L 3.3K 402 2 402
100 65 11 BI 1 2 2 TO SMC
Can be driven by VREG or CPU 5% SMC PROCHOT_3_3_L OUT 46 100
SMC & MXM THERMTRIP LEVEL SHIFTING 1/16W
B SILK_PART=SYS POWER
MF LF
402 CPU_PROCHOT_BUF B
3 CPRCHOT_R
6 3
MEM_EVENT 51 47 6
=PP3V3_S0_SMC_LS R5095 To PCH FROM SMC
D
2
Q5077 5 Q5077
0 Q5095 MMDT3904-X-G MMDT3904-X-G
1 MXM_THRMTRIP L 1 2 PM_THRMTRIP_L 100 46 IN SMC_PROCHOT 5 G S SOT 363 LF SOT 363 LF
R5097 MXM_THRMTRIP
1
OUT 21 100 2N7002DW-X-G
SOT 363 1 4
30 6 =PPSPD S0 MEM A 10K R5096 5%
6 3 1/16W 4
5% 3.3K
1/16W MF-LF
D 5% D 402
MF-LF
R50401 FROM MXM 402 2
1/16W
MF LF
10K MXM OVERT L 2
2 402
5
Q5096 6
5% 77 G S G S
1/16W IN
Q5096 2N7002DW-X-G D
MF-LF 2N7002DW-X-G SOT 363 Q5095
402 2 1 4 2N7002DW-X-G
SOT 363
SOT 363
2 G S
FROM DIMMS
FROM SMC
31 30 MEM_EVENT_L
IN
46
SMC THRMTRIP 1
IN
TO SMC
46 MEM_EVENT_A_L
MAKE BASE=TRUE
46 6
=PPVCCIO S0 SMC
TO/FROM SMC
1
R5087
46 MEM_EVENT_B_LI581 51 47 6 =PP3V3_S0_SMC_LS 5%
51
1/16W
1 MF-LF
R5086 R5088 2 402
3.3K
C THRMTRP1 1
0 2
5%
100 11 IN
CPU THRMTRIP L 1/16W
MF LF 5%
1/16W
2 402 MF-LF
C_THRMTRP 402
R5085
A FROM CPU
1
3.3K
2 C THRMTRP_L 6 3 SYNC MASTER=K62 JERRY SYNC DATE=01/09/2011 A
PAGE TITLE
5%
1/16W
MF LF
402
2
Q5086
MMDT3904-X-G
5
Q5086 SMC Support
SOT 363 LF MMDT3904-X-G DRAWING NUMBER SIZE
1 4 SOT-363-LF
REVISION
R
10.1.0
50 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D LPC+SPI Connector D
FRANK CONNECTOR
CRITICAL
LPCPLUS:YES
J5100
55909-0374
M-ST-SM
6 =PP3V3 G3H LPCPLUS 31 32
6 =PP5V S0 LPCPLUS
1 2 LPC_CLK33M_LPCPLUS IN 27 94
94 46 18 BI LPC_AD<0> 3 4 LPC_AD<2> BI 18 46 94
94 46 18 BI LPC_AD<1> 5 6 LPC_AD<3> BI 18 46 94
7 8
94 48 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB OUT 21 48 94
94 48 OUT SPI_ALT_MISO 11 12 SPI_ALT_CLK IN 48 94
94 46 18 IN LPC FRAME L 13 14 SPI ALT CS L IN 48 94
100 46 19 15 OUT PM CLKRUN L 15 16 LPC SERIRQ BI 18 46
47 46 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 19 46 100
100 27 IN DEBUG_RESET_L 19 20 SMC_TDI OUT 46 47
47 46 OUT SMC_TDO 21 22 SMC_TCK OUT 46 47
46 IN SMC_TRST_L 23 24 SMC_RESET_L OUT 46 47 100
46 OUT SMC_MD1 25 26 SMC_NMI OUT 46
47 46 43 IN SMC_TX_L 27 28 SMC_RX_L OUT 43 46 47

29 30 LPCPLUS GPIO OUT 21
33 34
C C
516S0573
Alternate SPI ROM Support

48 6 =PP3V3_S5_LPCPLUS
55 6 =PP3V3_S5_ROM LPCPLUS:YES
48 6 =PP3V3_S5_LPCPLUS
1 C5144
R5144 1 0.1UF
20%
20K LPCPLUS:YES 10V
2 CERM R5140 1
5% 402 100K
1/16W 5%
MF-LF 1/16W
402 2 U5100 MF LF
402 2
NC7SB3157P6XG
1 B1 SC70 SEL 6
94 55 OUT SPI_MLB_CS_L SPIROM USE_MLB 21 48 94
MAKE_BASE=TRUE
1
2 GND VCC 5 LPCPLUS:YES
R5145
B 94 48 OUT SPI_ALT_CS_L 3
0
4 94 SPI_CS0_L 1
0 2 SPI_CS0_R_L IN 18 94
B
B0 A
5% PLACEMENT_NOTE=Place near U1800
Pull-up on debug card VER 1 1/16W
MF-LF
CRITICAL 402
LPCPLUS:NO
R5146
1
0 2
5% PLACEMENT_NOTE=PLACE NEXT TO U5100
1/16W
MF-LF
402
SPI Bus Series Resistance Option

LPCPLUS:YES
R5156
33
94 48 OUT SPI_ALT_CLK 1 2 SPI_CLK_R IN 18 55 94
PLACEMENT NOTE=Place next to R6150 5%

1/16W
LPCPLUS:YES
MF LF
402 R5157
33
94 48 OUT SPI_ALT_MOSI 1 2 SPI_MOSI_R IN 18 55 94
LPCPLUS:YES 5%
1/16W
PLACEMENT NOTE=Place next to R6152
MF LF
R5158 402
33
94 48 IN SPI_ALT_MISO 1 2 SPI_MISO OUT 18 55 94
PLACEMENT NOTE=Place next to R6105 5%
A 1/16W
MF LF
402 SYNC MASTER=K62 AARON SYNC DATE=11/30/2009 A
PAGE TITLE
LPC+SPI Debug Connector

DRAWING NUMBER SIZE

REVISION
R
10.1.0
51 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH "SMBUS" CONNECTIONS PCH "SML 0" CONNECTIONS SMC "A" SMBUS CONNECTIONS
NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE
BUS A CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K74 CHOOSES 1
49 6 =PP3V3 S0 SMBUS 49 6 =PP3V3 S0 SMBUS
6 =PP3V3_S3_SMBUS_SMC_A
PCH R5208 1 1
R5209 MEMORY A DIMMS R5202 1 1
R5203 SMC R52701 1
R5271 ALS
U1800
2.2K
5%
2.2K
5% J3100-A/B
PCH 8.2K
5%
8.2K
5% U4900
4.7K
5% 5%
4.7K
(WRITE: 0X52 READ: 0X53)
1/16W 1/16W U1800 1/16W 1/16W 1/16W 1/16W
(MASTER) MF LF MF LF (DIMM0: WRITE: 0XA0 READ: 0XA1) MF LF MF LF (MASTER) MF-LF MF-LF
402
2 2
402 (MASTER) 402
2 2
402 402 2 2 402
(DIMM2: WRITE: 0XA2 READ: 0XA3)
D 97 18 SMBUS_PCH_CLK
MAKE_BASE=TRUE
=I2C_SODIMMA_SCL 30
97 18 SML PCH 0 CLK
MAKE_BASE=TRUE
46 SMB_A_S3_CLK 97 SMBUS_SMC_A_S3_SCL
MAKE BASE=TRUE
=SMB_ALS_SCL 44
D
97 18 SMBUS PCH_DATA =I2C_SODIMMA_SDA 30 46 SMB_A_S3_DATA 97 SMBUS_SMC_A_S3_SDA =SMB_ALS_SDA 44
MAKE_BASE=TRUE 97 18 SML_PCH_0_DATA MAKE BASE=TRUE
MAKE_BASE=TRUE
MEMORY B DIMMS
J3200-A/B
SMC "MANAGEMENT" SMBUS (BUS 1)
USES INTERNAL SMC CONTROLLER CHANNEL 1 ONLY
=I2C_SODIMMB_SCL 31
THIS PAGE DIFFERENT BETWEEN K60 AND K62. 6 =PP3V3_S0_SMBUS_SMC_MGMT
=I2C_SODIMMB_SDA 31
XDP (PCH)
J2550 R5290 1 1
R5291 PANEL TEMP SENSOR
SMC 2.2K 2.2K TMP421 ON TCON BOARD VIA J9002
MIKEY U4900 5%
1/16W
5%
1/16W
(SLAVE)
49 25 =SMBUS_XDP_SCL U6806
SMC SLAVE SMBUS "2" CONNECTIONS (MASTER) MF LF
402 2
MF LF
2 402
(WRITE: 0X9E READ: 0X9F)
=SMBUS XDP SDA USES INTERNAL SMC CONTROLLER CHANNEL 2 ONLY (NO CONNECTIONS, JUST PULLUP)
49 25 46 SMB_MGMT_CLK 97 SMBUS_SMC_MGMT_SCL SMB_DP_TCON_SLA_SCL 82
MAKE BASE=TRUE
=I2C_AUDIO_SCL 62 6 =PP3V3_S0_SMBUS_SMC_BSA
46 SMB_MGMT_DATA 97 SMBUS_SMC_MGMT_SDA SMB_DP_TCON_SLA_SDA 82
MAKE BASE=TRUE
=I2C_AUDIO_SDA 62
DISPLAY TCON
SMC R5280 1 1
R5281 PARADE ON TCON BOARD VIA J9002
100K 100K
U4900 5% 5% (SLAVE)
XDP (CPU) CK505 (SLAVE)
1/16W
MF LF
1/16W
MF LF (TBD WRITE: 0X1A READ: 0X1B)
J2500 U2600 402 2 2 402 (TO READ VENDOR ID
(WRITE: 0XD2 READ: 0XD3) AND PANEL ID)
46 SMB BSA CLK 97 SMBUS SMC BSA SCL
MAKE BASE=TRUE TCON ALSO HAS
C 49 25 =SMBUS_XDP_SCL =SMBUS_CK505_SCL 26 46 SMB_BSA_DATA 97 SMBUS_SMC_BSA_SDA

MAKE BASE=TRUE
MASTER BUS TO LUT ROM
AND EDID ROM
C
49 25 =SMBUS_XDP_SDA =SMBUS_CK505_SDA 26
MEM VREF MARGIN A

U2900
SMC "B" SMBUS CONNECTIONS
BUS B CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K60/62 CHOOSES 0
(WRITE: 0X5C READ: 0X5D)
SPTX BLC MICRO 6 =PP3V3_S0_SMBUS_SMC_B
VIA J602 =I2C VREFMRGN A_SCL 28
(WRITE: 0X6E READ: 0X6F)

=I2C_VREFMRGN_A_SDA 28
AC/DC PS TEMPS DISPLAY TCON TO SPTX OR O2M BLC
SMC R5260 1 1
R5261 EMC1403-[1,2] : ACDC THRU J600
(WRITE 0X98 OR 0X9A READ 0X99 OR 0X9B)
=SMB_BLC_PCH_SCL 2.0K 2.0K
6 U4900 5% 5%
1/16W 1/16W 3 SENSE POINTS PRIMARY SECONDARY AMB
=SMB_BLC_PCH_SDA (MASTER) MF LF MF LF 49 6 =PP3V3_S0_SMBUS
6
MEM VREF MARGIN B 402 2
2 402
1
U2910 46 SMB_B_S0_CLK 97 SMBUS_SMC_B_S0_SCL =SMB_ACDC_SCL 6 R5210 1 R5211 BLC MICRO
MAKE BASE=TRUE
NEED TO ADD PCH_SDA
(WRITE: 0X7C READ: 0X7D)
46 SMB_B_S0_DATA 97 SMBUS_SMC_B_S0_SDA =SMB_ACDC_SDA 6
DISPLAY TCON 2.2K
5% 5%
2.2K VIA J602
(SLAVE)
1/16W 1/16W
ISOLATION CIRCUITRY MAKE BASE=TRUE VIA J9002 MF LF MF LF (WRITE: 0X6E READ: 0X6F)
=I2C_VREFMRGN_B_SCL 28 402 2
(MASTER) 2 402
=I2C_VREFMRGN_B_SDA 28
AC/DC PS POWER 97
82
INA219: ACDC THRU J600 =SMB_DP_TCON_SDA SMB_BLC_TCON_SDA OUT 6
MAKE BASE=TRUE 97
(WRITE 0X80 READ 0X81) =SMB_DP_TCON_SCL SMB_BLC_TCON_SCL BI 6
MAKE BASE=TRUE 82
DP SDRV "A" OUTPUT VOLTAGE CURRENT POWER

NOTE: DISPLAY TCON HAS 4.7K PU.
U9310, PS8301 NOTE: SPTX BLC HAS 4.7K PU.
NOTE: O2MICRO BLC HAS NO PU.
(WRITE: 0X94, READ: 0X95)
B B
=I2C_DPSDRVA_SCL 85
T29 I2C CONNECTIONS
=I2C DPSDRVA SDA 85 SMC "0" SMBUS CONNECTIONS I2C BUS PULL-UP RAIL MUST REFLECT
USES INTERNAL SMC CONTROLLER CHANNEL 0 ONLY 6 =PP3V3_S0_T29I2C
WHEN USB POWER (VBUS) IS VALID.
6 =PP3V3_S0_SMBUS_SMC_0
T29 T29
DP SDRV "B" Also reserve 0x56 and 0x32 per spec
T29 PORT A MCU
U9510, PS8301 T29 IC R5230 1 1
R5231
(WRITE: 0XB4, READ: 0XB5) SMC R5250 1 1
R5251 MXM TEMP U9700
4.7K
5%
4.7K
5%
U9330
2.2K 2.2K GPU ON CARD - J8400 1/16W 1/16W (WRITE: 0X26 READ: 0X27)
U4900 5% 5% (MASTER) MF LF MF LF
1/16W 1/16W 402 402
=I2C_DPSDRVB_SCL 87
NV INSIDE (WRITE: 0X9E READ: 0X9F) 2 2
(MASTER) MF LF MF LF
EMC1402 ON AMD MXM CARD (WRITE 0X98 READ 0X99)
402 2 2 402 99 89 I2C_T29_SCL =I2C_T29AMCU_SCL 85
=I2C_DPSDRVB_SDA 87 MAKE BASE=TRUE
46 SMB 0 S0 CLK 97 SMBUS SMC 0 S0 SCL =SMB MXM THRM SCL 77
MAKE BASE=TRUE 99 89 I2C_T29_SDA =I2C_T29AMCU_SDA 85
MAKE BASE=TRUE
46 SMB_0_S0_DATA 97 SMBUS_SMC_0_S0_SDA =SMB_MXM_THRM_SDA 77
MAKE BASE=TRUE
EMC1414: U5520
DEV: CPU D,CPU HTSK
T29 PORT B MCU
U9530
PCH "SML 1" CONNECTIONS EMC1428: U5500
PROD: AMB L-SKIN,R-SKIN,ODD,
LCD,CPU PROX,MXM TEMPS
49 6 =PP3V3 S0 SMBUS (WRITE: 0x92 READ:0x93) =I2C T29BMCU SCL 87
=SMB_SNS1_SCL 52
=I2C_T29BMCU_SDA 87
NOSTUFF NOSTUFF
=SMB SNS1 SDA 52
PCH (FOR TEMP) R5204 1 1

R5205
A U1800
8.2K
5%
1/16W
5%
8.2K
1/16W
(SLAVE) MF LF MF LF
PAGE TITLE

402 2 2 402 R5206
0
PCIE MINI-CARD SMBUS CONNECTIONS
97 18 SML_PCH_1_CLK 1 2 DRAWING NUMBER SIZE
MAKE_BASE=TRUE
5%
X18 WI-FI MODULE 051-8442 D
97 18 SML PCH 1 DATA
MAKE_BASE=TRUE
1/16W
MF-LF R5207 TMP106: J3400
Apple Inc. REVISION
402 0 R
1 2 (WRITE: 0X90 READ: 0X91) 10.1.0
5%
=SMB_MINI_SCL
1/16W 33
MF-LF THE INFORMATION CONTAINED HEREIN IS THE
=SMB_MINI_SDA 33 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
52 OF 110
THE PCH address is user programmable by SPI ROM IV ALL RIGHTS RESERVED 49 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VDD 1.5V CPU VCC (VCORE) GPU MXM
SENSE RESISTOR CURRENT (IC5R) AND VOLTAGE (VC5R) SENSE IMON CURRENT (IC0C) AND VOLTAGE (VC0C) SENSE SENSE RESISTOR CURRENT (IG0R) AND VOLTAGE (VG0R) SENSE
OMIT_TABLE IMAX = 8.25A
R5300 R5330
PP1V5_S0_CPU_MEM_SNS 4.53K CRITICAL IMAX = 8.25A
0.002 6
=PPVCORE_S0_CPU SMC_VCORE_VSENSE
1% CPU_1V5_SENSE 65 16 13 6 1 2
OUT 46 97
R5361 PP12V_S0_MXM_SNS
1/4W
MF-LF R5301 1% 0.002 6
1206 4.53K2
1/16W
MF LF
1
C5330 1%
1/4W
6 =PP1V5_S0_PWR 1 2 1 SMC_CPU_1V5_VSENSE OUT 46 97 402 0.22UF
20% MF-LF R5360
3 4 1% OMIT_TABLE 6 3V 1206 18.2K2 SMC GPU VSENSE
1/16W
PLACEMENT NOTE PLACE C5330 NEAR SMC
PLACEMENT NOTE PLACE R5330 NEAR CPU
2 X5R PLACE C CLOSE TO SMC 6 =PP12V_S0_MXM_PWR 1 2 1 OUT 46 97
52 50 6 =PP3V3_S0_SENSE MF-LF
402
1 C5301 OMIT_TABLE
402
GND SMC AVSS 46 3 4 1%
0.22UF 47 50 97 1/16W 1
CPU_1V5_SENSE
20%
6.3V
R5331 MF-LF
402
R5362 1 C5362
C5300 PLACEMENT NOTE PLACE R5301 NEAR CPU 2 X5R 9.31K2 =PP3V3 S0 SENSE 6.04K 0.22UF
1 SNS_PS_VCORE_ISNS 52 50 6
D 0.22UF 402
GND_SMC_AVSS 1%
1%
1/16W
MF-LF
20%
6.3V
2 X5R D
3
1 2
V+
46 47 50 97
1/16W
MF-LF
C5331 1 C5360 2 402 402
402 0.01UF 0.22UF GND SMC AVSS 46 47 50 97
20% CPU_1V5_SENSE 1 2 20%
6.3V U5300 50 6 =PP5V S0 ISENSE 6.3V PLACEMENT NOTE PLACE R5360 NEAR CPU
X5R R5302 2 X5R
3
402 INA210 4.53K2 20% 402
97 SNS_CPU_1V5_N 5 IN- OUT 6
SC70 97 SMC CPU 1V5 ISENSE R 1 SMC_CPU_1V5_ISENSE OUT 46 97 16V V+
CERM
CPU_1V5_SENSE 1% OMIT_TABLE 402 U5360 R5363
SNS CPU 1V5 P 4 IN+ REF 1
1/16W
MF-LF
1 C5302 R5333 INA210 4.53K
97
402 0.22UF 10K U5330 97 SNS I MXM N 5 IN- SC70 OUT SMC
6 GPU R1 2 SMC GPU ISENSE OUT 46 97
20%
6.3V 98 65 IN VR_CPU_IMON 1 2 98 97 VR_ISNS_VCORE_P 1 5 OPA348 R5332
GND PLACEMENT NOTE PLACE C5302 NEAR SMC 2 X5R
1% SC70-5 5.1K 2 CRITICAL 1%
353S2073
PLACEMENT NOTE PLACE R5302 NEAR SMC
402 1/16W 4 1 SMC_VCORE_ISENSE 97 SNS_I_MXM_P 4 IN+ REF 1
1/16W
MF-LF
1 C5363
2
IMON MAX = 0.9V MF-LF OUT 46 97
402 0.22UF
GAIN = 200V/V GND_SMC_AVSS 46 47 50 97 402 5% 20%
VR_ISNS_VCORE_N 3 CRITICAL 1/16W 1 6.3V
2 MF-LF C5332 GND 2 X5R
IMAX = 2.79V 402 0.22UF 402
2
1 10%
THE NO_1V05_PCH_SENSE,
NO_CPU_VCCSA SENSE, AND
R5334 PLACEMENT NOTE PLACE C5332 NEAR SMC 2 6.3V
CERM-X5R
NO CPU_1V5_SENSE 10K PLACEMENT NOTE PLACE R5332 NEAR SMC
402 GND SMC AVSS
BOMOPTIONS SHOULD IDEALLY 1% 46 47 50 97
104S0018 1 RES,2 MILLIOHM,1206 R5300 CPU_1V5_SENSE NEVER BE USED AS TOTAL CPU POWER 1/16W
SENSING REQUIRES ALL MF-LF GND SMC AVSS 46 47 50 97
3 SENSORS. 2 402
101S0414 1 RES,0 OHM,1206,20 MILLIOHM MAX R5300 NO_CPU_1V5_SENSE
132S0080 2 CAP,0.22UF,402 C5301,C5302 CPU_1V5_SENSE
114S0312 1 RES,MTL FILM,1/16W,9.31K,0402 R5331 CPUVCORE-3PH
116S0004 2 RES,0 OHM,402 C5301,C5302 NO_CPU_1V5_SENSE
CPU VCCSA
114S0345 1 RES,MTL FILM,1/16W,21K,0402 R5331 CPUVCORE-4PH
DIMM VDD 1.5V (LIKELY DEVELOPMENT ONLY)
SENSE RESISTOR CURRENT (IM0R) AND VOLTAGE (VM0R) SENSE
SENSE RESISTOR CURRENT (ICSR) AND VOLTAGE (VCSR) SENSE
OMIT_TABLE
R5310 IMAX = 8.25A CPU VAXG R5370
IMAX = 8.25A
0.002 IMON CURRENT (IC0G) AND VOLTAGE (VC0G) SENSE 0.002 PP1V5_S3_MEM_SNS
C 1%
1/4W
PPVCCSA S0 INPUT SNS 6
CPU_VCCSA_SENSE
R5311
VAXG
1%
1/4W
MF-LF
6
DIMM_1V5_SENSE
R5371
C
MF-LF
=PPVCCSA S0 CPU R5340 1206 4.53K2
1206 13 6 4.53K2 4.53K =PP1V5 S3 MEM PWR 1 2 1 SMC DIMM VSENSE
69 6 =PPVCCSA_S0_INPUT_PWR 1 2 1 SMC_VCCSA_VSENSE OUT 46 97 65 17 13 6 =PPVAXG_S0_CPU 1 2 SMC_VAXG_VSENSE OUT 46 97
6 OUT 46 97
3 4 1% OMIT_TABLE 3 4 1% OMIT_TABLE
OMIT_TABLE 1%
1/16W
1/16W
MF-LF 1 C5311 1/16W 1
C5340 =PP3V3_S0_SENSE MF-LF 1 C5371
52 50 6 =PP3V3_S0_SENSE 402
MF LF
402 0.22UF 52 50 6 402
0.22UF
CPU_VCCSA_SENSE 0.22UF 20% DIMM_1V5_SENSE PLACEMENT NOTE PLACE R5371 NEAR CPU 20%
20% 6 3V
6.3V
2
C5310 PLACEMENT NOTE PLACE C5311 NEAR SMC
6.3V
2 X5R
X5R
402 GND_SMC_AVSS C5370 PLACEMENT NOTE PLACE C5372 NEAR SMC
2 X5R
402
0.22UF 402
VAXG
46 47 50 97
0.22UF GND SMC AVSS
GND_SMC_AVSS 46
3
46 47 50 97
R5341
3
1 2 47 50 97 1 2
V+ 21K V+
20% CPU_VCCSA_SENSE
1 2 SNS PS VAXG_ISNS 20% DIMM_1V5_SENSE
6.3V
X5R U5310 R5312 1% VAXG 6.3V
X5R U5370 R5372
402 INA210 4.53K2
1/16W
MF-LF
C5341 402 INA210 4.53K2 SMC DIMM ISENSE
97 SNS_VCCSA_N 5 IN- SC70
OUT 6 97 SMC_VCCSA_ISENSE_R 1 SMC_VCCSA_ISENSE 46 97 402 0.01UF 97 SNS_DIMM_1V5_N 5 IN- OUT97 6 SMC_DIMM_1V5_R 1
SC70 OUT 46 97
OUT
1% OMIT_TABLE 50 6 =PP5V_S0_ISENSE 1 2 DIMM_1V5_SENSE 1% OMIT_TABLE
CPU_VCCSA_SENSE
97 SNS_VCCSA_P 4 IN+ REF 1
1/16W
MF-LF
1 C5312 20% 97 SNS_DIMM_1V5_P 4 IN+ REF 1
1/16W
MF-LF
1 C5372
402 0.22UF 16V 402 0.22UF
20% CERM 20%
6.3V 6.3V
GND PLACEMENT NOTE PLACE C5312 NEAR SMC
2 X5R VAXG 402 GND 2 X5R
PLACEMENT NOTE PLACE R5312 NEAR SMC VAXG 402
402 R5343 353S2073 GND_SMC_AVSS 46
2
353S2073 U5340
2
47 50 97
GAIN = 200V/V GND SMC AVSS 10K OPA348
VAXG GAIN = 200V/V
46 47 50 97 98 65 IN VR_AXG_IMON 1 2 VR_ISNS_VAXG_P 1 5
R5342
1%
SC70-5 5.1K 2
IMON MAX = 0.9V 1/16W 4 1 SMC VAXG ISENSE OUT 46 97
MF-LF
402 5% OMIT_TABLE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION 98 97 VR_ISNS_VAXG_N 3 CRITICAL 1/16W 1 C5342 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
2 MF-LF
VAXG IMAX = 2.79V 402 0.22UF 132S0080 2 CAP,0.22UF,402 C5371,C5372 DIMM_1V5_SENSE
104S0018 1 RES,2 MILLIOHM,1206 R5310 CPU_VCCSA_SENSE 1 10%
R5344 PLACEMENT NOTE PLACE C5342 NEAR SMC 2 6.3V
CERM-X5R
101S0414 1 RES,0 OHM,1206,20 MILLIOHM MAX R5310 NO_CPU_VCCSA_SENSE 10K PLACEMENT NOTE PLACE R5342 NEAR SMC 402 116S0004 2 RES,0 OHM,402 C5371,C5372 PRODUCTION
1%
1/16W
132S0080 2 CAP,0.22UF,402 C5311,C5312 CPU_VCCSA_SENSE MF-LF GND SMC AVSS 46 47 50 97
2 402
B 116S0004 2 RES,0 OHM,402 C5311,C5312 NO_CPU_VCCSA_SENSE B
PCH 1.05V PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
SENSE RESISTOR CURRENT (IN1R) AND VOLTAGE (VN1R) SENSE 132S0080 2 CAP,0.22UF,402 C5340,C5342 VAXG
OMIT_TABLE 116S0004 2 RES,0 OHM,402 C5340,C5342 NO_VAXG

R5320 IMAX = 8.25A
NOTE: TOTAL CPU POWER = VC0C*IC0C
0.002 PP1V05_S0_PCH_SNS 6
+ VC5R*IC5R
1% 1V05_PCH_SENSE + VCSR*ICSR
+ VC0G*IC0G
1/4W
MF-LF
1206
R5321
4.53K2
1.05V FOR CPU VCCIO, CPU VCCSA & PCH 1.05V where
+ VV1R*IC1R
6 =PP1V05_S0_PCH_PWR 1 2 1 SMC_PCH_1V05_VSENSE OUT 46 97 IMON CURRENT (IV1R) AND VOLTAGE (VV1R) SENSE IC1R = IV1R - IN1R - ICSR
3 4 1% OMIT_TABLE
1/16W R5350
52 50 6 =PP3V3 S0 SENSE MF-LF
402
1 C5321 =PP1V05 S0 PWR
4.53K
SMC 1V05 VSENSE
1V05_PCH_SENSE 0.22UF 6 1 2
OUT 46 97
20%
6.3V 1%
C5320 PLACEMENT NOTE PLACE R5321 NEAR CPU 2 X5R
402
1/16W
MF LF
1
C5350
0.22UF GND SMC AVSS 46 402 0.22UF
20%
3
47 50 97
1 2 6 3V
PLACEMENT NOTE PLACE C5350 NEAR SMC 2 X5R
V+ PLACEMENT NOTE PLACE R5350 NEAR CPU
402
20% 1V05_PCH_SENSE GND_SMC_AVSS 46 47 50 97
6.3V
X5R U5320 R5322
402 INA210 4.53K2
97 SNS 1V05 PCH N 5 IN- SC70 OUT 6 SNS 1V05 PCH R 1 SMC PCH 1V05 ISENSE OUT 46 97
1V05_PCH_SENSE 1% OMIT_TABLE C5351

97 SNS_1V05_PCH_P 4 IN+ REF 1
1/16W
MF-LF
1 C5322 0.01UF
402 0.22UF =PP5V S0 ISENSE 1 2
20% 50 6
6.3V
GND 2 X5R
20%
PLACEMENT NOTE PLACE C5322 NEAR SMC 402 16V
353S2073
2
PLACEMENT NOTE PLACE R5322 NEAR SMC CERM

A GAIN = 200V/V GND SMC AVSS 46 47 50 97
R5353
402
1K U5350 PAGE TITLE

98 68 IN P1V05_IMON
IMON MAX = 2.7V
1
5%
2 VR_ISNS_P_1V05 1 5 OPA348
SC70-5 R5352
5.1K 2
CPU/PCH/GPU POWER SENSE
1/16W 4 1 SMC_1V05_ISENSE OUT 46 97 DRAWING NUMBER SIZE
MF-LF
104S0018 1 RES,2 MILLIOHM,1206 R5320 1V05_PCH_SENSE 402
VR_ISNS_N_1V05 3
5%
1/16W Apple Inc. 051-8442 D
CRITICAL 1 C5352 REVISION
2 MF-LF
101S0414 1 RES,0 OHM,1206,20 MILLIOHM MAX R5320 NO_1V05_PCH_SENSE IMAX = 2.7V 402 0.22UF R
10.1.0
10%
132S0080 2 CAP,0.22UF,402 C5321,C5322 1V05_PCH_SENSE PLACEMENT NOTE PLACE C5352 NEAR SMC 2 6.3V
CERM-X5R NOTICE OF PROPRIETARY PROPERTY: BRANCH
PLACEMENT NOTE PLACE R5352 NEAR SMC
402
116S0004 2 RES,0 OHM,402 C5321,C5322 NO_1V05_PCH_SENSE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
GND SMC AVSS 46 47 50 97 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
53 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
HDD OOB TEMPERATURE SENSING

C 6 =PP12V_S0_SENSE
C
1 1
C5400
R5400
110K 0.1UF
20%
1% 16V
1/16W 2 CERM
MF LF
402
Trip point 1.0V. 603
2 =PP3V3_S0_SMC_LS
51 47 6 =PP3V3_S0_SMC_LS 100 51 HDD_OOB_1V00_REF 6 47 51
Pull up 1.5V.
1
R5401 1
1
R5405
FROM DRIVE: C5401 1K
1 10K
LOW: 0.0V TO 0.3V R5402
180K
1%
1/16W
0.1UF
20%
8
U5400 5%
1/16W
HIGH: 1.2V TO 2.0V MF LF 2 16V
LM393 MF LF
5% CERM 2 2 402
1/16W
402
2 603 SOI-HF
MF LF V+
402 1 SMC_HDD_OOB_TEMP OUT
2
R5403 46 97
3.3K 3 GND
101 97 42 IN HDD_OOB_TEMP_FILT 1 2 97 HDD OOB TEMP R
CRITICAL
1.5V 5% 4
R5404 1 1/16W
MF LF
150K 402
5%
1/16W NOSTUFF
MF LF 1
402
2
R5406
0
5%
1/16W
MF LF
R5407 8
U5400 2 402
USE_HDD_OOB_L 1
10K
2 USE HDD OOB L R 6 LM393
100 20 IN SOI-HF
5% V+
1/16W 7
MF LF USE_HDD_OOB_PD
B 402
100 51
HDD_OOB_1V00_REF 5 GND
4
CRITICAL B
DRIVE ACTIVE = VALID SIGNAL PROTOCOL BETWEEN 0-2.0V.
DRIVE ASLEEP = HDD DRIVES HDD_OOB_TEMP LOW
DRIVE ABSENT = OOB IS PULLED HIGH UNLESS PCH DETERMINES SSD PRESENT AND DRIVES USE_HDD_OOB_L LOW WHICH THEN PULLS HDD_OOB_TEMP LOW.
NOTE: WILL BE CONNECTED TO SATA PWR CONNECTOR PIN 11

THIS PIN IS ORIGINALLY INTENDED FOR HDD LED OUTPUT,
AND ALSO FOR HDD STAGGERED PIN UP (FLOATING) OR IMMEDIATE SPIN-UP (GROUND).
BOTH FUNCTIONS NOT USED.

PAGE TITLE
HDD OOB SENSE

DRAWING NUMBER SIZE

REVISION
R
10.1.0
54 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SILK_PART=AMB TEMP MXM HTSK TEMP SENSOR SILK_PART=MXM HSK

AMBIENT TEMP SENSOR MXM
SNS T1: PRODUCTION TEMP SENSOR IC L5500
J5500
53780-8603 FERR-220-OHM
L5540
MXM
J5530
53398-8602
FERR-220-OHM M-RT-SM M-ST-SM
4 SNS_T1_5_P 1 2 3
52 50 6 =PP3V3_S0_SENSE 97 52 SNS_T1_1_P 1 2 97 52
MXM 0402
0402
1
R5500 1R5501 1R5502 1 C5501 101 97 SNS AMB P 1 1 C5514 MXM 97 SNS_MXM_P 1
C5500 1 6.81K 10K 20K 0.0022UF L5501 101 97 SNS AMB N 2 0.0022UF L5541 97 SNS MXM N 2
16
1% 5% 10% 10%
CRITICAL 1UF 1/16W
5%
1/16W 1/16W 2 50V FERR-220-OHM 3 2 CERM
50V FERR-220-OHM
10% CERM
10V MF-LF MF LF MF-LF
VDD X5R 2
2 402 2 402
2 402 97 52 SNS_T1_1_N 402 1 2 97 52 SNS_T1_5_N 402 1 2 4
D U5500
EMC1428-7
402 1
0402 5 0402
CRITICAL D
CRITICAL 518S0678
QFN 518S0677 Place Hsk sensor conn top side next MXM or CPU
97 52 SNS_T1_1_P 1 DP1 ALERT* 7 SNS_T1_ALERT_L
AMB (TA0p) 2
97 52 SNS_T1_1_N DN1 SILK_PART=ODD TEMP
SYS_SHND* 6 SNS T1 ADDR
SNS_T1_2_P 3 ODD TEMP SENSOR J5510 CPU PROXIMITY TEMP SENSOR
ODD (TO0p)
97 52 DP2/DN3
SMDATA 11 =SMB SNS1 SDA BI 49 52
L5510 53780-8602
97 52 SNS_T1_2_N 4 DN2/DP3 FERR-220-OHM
M-RT-SM SNS T1 6 P
SMCLK 12
97 52
10 =SMB_SNS1_SCL IN 49 52 SNS_T1_2_P 1 2 3
97 52 SNS_T1_4_P DP4/DN5 97 52
LEFT SKIN (TS2p) 9 0402 NOSTUFF
97 52 SNS T1 4 N DN4/DP5 TRIP/SET 5 SNS T1 TRIPSET 1 C5511 3
Set trip point to 125 C. 0.0022UF
101 97 SNS_ODD_P 1
Q5500
1 C5504
CPU PROX (TC0p)
97 52 SNS_T1_6_P 15 DP6/DN7 NC 13 NC 10% L5511 101 97 SNS_ODD_N 2
MMBT3904G 1 0.0022UF
10%
97 52 SNS_T1_6_N 14 DN6/DP7 2
50V
CERM
FERR-220-OHM SOT23 50V
2 CERM
402
97 52 SNS_T1_2_N 1 2 4 2 402
2 2 GND THRM_PAD 0402 97 52 SNS T1 6 N

OMIT OMIT CRITICAL
17
XW5504 SM
XW5505 518S0698 Place Q5500 (CPU Proximity Sensor) at the solder side
SM
at edge near backer plate of CPU to replace HeatSink Temp Sensor
OMIT 2 2 OMIT 1 1
XW5502 SM
SM XW5503
2 2
OMIT OMIT 1 1
PLACEMENT_NOTE=PLACE U5500 UNDER MXM HTSK TO GET MXM PROX TEMP
MLB Prox 0 (Tm0p)
CPU HTSK TEMP SENSOR
SM
XW5500 SM XW5501 RIGHT SKIN TEMP SENSOR SILK_PART=SKIN RIGHT TEMP SILK_PART=CPU HSK
1 1 L5520 J5520 L5522 J5521
FERR-220-OHM 53261-8602 FERR-220-OHM 53398-8602
97 52 SNS_T1_7_N M-RT-SM M-ST-SM
52 SNS T1 3 P
CPU HTSK (TC0h) 1 2 3 SNS T1 7 P 2 1
SNS T1 7 P 97 97 52 3
97 52
0402 0402
97 52 SNS T1 5 N 1 C5512 SNS_SKIN_RIGHT_P 1 1 C5522 97 SNS CPU H P 1
MXM HTSK (TG0h) 0.0022UF
SNS_T1_5_P L5521 0.0022UF
C 97 52
97 52 SNS T1 3 N
10%
2 50V
CERM
402
FERR-220-OHM
101 97 SNS SKIN RIGHT N 2
10%
50V
2 CERM FERR-220-OHM
L5523 97 SNS CPU H N 2
C
RIGHT SKIN (TS0p) SNS_T1_3_N 1 2 4 402
97 52 SNS T1 3 P
97 52
97 52 SNS_T1_7_N 2 1 4
0402 0402
CRITICAL CRITICAL
518S0665 518S0678
EMC1428-7: 6.8K PULL UP: I2C ADDRESS: WRITE: 0x92, READ: 0x93
LEFT SKIN TEMP SENSOR L5530

FERR-1000-OHM
97 52 SNS_T1_4_P 1 2 CONNECTOR COMBINED WITH CAMERA/BT
0402
1 C5513 SNS SKIN LEFT P 44 97 101
0.0022UF
10% L5531 SNS SKIN LEFT N 44 97 101
2 50V
CERM
FERR-1000-OHM
402
97 52 SNS_T1_4_N 1 2
0402
THIS PAGE DIFFERENT BETWEEN K60 AND K62.
B B
SNS T2: DEVELOPMENT TEMP SENSOR IC
DEVELOPMENT =PP3V3 S0 SENSE 6 50 52

97 10 SNS_CPU_THERMD_P
CPU THERMAL DIODE
(TC0D) 1 C5521 DEVELOPMENT DEVELOPMENT DEVELOPMENT
ONLY DP/N1 compatible with CPU thermal diode 0.0022UF
10%
C5520 1 1
R5520 1
R5521
50V 1UF 33.2K 10K
2 CERM 10%
1% 5%
402 6 3V
97 10 SNS_CPU_THERMD_N DEVELOPMENT 1 X5R 2 1/16W
MF LF
1/16W
MF LF
402 1
VDD 2 402
2 402
DEVELOPMENT
U5520
EMC1414-A
SILK_PART=LCD TEMP 2 DP1
MSOP
7
J5550 DEVELOPMENT THERM*/ADDR SNS_T2_ADDR
53261-8602 L5550 3 DN1 ALERT* 8 SNS T2 ALERT L
M-RT-SM FERR-220-OHM
3 4 DP2/DN3 9
1 2 97 SNS_T2_DP2 DEVELOPMENT SMDATA =SMB_SNS1_SDA BI 49 52
0402
1 97 SNS_LCD_H_P 1 C5550 5 DN2/DP3 SMCLK 10 =SMB_SNS1_SCL 49 52
0.0022UF IN
L5551
A 2 97 SNS LCD H N FERR-220-OHM
2 402
10%
50V
CERM
GND
6 SYNC MASTER=K62 MARK SYNC DATE=01/09/2011 A
1 2 97 SNS_T2_DN2 PAGE TITLE
4
0402
DEVELOPMENT
MLB Prox 1 (Tm1p) TEMP SENSORS
CRITICAL DRAWING NUMBER SIZE
518S0665
REVISION
EMC1414-A-AIZL: 33K PULL UP: I2C ADDRESS: WRITE: 0x78, READ: 0x79 R
LCD TEMP
(TL2p)
10.1.0
55 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D FAN 0 CRITICAL
L5610
220-OHM-1.4A D
54 53 6 =PP12V_S0_FAN 1 2 PP12V_S0_FAN0_L
VOLTAGE=12V
R56021 R5603 1 1 C5606 1 C5607

1.5K 1.5K 4.7UF
20% 20%
0.01UF
5%
1/4W 5%
1/8W 2 16V
CERM
16V
2 CERM
MF-LF 5 1206-1 402
1206 2 MF-LF
805 2
54 53 6 =PP3V3_S0_FAN R5605 CRITICAL
3.9K2
F0_VOLTAGE8R5 1 F0 GATESLOWDN
4 Q5600
R56061 5%
1/8W NTHS5443T1H
10K
5%
1/16W 3
MF-LF
805
C5601 1
1206A-03-HF ODD FAN
MF-LF
402 2 D Q5602 0.47UF
10%
2N7002 CRITICAL
1
2
3
6
7
8
16V
SMC_FAN_0_CTL 1 SOT23-HF1
X7R 2
805
J5600
46 G S CRITICAL 53780-8604
M-RT-SM
2 L5620 MIN_LINE_WIDTH=0.5MM 5
220-OHM-1.4A
FAN_0_PWR 1 2 101 FAN_0_PWR_L 1 MOTOR CONTROL
CRITICAL 0603 101 FAN_TACH0_L 2 TACH
3 3
D5600
1
C5602 GND
100UF 4 12V DC
54 53 6 =PP3V3 S0 FAN MMBD914XG 20%
1 2 16V
ELEC
SOT23 6.3X5.5-SM1-HF 6
R5600
1
10K 101 FAN_0_GND
518S0730
C 5%
1/16W
MF-LF
CRITICAL
L5600
MIN_NECK_WIDTH=0.25MM C
R5699 2 402 FERR-220-OHM
R5620
1
0
47K 5%
46 SMC_FAN_0_TACH 1 2 FAN_TACH0 1 2 1/10W
0402 MF-LF
5%
1/16W NOTE: ADDED TO PROTECT SMC 2 603
MF-LF
402 PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3
CRITICAL
FAN 1 220-OHM-1.4A
L5630
54 53 6 =PP12V_S0_FAN 1 2 PP12V_S0_FAN1_L
VOLTAGE=12V
C5608 1 1 C5628 1 C5609
R56101 2.2UF
10%
2.2UF
10%
0.01UF
20%
1.5K 2 16V
16V
5%
1/4W
R56071 16V 2
X5R X5R
603
2 CERM
402
MF-LF 1.5K 603
=PP3V3_S0_FAN 1206 2 5%
54 53 6 1/8W
MF-LF 5
1 805 2
R5611 R5609 CRITICAL
10K
5%
1/16W
MF-LF
F1_VOLTAGE8R5
3.9K
1
5%
2 F1 GATESLOWDN
4 Q5603 HD FAN
402 2 3 1/8W NTHS5443T1H
MF-LF 1206A-03-HF
Q5605 805 CRITICAL
B D
2N7002 C5603 1 CRITICAL
J5601
53780-8604
B
SMC_FAN_1_CTL 1 G S SOT23-HF1 0.47UF M-RT-SM
1
2
3
6
7
8
46 10% MIN_NECK_WIDTH=0.25MM
16V 2 MIN_LINE_WIDTH=0.5MM L5640 MIN_LINE_WIDTH=0.5MM 5
2
X7R
805
MIN_NECK_WIDTH=0.25MM 220-OHM-1.4A
FAN 1 PWR 1 2 101 FAN_1_PWR_L 1 MOTOR CONTROL
CRITICAL
0603 101 FAN_TACH1_L 2 TACH
3 D5601 1
C5605 3 GND
MMBD914XG 100UF 4 12V DC
20%
54 53 6 =PP3V3 S0 FAN 1 SOT23 2 16V
TANT
D-HF 6
1
R5601
10K
101 FAN_1 GND
518S0730
5% MIN_NECK_WIDTH=0.25MM
1/16W
MF-LF
2 402 C5605 IS POLY-TANT BECAUSE IT MUST BE PLACED ON THE BOTTOM CRITICAL
L5601
R5630
1
0
R5698 FERR-220-OHM 5%
1/10W
SMC FAN 1 TACH 1
47K 2 1 2 MF-LF
46 FAN_TACH1
2 603
5% 0402
1/16W PLACEMENT_NOTE=PLACE R5630 CLOSE TO J5601 Pin3
MF-LF
402

PAGE TITLE
HD AND OD FAN
DRAWING NUMBER SIZE

REVISION
R
10.1.0
56 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SMC’S FAN3 OUTPUT CONTROL FAN 2

CRITICAL
L5710
220-OHM-1.4A
53 6
=PP12V_S0_FAN 1 2 101 98 PP12V_S0_FAN2_L
0603 MIN_LINE_WIDTH=0.5MM
1 C5708 1 C5709 VOLTAGE=12V
4.7UF
20%
0.01UF
20%
1 16V 2 16V
=PP3V3 S0 FAN R5704 R5701 1 2 CERM
1206-1
CERM
402
54 53 6 1.5K 1.5K
5% 5%
1/4W 1/8W
MF-LF MF-LF
2 1206 805 2
5
C C
1
R5705
5%
10K
1/16W
F2 VOLTAGE8R5
R5703
1
3.9K 2
5%
F2 GATESLOWDN
4
CRITICAL CPU FAN
MF-LF
2 402
1/8W
MF-LF
Q5700
805 NTHS5443T1H
C5701 1 1206A-03-HF J5700
0.47UF CRITICAL
53780-8604
M-RT-SM
1
2
3
6
7
8
3 10%
D Q5702 16V 2
X7R
L5720 5
2N7002 805 220-OHM-1.4A
SOT23-HF1 FAN_2_PWR FAN_2_PWR_L
46
SMC FAN 3 CTL 1 G S MIN NECK WIDTH=0 25MM
1
0603
2 101

1 MOTOR CONTROL
MIN LINE WIDTH=0 5MM MIN LINE WIDTH=0 5MM 2 TACH
3
2
D5700
1
C5702 3 GND
MMBD914XG 100UF 4 12V DC
SOT23 20%
1 2 16V
ELEC
6.3X5.5-SM1-HF 6
CRITICAL
101 FAN_2_GND 518S0730
CRITICAL
54 53 6
=PP3V3_S0_FAN
1 MIN_NECK_WIDTH=0.25MM
R5700 1
10K
5% CRITICAL
0
R5720
1/16W
MF-LF
L5701 5%
R5797 2 402
FERR-220-OHM 1/10W
SMC FAN 3 TACH 47K FAN_TACH2 101 FAN_TACH2_L MF-LF
46 1 2 1 2 2 603
5% 0402
1/16W PLACEMENT_NOTE=PLACE R5720 CLOSE TO J5700 Pin3
MF-LF
402
B B
FAN 3 SMC CONTROL (UNUSED)

PAGE TITLE
CPU FAN
DRAWING NUMBER SIZE

REVISION
R
10.1.0
57 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
48 6 =PP3V3 S5 ROM
R6100 1 1
CRITICAL
8
R6101 C6100 1
3.3K 3.3K 1UF VDD
5% 5%
10%
1/16W 1/16W 6 3V
MF LF MF LF 2
402 2 2 402
CERM
402 U6100
R6150 64MBIT R6152
33 SOIC 33
94 48 18 IN SPI_CLK_R 1 2 94 SPI_CLK 6 SCK SI 5 94 SPI_MOSI 1 2 SPI_MOSI_R IN 18 48 94
5% 5%
PLACEMENT NOTE=PLACE CLOSE TO U6100
1/16W
SST25VF064C 1/16W
PLACEMENT NOTE=PLACE CLOSE TO U6100
MF LF R6105 MF LF
94 48 IN SPI_MLB_CS_L 402 1 CE* 33 402
SO 2 94 SPI_MISO_R 1 2 SPI_MISO OUT 18 48 94
SPI_WP_L 3 WP* OMIT
5%
SPI_HOLD_L 7 HOLD* 1/16W
MF LF
VSS 402
4
B B

PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE

REVISION
R
10.1.0
61 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC PLACE C6200 AS CLOSE TO PIN 9 AS POSSIBLE
APPLE P/N 353S2592 PP5V_AUDIO_HPAMP 56 98
IN
VD MUST BE LESS THAN OR EQUAL TO VL_HD
6 =PP1V5_S0_AUD_DIG
=PP3V3_S0_AUDIO IN 6 58 59 60 61 62
C6201 1 1 C6200
4.7UF 0.47UF
20% 10% PP4V5_AUDIO_ANALOG 56 58 59 61 98
4V 10V IN
X5R-1 2 2 X5R
CRITICAL
402 402 C6205 1 1 C6204C6206 C6207
C6208 1
1UF 0.47UF
0.47UF
1 1
10UF
10UF 10% 10%
20%
16V 2
C6202 1 1 10V
C6203 402-1
X5R 2
10V
2 X5R 10%
10V
20%
6.3V
0.47UF X5R 2 2 CERM-X5R
D 56 GND AUDIO HPAMP

POLY-TANT
CASE-B2-SM 10%
10V
10UF
20%
402
402 0402-1 D
24
46
25
X5R 2 2 16V
9
98 61 59 58 56 PP4V5_AUDIO_ANALOG POLY-TANT GND_AUDIO_HPAMP 56
IN
C6209 1 1 C6210 VD VA_REF VA_HP VA
402 CASE-B2-SM
GND_AUDIO_CODEC
1 2.2UF 2.2UF 56 57 58 59 60 61 62
1
R6200 20%
6.3V
20%
6.3V VBIAS_DAC 29 VBIAS_DAC TWEETERS R6205
2.67K CERM 2 2 CERM AUD_HP_PORT_L 0
1% 402-LF 402-LF HPOUT_L 38 MIN_LINE_WIDTH=0 1MM MIN_NECK_WIDTH=0 1MM OUT 59 5%
1/16W CS4206 FP 44 VHP_FILT+ CRITICAL 1/16W
MF-LF HPOUT_R 40 MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM AUD_HP_PORT_R MF-LF
2 402
CS4206_FN 41 VHP_FILT- U6201 OUT 58
2 402
CS4206B HPREF 39 MIN_LINE_WIDTH=0 2MM MIN_NECK_WIDTH=0 1MM AUD_HP_PORT_REF
QFN
NC TP AUD DMIC SDA1 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 AUD LO1 L P OUT 57 62
NC TP_AUD_GPIO_1 12 GPIO1/DMIC_SDA2
/SPDIF_OUT2
LINEOUT_L1- 34 AUD_LO1_L_N OUT 57 62
HP AMP 57 OUT AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_R_P OUT 57 62 HP AMP/LINE OUT

SPEAKERS 58 OUT AUD_GPIO_3 15 GPIO3 LINEOUT_R1- 37 AUD_LO1_R_N OUT 57 62
61 IN AUD SENSE A 13 SENSE_A LINEOUT_L2+ 31 AUD LO2 L P OUT 59 62
CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_L_N OUT 59 62 WOOFERS

CS4206_FLYC LINEOUT_R2+ 32 AUD_LO2_R_P OUT 58 62
45 FLYP
LINEOUT_R2- 33 AUD_LO2_R_N
C6211 1 1 C6212 43 FLYC OUT 58 62
2.2UF 2.2UF 42 FLYN

20% 20%
6.3V
CERM 2 2 6.3V
CERM MICBIAS 16 AUD_CODEC MICBIAS OUT 61
402-LF 402-LF MIN_LINE_WIDTH=0.20MM PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
MIN_NECK_WIDTH=0.15MM PART NUMBER
3 VL_HD
CS4206_FLYN MIN_LINE_WIDTH=0.20MM
VCOM 28 CS4206 VCOM MIN_NECK_WIDTH=0.15MM 353S2592 353S3199 U6201 CS4206A
1 VL_IF
PLACE TP FOR ALL HDA SIGNALS NEAR CODEC
LINEIN_L+ 21 AUD LI P L IN 57
94 18 IN HDA_BIT_CLK 6 BITCLK
LINEIN_C- 22 AUD LI COM IN 57
HDA_SYNC AUD_LI_P_R
C 94 18 IN
R6201 10 SYNC
LINEIN_R+ 23 IN 57
C
22
94 18 OUT HDA SDIN0 1 2 94 AUD SDI R 8 SDI MICIN_L+ 18 AUD MIC INP L IN 62
5% 5 SDO MICIN_L- 17 AUD_MIC_INN_L IN 62

1/16W
MF-LF MICIN_R+ 19 AUD_MIC_INR_P IN 61 62
402 11 RESET*
94 18 15 IN HDA_SDOUT MICIN_R- 20 AUD_MIC_INR_N IN 61 62
94 18 IN HDA_RST_L
100 84 IN AUD_SPDIF_IN_CODEC 47 SPDIF_IN
94 AUD_SPDIF_CHIP 48 SPDIF_OUT
VREF+_ADC 27 CS4206_VREF_ADC
NC
R6202 MIN_NECK_WIDTH=0.15MM
22 TP_CS4206_DMIC_SCL NC
94 60 OUT AUD_SPDIF_OUT 1 2 DMIC_SCL 4
5% R62031
1/16W 100K
MF-LF 1%
402 1/16W DGND THRM_PAD AGND
MF-LF
402 2
49
26
CRITICAL CRITICAL
1 1
C6213 C6214 DIFF FSINPUT= 2.45VRMS
1UF 10UF
10%
20V 2
20%
2 16V
SE FSINPUT= 1.22VRMS
TANT
CASE-P3-HF
POLY-TANT
CASE-B2-SM
DAC1 FSOUTPUT= 1.34VRMS
56 GND_AUDIO_HPAMP DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
62 61 60 59 58 57 56 GND_AUDIO_CODEC APN 152S1314

CRITICAL
T6250 61 57 PP5V AUDIO ISO
1.8UH-1.6A-243MOHM
ISOLATED 5 V POWER SUPPLY FOR HP AMP LPD3015-SM D6252 MIN NECK WIDTH=0 2MM
VOLTAGE=5V
B APPLE P/N 353S2456 56 6 IN =PP5V_S0_AUDIO 1 3 AUD_XFRMR_SEC 1
DO222-SM
2
B
4.5V POWER SUPPLY FOR CODEC MIN LINE WIDTH=0 4MM
STPS1L30MF
CRITICAL CRITICAL L1 L2
C6250 1 Q6250 NOSTUFF C6256 1
1
R6255 CRITICAL
MIN_LINE_WIDTH=0.40MM 10UF DMMT3906W-7-F 5 1.0K
20% 1 1UF C6258 1 1 C6259 1
VOLTAGE=4.5V 10V
X5R 2
SOT-363 R6258 10% 1%
1/10W
56 SC4503 SW 2 4
10UF
R6257
XW6212 603
1 1K 25V
X5R 2 MF-LF 150UF-.025-OHM 20%
4.99K
1% 20%
PP5V AUDIO HPAMP 56 98 1/16W
402 2 603 6.3V 2 10V
2 X5R
1%
1/10W
OUT TANT
MF-LF MF-LF
1
SC4503_SW_SNBR CASE-B2-SM 603

SM
6 2 402 MIN LINE WIDTH=0 4MM 2 603
MIN NECK WIDTH=0 2MM APN 128S0271
2
SC4503 FB DDROP
D6250
SOD-523
1
R6256 BAT54XV2T1
C6257 1 49.9K 1 62 60 57 56 GND AUDIO ISO
MIN_NECK_WIDTH=0.20MM 0.1UF 1% MIN NECK WIDTH=0 2MM
VOLTAGE=4.5V 10% 1/16W VOLTAGE=0V
16V
L6210 X7R-CERM 2 MF-LF
FERR-220-OHM VR6201
TPS71745
VOLTAGE=4.5V
402 2 402
R6260
=PP5V S0 AUDIO 1 2 4V5 REG IN 6 IN 1 PP4V5 AUDIO ANALOG
56 6 IN 98 SON
OUT OUT 56 58 59 61 98 R62541 1
10 2 GND_AUDIO_ISO 56 57 60 62
0402 CRITICAL 20
1% 1%
R6220 100 4V5_REG_EN 4 EN NR/FB 3 4V5_NR SOT-363 1/10W 1/10W
2 MF-LF MF-LF
0 DMMT3906W-7-F 603 2 603
56 6 IN =PP5V_S0_AUDIO 1 2
GND NC 5 MIN_LINE_WIDTH=0.4MM APN 353S3080 Q6250 D6251
5%
2
MIN_NECK_WIDTH=0.2MM CRITICAL R6253 SOD-523
1/16W NOSTUFF SC4503_SW 56 43.2K2
MF-LF
402 1 C6221 1 C6222 C6223 1 1 C6224 MIN LINE WIDTH=0 3MM
SC4503 FB RDIV
3
SC4503 FB PNP 1
4
SC4503 FB FILT 2 1 SC4503 SW D
0.1UF 1UF 1%
1UF 1UF 10%
16V
10%
10V R6250 1 1/16W BAT54XV2T1
10% 10% 1
R6251 MF-LF
5
SW 1
10V 10V X7R-CERM 2 2 X5R

40.2K 402
A 2 X5R
402-1
2 X5R
402-1
402 402-1
GND_AUDIO_CODEC 56 57 58 59 60 61 62
1%
1/16W
MF-LF
IN
U6250 1%
3.40K
1/16W
NOSTUFF NOSTUFF SYNC MASTER=K62 DAVID SYNC DATE=01/09/2011 A
NOSTUFF MIN_LINE_WIDTH=0.5MM 402 2
SC4503 MF-LF C6254 1 1 C6261 1
R6259 C6255 1 PAGE TITLE
R6212
VOLTAGE=0V TSOT-23
4 SHDN*/SS
MIN NECK WIDTH=0 2MM 2 402 0.01UF
10%
16V
0.001UF
10%
50V 1%
100K 0.001UF
10%
50V
AUDIO: CODEC/REGULATOR
1
0 2
SC4503_SHDN_L FB 3 SC4503_FB CERM 2 2 X7R 1/16W X7R 2 DRAWING NUMBER SIZE
MF-LF
5%
SYM VER 2
CRITICAL NOSTUFF
402 402
2 402
402
1
1/16W
MF-LF C6252 1 1 C6251 C6253 1 R6252 R
REVISION
402
0.1UF 0.1UF GND 1UF 1%
12.4K 10.1.0
10% 10% 10% NOTICE OF PROPRIETARY PROPERTY:
R6210
2
16V 16V 10V 1/16W BRANCH

0 XW6211 X7R-CERM 2 2 X7R-CERM X5R 2 MF-LF
1 2 GND_AUDIO_HPAMP 56
402 402 402-1 2 402 THE INFORMATION CONTAINED HEREIN IS THE
MIN_LINE_WIDTH=0.2MM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1
5% SM MIN NECK_WIDTH=0.1MM
1/10W
MF-LF
VOLTAGE=0V I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
62 OF 110
603 SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SIGNAL_MODEL=EMPTY
C6362
220PF
1 2
5%
25V
CERM
402
R6362
7.87K2
1
R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
1%
1/16W
MF-LF MAX97220_OUTR OUT 57 60 61 56 PP5V_AUDIO_ISO
402
D CRITICAL
C6361 R6361
SIGNAL_MODEL=EMPTY D
33UF
AUD_LO1_R_N 1 2 62 AUD_LO1_R_C_N 1
10K 2 MAX97220_INR_N C6350 1 1 C6351 C6352 1 1 C6353
62 56 IN OUT 57 62
0.1UF 10UF 1UF 1UF
1% 10% 20% 10% 10%
1/16W 16V 10V 10V 10V
20% X7R-CERM 2 2 X5R X5R 2 2 X5R
6.3V MF-LF
402 402 603 402-1 402-1
TANT
CASE-A
62 60 57 56 GND_AUDIO_ISO GND_AUDIO_ISO 56 57 60 62
CRITICAL
C6363 R6363
13
33UF
9
10K
62 56 IN AUD_LO1_R_P 1 2 62 AUD_LO1_R_C_P 1 2 MAX97220_INR_P OUT 57 62
PVDD
SVDD
SVDD2
1%
20% 1/16W R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
6.3V MF-LF
TANT 402
CASE-A
SIGNAL_MODEL=EMPTY 62 57 IN MAX97220 INR N 14 INL- OUTL 12 MAX97220 OUTR OUT 57 60
SIGNAL_MODEL=EMPTY 15 INL+ CRITICAL MIN_LINE_WIDTH=0.4MM
R63641 62 57 MAX97220_INR_P MIN_NECK_WIDTH=0.2MM
7.87K
1 C6364 IN
U6350 BIAS 11 MAX97220_BIAS
1% 220PF MAX97220AETE MIN_NECK_WIDTH=0.2MM
1/16W 5%
25V 62 57 IN MAX97220_INL_P 7 INR+ TQFN OUTR 10 MAX97220_OUTL OUT 57 60
MF-LF 2 CERM MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
402 2 402 L6350 62 57 IN MAX97220_INL_N 8 INR- MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
R6365 FERR-220-OHM C1P
2
MAX97220_C1P
0
GND_AUDIO_ISO 1 2 MAX97220_SGND AUD_GPIO_2 1 2 MAX97220_SHDN_L 16 SHDN* C1N 4
17 THM_PAD
62 60 57 56 56 IN
5% 0402 1 C6355 1 C6356
PGND
SGND
PVSS
1/16W
MF-LF 1UF 1UF
402 SIGNAL_MODEL=EMPTY 10% 10%
1 SIGNAL_MODEL=EMPTY 1 2 10V
X5R 2 10V
X5R
R6374 1 C6374 R6350 402-1 402-1
5
7.87K 220PF 100K
1% 5%
1/16W 5% 1/16W MAX97220_C1N
MF-LF 2 25V
CERM MF-LF MIN_LINE_WIDTH=0.4MM
402 2 402 402 2 MIN_NECK_WIDTH=0.2MM
C CRITICAL
C6373
C
33UF R6373
10K MAX97220 PVSS
62 56 IN AUD_LO1_L_P 1 2 62 AUD_LO1_L_C_P 1 2 MAX97220_INL_P OUT 57 62 MIN_LINE_WIDTH=0.5MM
1% VOLTAGE=0V
20% 1/16W
6.3V
TANT
MF-LF
402
1 C6354
CASE-A 1UF
10%
10V
2 X5R
CRITICAL 402-1
C6371 R6371
33UF
10K
62 56 IN AUD_LO1_L_N 1 2 62 AUD_LO1_L_C_N 1 2 MAX97220_INL_N OUT 57 62
1%
20% 1/16W 62 60 57 56 GND_AUDIO_ISO
6.3V MF-LF
TANT 402
CASE-A SIGNAL_MODEL=EMPTY
MAX97220_OUTL OUT 57 60
R6372
1
7.87K2
1%
1/16W
MF-LF
402
C6372
220PF
1 2
5%
25V
CERM
402 CODEC Nom SE RIN = 20K OHMS
SIGNAL_MODEL=EMPTY
FC = 3.62 HZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
B NET RIN = 18K OHMS B
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM MIN_NECK_WIDTH=.2MM
CRITICAL MIN_LINE_WIDTH=.3MM
MIN_NECK_WIDTH=0.2MM R6300 C6300
AUD_LI_LF 22UF
7.87K2
60 IN AUD_LI_L 1 2 1 AUD_LI_P_L OUT 56
1%
1/16W 20%
MF-LF 6.3V
402 TANT
CASE-P
NOSTUFF
R63011 1 C6301
21.5K 820PF
1% 10%
1/16W 50V
MF-LF 2 CERM
402 2 402
MIN_NECK_WIDTH=0.2MM CRITICAL MIN_NECK_WIDTH=.2MM

MIN_LINE_WIDTH=0.3MM C6302 MIN_LINE_WIDTH=.3MM
22UF
60 IN AUD LI GND 2 1 AUD LI COM OUT 56
20%
6.3V
1 TANT
R6303 CASE-P
10
1%
1/16W NOSTUFF
MF-LF
2 402
R63051 1 C6304
21.5K 820PF
1% 10%
1/16W
GND AUDIO CODEC 2 50V
A 62 61 60 59 58 56 IN MF-LF
402 2
CERM
402
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
SYNC MASTER=K62 DAVID SYNC DATE=01/09/2011 A
PAGE TITLE
MIN_NECK_WIDTH=0.2MM R6306
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
CRITICAL
C6303 AUDIO: FILTER/BUFFER
7.87K2 AUD_LI_RF 22UF DRAWING NUMBER SIZE
60 IN AUD_LI_R 1 2 1 AUD_LI_P_R OUT 56
1% REVISION
1/16W 20% R
MF-LF
402
6.3V
TANT
10.1.0
CASE-P NOTICE OF PROPRIETARY PROPERTY: BRANCH
63 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RIGHT CH SPEAKER AMP
APPLE P/N 353S3069
59 6 IN =PP12V S0 AUDIO SPKRAMP
CRITICAL
C6400 1 C6401 C6402 1 C6403 C6404 1 C6405 R6402 = HIGH = 400 KHZ
1
=PP3V3_S0_AUDIO
1 1 1
C6406 SPEAKER AMP GAIN = +9 DB
10UF 0.1UF 62 61 60 59 56 6
0.1UF 1UF 0.1UF 1UF 220UF
10%
25V 2
10%
2 25V
NOSTUFF NOSTUFF 10%
25V 2
10%
2 25V
10%
25V 2
10%
2 25V
20%
2 16V
SPEAKER AMP RIN = 210K NOMINAL W/ +9 DB GAIN
X5R X5R X5R X5R X5R X5R
805 402 R64021 R64041 1
R6406 402 603-1 402 603-1
ELEC
SM-CASE-C1-HF
FC_HPF, TWEETERS = ~924 HZ (820 PF)
5%
0
5%
0
5%
0 FC_HPF, WOOFERS = ~23 HZ (0.033 UF)
1/16W 1/16W 1/16W
D MF-LF
402 2
MF-LF
402 2
MF-LF
2 402
D
AUD_RAMP_GAIN0
INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS AUD_RAMP_GAIN1 C6413 SIGNAL_MODEL=EMPTY

0.22UF CRITICAL
L6400 C6408 1 1 1 2 L6404
FERR-1000-OHM 820PF R6405 R6407 AUD_RAMP_BSPL
MIN LINE WIDTH=0 20MM 220-OHM-25%-2.5A
1 2 1 2
0 0 MIN NECK WIDTH=0 15MM 20%
AUD HP R N AUD_RAMP_RINC_P AUD_RAMP_RIN_P
26
27
14
15
62 58 IN 62 62 5% 5% 25V 1 2
AUD RAMP OUTPL AUD SPKR RWFR OUT P
AVCC 4
1/16W 1/16W X5R OUT 60 62
0402 MF-LF MF-LF MIN LINE WIDTH=0 6MM
10% 402 2 603 0603
50V 2 402 MIN NECK WIDTH=0 25MM
PVCCL
PVCCR
CERM SIGNAL_MODEL=EMPTY
402
CRITICAL
L6401 C6409 L6405
FERR-1000-OHM 820PF
U6400 220-OHM-25%-2.5A
62 58 AUD_HP_R_P 1 2 62 AUD RAMP RINC N 1 2 62 AUD RAMP RIN N
IN
0402
TPA3117D2 C6414 AUD_RAMP_OUTNL
1 2 AUD_SPKR_RWFR_OUT_N OUT 60 62
10% 9 RINP QFN BSPL 25 0.22UF MIN NECK WIDTH=0 25MM 0603
50V CRITICAL
CERM 8 RINN OUTPL 24 AUD RAMP BSNL 1 2
OUTNL 22 MIN NECK WIDTH=0 15MM
1 LINN 20%
L6402 C6410 32 LINP
BSNL 21 25V
X5R
FERR-1000-OHM 0.033UF 603
1 2 AUD_RAMP_LINC_N 1 2 AUD_RAMP_LIN_N PP5V_RAMP_VREG
62 56 IN AUD LO2 R N 62 62 MIN NECK WIDTH=0 20MM
3
GAIN0 BSPR
17
C6415 SIGNAL_MODEL=EMPTY
0402
R6408 GAIN1 OUTPR 0.22UF CRITICAL
10%
16V 10 OUTNR 19 AUD_RAMP_BSPR 1 2 L6406 OUTPUT POLARITY FLIP TO
X5R 1 2 AUD_RAMP_REG_OUT 6 REG_OUT 20 MIN LINE WIDTH=0 20MM 220-OHM-25%-2.5A MAKE LAYOUT MORE LOGICAL
402 BSNR MIN NECK WIDTH=0 15MM
1% 20%
L6403 C6411 1/16W
MF-LF
AUD RAMP PLIMIT 7 PLIMIT 25V
X5R
AUD RAMP OUTPR 1 2 AUD SPKR RTWT OUT N OUT 60 62
FERR-1000-OHM 0.033UF 402 12 603 MIN LINE WIDTH=0 6MM
MIN NECK WIDTH=0 25MM 0603
11 PBTL
62 56 AUD_LO2_R_P 1 2 62 AUD RAMP LINC P 1 2 62 AUD RAMP LIN P 13
IN
0402 31 28 SIGNAL_MODEL=EMPTY
C 10%
16V
X5R
AUD_RAMP_FSEL
30
FSEL
SD*
NC
29 CRITICAL
L6407
C
402 10
220-OHM-25%-2.5A
PGND
AGND
THRM
R6409
PAD
AUD_RAMP_OUTNR 1 2 AUD_SPKR_RTWT_OUT_P
0 C6416 OUT 60 62
AUD_RAMP_PBTL
59 AUD SPKRAMP MUTE L 1 2 0.22UF MIN NECK WIDTH=0 25MM 0603
OUT
AUD_RAMP_BSNR 1 2
18
23
33
5% CRITICAL CRITICAL
1/16W MIN LINE WIDTH=0 20MM
R6400 MF-LF
402
20% SIGNAL_MODEL=EMPTY C6420 1 C6422 1 SIGNAL_MODEL=EMPTY
0 25V 1000PF 1000PF
58 56 AUD GPIO 3 1 2 X5R 5% 5%
IN 603 25V 25V
5% NP0-C0G 2 NP0-C0G 2
1/16W 402 402
MF-LF
402 NOSTUFF 1
NOSTUFF
1 C6417 R6410 1 C6418 1R6403
2.2UF 10K 1UF 0
R64011 1 C6412 20% 1% 10% 5%
CRITICAL CRITICAL
100K
5% 100PF 2 10V
X5R-CERM 1/16W
MF-LF
10V
2 X5R 1/16W
MF-LF
SIGNAL_MODEL=EMPTY 1 C6419 1 C6421 SIGNAL_MODEL=EMPTY
1/16W 5% 402 402 2 402 1000PF 1000PF
MF-LF 2 50V 2 402 5% 5%
CERM 25V 25V
402 2 402 2 NP0-C0G 2 NP0-C0G
402 402
CRITICAL
SE-TO-DIFF CONVERTER
3.3UF R6453 R6454
21K 21K
56 AUD_HP_PORT_R 2 1 AUD_R_SE_DIFF_IN 1 2 AUD_R_SE_DIFF_IN_R 1 2 AUD_SE_DIFF_SHDN_L 59
1% 1%
10% 1/16W 1/16W
16V MF LF MF LF
TANT 402 402
SMA HF1
R6460
B 1
0 2 AUD GPIO 3 IN 56 58
B
5%
1/16W
B4
MF-LF
402
V- 1
C3 C4
AUD_HP_R_P R6461
U6450 C1 OUT 58 62 100K
5%
UCSP 1/16W
C2
V+ MAX4253 MF-LF
B1
CRITICAL 2 402
SIGNAL_MODEL=EMPTY
R6455
2.21K
1 2
1%
1/16W SIGNAL_MODEL=EMPTY
MF LF
402 R6457
2.21K
AUD R SE DIFF P INV 1 2
1%
SIGNAL_MODEL=EMPTY 1/16W
MF LF
R6458 402
2.21K
1 2
1%
MF LF
402 R6456
2.21K
AUD_R_SE_DIFF_N_INV 1 2
1%
1/16W
MF LF
402
98 61 59 56 PP4V5_AUDIO_ANALOG
A R6450 1 CRITICAL
21K B1 PAGE TITLE
1%
1/16W
MF LF
59 AUD_SE_DIFF_VBIAS
MIN LINE WIDTH 0 20MM
A2
V+
MAX4253
UCSP
A1
AUD_HP_R_N
AUDIO: SPEAKER AMP 1
402 DRAWING NUMBER SIZE
C6450 1 1
C6451 2
MIN NECK WIDTH 0 15MM
U6450 OUT 58 62
051-8442 D
4.7UF 0.47UF A3 A4
Apple Inc.
20% 10% V- REVISION
6.3V 2 2
10V B4 R
X5R
402
X5R
402 CRITICAL 10.1.0
R6451 1 1
NOTICE OF PROPRIETARY PROPERTY:
21K C6452 BRANCH
1% 3.3UF THE INFORMATION CONTAINED HEREIN IS THE
1/16W 10% PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MF LF 2 16V THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 TANT
2 SMA HF1 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
64 OF 110
62 61 60 59 57 56 GND_AUDIO_CODEC SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LEFT CH SPEAKER AMP
APPLE P/N 353S3069
58 6 IN =PP12V S0 AUDIO SPKRAMP
CRITICAL
C6500 1 C6501 C6502 1 C6503 C6504 1 C6505 R6502 = LOW = 300 KHZ
1
=PP3V3_S0_AUDIO
1 1 1
C6506 SPEAKER AMP GAIN = +9 DB
10UF 0.1UF 62 61 60 58 56 6
0.1UF 1UF 0.1UF 1UF 220UF
10%
25V 2
10%
2 25V
NOSTUFF NOSTUFF 10%
25V 2
10%
2 25V
10%
25V 2
10%
2 25V
20%
2 16V
SPEAKER AMP RIN = 210K NOMINAL W/ +9 DB GAIN
X5R X5R X5R X5R X5R X5R
805 402 R65041 1
R6506 402 603-1 402 603-1
ELEC
SM-CASE-C1-HF
FC_HPF, TWEETERS = ~924 HZ (820 PF)
5%
0
5%
0 FC_HPF, WOOFERS = ~23 HZ (0.033 UF)
1/16W 1/16W
D MF-LF
402 2
MF-LF
2 402
D
AUD_LAMP_GAIN0
INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS AUD_LAMP_GAIN1 C6513 SIGNAL_MODEL=EMPTY

0.22UF CRITICAL
L6500 C6508 1 1 1 2 L6504
FERR-1000-OHM 820PF R6505 R6507 AUD_LAMP_BSPL
MIN LINE WIDTH=0 20MM 220-OHM-25%-2.5A
1 2 1 2
0 0 MIN NECK WIDTH=0 15MM 20%
AUD HP L N AUD_LAMP_RINC_P AUD_LAMP_RIN_P
26
27
14
15
62 59 IN 62 62 5% 5% 25V 1 2
AUD LAMP OUTPL AUD SPKR LWFR OUT P
AVCC 4
1/16W 1/16W X5R OUT 60 62
0402 MF-LF MF-LF MIN LINE WIDTH=0 6MM
10% 402 2 603 0603
PVCCL
PVCCR
CERM
402 SIGNAL_MODEL=EMPTY
CRITICAL
L6501 C6509 L6505
FERR-1000-OHM 820PF
U6500 220-OHM-25%-2.5A
62 59 AUD_HP_L_P 1 2 62 AUD LAMP RINC N 1 2 62 AUD LAMP RIN N
IN
0402
TPA3117D2 C6514 AUD_LAMP_OUTNL
1 2 AUD_SPKR_LWFR_OUT_N OUT 60 62
10% 9 RINP QFN BSPL 25 0.22UF MIN NECK WIDTH=0 25MM 0603
50V CRITICAL
CERM 8 RINN OUTPL 24 AUD LAMP BSNL 1 2
OUTNL 22 MIN NECK WIDTH=0 15MM
1 LINN 20%
L6502 C6510 32 LINP
BSNL 21 25V
X5R
FERR-1000-OHM 0.033UF 603
1 2 AUD_LAMP_LINC_N 1 2 AUD_LAMP_LIN_N PP5V_LAMP_VREG
62 56 IN AUD LO2 L N 62 62 MIN NECK WIDTH=0 20MM
3
GAIN0 BSPR
17
0402
R6508 GAIN1 OUTPR 0.22UF CRITICAL
10%
16V 10 OUTNR 19 AUD_LAMP_BSPR 1 2 L6506 OUTPUT POLARITY FLIP TO
X5R 1 2 AUD_LAMP_REG_OUT 6 REG_OUT 20 MIN LINE WIDTH=0 20MM 220-OHM-25%-2.5A MAKE LAYOUT MORE LOGICAL
402 BSNR MIN NECK WIDTH=0 15MM
1% 20%
L6503 C6511 1/16W
MF-LF
AUD LAMP PLIMIT 7 PLIMIT 25V
X5R
AUD LAMP OUTPR 1 2 AUD SPKR LTWT OUT N OUT 60 62
FERR-1000-OHM 0.033UF 402 12 603 MIN LINE WIDTH=0 6MM
MIN NECK WIDTH=0 25MM 0603
11 PBTL
62 56 AUD_LO2_L_P 1 2 62 AUD LAMP LINC P 1 2 62 AUD LAMP LIN P 13
IN
0402 31 28 SIGNAL_MODEL=EMPTY
C 10%
16V
X5R
AUD_LAMP_FSEL
30
FSEL
SD*
NC
29 CRITICAL
L6507
C
402 10
220-OHM-25%-2.5A
PGND
AGND
THRM
R6509
PAD
AUD_LAMP_OUTNR 1 2 AUD_SPKR_LTWT_OUT_P
0 C6516 OUT 60 62
AUD_LAMP_PBTL
58 AUD SPKRAMP MUTE L 1 2 0.22UF MIN NECK WIDTH=0 25MM 0603
IN
AUD_LAMP_BSNR 1 2
18
23
33
5% CRITICAL CRITICAL
1/16W MIN LINE WIDTH=0 20MM
MF-LF
402
20% SIGNAL_MODEL=EMPTY C6520 1 C6522 1 SIGNAL_MODEL=EMPTY
25V 1000PF 1000PF
X5R 5% 5%
603 25V 25V
NP0-C0G 2 NP0-C0G 2
402 402
NOSTUFF 1
R65021 1 C6517 R6510 1 C6518 1R6503
0 2.2UF 10K 1UF 0 CRITICAL CRITICAL
5% 20% 1% 10% 5%
1/16W
MF-LF
2 10V
X5R-CERM 1/16W
MF-LF
10V
2 X5R 1/16W
MF-LF
SIGNAL_MODEL=EMPTY 1 C6519 1 C6521 SIGNAL_MODEL=EMPTY
402 2 402 402 2 402 1000PF 1000PF
2 402 5% 5%
25V 25V
2 NP0-C0G 2 NP0-C0G
402 402
CRITICAL
SE-TO-DIFF CONVERTER
SIGNAL_MODEL=EMPTY
C6553
3.3UF R6553 R6554
21K 21K
56 AUD_HP_PORT_L 2 1 AUD_L_SE_DIFF_IN 1 2 AUD_L_SE_DIFF_IN_R 1 2
1% 1%
10% 1/16W 1/16W
16V MF LF MF LF
TANT 402 402
SMA HF1
B AUD_SE_DIFF_SHDN_L IN 58
B
B4
C3 V- C4
AUD_HP_L_P
U6550 C1 OUT 59 62
UCSP
C2
V+ MAX4253
B1
SIGNAL_MODEL=EMPTY CRITICAL
R6555
2.21K
1 2
1%
MF LF
402 R6557
2.21K
AUD L SE DIFF P INV 1 2
1%
SIGNAL_MODEL=EMPTY 1/16W
MF LF
R6558 402
2.21K
1 2
1%
MF LF
402 R6556
2.21K
AUD_L_SE_DIFF_N_INV 1 2
1%
1/16W
MF LF
402
98 61 58 56 PP4V5_AUDIO_ANALOG
A CRITICAL
B1 PAGE TITLE
A2
V+
MAX4253
UCSP
A1
AUD_HP_L_N
AUDIO: SPEAKER AMP
DRAWING NUMBER SIZE
C6550 1 1
C6551 U6550 OUT 59 62
051-8442 D
4.7UF 0.47UF 58 AUD SE DIFF VBIAS A3 A4
Apple Inc.
20% 10% V- REVISION
6.3V 2 2
10V B4 R
X5R
402
X5R
402 10.1.0
65 OF 110
62 61 60 58 57 56 GND_AUDIO_CODEC SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPEAKER CABLE CONNECTORS
APPLE P/N 518S0748
INTERNAL MIC CON APPLE P/N 518S0656
APPLE P/N 518S0677
PROPERTIES FOR ALL SPKR NETS
PROPERTIES FOR ALL SPKR NETS CRITICAL CRITICAL
CRITICAL
J6602 J6603
J6601 78048-0573
78048-0473 M-RT-SM
L6600 53780-8603 M-RT-SM
M-RT-SM
FERR-1000-OHM 4 1
62 59 IN AUD_SPKR_LWFR_OUT_P 1
62 58 IN AUD_SPKR_RWFR_OUT_P WOOFER (BL) 2
AUD_MIC1_IN_N 1 2 WOOFER (BR) 62 59 AUD SPKR LWFR OUT N
D
62 61 OUT
0402
62 AUD_MIC_IN1_CONN_N
1
62 58
62 58
IN
IN
AUD_SPKR_RWFR_OUT_N
AUD_SPKR_RTWT_OUT_P
2
3 NO_TEST
IN
NC NC J6702 3 3 D
2
TWEETER (FR) 4
62 59 IN AUD_SPKR_LTWT_OUT_P 4
L6602 GND_AUDIO_MIC1 CONN 62 58 IN AUD_SPKR_RTWT_OUT_N TWEETER (FL) AUD_SPKR_LTWT_OUT_N 5
MIN_LINE_WIDTH=0.3MM 62 59 IN
FERR-1000-OHM MIN NECK_WIDTH=0.2MM 3
VOLTAGE=0V
62 61 OUT AUD_MIC1_IN_P 1 2 62 AUD_MIC_IN1_CONN_P
5
0402
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
CRITICAL 2 2
CRITICAL
DZ6600 DZ6601 1
R6600
6.8V-100PF 6.8V-100PF 0
402 402 5%
1/16W
MF-LF
1 1 2 402
C C
R6601
22
100 94 84 OUT AUD_SPDIF_IN 1 2
L6604 5%
1/16W
FERR-1000-OHM MF-LF
402
61 59 58 56 6 IN =PP3V3_S0_AUDIO 1 2
62
0402
L6605 REMOTE I/O CONNECTOR
FERR-1000-OHM APPLE P/N 518S0723
61 OUT AUD_LI_TIP_DET 1 2
CRITICAL L6610 0402
10-OHM-1A
CRITICAL
AUD_LI_GND 1 2
57 OUT
MIN_LINE_WIDTH=0.3MM 0402 L6607
J6600
MIN_NECK_WIDTH=0.2MM FERR-1000-OHM 20143-020E-20F
F-RT-SM
57 OUT AUD_LI_R 1 2 21
0402
MIN_LINE_WIDTH=0.3MM L6608 1
MIN_NECK_WIDTH=0.2MM FERR-1000-OHM
101 AUD_SPDIFIN_JACK 2
57 OUT AUD LI L 1 2
MIN_LINE_WIDTH=0 4MM MIN_NECK_WIDTH=0 2MM VOLTAGE=3 3V 101 98 PP3V3_AUDIO_SPDIF_JACK 3
0402 L6609 101 AUD LI DET JACK 4
FERR-1000-OHM MIN_LINE_WIDTH=0 4MM MIN_NECK_WIDTH=0 2MM
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD_LI_GND_JACK 5
62 61 59 58 57 56 OUT GND_AUDIO_CODEC 1 2
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD LI R JACK 6
AUD_LI_GND_JACK 7
MIN_NECK_WIDTH=0.1MM FERR-1000-OHM MIN_LINE_WIDTH=0 4MM MIN_NECK_WIDTH=0 2MM
B 62 OUT HS_MIC_HI 1
0402
2 MIN_LINE_WIDTH=0 4MM
MIN_LINE_WIDTH=0 4MM
MIN_NECK_WIDTH=0 2MM
MIN_NECK_WIDTH=0 2MM
101 AUD_LI_L_JACK
AUD_GND_DET_JACK
8
9
B
MIN_LINE_WIDTH=0 4MM MIN_NECK_WIDTH=0 2MM 101 HS_MIC_HI_JACK 10
MIN_LINE_WIDTH=0 4MM MIN_NECK_WIDTH=0 2MM 101 AUD_HP_GND_JACK 11
R6617 MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD_HP_L_JACK 12
GND AUDIO ISO 1
0 2 AUD HP GND JACK 13
62 57 56 OUT
CRITICAL 5% MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD HP R JACK 14
1/10W
L6616 MF-LF
603
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD HP TYPEDET JACK 15
FERR-120-OHM-1.5A MIN_LINE_WIDTH=0 4MM MIN_NECK_WIDTH=0 2MM 101 AUD_IP_PERPH_JACK 16
57 IN MAX97220_OUTL 1 2 MIN_LINE_WIDTH=0 4MM MIN_NECK_WIDTH=0 2MM 101 AUD_HP_TIPDET_JACK 17
0402 L6618 CRITICAL PP3V3_AUDIO_SPDIF_JACK 18
FERR-120-OHM-1.5A 19
57 IN MAX97220_OUTR 1 2 20
MIN_NECK_WIDTH=0.1MM FERR-1000-OHM 23
61 OUT AUD HP TYPE 1 2 24
0402 L6615
MIN_LINE_WIDTH=0.2MM FERR-1000-OHM 22
62 61 OUT AUD_IP_PERPH_DET 1 2

MIN_NECK_WIDTH=0.1MM FERR-1000-OHM
61 OUT AUD_HP_TIP_DET 1 2
0402
AUD_SPDIF_OUT CRITICAL CRITICAL 2

CRITICAL 2
CRITICAL 1 C6611 1 C6613 1 C6615
94 56 IN 2 2 DZ6607 DZ6609 0.01UF 0.01UF 0.01UF
C6600 1 1 C6601 DZ6603 DZ6605 6.8V-100PF 6.8V-100PF
10%
2 16V
10%
2 16V
10%
2 16V
A 1UF
10%
10V 2
0.47UF
10%
2 10V
6.8V-100PF
402
6.8V-100PF
402
402 402
CRITICAL
CERM
402
CRITICAL
CERM
402
CERM
402
X5R
402-1
X5R
402
C6604 1 CRITICAL 1 C6608 1 1
DZ6610
2
DZ6612
2 C6614 1 PAGE TITLE
1
0.01UF
10%
1
DZ6606
ESDALC5-1BM2
2
0.01UF
10%
16V
6.8V-100PF 6.8V-100PF
0.01UF
10%
16V
Audio: MLB to I/O Conn.
16V CERM 2 402 402 CERM 2 DRAWING NUMBER SIZE
CERM 2 SOD882
402
402
1 1
402
1 REVISION
R
10.1.0
66 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Internal Microphone Impedance Matching

R6743
2.2K 2
AUD_INTMICBIAS 1 AUD_CODEC_MICBIAS IN 56
5%
1/16W
CRITICAL MF-LF
402
SIGNAL_MODEL=EMPTY 1
R6793 C6751 1
3.40K 4.7UF
1% 20%
1/16W 6.3V 2
D MF-LF
2 402
TANT
603-HF
GND_AUDIO_CODEC 56 57 58 59 60 61 62
D
C6795
0.1UF
62 60 IN AUD_MIC1_IN_P 1 2 AUD_MIC_INR_P OUT 56 62
1 10%
C6750 1 R6791 16V
X5R
0.0082UF 100K 402
10% 5%
25V 2
X7R
1/16W
MF-LF C6796
402 2 402 0.1UF
62 60 IN AUD_MIC1_IN_N 1 2 AUD_MIC_INR_N OUT 56 62
10%
16V
1 X5R
R6792 402
3.40K
SIGNAL_MODEL=EMPTY 1%
1/16W
MF-LF
2 402
XW6702
SM
AUD_MIC1_IN_G 1 2 GND_AUDIO_CODEC 56 57 58 59 60 61 62
IPHS HS Detect Debounce CKT

61 IN JACK_DET_V_FILT 62 61 60 59 58 56 6 =PP3V3_S0_AUDIO
1
R6797 R67981 R67681
100K
10K 100K 5%
5% 5% 1/16W
L6700 1/16W 1/16W MF-LF
FERR-220-OHM MF-LF MF-LF 402 2 R6799
C 98 61 59 58 56 PP4V5_AUDIO_ANALOG 1 2
2 402 402 2
AUD IP PERPH DET DB 1
0 2 AUD IP PERIPHERAL DET
OUT 20 100
C
0402 5%
1/16W
NOSTUFF 6 MF-LF
JACK_DET_V_FILT 402
L6701 MIN_LINE_WIDTH=0.4MM
OUT 61
D
FERR-220-OHM MIN_NECK_WIDTH=0.2MM
1 2
R6796 Q6701
62 61 60 59 58 56 6 =PP3V3_S0_AUDIO AUD_IP_PERPH_DET_INV 0 AUD_IP_PERPH_DET_R G
0402
1 2 2 NTZD3154NT1H
5% SOT-563-HF
1/16W
1 C6700 3 MF-LF
402
S
0.1UF
10% D 1
16V
2 X5R
402
R6700 Q6701 NOSTUFF
17.4K2
62 60 IN AUD_IP_PERPH_DET 1 AUD_IP_PER_DEB 5 G NTZD3154NT1H 1 C6797
62 61 60 59 58 57 56 GND_AUDIO_CODEC 1%
SOT-563-HF 0.1UF
1/16W 10%
MF-LF
402
1 C6740 S 2 16V
X5R
0.1UF 402
10% 4
2 16V
X5R
R6710 402
GND_AUDIO_CODEC
0
62 61 60 59 58 57 56 1 2 JACK_L_RTN_0
5%
1/16W
MF-LF
402
Digital Out Headphone Out LI Insert Detect

(DETECT B) (DETECT D) (DETECT C)
B 61 56 IN AUD_SENSE_A
61 56 IN AUD_SENSE_A 61 56 IN AUD_SENSE_A
B
57 56 IN PP5V_AUDIO_ISO CRITICAL 98 61 59 58 56 IN PP4V5_AUDIO_ANALOG
1 61 IN JACK_DET_V_FILT 1
1
R6794 R6744
R6790 20K 5.11K
10K
0.1%
1/16W R67951 1%
1/16W R67301 1
R6701
5% MF 100K MF-LF 10K 10K
1/16W 2 402 5% 2 402 5% 1%
MF-LF 1/16W 1/16W 1/16W
2 402 AUD_Q6702_D3 NC MF-LF
402 2 AUD_Q6701_D6 NC MF-LF
402 2
MF-LF
2 402
6 3
D D
Q6700 Q6702 60 IN AUD LI TIP DET
60 AUD HP TYPE 2 G NTZD3154NT1H AUD HP TYPE INV 5 G NTZD3154NT1H
IN
SOT-563-HF SOT-563-HF
S S
AUD_LI_TIP_DET_INV
1 4
61 IN JACK_DET_V_FILT
6
AUD HP TIP DET INV D

1
R6762 Q6703
10K 2 G NTZD3154NT1H
A 5%
1/16W
MF-LF 3 6
S
SOT-563-HF
2 402 3 PAGE TITLE
D D
Q6700 Q6702 DP Audio Enable 1 D AUDIO: Detects/Grounding
AUD HP TIP DET 5 G NTZD3154NT1H 2 G NTZD3154NT1H DP_GPU_T29_SEL Q6703 DRAWING NUMBER SIZE
60 IN
SOT-563-HF SOT-563-HF 94 84 18 IN
5 G NTZD3154NT1H
SOT-563-HF
REVISION
S S R
S 10.1.0
4 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
4
R6711 R6712 THE INFORMATION CONTAINED HEREIN IS THE
0 0 62 61 60 59 58 57 56 GND_AUDIO_CODEC THE POSESSOR AGREES TO THE FOLLOWING: PAGE
GND_AUDIO_CODEC 1 2 JACK_L_RTN_1 GND_AUDIO_CODEC 1 2 JACK_L_RTN_2
62 61 60 59 58 57 56
5%
62 61 60 59 58 57 56
5%
67 OF 110
1/16W 1/16W SHEET
MF-LF MF-LF III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
402 402 IV ALL RIGHTS RESERVED 61 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
AUDIO * 0 1 MM ? AUDIODIFF * Y 0 1 MM 0 1 MM 10 MM 0 1 MM 0 1 MM
FUNCTION VOLUME/MUTE CONVERTER PIN COMPLEX SHDN DET ASSIGNMENT
HP/LINE OUT 0X03 (3) 0X03 (3) 0X0A (10,D) GPIO_2 0X0A (D) SPKROUT * 0 2 MM ? SPKROUTDIFF * Y 0 6 MM 0 25 MM 10 MM 0 2 MM 0 2 MM
PRIMARY SPKRS (WFR) 0X04 (4) 0X04 (4) 0X0B (11) GPIO_3 N/A
SECONDARY SPKRS (TWT) 0X02 (2) 0X02 (2) 0X09 (09) GPIO_3 N/A
NET TYPE
SPDIF OUT N/A 0X08 (8) 0x10 (16) N/A 0X0D (B) NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
ELECTRICAL CONSTRAINT SET PHYSICAL SPACING
AUDIODIFF * AUDIODIFF
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD HP L P 59
I213
SPKROUTDIFF * SPKROUTDIFF I214 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD HP L N 59
CODEC INPUT SIGNAL PATHS AUD HP R P 58
D FUNCTION
CONVERTER PIN COMPLEX ENABLE/CONTROL DET ASSIGNMENT
I215
I216
AUDIO DIFFPAIR
AUDIO DIFFPAIR
AUDIODIFF
AUDIODIFF
AUDIO
AUDIO AUD HP R N 58 D
LINE IN I217 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 L P 56 57
0X05 (5) 0X12 (12,C) N/A 0X12 (C)
SPDIF IN I218 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 L N 56 57
0X07 (7) 0x0F (15) N/A N/A
INTERNAL MIC I211 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 R P 56 57
0X06 (6) 0X0E (14,LEFT & RIGHT) N/A N/A
EXTERNAL MIC I212 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 R N 56 57
0X06 (6) 0X0D (13,V22,B,LEFT) COUGAR POINT GPIO 16 COUGAR POINT GPIO 5 (RCVR INT)
COUGAR POINT GPIO 3 (PERIPH DET) I210 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO2 L P 56 59
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO2 L N 56 59

I209
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO2 R P 56 58
I208
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO2 R N 56 58
I206
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP LINC P 58
I207
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP LINC N 58
I204
I205 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP RINC P 58
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP RINC N 58

I203
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP LIN P 58
I220
I219 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP LIN N 58
MIKEY RECEIVER
WRITE: 0X72 READ: 0X73
CKT
APN 353S2640
I222
I221
I224
I223
AUDIO DIFFPAIR
AUDIO DIFFPAIR
AUDIO DIFFPAIR
AUDIO DIFFPAIR
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIO
AUDIO
AUDIO
AUDIO
AUD RAMP RIN P
AUD RAMP RIN N
AUD LAMP LINC P
AUD LAMP LINC N

58
58
59
59
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP RINC P 59

I226
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP RINC N 59
I225
I227 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP LIN P 59
L6800 MIN NECK_WIDTH=0.15MM
VOLTAGE=3.3V I229 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP LIN N 59
FERR-1000-OHM AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP RIN P 59
98 62 PP3V3_S0_HS_F I228
61 60 59 58 56 6 IN =PP3V3 S0 AUDIO 1 2
I230 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP RIN N 59
0402 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 L C P 57
I232
C I233
I235
AUDIO DIFFPAIR
AUDIO DIFFPAIR
AUDIODIFF
AUDIODIFF
AUDIO
AUDIO
AUD LO1 L C N
AUD LO1 R C P
57
57
C
I234 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 R C N 57
R6802 I236 AUDIO DIFFPAIR AUDIODIFF AUDIO MAX97220 INL P 57
0
49 IN =I2C_AUDIO_SCL 1 2
I238 AUDIO DIFFPAIR AUDIODIFF AUDIO MAX97220 INL N 57
5% I237 AUDIO DIFFPAIR AUDIODIFF AUDIO MAX97220 INR P 57

1/16W
MF-LF I239 AUDIO DIFFPAIR AUDIODIFF AUDIO MAX97220 INR N 57
402
AUD SPKR RWFR OUT P
R6803 1
1 C6800 I240 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT 58 60
0 R6806 1UF I241 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR RWFR OUT N 58 60
49 BI =I2C_AUDIO_SDA 1 2 10K 10%

2 10V
1 C6801 I242 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR RTWT OUT P 58 60
A2
5% X5R 0.1UF
5% 1/16W 402 CRITICAL I243 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR RTWT OUT N 58 60
1/16W MF-LF 10%
MF-LF
2 402 2 16V
X5R AVDD I244 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR LWFR OUT P 59 60
402 402 MIN_LINE_WIDTH=0.15MM
R6804 U6806
CD3282A1
MIN_LINE_WIDTH=0.15MM MIN_LINE_WIDTH=0.15MM
I246 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR LWFR OUT N 59 60
MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM I245 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR LTWT OUT P 59 60
0 WCSP
100 20 OUT AUD_I2C_INT_L 1 2
C1 HS_MIC_BIAS I247 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR LTWT OUT N 59 60
HS_SCL C3 SCL MICBIAS
5% I252 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD MIC1 IN P 60 61
1/16W
MF-LF HS_SDA B3 SDA DETECT B1 HS_SW_DET AUDIO DIFFPAIR AUDIODIFF AUDIO AUD MIC1 IN N 60 61
I253
402
62 HS_RST D3 D1 I254 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD MIC INR P 56 61
R6805 HS_INT_L INT* BYPASS HS_RX_BP
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD MIC INR N 56 61
I255
AUD_IPHS_SWITCH_EN 1
0 2 A3
100 21 IN ENABLE I256 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD MIC IN1 CONN P 60
CRITICAL
5%
HS_HDET A1
1 C6802 1 I257 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD MIC IN1 CONN N 60
1/16W
MF-LF
HDET 0.01UF C6803
402 10% 4.7UF
C2 DGND
D2 AGND
1
B2 CS 2 25V
X7R
20%
R6816 R6807 402 2 6.3V
TANT
AUD IP PERPH DET 2
0 1
100K 603-HF
61 60 IN 5%
1/16W
5% MF-LF
1/16W
MF-LF 2 402
B 402
B
62 61 60 59 58 57 56 GND AUDIO CODEC
1 1
R6808 R6809
1K 2.2K
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402
98 62 PP3V3_S0_HS_F
C6810 1 1 C6811 8
1UF
10%
0.1UF
10% MIN_LINE_WIDTH=0.15MM R6810
MIN_NECK_WIDTH=0.1MM C6804 MIN_LINE_WIDTH=0.15MM
10V 16V VCC MIN_NECK_WIDTH=0.1MM 0.1UF
HS_MIC_HI X5R 2 2 X5R
HS_MIC_HI_SW 1
2.2K 2 AUD_MIC_INF 1 2 AUD_MIC_INP_L
60 IN
MIN_LINE_WIDTH=0.15MM 402 402 U6807 OUT 56
MIN_NECK_WIDTH=0.1MM 5%
NX3L2G66GD 1/16W 10%
1 1Y 1Z 2 1 16V
7 1E
R6812 MF-LF
402 1 C6806 X5R
402
100K 0.0082UF
SOT996-2 5% 10%
5 2Y 2Z 6 1/16W
HS_MIC_LO MF-LF 2 25V
X7R C6805 MIN_LINE_WIDTH=0.15MM
R6814 VOLTAGE=0V
MIN_LINE_WIDTH=0.15MM AUD_SW_SEL 3 2E 2 402 MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM 402
0.1UF
0 MIN_NECK_WIDTH=0.1MM
60 57 56 GND_AUDIO_ISO 2 1
GND HS_MIC_LO_SW 1 2 AUD_MIC_INN_L OUT 56
5%
10%
1/16W
MF-LF R6815 4 16V
X5R
402
HS RST 0 1 402
A 2 1
R6811
PLACE R6814 NEAR J6600
62
5%
1/16W 5%
0 FLP = 8.82 KHZ
FHP = 80 HZ SYNC MASTER=K62 DAVID
PAGE TITLE
SYNC DATE=01/09/2011 A
MF-LF 1/16W
402 MF-LF
2 402 AUDIO: Mikey
DRAWING NUMBER SIZE
62 61 60 59 58 57 56 GND AUDIO CODEC Apple Inc. 051-8442 D

REVISION
R
10.1.0
68 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SLP_S4 ENABLES
64 63 11 6 =PP3V3_S5_PWRCTL
C6910
R6971 0 1UF
0 2 1
100 47 46 19 5 PM_SLP_S5_L 1 2
5% 20%
1/16W 10V
D MEMVTT_EN SEQUENCE
MF-LF
402
NOSTUFF
CERM
402 D
R6972 14 74LVC08
=PP3V3_S0_PWRCTL PM SLP S4 L 1
0 2 100 PM SLP S4 1 L R 1 TSSOP-HF R6911
100 63 47 46 32 19 5
81 74 64 6
3
33 PM EN P3V3 S3 FET
5%
U6900 100 S4 ENABLES 1 2 74 100
1/16W
MF-LF 2 08 5% Enable FET
402 1/16W
MF-LF
1 1 7 402
R6951 R6952
10K 10K R6912
5%
1/16W
5%
1/16W 1
33 2 PM EN P5V S3 REG 71 100
MF-LF MF-LF
2 402 2 402 5% ENABLE REGULATOR
1/16W
PM EN DDRVTT S0 REG MF-LF
32 63 72 100
64 63 11 6 =PP3V3_S5_PWRCTL 402
NOSTUFF
1 C6951 1
NOSTUFF
C6953
100PF 1
5%
50V
2 CERM
3
Q6911 10%
0.1UF R6915
VTT_REG_PGOOD_L 5
2 16V 1 10K
402 MMDT3904-X-G
SOT 363 LF
X5R
402 R6916 5%
1/16W
NOSTUFF NOSTUFF
100K MF-LF 1
C6920 1
C6921
4 5% 2 402 0 47UF 0 47UF
1/16W 10% 10%
MF-LF
2 402
CPU_SKTOCC 94 2
6 3V
2
6 3V
R6950 6 CERM-X5R
402
CERM-X5R
402
1
10K 2 2
Q6911
64 63 PM_PGOOD_P1V05_S0_REG 100 CPUVTT_REG_PGOOD_R MMDT3904-X-G 3
100 68
5% SOT 363 LF
D
1/16W
MF-LF
NOSTUFF 1 Q6910
402 1 C6952 1
2N7002
SOT23-HF1
0.47UF 100 11 CPU_SKTOCC_L G S
10%
2 6.3V
CERM-X5R 2
402
R6970
C 1
NOSTUFF
R6917 PLACE TOP SIDE
100 83 71 63 PM_PGOOD_P5V_S3_REG 1
0 2 PM_EN_USB_PWR 43 94
C
10K 5% NOSTUFF
5% REWORK TO POWER UP WITH NO CPU 1/16W
1
1/16W MF-LF
402
C6924
MF-LF
0 47UF
2 402 10%
6 3V
2 CERM-X5R
402
=PP3V3_S5_PWRCTL
64 63 11 6
14 74LVC08 NOSTUFF
PM_SLP_S4_L TSSOP-HF
100 63 47 46 32 19 5 4
PM_EN_DDR1V5_S3_REG
R6931
6 72 100 33
5
U6900 100 74 64 63 PM_PGOOD_P3V3_S0_FET 1 2 PM EN P1V5 S0 FET 63 74 100
08 5%
1/16W
7 MF-LF
402
100 83 71 63 PM_PGOOD_P5V_S3_REG
64 63 11 6 =PP3V3 S5 PWRCTL
SLP_S3 ENABLES
NOSTUFF OTHER RAILS ENABLED BY P3V3_S0 AND P5V_S0:
R6946 PP1V8_S0 VREG (CPU PLL)
33
2
R6955 1 2 PM EN P3V3 S0 FET 63 74 100
5% OUT
10K
=PP3V3_S5_PWRCTL 5%
64 63 11 6 1/16W Enable FET
MF LF 1/16W
402 MF-LF
402
1
14 74LVC08
P3V3_S5_PWRCTL_U6900_R 10 TSSOP-HF R6947
B 9
U6900
8 1
33 2 PM EN P5V S0 FET OUT 74 100 B
100 64 PGOOD P12V S0 08 5% Enable FET
14 74LVC08 NOSTUFF
1/16W
MF-LF
13 TSSOP-HF 7 NOSTUFF
100 47 46 36 32 26 19 5 PM_SLP_S3_L 402
2 R6944 2 R6941
11 PM_EN_P12V_S0_FET 5% 5%
10K
U6900 6 100
33
1/16W 1/16W
100 72 5 PM PGOOD DDR1V5 S3 REG 12 08 MF LF MF LF
402 402
1 1
7
PM_SLP_S3_BUF_L 100
OPTION TO DELAY 1V8 Enable FET

=PP12V_S0_PWRCTL R6932 PM EN P1V5 S0 FET 63 74 100
6 64 81
PM PGOOD P3V3 S0 FET 1
33 2
100 74 64 63
5% PM_EN_DDRVTT_S0_REG
32 63 72 100
1/16W
MF-LF Enable regulator OPTIONAL SEQUENCE TO DELAY 3V,1V5
402
1 NOSTUFF
R6934
82K R6990 NOSTUFF
NOSTUFF NOSTUFF NOSTUFF NOSTUFF R6930
5% 33 1 1 1 1
33 PM EN P3V3 S0 FET
1/16W
100 74 64 63 PM_PGOOD_P5V_S0_FET 1 2
PM_EN_P1V8_S0_REG 72 100
C6947 1
C6941 C6945 C6946 100 74 64 63 PM PGOOD P5V S0 FET 1 2 63 74 100
MF-LF
0 47UF C6944 0 47UF 0 47UF 0 47UF
2 402 5%
1/16W 10% 0 47UF 10% 10% 10%
5%
1/16W
6 3V 6 3V 6 3V 6 3V
MF-LF 2 CERM-X5R
10%
6 3V
2 CERM-X5R
2 CERM-X5R
2 CERM-X5R
MF-LF
402 2 402
402 CERM-X5R 402 402 402
PM_PGOOD_P5V_S0_FET NOSTUFF
63 64 74 100
1 C6994
402
R6933
1
33 2 PM EN P1V5 S0 FET
0 47UF 100 74 64 63 PM_PGOOD_P5V_S0_FET 63 74 100
10%
1 6 3V 5%
R6935 2 CERM-X5R 1/16W
MF-LF
33K 402
402
5%
1/16W
MF-LF
2 402
A NOSTUFF SYNC MASTER=K62 SIJI SYNC DATE=01/09/2011 A
R6942 Enable regulator CPUVTT VREG/ NOTE: PM_PGOOD_P1V05_S0_REG ENABLES VCCSA REGULATOR CIRCUIT ON PAGE 70 PAGE TITLE
33
1 2 PM_EN_P1V05_S0_REG 68 100
PCH CORE
100 68 64 63
PM_PGOOD_P1V05_S0_REG
MAKE_BASE=TRUE
=PM_EN_VCCSA_S0_CPU POWER SEQUENCING ENABLES
5% DRAWING NUMBER SIZE
1/16W NOSTUFF
MF-LF
402
1 C6942
1UF REVISION
10%
R
R6936 2
6 3V
CERM
10.1.0
33 402
100 74 64 63 PM_PGOOD_P3V3_S0_FET 1 2
Enable regulator THE INFORMATION CONTAINED HEREIN IS THE
5% VCCSA REGULATOR PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
OPTION TO DELAY 1V05 1/16W 100 64 PM_PGOOD_PVCCSA_S0_REG PM_EN_PVCORE_CPU 65 100 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF-LF
402
MAKE_BASE=TRUE TO ENABLE OF CPU VCORE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
69 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PGOOD COMPARATORS FOR PP1V8_S0 AND PP12V_S0
=PP3V3_S0_PWRCTL
81 74 64 63 6
81 64 63 6 =PP12V_S0_PWRCTL
=PP3V3_S5_PWRCTL =PP3V3_S5_PWRCTL
1 64 63 11 6 6 11 63 64
R7020
1
64.9K
1%
R7017
1/16W 10K 1 NOSTUFF
MF LF 5% R7067 1
2 402 1/16W
MF-LF 10K
R7050
1
R7007 1 R7018 2 402
5%
1/16W
1K
5%
10K PGOOD_P1V8_S0 100 MF LF 1/16W
1
49.9K 5% 402
2 MF LF
R7021 1% 1/16W 402

2 =PP3V3_S0_PWRCTL
10K
1/16W MF-LF
2 402
R7066 81 74 64 63 6
D
D 1%
1/16W
CRITICAL
MF LF
402
2
PGOOD_1V8_S0_G2
3
Q7011 100 71 27 PM_PGOOD_P3V3_S5_REG 1

0 2 RSMRST_PWRGD OUT 46 100
2
MF LF
402 8 U7080 5
MMDT3904-X-G 5% To SMC (2) 1
1V60 COMP REF 6 LM393 6
SOT 363 LF
1/16W
MF-LF
NOSTUFF R7061
V+ SOI-HF 4
402 1 C7059 10K
7 PGOOD_1V8_S0_G1 2
Q7011 0.1UF 5%
R7002 MMDT3904-X-G 10%
1/16W
MF-LF
2.0K 2 5 GND SOT 363 LF
2 16V 2 402
6 =PP1V8_S0_PWRCTL 1 1V80_COMP_REF 1
X5R
402
1% 4
1/16W
MF-LF R7063
402 (1.67V/1.22V; 132mV Hysteresis)
PVCCSA_EN_L 1
33 2 PM_EN_PVCCSA_S0_REG_L 100
FROM THIS SMC GENERATES PM_RSMRST_L
WHICH GOES INTO RSMRST_L OF PCH 5%
DELAY IS ABOUT 200MS 1/16W
MF-LF
3 402
R7060 D
Q7010 NOSTUFF
0 2N7002
63 =PM_EN_VCCSA_S0_CPU 1 2 VTTS3PG_1
1 G S SOT23-HF1
1 C7061
83 74 6
=PP3V3_S3_PWRCTL 5% 0.1UF
74 64 33 6 =PP12V S5 PWRCTL 1/16W NOSTUFF 10%
MF-LF 16V
2 2 X5R
402 1 C7066 402
1 0.1UF
R7080 1 10%
33.2K R7086 2 16V
X5R
1%
1
10K 402
1/16W
MF LF 74 64 33 6 =PP12V S5 PWRCTL R7084 5%
1/16W =PP3V3_S0_PWRCTL
2 402 10K MF-LF 81 74 64 63 6
5% 2 402
1/16W
1
C7080 R70831 MF-LF PGOOD_P12V_S0 63 100
VCCSA ENABLE SIGNAL
2 402 1
1
R7081
0.1UF 49.9K
1%
3 1
R7091 R7092
20%
1/16W 10K
100K 2
16V
CERM MF LF PGOOD_12V S0 G2 D
Q7080 10K 5%
1% 603 CRITICAL 402
2 5% 1/16W
1/16W
6
2N7002DW-X-G 1/16W MF-LF
MF LF
U7080 SOT 363 MF-LF 2 402
C 2 402
100 9V_COMP_REF 2
8
LM393
SOI-HF
D Q7080
2N7002DW-X-G
5 G S
4
2 402 PM_PGOOD_PVCCSA_S0_REG
63 64 100 C
V+ PVCCSA_L
R7082 1 PGOOD 12V S0 G1 2 G S
SOT 363
R7093 3
10K Q7090
1
2.0K 2 3 GND 1 2 PVCCSA_R_L 5
MMDT3904-X-G
81 64 63 6 =PP12V_S0_PWRCTL 100 12V_COMP_REF 1
SOT 363 LF
5%
1% 4 1/16W
1/16W MF-LF 4
MF-LF 402
402
(9V/9.58V; 580mV Hysteresis) R7090 6
1K 2
Q7090
6 =PPVCCSA_S0_PWRCTL 1 2 VCCSAPG_1
MMDT3904-X-G
5% SOT 363 LF
1/16W NOSTUFF
MF-LF 1
402 1 C7091
0.1UF
10%
16V
2 X5R
402
S0 RAILS PGOOD
VCCSA POWERGOOD
=PP3V3 S0 PWRCTL 6 63 64 74 81
81 74 64 63 6 =PP3V3 S0 PWRCTL
1 C7050
0 1UF
1
C7022
20% 0 1UF
NOSTUFF
10V
4
14 74LVC08
TSSOP-HF
2 CERM
2
20%
10V R7052
100 72 PM_PGOOD_P1V8_S0_REG 402 CERM
402 1
33 2
100 64 5 PGOOD_PCH_S0
B 81 74 64 63 6 =PP3V3 S0 PWRCTL
100 PGOOD_CPU_S0 5
U7000
08
6
R7032
5%
1/16W
B
MF-LF
7 1
33 2
402
PM MXM EN 77 100
14 74LVC08 74LVC08 5% NOSTUFF

PM PGOOD PVCCSA S0 REG 1 TSSOP-HF
PM_PGOOD_PVCORE_CPU 1
14
TSSOP-HF 1/16W SMC
100 64 63
3
100 65 25 5
3
MF-LF
402 R7053
U7000 U7050100 PGOOD_SYSPWROK
1
33 2 ALL_SYS_PWRGD_SMC
PM_PGOOD_P1V5_S0_FET 2 08 2 46 64 100
100 74 64 11
100 94 64 PGOOD_PCH_S0_R 08
5%
7 1/16W NOSTUFF
7 MF-LF
402 R7022
33 R7094
1 2 SMC DELAYED PWRGD 47 64 100
33
5% 100 68 64 63 PM PGOOD P1V05 S0 REG 1 2
81 74 64 63 6 =PP3V3 S0 PWRCTL 1/16W
MF-LF 5%
402 1/16W
NOSTUFF MF-LF
=PP3V3_S0_PWRCTL PM_ASW_PWRGD
81 74 64 63 6
R7099 402 19 64 100
R7029 ALL_SYS_PWRGD 1
33 2 PM_PECI_PWRGD
0 14 74LVC08 100 94 46 100
14 74LVC08 PGOOD_SYSPWROK_R 13 TSSOP-HF
81 74 64 63 6 =PP3V3 S0 PWRCTL
100 94 PGOOD_CPU_UNCORE 10 TSSOP-HF R7035 1 2 100
11
5%
1/16W
8 100 33 ALL_SYS_PWRGD_SMC
5%
U7050 R7023 MF-LF NOSTUFF
PGOOD_PCH_S0 1 2 1/16W 402
9
U7050 64 5 46 64 100
MF-LF 100 77 PM MXM PGOOD 12 08 33 1 C7056
08 5% 402 1 2 ALL_SYS_PWRGD_R 5 32 100
1/16W
7
OUT 0.47UF
MF-LF 5% 10%
7
14 74LVC08 402 1/16W
R7028 2 6.3V
CERM-X5R
MF-LF
100 74 63 PM_PGOOD_P5V_S0_FET 13 TSSOP-HF 402 33 402
1 2 PM_SYS_PWRGD 19 32 100
11 PGOOD_5V_1V05_3V3 =PP3V3_S0_MXM =PM_MXM_PGOOD_PULLUP
U7000 100 94 77 76 21 6 77
5%
12 08 PULL-UP ON MXM PAGE 1/16W
MF-LF
402
7
NOSTUFF
R7024 R7054 R7078
A 1
0 2 100 94 64 PGOOD_PCH_S0_R 1
0 2 100 PM_PCH_PWRGD_R
1
33 2 PM PCH PWRGD 19 21 100 SYNC MASTER=K62 SIJI SYNC DATE=01/09/2011 A
5% PAGE TITLE
=PP3V3 S0 PWRCTL
5%
1/16W
MF-LF
5%
1/16W
MF-LF NOSTUFF
1/16W
MF-LF
402
NOSTUFF POWER SEQUENCING PGOOD
74 64 63 6 =PP3V3 S0 PWRCTL
6 63 64 74 81
402
1
402
1 C7023
1 C7055 DRAWING NUMBER SIZE
81
74LVC08 OPTION FOR SMC TO OUPUT R7031OPTION FOR PCH PWROK
TO BE DRIVEN BY SAME
AND SYSPWROK
SIGNAL 0.47UF
0.47UF 051-8442 D
TSSOP-HF 74LVC08 DELAYED PWRGD (BY 99MS) R7030 100K
5% 10%
10%
2 6.3V
Apple Inc. REVISION
14 14 0 1/16W 2 6.3V CERM-X5R R
100 68 64 63 PM_PGOOD_P1V05_S0_REG 10 100 94 PGOOD_3V3_1V05 4 TSSOP-HF 100 64 47 SMC_DELAYED_PWRGD 1 2 MF-LF
CERM-X5R
402
402
10.1.0
8 6 PM_PGOOD_CK505 5% 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
U7000 U7050 26
100 74 63 PM PGOOD P3V3 S0 FET 9 08 100 74 64 11

PM_PGOOD_P1V5_S0_FET 5 08
1/16W
MF-LF R7079 THE INFORMATION CONTAINED HEREIN IS THE
402
1
33 2
7 7
PM_ASW_PWRGD 19 64 100 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5%
1/16W
70 OF 110
MF-LF SHEET
ALL SYS PWRGD CIRCUIT 402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
50 17 13 6 =PPVAXG_S0_CPU
SM R7160
1K
CPU CORE/AXG REG 1.1V/75A O/P= PPVCORE_S0_CPU_REG
1 98 2 VR AXG VSNS XW P
VOLTAGE=1 1V
1 2
R7162 =PP3V3 S0 VRD
OMIT NET PHYSICAL TYPE SNS DIFF 5% 10 98 VR_AXG_VSEN 6 65 68
XW7120 R7161 1/16W

MF-LF
1 2
R7127
1
0 2 VR_AXG_VSNS_R_P
402 5%
1/16W
SIGNAL_MODEL=EMPTY
67 6
=PP5V S0 VRD 2
2.2 1 98 65 PP5V S0 CPU VCORE_VCC
MF-LF
402 NOSTUFF 5% MAX_NECK_LENGTH=3MM
5%
98 13 IN CPU VAXG SENSE P 1/16W
MF-LF
1 C7155 1/8W
MF-LF
1
R7195
402 1.25 mOhm loadline 0.0022UF 805
VOLTAGE=5V 10K
98 13 IN CPU_VAXG_SENSE_N 10% 5%
2 50V
D R7163
0
R7164
10 VR_AXG_RGND
CERM
402
1/16W
MF-LF
2 402
D
1 2 VR_AXG_VSNS_R_N 1 2 98
5% 5%
1 C7157 CPU VCORE
XW7130
1/16W
MF-LF
R7165
1/16W
MF-LF
1 C7156
SM 402
1K
402
10%
0.0022UF 0.0022UF
10% 1 C7114 VOUT = VCORE
1 2 AXG VSNS XW N 1 2 50V
98 VR
VOLTAGE=0V
50V
2 CERM 2 CERM R7157 1 10UF CPUVCORE-3PH PEAK = 75A
NET PHYSICAL TYPE SNS DIFF 5% 402 402 10%
1K 25V 1
OMIT 1/16W
MF-LF 5% 2 X5R R7106 AVG = 55A
402 65
AGND_CPU =PP3V3 S0 VRD 1/16W
MF-LF
805
1
NOSTUFF 0
68 65 6
402 2
AGND_CPU R7101 5%
1/16W VR_AXG_PWM
0 MF-LF OUT 67 98
C7116 R7128 5%
1/16W 1NOSTUFF 1
NOSTUFF
2 402
0.0022UF
1 2 98 VR SEN R2 1
249 2
MF-LF
2 402
R7102 R7104
0
1
R7107
0 5% 0
2
1
R7189 C7113
RT7103
1% 1 5% 1/16W 5%
10% 1/16W 1/16W MF-LF 1/16W
50V MF-LF 1K 0.1UF MF-LF 2 402 MF-LF
6.8K
0603
CERM 402 5% 10% 2 402 2 402
402 1/16W
MF-LF
16V
2 X5R R7108
OMIT OMIT 2 402 402 NOSTUFF NOSTUFF 1
110 2
R7129 R7130 98 VR_SEN_R1 NOSTUFF 1
R7103 1R7105
0 806 1 0 1%
R7131 R7100
1
1 2 98 VR SEN R3 1 2
5% 0 1/16W
10 0 5% MF-LF
1% 1/16W 1/16W 402
5% 1/16W 1 2 5% MF-LF
1/16W NOSTUFF MF LF
LOCAL 5V
35
MF-LF 1/16W 2 402 DIFFERENTIAL PAIR=VR AXG ISNS
MF-LF 5% MF-LF 2 402 1 C7101
402 402 1/16W
MF-LF
1 C7115 98 VR_AXG_TM 2 402 1 C7100 0.1UF
1 C7102 VR AXG ISNS P IN 67 98
402 0.01UF VCC 10% 220PF

220PF 10%
VR_AXG_ISNS_N
20%
16V
98 VR AXG PWM R 5% 2 16V
X5R 2 50V
C7117
2 CERM
402
U7100 25V
2 CERM 402 X7R-CERM
402
IN 67 98
R7132 3900PF ISL6364 402 DIFFERENTIAL PAIR=VR AXG ISNS
9.09K2 98 VR_AXG_COMP_RC 1 2 QFN

1 AGND CPU 65 23 TMS PWMS 26 AGND_CPU
65
1%
1/16W 10% 20 ISENS+ 24 98 VR_AXG_ISNS_R_P R7109
1.02K2
C MF-LF
402
C7118
50V
X7R
0402 R71411 OMIT
2 1.21K 98 VR AXG HFREQ COMP
VSENS
16 HFCOMPS/DVCS
ISENS- 25 98 VR_AXG_ISNS_R_N
1%
1
1/16W 402 MF-LF
C
39PF 1% 1/16W MF-LF 402 PWM1 38 98 VR_CPU_PWM1_R R7110 2 1 0 VR_CPU_PWM1 66 98
OUT
19 1/16W 5% MF-LF 402
1 2 98 VR_AXG_FB FBS ISEN1+ 46 VR_CPU_ISNS1_P IN 66 98
DIFFERENTIAL PAIR=VR CPU ISNS1
ISEN1- 45 98 VR_CPU_ISNS1_R_N
5%
50V
21 RGNDS 1 C7103 1 C7104 VR_CPU_ISNS1_N
C7119 R7133 CERM
18 PWM2 36 98 VR_CPU_PWM2_R 220PF 0.1UF DIFFERENTIAL PAIR=VR CPU ISNS1
IN 66 98
4700PF 402 98 VR AXG COMP COMPS 10% 10%

VR CPU PSICOMP2 1 2 98 VR CPU PSICOMP1 301 ISEN2+ 42 50V
2 X7R-CERM 2 16V
X5R
98 1 2
13 402
100 64 25 5 OUT PM_PGOOD_PVCORE_CPU VR_RDY ISEN2- 41 98 VR_CPU_ISNS2_R_N 402
10%
1% AGND_CPU
1/16W 65
100V
CERM
MF-LF
402
98 65 PP5V_S0_CPU_VCORE_VCC R7140 1 2 953K
MF-LF 402
VR AXG TCOMP 30 BTS_DES_TCOMPS
98 PWM3 39 98 VR_CPU_PWM3_R R71111 2 1.02K
R7134
402 C7120 R7156 1 2 953K
1/16W
1%
98 VR CPU SUTH 29 BT_FDVID_TCOMP ISEN3+ 48 0
1% 1/16W MF-LF 402
VR_CPU_PWM2
390PF 1%1/16W MF-LF 402
R7142 1 216.5K OMIT 98 VR CPU N PSI 28 NPSI_DE_IMAX R7112 2 1 OUT 66 98
249 ISEN3- 47 98 VR_CPU_ISNS3_R_N 1/16W 5% MF-LF 402
1 2 1/16W 1% MF-LF402 VR_CPU_ISNS2_P
1 2 98 VR_CPU_FB_RC R7143 1 215.0K OMIT 98 VR CPU FDVID 27 ADDR_IMAXS_TMAX DIFFERENTIAL PAIR=VR CPU ISNS2
IN 66 98
1% 1% 1/16W MF-LF 402 PWM4 37 98 VR_CPU_PWM4_R

1/16W 10%
50V
98 13 IN
CPU VIDSCLK 12 SVCLK
ISEN4+ 44
1 C7105 1 C7106 VR_CPU_ISNS2_N
MF-LF
402 CERM 98 13 OUT
CPU_VIDALERT_L 11 SVALERT* 220PF 0.1UF DIFFERENTIAL PAIR=VR CPU ISNS2
IN 66 98
402 CPU VIDSOUT 10 SVDATA ISEN4- 43 98 VR_CPU_ISNS4_R_N 10% 10%

16V
98 13 BI 50V 2 X5R
2 X7R-CERM
402 402
OMIT 4 VSEN FSS_DRPS 22 VR_AXG_SW_FREQ
98
AGND_CPU
R7135 R7136 3 R71131
65
2 1.02K
1.33K2
1 98 VR CPU FB R 1
1.02K2 RGND VR_RDYS 17 PM_PGOOD_PVAXG 1% 1/16W MF-LF 402
98 VR CPU FB 7 FB R7114 2 1 0 VR_CPU_PWM3 66 98
OUT
1% 1%
98 VR CPU PSICOMP 6 IMONS 14 VR_AXG_IMON 1/16W 5% MF-LF 402
1/16W
R7121 1/16W PSICOMP VR_CPU_ISNS3_P IN 66 98
MF-LF MF-LF DIFFERENTIAL PAIR=VR CPU ISNS3
402 10 402 OMIT FS_DRP 34 VR CPU_SW_FREQ
5% 1/16W
1 2
MF-LF 402
R7144
1/16W
1 2 2.55K
MF-LF 402
98 VR CPU HFREQ COMP 5 HFCOMP
98
1 C7107 1 C7108
1%
RAMP_ADJ 2 98 VR_CPU_RAMP_ADJ 220PF 0.1UF VR_CPU_ISNS3_N
98 VR CPU COMP 8 COMP 10% 10%
16V DIFFERENTIAL PAIR=VR CPU ISNS3
IN 66 98
EN_VTT 40 PM_EN_PVCORE_CPU IN 63 100

2 50V
X7R-CERM
2 X5R
VR CPU IAUTO 32 SICI 402
C7122 98 402
AGND_CPU
82PF 65
98 50 VR_CPU_IMON 9 IMON EN_PWR 1 98 VR_EN_PWR_OVP R71151 2 1.02K
B 1 2
OMIT
100
11 CPU_PROCHOT_L
OUT
R7199 1 2 0 VR_HOT_L 15 VR_HOT*
RSET 33 CPUVCORE-4PH
0
1% 1/16W MF-LF 402
B
5%
50V
47 5% 1/16W MF-LF 402 98 VR_CPU_TM 31 R7184 2 1 VR CPU PWM4 OUT 67 98
TM
R7145 CERM
402 C7123 THRM 1/16W 5% MF-LF 402 VR CPU ISNS4 P
DIFFERENTIAL PAIR=VR CPU ISNS4
IN 67 98
4.99K2 820PF PAD CPUVCORE-4PH CPUVCORE-4PH

1 98 VR CPU FB2 1 2
R7149 1 R7150 1 R7151 1
OMIT 1 C7187 1 C7188
49
1 220PF 0.1UF VR_CPU_ISNS4_N
1%
1/16W 10%
1 C7124 R7152 1 30.1K 26.1K 255K R7158 R7120 1 1 R7155 10% 10%
16V DIFFERENTIAL PAIR=VR CPU ISNS4
IN 67 98
MF-LF 50V 0.01UF 0 NOSTUFF 1% 1% 1% 255K 105K 50V

2 X7R-CERM 2 X5R
402 CERM 20% 5% 1/16W 1/16W 1/16W 1% 98 VR_RSET 124K 402
402 16V 1/16W MF-LF MF-LF MF-LF 1/16W 1% 1% 402
2 CERM
MF-LF R7146 1 R7147 1 R7148 1 402 2 402 2 402 2 MF-LF OMIT 1/16W 1/16W 1
R7118 AGND CPU 65
402 402 2 110 90.9 54.9 2 402 R7119 1 MF-LF
402 2
MF-LF
2 402
1.18M R71851 2 1.02K
5% 1% 1% 1% 1% 1/16W MF-LF 402
98 65 PP5V S0 CPU VCORE_VCC 1/16W 1/16W 1/16W 12.4K 1/16W
MF-LF MF-LF MF-LF 1% MF CPUVCORE-4PH
402 2 402 2 402 2 1/16W 2 402
MF-LF NOSTUFF
402 2
2
AGND_CPU
RT7104
65
PP5V_S0_CPU_VCORE_VCC R7181 1
R7159 1 =PPVCCIO_S0_CPU 65 98
10K
6.8K
16 13 11 10 6
0603
1K NOSTUFF
5% 1 C7132 R7179 1 AGND_CPU 65
65 AGND_CPU 1
R7122 5%
1/16W
1/16W 0.1UF 100K MF-LF
MF-LF 10% 1 C7126 100K 5% 402 2
402 2 5%
2 16V
X5R 0.1UF 1/16W 1/16W
MF-LF
MF-LF AGND CPU
1
402 10%
2 402
65
16V 402 2
2 X5R PP12V S0 CPU FLTRD 65 66 67 98
402
65 AGND_CPU 1 C7112 PP5V S0 CPU VCORE VCC 65 98
MAX_NECK_LENGTH=3MM 1 0.1UF NOSTUFF
65 AGND CPU
1
OMIT MIN_NECK_WIDTH=0.3MM
R7123 10% R7180 1
R7153 2.74K
VR_EN_PWR_OVP_R
50 16 13 6 =PPVCORE_S0_CPU 845
VOLTAGE=0V 1%
16V
2 X5R 100K
SM R7166 1%
1/16W
MF-LF
402 5%
1/16W
1K C7127
VR_CPU_IMON_R
1/16W 1 MF-LF
2 402
1 98 2 VR CPU VSNS XW P 1 2
R7167 MF-LF 402 2
XW7101
27.0NF
2
OMIT
VOLTAGE=1 1V
NET PHYSICAL TYPE SNS DIFF 5% 10 98 VR_CPU_VSEN 2 402 10%
1/16W 1 2 10V
2 X5R
R7168 50 98
SM
OUT
XW7123 MF-LF
A
OMIT
1
0 402 5% SIGNAL_MODEL=EMPTY 1
OMIT 402 R7124 A
1 2 VR_CPU_VSNS_R_P 1/16W
R7154 6.65K OMIT SYNC MASTER=K62 AARON SYNC DATE=N/A
1
MF-LF
NOSTUFF 9.76K 1% 1 PAGE TITLE
5% 402 98
1/16W R7125
98 13 IN CPU VCC SENSE P 1/16W
MF-LF
1 C7158
0.0022UF
98
1%
1/16W
MF-LF
MF-LF
2 402 5%
1K VREG: PPVCORE S0 CPU
402 1.25 mOhm loadline C7111
VR_AXG_IMON_R
1
98 13 IN CPU_VCC_SENSE_N 10% 2 402
AGND_CPU
1/16W DRAWING NUMBER SIZE
2 50V
CERM 65
MF-LF 0.1UF 051-8442 D
R7169 R7170 402 152-0118 2 402 10% Apple Inc.
0 10 AGND_CPU CRITICAL 2 16V REVISION
2 VR_CPU_VSNS_R_N 98 VR_CPU_RGND 65 X5R
1 1 2
L7100 1
OMIT 402 R
10.1.0
5% 5%
1 C7160
0.24UH+/-20%-0.00042OHM-40A R7126 NOTICE OF PROPRIETARY PROPERTY: BRANCH
XW7133
1/16W
MF-LF
R7171
1/16W
MF-LF
1 C7159 0.0022UF =PP12V_S0_VRD 1 2 PP12V_S0_CPU_FLTRD 1%
13.7K
SM 402 402 0.0022UF 10%
6
NET PHYSICAL_TYPE=POWER
65 66 67 98
98 1/16W PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
1 2
1K 10% 50V SDP1108M-TH VOLTAGE=12V MF-LF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
98 VR CPU VSNS XW N 1 2 50V 2 CERM
2 CERM 2 402
VOLTAGE=0V
NET PHYSICAL TYPE SNS DIFF 5% 402 402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 71 OF 110
OMIT 1/16W
MF-LF
CPU CORE INPUT FILTER II NOT TO REPRODUCE OR COPY IT
SHEET
AGND_CPU 65 AGND_CPU III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
402 65
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
98 67 65
PP12V_S0_CPU_FLTRD
NET_SPACING_TYPE=POWER
CRITICAL CRITICAL CRITICAL CRITICAL
1 1 THESE TWO CAPS ARE FOR EMC
C7272 C7270 1
C7271 Q7201
CRITICAL
CRITICAL CRITICAL
220UF 220UF 220UF NOSTUFF
376S0772 IRF6710
1
C7205 1 1 C7215 1 1
20% 20% 20% 1 R7205 R7201 S1 220UF C7206 C7207 C7281 1 C7210 1 C7211
10UF
2 16V
ALUM-POLY
8X7-TH
2 16V
ALUM-POLY
8X7-TH
2 16V
ALUM-POLY
8X7-TH
R7202
5%
1/10W
MF-LF
10
5%
1/10W
0
1
1 10
5%
1/10W
MF-LF
PHASE 1 D
1
2
5
20%
2 16V
ALUM-POLY
8X7-TH
10UF
10%
2 16V
X5R-CERM
0805
10%
2 16V
X5R-CERM
0805
1UF
10%
2 16V
X5R
603
1UF
10%
2 16V
X5R
603
2 50V
X7R
0.001UF
10%
402
2 25V
X5R
1UF
10%
402
603 2 MF-LF
603 2 2 603 4 G 6
98 VR CPU DRV1 VCC 98 VR_CPU_DRV1_PVCC CRITICAL R7208
NET_PHYSICAL_TYPE=POWER 3 S CRITICAL 0.0005
NO_TEST=TRUE 1 C7201
NET_PHYSICAL_TYPE=POWER L7201 1%
PPVCORE_S0_CPU_REG
D 98 VR_CPU_DRV1_UVCC
NO_TEST=TRUE
1UF
10%
2 16V
98 VR CPU BOOT1 RC
NET_PHYSICAL_TYPE=VR_CTL_PHY SWITCH_NODE=TRUE
0.24UH+/-20%-0.00042OHM-40A
1 2 PPVCORE_S0_CPU_REG1
1W
MF
0612
6 66 67 D
NO_TEST=TRUE X5R NET_SPACING_TYPE=VR_CONTROL 1 2
603
R72041 DIDT=TRUE 3 4
9
SDP1108M-TH
7
NOSTUFF
NO_TEST=TRUE
VCC UVCC LVCC
5%
0 1 C7203 R72061
U7201 1/10W 0.22UF 2.2
MF-LF 10% 5%
ISL6622 603 2 16V 1/8W
2 X7R MF-LF
DFN 98 VR_CPU_DRV1_BOOT 603 805 2
VR_CPU_DRV1_GDSEL 3 GDSEL
98
BOOT 2 NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL
NO_TEST=TRUE
NOSTUFF VR CPU PH1 SNUB 98
C7202 1 1 C7200 1
R7207 UGATE 1 98 VR_CPU_DRV1_UGATE 1 2 6 7
CRITICAL DIDT=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY
1UF 1UF 0 NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY NET_SPACING_TYPE=VR_CONTROL D CRITICAL DIDT=TRUE
10% 10% 5% PHASE 10 98 VR CPU PHASE1 1 C7208 NET_SPACING_TYPE=SWITCHNODE
16V 2
X5R 2 16V
X5R 1/10W
MF-LF NET PHYSICAL TYPE=POWER DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE Q7202 0.001UF
603 603 603 4 PWM LGATE 6 98 VR_CPU_DRV1_LGATE 5 G IRF6795 10%
2 DIDT=TRUE DIRECTFET-MX 50V
2 CERM
NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY NET_SPACING_TYPE=VR_CONTROL S
THRML 402
GND PAD NOSTUFF
376S0771 3 4 VR_CPU_ISNS1_P
11
OUT 65 98
VR_CPU_PWM1
98 65 IN VR_CPU_ISNS1_N OUT 65 98
CRITICAL THESE TWO CAPS ARE FOR EMC

CRITICAL CRITICAL CRITICAL
376S0772 Q7221
IRF6710
1
C7225 1 C7226 1 C7229 1 C7282 1 C7227 1 C7230 1 C7231
R72221
10
5%
NOSTUFF
R72251
0
1
R7221
10
5%
1/10W
PHASE 2 S1
D
1
2
220UF
20%
2 16V
ALUM-POLY
8X7-TH
10UF
10%
16V
2 X5R-CERM
0805
10%
16V
10UF
2 X5R-CERM
0805
10%
2 16V
X5R
603
1UF 1UF
10%
2 16V
X5R
603
0.001UF
10%
2 50V
X7R
402
1UF
10%
2 25V
X5R
402
1/10W 5% MF-LF 5
1/10W
C VR_CPU_DRV2_VCC
MF-LF
603 2 MF-LF
603 2
2 603 4 G 6
CRITICAL
C
98
NET_PHYSICAL_TYPE=POWER VR_CPU_DRV2_PVCC 3 S
CRITICAL
R7228
NO_TEST=TRUE 98 0.0005
98 VR_CPU_DRV2_UVCC NET_PHYSICAL_TYPE=POWER
98 VR_CPU_BOOT2_RC L7221 1%
1W PPVCORE S0 CPU REG
NO_TEST=TRUE NET_PHYSICAL TYPE=VR_CTL_PHY 0.24UH+/-20%-0.00042OHM-40A MF 6 66 67
NET_PHYSICAL_TYPE=POWER NET_SPACING_TYPE=VR_CONTROL SWITCH_NODE=TRUE 98 PPVCORE_S0_CPU_REG2
0612
NOSTUFF
1 C7221 1 2 1 2
C7222 1 1 C7220 1UF R72241 DIDT=TRUE 3 4
7
SDP1108M-TH
9
1UF 10% NO_TEST=TRUE 1 C7223

10% 1UF VCC PVCC
16V
2 X5R 0 NOSTUFF
10% 152-0118
16V 2 16V 603 5% 0.22UF R72261
X5R
603
2 X5R
603
U7221 1/10W
MF-LF
10%
2 16V 2.2
ISL6612 603 2 X7R 5%
603 1/8W
QFN1 MF-LF
NO_TEST=TRUE 805 2
4 PWM BOOT 2 98 VR_CPU_DRV2_BOOT
98 65 IN
VR CPU PWM2 CRITICAL NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL VR CPU PH2 SNUB 98
UGATE 1 98 VR_CPU_DRV2_UGATE 1 2 6 7
NET_PHYSICAL_TYPE=VR_CTL_PHY
NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL D CRITICAL DIDT=TRUE
PHASE 10 98 VR_CPU_PHASE2 1 C7228 NET_SPACING_TYPE=SWITCHNODE
98 VR_CPU_DRV2_GDSEL 3 NC Q7222
NET_PHYSICAL TYPE=POWER DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE 0.001UF
NOSTUFF 8 NC LGATE 6 98 VR_CPU_DRV2_LGATE 5 G IRF6795 10%
1 DIRECTFET-MX 50V
2 CERM
R7227 THRML
NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL S 402
0 GND PAD NOSTUFF
5% 3 4 VR_CPU_ISNS2_P
5
376S0771
11
1/10W OUT 65 98
MF-LF
2 603
VR_CPU_ISNS2_N OUT 65 98
CRITICAL CRITICAL THESE TWO CAPS ARE FOR EMC

CRITICAL CRITICAL
B 1
Q7241
IRF6710
1
C7245
220UF
1 C7246
10UF
1 C7249
10UF
1 C7283
1UF
1 C7247
1UF
1 C7250
0.001UF
1 C7251
1UF
B
R72421
10
5%
1/10W
NOSTUFF
R7245
5%
0
1
R7241
10
5%
1/10W
MF-LF
PHASE 3 376S0772 S1
D
1
2
20%
2 16V
ALUM-POLY
8X7-TH
10%
2 16V
X5R-CERM
0805
10%
16V
2 X5R-CERM
0805
10%
16V
2 X5R
603
10%
2 16V
X5R
603
10%
50V
2 X7R
402
2 X5R
10%
25V
402
MF-LF 1/10W 5
603 2 MF-LF 2 603
603 2 4 G 6
98 VR_CPU_DRV3_VCC CRITICAL R7248
NO_TEST=TRUE NET_PHYSICAL_TYPE=POWER 98 VR_CPU_DRV3_PVCC 3 S CRITICAL 0.0005
98 VR_CPU_DRV3_UVCC NET_PHYSICAL_TYPE=POWER 98 VR_CPU_BOOT3_RC L7241 1%
1W PPVCORE_S0_CPU_REG
NET_PHYSICAL_TYPE=POWER NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY 0.24UH+/-20%-0.00042OHM-40A MF 6 66 67
1 C7241 NET_SPACING_TYPE=VR_CONTROL SWITCH_NODE=TRUE 98 PPVCORE_S0_CPU_REG3
0612
1 2 1 2
NOSTUFF 1UF R72441 DIDT=TRUE
C7242 1 1 C7240 3 4
7
SDP1108M-TH
9
10% NO_TEST=TRUE 1 C7243

1UF 1UF VCC
16V
2 X5R 0 NOSTUFF 152-0118
PVCC 0.22UF
10% 10% 603 5% 10% R72461
16V 2
X5R 2 X5R
16V U7241 1/10W
MF-LF 2 16V
X7R 2.2
603 603 ISL6612 603 2 603 5%
376S0771 1/8W
QFN1 MF-LF
98 VR_CPU_DRV3_BOOT NO TEST=TRUE 805 2
4 PWM BOOT 2
NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL 1 2 6 7
VR_CPU_PWM3 CRITICAL VR CPU PH3 SNUB 98
98 65 IN UGATE 1 98 VR_CPU_DRV3_UGATE NO TEST=TRUE D CRITICAL
PHASE 10
98 VR_CPU_PHASE3
DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL Q7242 DIDT=TRUE
1 C7248 NET_SPACING_TYPE=SWITCHNODE
98 VR_CPU_DRV3_GDSEL 3 NC 5 G IRF6795
NOSTUFF NET_PHYSICAL_TYPE=POWER DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE DIRECTFET-MX 0.001UF
1 8 NC LGATE 6 S 10%
R7247 98 VR_CPU_DRV3_LGATE 2 50V
CERM VR_CPU_ISNS3_P
0 THRML 3 4 402 OUT 65 98
5% GND PAD NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL NOSTUFF
1/10W NO_TEST=TRUE
VR_CPU_ISNS3_N
5
11
MF-LF 65 98
OUT
2 603
A A
OUTPUT BULK DECOUPLING: 128S0209
PPVCORE S0 CPU REG
SYNC MASTER=K62 AARON
PAGE TITLE
SYNC DATE=N/A
6 66 67 VREG: CPU CORE - PHASES 1-3

DRAWING NUMBER SIZE
75A MAX 051-8442 D
Apple Inc.
1
C7260 1
C7261 1
C7262 1
C7263 1
C7264 1
C7265 R
REVISION
330UF-0.0045OHM
20% 20%
330UF-0.0045OHM 330UF-0.0045OHM
20%
330UF-0.0045OHM
20%
330UF-0.0045OHM
20%
330UF-0.0045OHM
20%
10.1.0
2 2V
POLY
2 2V
POLY
2 2V
POLY
2 2V
POLY
2 2V
POLY
2 2V
POLY
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM THE INFORMATION CONTAINED HEREIN IS THE
72 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP12V_S0_CPU_FLTRD THESE TWO CAPS ARE FOR EMC
D 98 67 66 65
CPUVCORE-4PH CPUVCORE-4PH CPUVCORE-4PH CPUVCORE-4PH
D
CRITICAL CRITICAL CRITICAL CRITICAL CPUVCORE-4PH CPUVCORE-4PH CPUVCORE-4PHCPUVCORE-4PH
CPUVCORE-4PH
CPUVCORE-4PH Q7301 1
C7304 1 C7305 1 C7306 1 C7307 1 C7319 1 C7308 1 C7309
1 IRF6710 220UF 10UF 10UF 1UF 1UF 1UF 1UF
R73111
5%
1/10W
10
NOSTUFF
R73121
5%
0
R7313
5%
10
1/10W
MF-LF
PHASE 4 376S0772 S1
D
1
2
20%
2 16V
ALUM-POLY
8X7-TH
10%
16V
2 X5R-CERM
0805
10%
16V
2 X5R-CERM
0805
2
10%
16V
X5R
603
10%
2 16V
X5R
603
10%
2 16V
X5R
603
10%
2 16V
X5R
603
MF-LF 1/10W 5
603 2 MF-LF 2 603 CPUVCORE-4PH
603 2 4 G 6
98 VR_CPU_DRV4_VCC CPUVCORE-4PH CRITICAL R7301
NET_PHYSICAL_TYPE=POWER 98 VR_CPU_DRV4_PVCC 3 S CRITICAL 0.0005
NO TEST=TRUE
98 VR_CPU_DRV4_UVCC NET_PHYSICAL_TYPE=POWER 98 VR_CPU_BOOT4_RC L7301 1%
1W PPVCORE_S0_CPU_REG
NET_PHYSICAL_TYPE=POWER NO_TEST=TRUE CPUVCORE-4PH NET_PHYSICAL_TYPE=VR_CTL_PHY 0.24UH+/-20%-0.00042OHM-40A MF 6 66
1 C7311 NET_SPACING_TYPE=VR_CTL SWITCH_NODE=TRUE 98 PPVCORE_S0_CPU_REG4
0612
CPUVCORE-4PH 1 2 1 2
NOSTUFF 1UF R73031 DIDT=TRUE CPUVCORE-4PH
C7312 1 1 C7310 3 4
7
CPUVCORE-4PH SDP1108M-TH
9
10% NO_TEST=TRUE 1 C7303
1UF 1UF VCC
16V
2 X5R 0 CPUVCORE-4PH NOSTUFF 152-0118
PVCC 0.22UF
10% 10% 603 5% 10% R73021
16V
X5R 2 2 X5R
16V U7301 1/10W
MF-LF 2 16V
X7R 2.2
603 603 ISL6612 603 2 603 5%
376S0771 1/8W
QFN1 MF-LF
98 VR_CPU_DRV4_BOOT NO TEST=TRUE 805 2
4 PWM BOOT 2 NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL 1 2 6 7
VR CPU PWM4 CRITICAL
NO TEST=TRUE CRITICAL
VR CPU PH4 SNUB 98
98 65 IN UGATE 1 98 VR_CPU_DRV4_UGATE D NET_PHYSICAL_TYPE=VR_CTL_PHY
PHASE 10
98 VR_CPU_PHASE4
DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL Q7302 DIDT=TRUE
1 C7302 NET_SPACING_TYPE=SWITCHNODE
98 VR_CPU_DRV4_GDSEL 3 NC 5 G IRF6795
NOSTUFF NET_PHYSICAL_TYPE=POWER DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE DIRECTFET-MX 0.001UF
1 8 NC LGATE 6 S 10%
R7310 98 VR_CPU_DRV4_LGATE NO_TEST=TRUE
CPUVCORE-4PH 50V
2 CERM VR_CPU_ISNS4_P
0 GND
THRML 3 4 402 OUT 65 98
5% PAD NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL NOSTUFF
1/10W
VR_CPU_ISNS4_N
11
MF-LF 65 98
OUT
2 603
C C
AXG PHASE (MAX 15A)
=PP5V S0 VRD 98 67 66 65
PP12V S0 CPU FLTRD THESE TWO CAPS ARE FOR EMC
65 6
CRITICAL CPUVCORE-4PH
CRITICAL
1 C7325 1 1 C7329
R7321 10UF
C7326 1UF
10% 10UF 10%
1 0 376S0906 10%
5% CRITICAL 2 16V
X5R-CERM 16V
2 X5R-CERM 2 16V
X5R
1/10W 98 VR AXG BOOT1 RC 0805 0805 603
MF-LF NET_PHYSICAL_TYPE=VR_CTL_PHY
2 603 1 C7323 Q7324
98 VR_AXG_DRV1_PVCC R73241 DIDT=TRUE 0.22UF CSD58864Q5D CRITICAL R7328
NET_PHYSICAL_TYPE=POWER 10% SON5X6 VIN 1 CRITICAL
1 NET SPACING TYPE=VR CONTROL 3 TG 0.0005
1 C73211/10W
5% NO_TEST=TRUE 2 16V
X7R L7321 1%
VOLTAGE=12V 10%
1UF MF-LF 603 VSW 6 0.68UH-7.6MOHM-12A 1W
MF PPVAXG_S0_REG 6
16V 603 2 PPVCORE_S0_AXG_REGOUT 0612
NO_TEST=TRUE 2 PPVCORE_S0_AXG_REG1
B 2 X5R
603
4 TGR 7 98 1 1 2
B
7
8 NET_SPACING_TYPE=SWITCHNODE PIC0504H-SM 3 4
1
C7330 1
C7331
1 C7332 1 C7333
VCC R73261 152S1268 330UF-0.0045OHM 330UF-0.0045OHM 10UF 10UF
U7322 98 VR_AXG_DRV1_BOOT NO_TEST=TRUE 5 BG 2.2
5%
20% 20%
20%
2 10V
20%
2 10V
ISL6620 NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NOSTUFF 1/8W 2 2V 2 2V X5R X5R
POLY POLY 603 603
QFN NET_SPACING_TYPE=VR_CONTROL PGND MF-LF CASE-D2-SM CASE-D2-SM
VR_AXG_PWM 805 2
98 65 4 PWM BOOT 2 R7325
9
IN
2
1 1 VR AXG PH1 SNUB 98
9 EN UGATE 1 98 VR AXG DRV1 UGATE NO_TEST=TRUE VR AXG DRV1 UGATE R
CRITICAL NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE 5% NET_PHYSICAL_TYPE=VR CTL_PHY NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY
1/10W DIDT=TRUE
PHASE 10 98 VR_AXG_PHASE1 VR CONTROL MF-LF
DIDT=TRUE VR_CTL 1 C7328NET_SPACING_TYPE=SWITCHNODE
3 NC
NET_PHYSICAL_TYPE=POWER DIDT=TRUE 603 NET_SPACING_TYPE=SWITCHNODE NO_TEST=TRUE 0.001UF
8 NC LGATE 6 98 VR_AXG_DRV1_LGATE 10%
NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL NO_TEST=TRUE 50V
2 CERM
THRML 402
GND PAD
NOSTUFF
VR_AXG_ISNS_P
5
11
OUT 65 98
VR_AXG_ISNS_N OUT 65 98
A SYNC MASTER=K62 AARON SYNC DATE=N/A A

PAGE TITLE
VREG:AXG PHASE/CORE - CAPS

DRAWING NUMBER SIZE

REVISION
R
10.1.0
73 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
65 6 =PP3V3_S0_VRD
1V05 REGULATOR for CPU & PCH VCCIO O/P= PP1V05_S0_REG
1
R7411
10K
5%
1/16W
MF-LF
2 402
98 50 OUT P1V05_IMON R7467 6 =PP12V_S0_P1V05_VREG
DIDT TRUE NET SPACING TYPE POWER
2.2
1 2
100 64 63 OUT PM_PGOOD_P1V05_S0_REG
5% THESE TWO CAPS ARE FOR EMC
D
1/10W
MF-LF
603
R7460
R7480 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D
2.2 1 1 1 1 1 1 1 1
=PP5V_S0_P1V05_VREG 1
2.2
2 5V_S0_P1V05REG_VIN
98 PP12V_S0_P1V05_VREG_VIN 1 2
C7427 C7426 C7420 C7421 C7422 C7423 C7424 C7425
6 VOLTAGE=12V 10UF 10UF 1UF 1UF 1UF
VOLTAGE=5V 0 6 mm 5% 100UF 220UF 220UF
5% 0 6 mm 0 2 MM 1/10W 20% 20% 20% 10% 10% 10% 10% 10%
1/10W MF-LF 16V 16V 16V 16V 16V
0 2 MM 1 2 16V 2 16V 2 16V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R 2 X5R
MF-LF C7430 603 376S0772 POLY ALUM-POLY ALUM-POLY
603 6.3X6-TH 8X7-TH 8X7-TH 0805 0805 603 603 603
1UF
6 =PP3V3_S0_P1V05_VREG
NOSTUFF 98 5V_S0_P1V05REG_VDD 10% Q7420
C7465 1 C7461 1 VOLTAGE=5V
1 C7462 2 16V
X5R
IRF6710
0 6 mm S1
NOSTUFF 1UF 1UF 1UF 402 1
1 1 1 NOSTUFF 1 10% 10% 0 2 MM 10% D
R7490 R7491 R7492 R7484 16V 16V 16V GND P1V05S0 AGND 68 2
X5R 2 X5R 2 2 X5R
16
22
20.0K 20.0K 20.0K 20.0K 1
1% 1% 1% 1% R7461 402 402 402 5
1/16W 1/16W 1/16W 1/16W 1K VDD PVCC 4 G 6
MF-LF MF-LF MF-LF MF-LF 5% (PP1V05S0_UGATE)
2 402 2 402 2 402 402 2 1/16W MIN LINE WIDTH=0 5 MM
P1V05_REG_VID0
MF-LF
2 402
U7401 MIN NECK WIDTH=0 2 MM
GATE NODE=TRUE 3 S
1 RBIAS QFN DIDT TRUE

P1V05S0_RBIAS VIN 14
ISL9563A
NET SPACING TYPE SWITCHNODE
R7474 C7464
P1V05S0_SOFT 2 SOFT 0 0.22UF
P1V05_REG_VID1 UGATE
98 18 P1V05S0_UGATE 1 2 P1V05S0 BOOT R 1 2
R7420
0 25 MM CRITICAL 0.0005
5%
28 IMON BOOT
98 17 P1V05S0 BOOT 1/10W
0 2 MM
DIDT TRUE
16V
X7R
L7420 1%
1W
NET SPACING TYPE VR CTL 0 2 MM
0 25 MM
MF LF
603
NET SPACING TYPE VR CTL 603 0.36UH-45A-0.76MOHM MF
31 10% 0612
P1V05_REG_VID2 PGOOD PHASE 19 DIDT TRUE
1
98 P1V05S0_PHASE (P1V05S0_PHASE) 98 2 P1V05S0_PHASE_L 1 2 PP1V05_S0_REG 6 68
24 VID0 MIN LINE WIDTH=0 5 MM NET SPACING TYPE SWITCHNODE MIN LINE WIDTH=0 5 MM
MIN NECK WIDTH=0 2 MM MSQ1211R36LF-TH MIN NECK WIDTH=0 2 MM 3 4
25
1 NOSTUFF VID1 DIDT TRUE
1 NOSTUFF 1 SWITCH NODE=TRUE
DIDT TRUE
R7493 R7494 R7495 26 VID2 CRITICAL NET PHYSICAL TYPE=POWER 1 NOSTUFF
C7463
20.0K 20.0K 20.0K 0.0022UF
1% 1% 1% P1V05_REG_VID3 27 VID3
1/16W 1/16W 1/16W 1 2 6 7 10%
23 50V
MF-LF MF-LF MF-LF 1 NC NC 2 CERM
2 402 2 402 2 402 R7483 D 376S0771 402
IN PM_EN_P1V05_S0_REG 29 VR_ON DIDT TRUE
20.0K
1% P1V05S0_FDE 30 AF_EN LGATE
98 21 P1V05S0_LGATE Q7421 98 P1V05S0 SNUBBER
1/16W
32
(P1V05S0_LGATE) 5 G IRF6795 MIN NECK WIDTH=0 4MM
MF-LF FDE DIRECTFET-MX NET SPACING TYPE VR CTL
C 402 2
98
98
P1V05S0_VSEN
P1V05S0 RTN
8
9
VSEN
RTN
MIN NECK WIDTH=0 2 MM
GATE NODE=TRUE
DIDT TRUE
S 1NOSTUFF
R7462
0.499
98 P1V05S0_ISP_R
C
3 4
NET SPACING TYPE SWITCHNODE 1%
1/10W
98 P1V05S0_VW 4 VW MF
2 603 (P1V05S0_V0)
1
VO
98 12 P1V05S0_VO R7464
1K
1%
98 P1V05S0_COMP 5 COMP OCSET 3 98 P1V05S0_OCSET 1/16W
MF-LF
2 402
98 P1V05S0_FB 6 FB ISP
98 13 P1V05S0_ISP
ISN
98 11 P1V05S0_ISN
P1V05_S0_VDIFF 7 VDIFF
1NOSTUFF
98
1
ICOMP
98 10 P1V05S0_ICOMP R7469 1 C7473 R7470
9.31K 0.01UF 10K
68 6 PP1V05_S0_REG PGND VSS THRM_PAD 1% 10% 1%
1/16W 50V 1/16W
MF-LF 2 X7R MF-LF
20
15
33
1
R7463 (P1V05S0_VO) 2 402 402 2 402
100 1
1% C7476 1 R7472
1/16W 0.1UF 150K 1
MF-LF 10% 1% R7473 1 1
R7466 2 402 16V 1/16W C7477 C7478
X7R-CERM 2 MF-LF 10K 0.1UF 0.1UF
20 (P1V05S0_VSEN) 402 2 402 1% 10% 10%
98 13 CPU_VCCIO_SENSE_P 1 2 1/16W
MF-LF 2 25V
X5R 2 25V
X5R
1%
1/16W 1 C7470 (P1V05S0_ISP) 2 402 402 402
MF-LF
402 0.001UF (P1V05S0_ISN)
10%
R7468 2 50V
20 X7R
CPU_VCCIO_SENSE_N 1 2 402 1
98 13
(P1V05S0_RTN) XW7461 R7475
1% SM 45.3K
1/16W
MF-LF 1 2
1%
1/16W
OUTPUT BULK DECOUPLING
402
1
68 GND_P1V05S0_AGND MF-LF
R7471 VOLTAGE=0V OMIT 2 402 68 6 PP1V05_S0_REG
B 100
1%
MIN NECK WIDTH=0 2 MM (P1V05S0_ICOMP) B
1/16W 1 1 1 1 1 1
MF-LF C7443 C7444 C7445 C7446 C7428 C7429
2 402 330UF-0.0045OHM 330UF-0.0045OHM 330UF-0.0045OHM 330UF-0.0045OHM 22UF 22UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V
2 2V 2 2V 2 2V 2 2V 2 CERM-X5R 2 CERM-X5R
POLY POLY POLY POLY
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM 805 805
(P1V05S0_VW)
C7479 1
0.001UF
C7480 10%
50V
33PF X7R 2 1
1 2 402 R7476
6.65K
5% 1%
1/16W
50V 1.05V DEFAULT, OTHER VALUES TBD
CERM C7481 MF LF
R7477 402 0.001UF 2 402
150K 1 2
1 2 P1V05S0_COMP_C
(P1V05S0_COMP)
1%
1/16W 10% VID<3:0> Voltage
MF LF 50V
402 CERM
402 (P1V05S0_FB) 0000 +1.100V
C7482 0011 +1.050V
R7478 0.001UF
1
200 2 1 2
P1V05S0_VDIF_C
1%
1/16W 10%
MF-LF R7479 50V
402 2.21K2 CERM
1 402
(P1V05S0_VDIFF)
1%
A 1/16W
MF-LF
402
SYNC MASTER=K62 AARON SYNC DATE=12/08/2009 A
PAGE TITLE
1V05 REGULATOR
DRAWING NUMBER SIZE

REVISION
R
10.1.0
74 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCCSA 0.925V (8.8A MAX)

D D
=PPVCCIO_S0_CPU_VCCSA 6
NOTE: THIS RAIL IS COMING FROM PPVCCSA_S0_INPUT_SNS AFTER SENSE RES

CRITICAL
U7505
R7531 ISL21070
100 SOT23-3 C7551
6 =PP3V3_S5_CPU_VCCSA 1 2 VCCSA_REF 1 VIN VOUT 2 10PF
5% 1 2
1/16W
MF-LF
402 5%
GND 50V
CERM
402
3
1 C7515 1 C7516
1UF 1UF
10% 10%
R7550 C7550
2 10V
X5R 2 10V
X5R 560PF
402 402 1
49.9K
2 VCCSA_FIL 1 2 5
1%
1/16W 10%
MF-LF 50V D
402 CERM
402 R7505
0
Q7500
1 2 98 VCCSA GATE 4 G IRFH3702TRPBF
NET_PHYSICAL_TYPE=VR_CTL_PHY S PQFN
5% DIDT=TRUE
1/16W NET_SPACING_TYPE=VR_CTL
MF-LF
402
376S0910
1
C 4 NOSTUFF
C
98 VCCSA_CNTRL_INPUT1 3 R7506 PPVCCSA_S0_FET 6
1K
1 VCCSA_OUT 1 2
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
5% 1 C7507 1 C7508
LM358-SOI-HF NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE 1/16W
DIDT=TRUE
NET_SPACING_TYPE=POWER 1
C7509 1
C7510
2 8 U7501 NET_SPACING_TYPE=VR_CTL MF-LF
402 220UF-25MOHM 220UF-25MOHM
10UF
10%
10UF
10%
20% 20% 6.3V
2 X5R 2 6.3V
2 6V X5R
2 6V POLY-TANT 805 805
POLY-TANT
=PP12V_S0_CPU_VCCSA 6 CASE-D2E-SM CASE-D2E-SM
1 Place C7507 inside cavity

R7504 Place C7508 inside cavity
2.2
5%
1/10W
MF-LF
2 603
98 VCCSA_PWR_RC
1 C7502 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

1UF
10%
2 25V
X5R
128S0330 2 POLYTANT,6V,220UF,25MOHM C7509,C7510
603-1
R7507 R7535
5.49K 22
98 VCCSA_CNTRL_INPUT2 1 2 VCCSA_CNTRL_INPUT2_R 1 2
1% 5%
1/16W 1/16W
B MF-LF
402
MF-LF
402 B
NOSTUFF
C7512
10PF
1 1 2
R7533
10K 5%
1% 50V
1/16W CERM
MF-LF 402
2 402
R7552 C7552
560PF
1
1K 98
2 VCCSA_CRL 1 2
5%
1/16W 10%
MF-LF 50V
402 CERM
402
R7503
0
98 13 CPU_VCCSA_SENSE 1 2
5%
1/16W
MF-LF
402 1 C7501
100PF
5%
50V
50 6
=PPVCCSA_S0_INPUT_PWR 2 CERM
402
4 CRITICAL
1 C7504 1 C7505
A 5
1
C7506
330UF-0.009OHM
20%
4.7UF
20%
0.1UF
20%
PAGE TITLE
2 2V 2 6.3V 10V
2 CERM
7
LM358-SOI-HF
POLY
CASE-D2-HF
X5R-CERM1
402 402 CPU VCCSA REGULATOR
6 8 U7501 DRAWING NUMBER SIZE

REVISION
R
10.1.0
NOTE: THIS POWER RAIL IS BEFORE THE SENSE RES R5310 THE INFORMATION CONTAINED HEREIN IS THE
75 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE 3 PHASE/4 PHASE BOM OPTIONS

D D
116S0066 1 RES,1K,5%,0402 R7125 CPUVCORE-4PH
114S0303 1 RES,7.5K,5%,0402 R7125 CPUVCORE-3PH
114S0211 1 RES,845,1%,0402 R7153 CPUVCORE-4PH
C 114S0225 1 RES,1.21K,1%,0402 R7141 CPUVCORE-4PH C

114S0331 1 RES,15K,1%,0402 R7143 CPUVCORE-3PH
116S0004 1 RES,0R,1%,0402 R7129 CPUVCORE-4PH
132S8221 1 CAP,820PF,10%,0402 C7123 CPUVCORE-4PH
132S1534 1 CAP,0.0012UF,10%,0402 C7123 CPUVCORE-3PH
B B

PAGE TITLE
CPU 3P/4P BOM OPTIONS

DRAWING NUMBER SIZE

REVISION
R
10.1.0
76 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
3V3 S5 REGULATOR C7719 1 C7766 1 C7767 1 C7768 1 C7758 1 C7765 1
71 6
=PP12V_S5_P5VS3_VREG
100UF
20%
16V
POLY
6 3X6 TH
2
100UF
20%
16V
POLY
6 3X6 TH
2
100UF
20%
16V
POLY
6 3X6 TH
2
100UF
20%
16V
POLY
6 3X6 TH
2
10UF
10%
16V
X5R CERM
0805
2
10UF
10%
16V
X5R CERM
0805
2 5V S3 REGULATOR
EMC CAPS
PLACE CLOSE TO FET
DIDT TRUE
=PP3V3 S5 VRD 6
Power Rating ?
C7718 1 C7712 1 C7710 1 1 C7711 1 C7722
100UF 10UF 10UF 1
20% 10% 10%
1UF
10%
1UF
10%
R7726
16V 2 16V
X5R CERM 2 16V
X5R CERM 2 2 16V 2 16V
=PP12V S5 P5VS3 VREG 6 71 20K
POLY X5R X5R 5%
6 3X6 TH 0805 0805
603 603 1/16W
MF-LF
NOSTUFF 2 402
1
R7725 PP5V_S5_LDO 6
20K EMC: C7754,C7755
3V3 OUTPUT 5% PLACE AT Q7330
2
1/16W
MF-LF
2 402
R7776
CRITICAL
RJK0384DPA
Q7710 D1
1 C7754 1 C7755 5V OUTPUT
L7710 1UF 1UF
PP3V3_S5_REG 2
0.002
1
WPAK G1 1 (P3V3S5 UGATE) 10% 10%
6 2.2UH-14A 376S0801 MIN NECK WIDTH=0 2MM
2 16V 2 16V
1 1 X5R X5R
1%
1206
1/4W
MF LF 1 2 NET_PHYSICAL_TYPE=POWER 7 S1/D2 MIN LINE WIDTH=0 6MM C7742 R7740 1 603 603
GATE NODE=TRUE R7741
C PP3V3_S5 REG_R
MMD06CZ-SM
1
DIDT TRUE
C7730
NET SPACING TYPE=VR CONTROL
4.7UF
20%
6.3V
2 CERM
5%
2.2
1/8W 5%
1 EMC: C7763 C7764
PLACE AT L7750.2
C
98
NET_PHYSICAL_TYPE=POWER C7790
R7790 5%
1000PF G2 6 (P3V3S5_LGATE) 603 MF-LF
2 805
1/8W
MF-LF
DIDT TRUE
PP5V_S3 REG 6
0.01UF MIN NECK WIDTH=0 2MM 2 805 5
1 2 CERM 1 15.8K 2 25V
NP0-C0G MIN LINE WIDTH=0 6MM P5V_S5_LDO_R PM_PGOOD_P5V_S3_REG 1 1
16V 2
402 GATE NODE=TRUE OUT 63 83 100
C7763 C7764
10% 402 1% NOSTUFF
S2 NET SPACING TYPE=VR CONTROL D
P5V_S5_VCC1 10% 10%
1/16W
Q7750
3
MF LF 1 C7741 50V
2
50V 2
1 NET SPACING TYPE=VR CTL 4 G X7R X7R
R7791 402
NOSTUFF C7740 1 1UF 1 C7743 MIN LINE WIDTH=0 6MM
FDMS0346 402 402
15.8K 1 10% MIN NECK WIDTH=0 2 MM POWER56
1%
R7730 1UF 16V
2 X5R 1UF
10% 10% NET_SPACING_TYPE=VR_CONTROL 376S0875
P5VS3_REG_BOOT_R
0.499
NET_SPACING_TYPE=VR_CONTROL
1/16W 16V 603 16V
MIN_NECK_WIDTH=0.2 MM
MF LF 1% X5R 2 2 X5R S R7775
2 402 1/10W 603 603
MF CRITICAL 0.002
2 1
2 603 1 2 3 L7750 1% 1/4W
VCC1 5
4
C7756 2.2UH+/-20%-0.0069OHM-16A 1206 MF LF
R7750 0.1UF
VCC2
VIN_5V_S5_REG_RC 2
0 1 2 1 1 2
P3V3S5 REG SNUB 18 LDO5 VIN 17 PIC1005H-SM PP5V_S3_REG_R
98
C7714 R7710 5% DIDT TRUE
NET_SPACING_TYPE=SWITCHNODE
DIDT TRUE 10%
1
X7R
2 98 P3V3S5_REG_BOOT_R 1
0
2
U7700 FCCM 3 TP_P5VS3_REG_FCCM
1/10W
MF-LF
10%
25V
X5R NOSTUFF
DIDT TRUE NET_PHYSICAL_TYPE=POWER NET_PHYSICAL_TYPE=POWER
603
5%
ISL62383 402 C7757 1
MIN LINE WIDTH=0 6MM PM_PGOOD_P3V3_S5_REG 7 PGOOD1
0.1UF DIDT TRUE 1/10W 100 64 27 QFN PGOOD2 1 MIN NECK WIDTH=0 2 MM 0.001UF C7770
NET SPACING TYPE=VR CONTROL MF LF
603
CRITICAL MIN LINE WIDTH=0 6MM 10%
50V
R7770 27.0NF
(P3V3S5 PHASE) 98 P3V3S5_REG_UGATE 14 UGATE1 UGATE2 22 98 P5VS3_REG_UGATE NET_SPACING_TYPE=VR_CONTROL CERM 2 9.76K 1 2 OUTPUT BULK DECOUPLING:
DIDT TRUE 2 1
DIDT TRUE 402
NET SPACING TYPE=VR CONTROL98 P3V3S5_REG_BOOT 15 BOOT1 BOOT2 21 98 P5VS3_REG_BOOT 1% 1/16W
MIN NECK WIDTH=0 2MM DIDT TRUE 402 MF LF 10%
DIDT TRUE MIN NECK WIDTH=0 2 MM 10V
MIN LINE WIDTH=0 6MM 5V SNUBBER CRITICAL CRITICAL
98 P3V3S5_REG_PHASE 13 PHASE1 PHASE2 23 98 P5VS3_REG_PHASE MIN LINE WIDTH=0 6MM X5R
402
DIDT TRUE DIDT TRUE
DIDT TRUE
MIN LINE WIDTH=0 4MM C7761 1 1
C7762
98 P3V3S5 REG LGATE 16 LGATE1 LGATE2 20 98 P5VS3 REG LGATE MIN NECK WIDTH=0 2 MM
5
MIN NECK WIDTH=0 2 MM
1 1
330UF 330UF
NET SPACING TYPE=SWITCHNODE
NET PHYSICAL TYPE=POWER DIDT TRUE DIDT TRUE MIN LINE WIDTH=0 6MM NET SPACING
1 TYPE=SWITCHNODE C7760 C7769 20%
6.3V 2
20%
R7752 10UF 10UF 2 6.3V
OUTPUT BULK DECOUPLING: PLACEMENT NOTE=PLACE NEXT TO C7716 98 P3V3S5_REG_ISEN 10 ISEN1 ISEN2 26 98 P5VS3_REG_ISEN NET SPACING TYPE=VR CONTROL
1
POLY-TANT POLY-TANT
0.499 CASE-D3L-SM CASE-D3L-SM
D R7771 2 20% 6.3V 20% 6.3V
2 1
98 P3V3S5_REG_OCSET 11 OCSET1 OCSET2 25 98 P5VS3_REG_OCSET 1% 1/10W 9.76K CERM 805-1 2 CERM 805-1
128S0237
B 1 C7717 1
CRITICAL
XW7716
SM
98 P3V3S5 REG VOUT1 9 VOUT1 VOUT2 27 98 P5VS3 REG VOUT2 CRITICAL
4 G MF 603
2 NOSTUFF
1%
1/16W
MF LF
B
C7715 C7721 1 Q7751 402 2
P3V3S5_REG_FB_R
10UF 10UF OMIT 98 P3V3S5_REG_FB

10% 330UF 1 8 FB1 FB2 28 98 P5VS3_REG_FB
10% 16V
2
20% R7724 FDMS0355S S
R77201
16V 6.3V 2
X5R CERM 2 X5R CERM 976 POWER56
0805 POLY-TANT 1 6 FSET1 FSET2 2 98 P5VS3_REG_FSET2
0805 CASE-D3L-SM 45.3K
1%
1%
1/16W
R7722 1 2 3 2
MF-LF 68K 12 EN1 24
<Ra> 1/16W
MF-LF 402 2 5% EN2 376S0917
402 2 1/16W
MF-LF THRM SM XW7751
2 402 PAD PGND OMIT
1
29
19
C7720 1 100 PM_EN_P3V3_S5_REG
R7721 1 1000PF
1 C7723 1 C7716 <Rb> 10.0K 5% 1
0.1UF 0.1UF 0 5%
25V
NP0 C0G 2 R7723
20% 20%
1/16W
MF
402 33K
2
16V
2
16V
402
5% 98 P3V3S5_REG_FSET1
CERM CERM 2 1/16W
603 603 MF-LF
2 402 1 C7701 1
R7701
0.01UF 16.5K
EMC CAPS Vout = 0.6V * (1 + Ra / Rb) 10% 1%
16V
P5VS5_REG_FB_R
PLACE CLOSE 2 CERM 1/16W
TO L 402 MF-LF R77591 R77551
2 402 976 75K RA
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2
100 63
PM_EN_P5V_S3_REG RB
C7759 1 1
1 NOSTUFF R7756
1 C7747 R7747 1000PF 10K
0.01UF 16.5K 1 C7777 5% 1%
25V
10% 1% 0.001UF NP0-C0G 2 1/16W
2 16V
CERM
1/16W
MF-LF 10% 402 MF LF
402 50V 2 402
2 402 2 CERM
A 402
PAGE TITLE
5V S3 / 3V3 S5 VREGS
DRAWING NUMBER SIZE

REVISION
R
10.1.0
77 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.5 V DDR SUPPLY PPDDR_S3_REG

NET_PHYSICAL_TYPE=POWER VOUT = 1.5V
PEAK = 11A
=PP12V_S5_DDR_VREG AVG = 6.7A
D 6
NET_PHYSICAL_TYPE=POWER DIDT TRUE
EMC CAPS
PLACE CLOSE TO FET D
=PP5V_S3_DDR_VREG R7801 CRITICAL CRITICAL
6
1 C7833 1 C7834 EMC CAPS
NET_PHYSICAL_TYPE=POWER 1
4.7
2 98 PP5V_S3_DDR_REG_V5FILT C7830 1 C7831 1 1
C7832 1UF 1UF PLACE CLOSE TO L7830
MIN LINE WIDTH=0 6 mm NET_PHYSICAL_TYPE=POWER 270UF 270UF 10UF 10% 10%
5% MIN NECK WIDTH=0 2 mm 20% 20% 10%
16V 2 16V
X5R 2 16V
X5R
1/16W VOLTAGE=5V 16V 2 16V 2 2 X5R CERM 603 603
MF LF ELEC ELEC 1 C7838 1 C7839
402 8X9-TH1 8X9-TH1 0805
6 =PP3V3_S3_VRD 0.001UF
10%
0.001UF
10%
50V 50V
1
C7815 2 2 X7R
R7810 1
R7841
X7R
R7820 1
C7800 1
C7801 1
10UF 402 402
3.57K 4.7
15
14
23
20%
10K 4.7UF 1UF 6 3V 1% (DDRREG_DRVH) 1 2 DDR_REG_UGATE_R
20% 10% 2
5% 6 3V 10V X5R 1/16W MIN LINE WIDTH=0 6 mm MIN LINE WIDTH=0 6 mm CRITICAL
1/16W CERM 2 X5R 2 V5IN V5FILT VLDOIN 603 MF LF MIN NECK WIDTH=0 2 mm C7840 5%
1/10W
MF LF 402
402
2
603 402 2 DIDT TRUE 0.1UF MF LF
603
DIDT TRUE
VR CTL Q7830
6 COMP VDDQSNS 8
98 DDR_REG_BOOT_R 1 2 CSD58864Q5D
DIDT TRUE SON5X6 VIN 1 CRITICAL
CRITICAL 3 TG
PM_EN_DDRVTT_S0_REG MODE 4 98 DDR_REG_VDDQSNS
20%
25V L7830
100 63 32 IN 10 S3 VTT Enable
R7840 CERM
603
VSW 6 1.5UH-15%-22A-3.3MOHM
100 63 IN PM EN DDR1V5 S3 REG 11 S5 VDDQ/VTTREF Enable 0 SPACING TYPE SWITCHNODE 4 TGR 7 1 2
VBST 22 98 DDR_REG_BOOT 1 2 MIN LINE WIDTH=0NET
6 mm 98 DDR_REG_PHASE_R PP1V5_S3_REG 6
100 63 5 OUT PM PGOOD DDR1V5 S3 REG 13 PGOOD VDDQ PGOOD U7800 DIDT TRUE MIN LINE WIDTH=0 6 mm MIN NECK WIDTH=0 2 mm
8 SDP1182M-TH NET_PHYSICAL_TYPE=POWER
MIN NECK WIDTH=0 2 mm 5% NET SPACING TYPE VR CONTROL MIN LINE WIDTH=0 6 mm
NET SPACING TYPE=VR CONTROL 1/10W MIN NECK WIDTH=0 2 mm
TPS51116 DRVH 21 98 DDR_REG_UGATE MF-LF DIDT TRUE NOSTUFF 1 OUTPUT BULK DECOUPLING:
TP_PPVTT_S3_DDR_BUF 10mA max load
5 VTTREF
QFN NET SPACING TYPE=VR CONTROL 603
5 BG NET SPACING TYPE=VR CTL C7841
1000PF CRITICAL 1
(NOT USED) Vout = VDDQSNS/2 SYM (2 OF 2) LL 20 98 DDR REG PHASE (DDRREG LL) 5% 1 CRITICAL C7837
24 VTT MIN LINE WIDTH=0 6 mm DIDT TRUE PGND 25V
NP0-C0G 2
C7835 1
C7836 10UF
OMIT Vout = VTTREF MIN NECK WIDTH=0 2 mm 330UF 330UF 20%
9
402 1V5 SNUBBER 20% 6 3V
XW7803 DRVL 19 98 DDR_REG_LGATE (DDRREG_DRVL) 98
2 2.5V
20% 2 X5R
SM NET SPACING TYPE=VR CONTROL MIN LINE WIDTH=0 6 mm DIDT TRUE
POLY-TANT 2 2.5V 603
6
PPVTT_S0_DDR_LDO 1 2 DDR REG VTTSNS
98 2 VTTSNS
MIN NECK WIDTH=0 2 mm MIN LINE WIDTH=0 4MM
CASE-D2E-SM3 POLY-TANT
CASE-D2E-SM3
NO_TEST=TRUE CS 16 98 DDR_REG_CS DIDT TRUE
FEEDBACK THROUGH SHORT NET SPACING TYPE SWITCHNODE
SHOULD NOT NEED TP NC 7 NC0
12 NC1 VDDQSET 9 98 DDR_REG_FB 1NOSTUFF
NC R7831
C CRITICAL CRITICAL VTTGND THRM_PAD GND PGND CS_GND
OMIT
0.499
1%
1/10W
2
OMIT
C
C7804 1
1
C7803 XW7831 XW7830
25
18
17
PLACEMENT NOTE=PLACE NEXT TO Q7831 MF SM
22UF 22UF SM
2 603
20%
6 3V 20% 98 DDR_REG_CSGND (DDRREG CSGND) 1 2 1
2 6 3V
CERM X5R 2 MIN LINE WIDTH=0 2 mm
CERM X5R PLACEMENT NOTE=PLACE NEXT TO L7830
805-3 805 3 MIN NECK WIDTH=0 2 mm
98 DDR_REG_PGND (DDRREG VDDQSNS)

MIN NECK WIDTH=0 2 mm NOSTUFF 1
1
2
2MIN NECK WIDTH=0 2 mm
C7820 1 R7832 <Ra>
C7805 XW7800 15.0K
0.033UF XW7801 100PF 1%
SM 5%
10% OMIT SM 50V 1/16W
16V OMIT CERM 2 MF LF
X5R 2
2 402
1 402
402 1
(DDRREG FB)
1
R7833 <Rb>
STATE S3 S5 VDDQ VTTREF VTT AGND_DDR_REG
Vout = 0.75V * (1 + Ra / Rb) 15.0K
S0 HI HI ON ON ON MIN LINE WIDTH=0 6 mm
1%
1/16W
S3 LO HI ON ON OFF MIN NECK WIDTH=0 2 mm
VOLTAGE=0V
MF LF
2 402
S5 LO LO OFF OFF OFF
B B
1.8 V SUPPLY
1A Average current
6
=PP5V_S0_P1V8_REG Vo=0.8*(1+ Ra/Rb)
Vo=0.8*(1+ 59/47)=1.804V
1 C7854 1 C7855 1 R7853 1 R7854
22UF 22UF
20% 20% 100K 100K
2 6.3V 2 6.3V
1
2
X5R-CERM-1 X5R-CERM-1 5% 5%
603 603 1/16W 1/16W
MF-LF MF-LF VDD
2 402 2 402 VIN
CRITICAL
U7850 L7850
ISL8013A 1.5UH-4A
QFN LX0 13
100 63
PM_EN_P1V8_S0_REG 5 EN CRITICAL LX1 14
98 P1V8 REG PHASE 1 2
PP1V8_S0_REG
MMD04BZ-SM 6
LX2 15 NET PHYSICAL_TYPE=POWER
DIDT TRUE
100 64 PM_PGOOD_P1V8_S0_REG 7 PG SWITCHNODE NET_PHYSICAL_TYPE=POWER
8 1
98 P1V8_REG_SYNC 4 SYNCH
VFB
98 P1V8_REG_VFB 1 <Ra> R7850
59.0K
A NOSTUFF
CONTINUOUS MODE
NC
16
6 C7850 5%
47PF
50V 2 1/16W 1%
MF-LF 402
1 R7860 402 CERM 2
1 C7852 1 C7853 PAGE TITLE
100K
SGND PGND THRM_PAD 22UF
20%
6.3V
22UF
20%
6.3V
1.5V / 1.8V VREGS
5% 1 2 X5R-CERM-1 2 X5R-CERM-1 DRAWING NUMBER SIZE
R7851
9
10
11
12
17
1/16W
MF-LF <Rb> 47.0K
603 603
2 402 REVISION
1/16W 1% R
MF-LF 402 10.1.0
2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
78 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator
6
=PP12V G3H 3V42
NET_SPACING_TYPE=POWER 98 P3V42G3H_BOOST
C7900 1
3
C7910 1 VIN BOOST
0.22UF
10UF 20% CRITICAL
1 10% 6.3V 2
R7910 25V 2 U7900 X5R L7900
6.98K
1%
X5R
805 LT3470A
DFN
402
33UH PP3V42 G3H REG 6
1/16W 100 3V42G3H_SHDN_L 8 SHDN* P3V42G3H_SW 1 2
MF-LF SW 4 98
402 2
BIAS 2 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
CDPH4D19FHF-SM Vout = 3.425
C NC
7 NC CRITICAL
FB 1
SWITCH_NODE=TRUE DIDT=TRUE
NET_SPACING_TYPE=SWITCHNODE 250mA max output C
THRM
(Switcher limit)
GND PAD 1
C7901 1 <Ra> R7900
9
22pF 348K
1%
353S2171 5%
50V 1/16W 1 C7902
CERM 2 MF-LF
402 2 22UF
402 20%
2 6.3V
X5R-CERM-1
1 98 P3V42G3H_FB 603
R7911 1 C7911
2.1K 1000PF
1%
1/16W 5% <Rb> R79011
MF-LF 2 25V
NP0-C0G 200K
402 2 402 1%
1/16W
MF-LF
402 2
Vout = 1.25V * (1 + Ra / Rb)
B B

PAGE TITLE
3.42 G3HOT SUPPLY

DRAWING NUMBER SIZE

REVISION
R
10.1.0
79 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5V S0 FET (6.6A PK/3.1A AVG) 3.3V S0 FET (2.9APK / 2.0A AVG) 3.3V S3 FET (3.4A PK / 1.6A AVG)
74 64 33 6 =PP12V S5 PWRCTL
74 64 33 6 =PP12V_S5_PWRCTL
1 C8000 =PP12V_S5_PWRCTL
0.1UF 1 C8053 74 64 33 6
10%
CRITICAL 16V
2 X5R 0.1UF 1 C8050
CRITICAL 10%
Q8000 402
Q8053 2 16V
X5R
0.1UF
10%
IRFH3702TRPBF 402 CRITICAL 16V
2 X5R
IRFH3702TRPBF
PQFN
PP5V S0 FET PQFN
Q8050 402
6
IRFH3702TRPBF
D 6 =PP5V S3 S0FET PP3V3 S0 FET 6
PQFN
D
S
=PP3V3_S5_S0FET PP3V3_S3_FET
1
6 6
S
5
1
6 =PP3V3_S5_S3FET
S
5
1
G
81 74 64 63 6 =PP3V3 S0 PWRCTL
G
81 74 64 63 6 =PP3V3_S0_PWRCTL
83 64 6 =PP3V3 S3 PWRCTL
NOSTUFF
G
4
1
1
R8000 VCC
P5V_S0_EN_G
1
10K 1
R8050
4
P3V3_S0_EN_G
1
5%
U8000 VCC R8051
1
1/16W 10K
P3V3_S3_EN_G
MF-LF 5% 10K VCC
2 402
SLG5AP001 1/16W
MF-LF
U8053 5%
1/16W
5D TDFN
ON 2 2 402 SLG5AP001 MF-LF U8050
5D TDFN
ON 2 2 402 SLG5AP001
7G CRITICAL S6 TDFN
5D ON 2
7G CRITICAL S6
64 63PM_PGOOD_P5V_S0_FET 8 PG NC 3
100 7G S6
100 64 63 PM_PGOOD_P3V3_S0_FET 8 PG NC 3 CRITICAL
THRM
PAD GND 100 34 PM PGOOD P3V3 S3 FET 8 PG NC 3
THRM
4
PAD GND
THRM
4
PAD GND
4
100 63 IN PM EN P5V S0 FET
100 63 IN PM_EN_P3V3_S0_FET
1.5V S0 FET (4.8A PK / 4.8A AVG)

C CRITICAL
Q8025
C
IRFH3702TRPBF
PQFN
6 =PP1V5_S3_S0FET PP1V5_S0_FET 6
D
S
5
1
G
1 C8025
0.1UF
4
10%
2 16V
X5R
74 64 33 6 =PP12V_S5_PWRCTL 402
P1V5_S0_EN_G
81 74 64 63 6 =PP3V3_S0_PWRCTL
1
1
R8020 VCC
10K
5%
1/16W
U8025
MF-LF SLG5AP001
2 402 5D TDFN
ON 2
7G CRITICAL S6
100 64 11 PM_PGOOD_P1V5_S0_FET 8 PG NC 3
THRM
PAD GND
9
B B

PAGE TITLE
S3+S0 FETS
DRAWING NUMBER SIZE

REVISION
R
10.1.0
80 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
THE NMOS PMOS SHARING FOOTPRINT WILL NOT WORK DUE TO THE REVERSE POLARITY OF BODY DIODE.
PROTO-3:
Q8110 P-CH MOSFET 376S0933 4.6-MOHM 20A (WHEN USED W/Q8112)
IRFH9310PBF
=PP12V_G3H_S5_FET ADD C8111 2.2UF PQFN R8132
6 CRITICAL 0.005
1%
1W
10Amp-7Amp
NOSTUFF
R8103 98 PP12V S5 RSN
MF
2512 PP12V S5 FET
5
1 2 6 98
100 PP12V_SLG1
D
1 2
98 NET_PHYSICAL_TYPE=POWER 3 4
VOLTAGE=12V
5% 1 C8100 MIN_LINE_WIDTH=1mm
G
1/10W MIN_NECK_WIDTH=0.5mm
MF-LF 1UF NOSTUFF NOSTUFF
4
603 10% R8104 C8110 1
2 16V
X5R 0 R81101 C8111 1
0.47UF
1 2
603 353S3098 2.2UF 10%
NOSTUFF 10K
1
5% 10% 16V 2
VCC 5% 16V X7R
1/16W 1/16W
MF-LF X7R-CERM 2 805
NC
MF-LF
NC
U8100 402 402 2 805
(2.4-5.5V) SLG5AP026
SMC_PM_G2_EN 2 TDFN 5 S5_D_ON1 REMOVE R8132 BEFORE DVT
100 46 ON D1 R8111
High=3.3V 3 6 S5 S ON1 NOSTUFF
1
10K 2 100 S5 MSFT G1
NOSTUFF NC D2 R8105
R81001 7 S5_GT_ON 1
0 2
5%
100K CRITICAL
G
5% MF-LF
1/16W
MF-LF R8101
5% 1/16W 402 402 0
C 1/16W
MF-LF
402 2 THRM
PG 8
NOSTUFF
PGOOD P12V S5 G3H 1
5%
2 TP PGOOD P12VS5 G3H
C
GND PAD R8106 1/16W
S5_DG_1 MF-LF
9
100
1
0 2
402
NOSTUFF
5%
1/16W
MF-LF 1
402 R8112
10K
5% 402
MF-LF
1/16W
2
100 SMC_PM_G2_EN_L
3
D
R8113 Q8112
0 100 SMC_PM_G2_EN_R 2N7002
1 2 1 G S SOT23-HF1
5%
1/16W 2
MF-LF
402
B B

PAGE TITLE
12V S0 & 12V S5 switch

DRAWING NUMBER SIZE

REVISION
R
10.1.0
81 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- =PP3V3_S0_MXM
- =PP5V_S0_MXM
- =PPV_S0_MXM_PWRSRC
Signal aliases required by this page:

(NONE)
D BOM options provided by this page: D

- MXM
MXM
77 76 64 21 6 =PP3V3_S0_MXM CRITICAL
MXM
MXM
R84001 J8400 =PP3V3 S0 MXM 6 21 64 76 77
100K B35P101-0121 J8400 MXM MXM

5%
1/16W F-RT-SM B35P101-0121 1 C8415 1 C8416
MF-LF F-RT-SM
402 2
(2 OF 4)
(4 OF 4) 0.001UF 22UF
APPLE P/N: 516S0699 10% 20%
2 50V
X7R 2 6.3V
CERM-X5R
100 9 MXM CLKREQ L 154 CLK_REQ* DP_A_AUX* 277 MXM DP A AUX N 79 6 =PP5V S0 MXM 1 278 402 805-3
DP_A_AUX 279 MXM_DP_A_AUX_P 79 MXM MXM 3 3V3 280
MXM_PCIE_STD_SWING_L 19 PEX_STD_SW*
77
DP_A_HPD 276 MXM DP A HPD

C8410 1 1 C8401 5 5V
9 CLK_100M_MXM_P 155 PEX_REFCLK
79
0.001UF 22UF 7
10% 20%
9 CLK_100M_MXM_N 153 PEX_REFCLK* DP_A_L0* 253 MXM_DP_A_ML_N<0> 79
50V 2 2 6.3V 9 E2
X7R CERM-X5R
255 MXM_DP_A_ML_P<0> 402 805-3 PWR_SRC E1 =PP12V_S0_MXM
DP_A_L0 79 6
9 MXM_RESET_L 156 PEX_RST*
DP_A_L1* 259 MXM_DP_A_ML_N<1> 79
93 78 MXM PCIE D2R N<0> 147 PEX_RX0* DP_A_L1 261 MXM DP A ML P<1> 79 MXM MXM MXM MXM
93 78 MXM PCIE D2R P<0> 149 PEX_RX0 DP_A_L2* 265 MXM DP A ML N<2> 79 C8400 1 1 C8412 1 C8413 1 C8414
93 78 MXM_PCIE_D2R_N<1> 141 PEX_RX1* DP_A_L2 267 MXM_DP_A_ML_P<2> 79 22UF 0.001UF 0.001UF 0.001UF
20% 10% 10% 10%
MXM_PCIE_D2R_P<1> 143 271 MXM_DP_A_ML_N<3> 35V 2 50V 50V 50V
93 78 PEX_RX1 DP_A_L3* 79 2 X7R 2 X7R 2 X7R
MXM_PCIE_D2R_N<2> MXM_DP_A_ML_P<3>
MXM SPEC POWER REQUIREMENTS ELEC
6.3X5.5-SM1 402 402 402
93 78 135 PEX_RX2* DP_A_L3 273 79
(NOT NECESSARILY THE SAME FOR EVERY MODULE)
93 78 MXM_PCIE_D2R_P<2> 137 PEX_RX2
DP_B_AUX* 270 MXM DP B AUX N 79 96 VOLTAGE CURRENT POWER
93 78 MXM_PCIE_D2R_N<3> 121 PEX_RX3*
C DP_B_AUX 272 MXM_DP_B_AUX_P
C
PCI-E
79 96
93 78 MXM_PCIE_D2R_P<3> 123 PEX_RX3 3V3 1.0 A 3.3 W
DP
93 78 MXM PCIE D2R N<4> 115 PEX_RX4* DP_B_HPD 274 MXM DP B HPD 79 5V 2.5 A 12.5 W
93 78 MXM PCIE D2R P<4> 117 PEX_RX4 PWR (7-20V) UP TO 10 A PLATFORM DEPENDENT
DP_B_L0* 246 MXM_DP_B_ML_N<0> 79 96
DP_B_L0 248 MXM_DP_B_ML_P<0> 79 96
DP_B_L1* 252 MXM_DP_B_ML_N<1> 79 96
DP_B_L1 254 MXM DP B ML P<1> 79 96
DP_B_L2* 258 MXM_DP_B_ML_N<2> 79 96
DP_B_L2 260 MXM_DP_B_ML_P<2> 79 96
DP_B_L3* 264 MXM_DP_B_ML_N<3> 79 96
93 78 MXM PCIE D2R N<8> 91 PEX_RX8*
DP_B_L3 266 MXM_DP_B_ML_P<3> 79 96
MXM_PCIE_D2R_N<9> 85 PEX_RX9* DP_C_AUX* 223 MXM_DP_C_AUX_N
93 78
93 78 MXM_PCIE_D2R_P<9> 87 PEX_RX9 DP_C_AUX 225 MXM_DP_C_AUX_P

84 96
84 96
MXM DP PORT ROUTING
93 78 MXM_PCIE_D2R_N<10> 79 PEX_RX10* K62 K60
DP_C_HPD 234 MXM_DP_C_HPD 84
93 78 MXM_PCIE_D2R_P<10> 81 PEX_RX10 DP A EXT DP1 EXT DP1
93 78 MXM_PCIE_D2R_N<11> 73 PEX_RX11* DP_C_L0* 199 MXM_DP_C_ML_N<0> 84 96 DP B T29 DP2 T29 DP2
93 78 MXM_PCIE_D2R_P<11> 75 PEX_RX11 DP_C_L0 201 MXM_DP_C_ML_P<0> 84 96 DP C INT DP INT DP
93 78 MXM_PCIE_D2R_N<12> 67 PEX_RX12* DP_C_L1* 205 MXM_DP_C_ML_N<1> 84 96 DP D T29 DP1 T29 DP1
93 78 MXM_PCIE_D2R_P<12> 69 PEX_RX12 DP_C_L1 207 MXM_DP_C_ML_P<1> 84 96 DP E EXT DP2
93 78 MXM_PCIE_D2R_N<13> 61 PEX_RX13* DP_C_L2* 211 MXM_DP_C_ML_N<2> 84 96
93 78 MXM_PCIE_D2R_P<13> 63 PEX_RX13 DP_C_L2 213 MXM_DP_C_ML_P<2> 84 96
93 78 MXM_PCIE_D2R_N<14> 55 PEX_RX14* DP_C_L3* 217 MXM_DP_C_ML_N<3> 84 96
93 78 MXM_PCIE_D2R_P<14> 57 PEX_RX14 DP_C_L3 219 MXM_DP_C_ML_P<3> 84 96
DP_D_AUX* 230 MXM_DP_D_AUX_N 79 96
93 78 MXM PCIE D2R P<15> 51 PEX_RX15
DP_D_AUX 232 MXM_DP_D_AUX_P 79 96
93 78 MXM_PCIE_R2D_N<0> 148 PEX_TX0*

B 93 78 MXM_PCIE_R2D_P<0> 150 PEX_TX0
DP_D_HPD 236 MXM_DP_D_HPD 79
B
93 78 MXM PCIE R2D N<1> 142 PEX_TX1* DP_D_L0* 206 MXM DP D ML N<0> 79 96
93 78 MXM PCIE R2D P<1> 144 PEX_TX1 DP_D_L0 208 MXM DP D ML P<0> 79 96
93 78 MXM_PCIE_R2D_N<2> 136 PEX_TX2* DP_D_L1* 212 MXM_DP_D_ML_N<1> 79 96
93 78 MXM_PCIE_R2D_P<2> 138 PEX_TX2 DP_D_L1 214 MXM_DP_D_ML_P<1> 79 96
93 78 MXM PCIE R2D N<5> 108 PEX_TX5*

93 78 MXM PCIE R2D P<5> 110 PEX_TX5
93 78 MXM_PCIE_R2D_P<6> 104 PEX_TX6
93 78 MXM PCIE R2D N<9> 84 PEX_TX9*
93 78 MXM PCIE R2D P<9> 86 PEX_TX9
MXM PCIE R2D N<13> 60
A 93 78
93 78 MXM PCIE R2D P<13> 62

PEX_TX13*
PEX_TX13 SYNC MASTER=K62 AARON SYNC DATE=N/A A
93 78 MXM PCIE R2D N<14> 54 PEX_TX14* PAGE TITLE
93 78 MXM_PCIE_R2D_P<14> 56 PEX_TX14 MXM PCIe, DP & Power

93 78 MXM_PCIE_R2D_N<15> 48 PEX_TX15* DRAWING NUMBER SIZE
REVISION
R
10.1.0
84 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP3V3_S0_MXM

- =SMB_MXM_THRM_DATA - =PM_MXM_PGOOD_PULLUP PULLUPS & PULLDOWNS AT MXM CONNECTOR
- =SMB_MXM_THRM_CLK
D BOM options provided by this page: D

FLOAT = NORMAL VGA MODE
GND = SECONDARY DISPLAY CARD NOSTUFF
R8510
2
0 1
MXM 77 MXM VGA DISABLE L
MXM
MF-LF 5% 1/16W
J8400 J8400 402

MXM
B35P101-0121 B35P101-0121 FLOAT = LOW SWING
GND = HIGH SWING R8504
F-RT-SM F-RT-SM 0
(1 OF 4) (3 OF 4) 76 MXM_PCIE_STD_SWING_L 2 1
79 MXM_DP_E_AUX_P 35 LVDS_DDC_CLK
MF-LF 5% 1/16W
79 MXM DP E AUX N 33 LVDS_DDC_DAT VGA_DISABLE* 21 MXM VGA DISABLE L 77 11 145
402
13 146
79 MXM_DP_E_HPD 31 DVI_HPD GPIO0 26 TP_MXM_GPIO0
15 151
GPIO1 28 TP_MXM_GPIO1
79 MXM_DP_E_ML_N<3> 176 LVDS_LCLK* 17 152
GPIO2 30 TP_MXM_GPIO2
79 MXM_DP_E_ML_P<3> 178 LVDS_LCLK 36 157
HDMI_CEC 29 TP_MXM_HDMI_CEC 37 166
79 MXM DP E ML N<2> 200 LVDS_LTX0*
46 173
79 MXM_DP_E_ML_P<2> 202 LVDS_LTX0 OEM0 38
47 174 =PP3V3_S0_MXM 6 21 64 76 77
OEM1 39
79 MXM DP E ML N<1> 194 LVDS_LTX1* 52 179
OEM2 40
79 MXM_DP_E_ML_P<1> 196 LVDS_LTX1 53 180
OEM3 41
58 185
79 MXM_DP_E_ML_N<0> 188 LVDS_LTX2* OEM4 42
59 186
79 MXM DP E ML P<0> 190 LVDS_LTX2 OEM5 43
LVDS
64 191
OEM6 44
96 79 MXM_LVDS_A_DATA_N<3> 182 LVDS_LTX3* 65 192
OEM7 45
MXM_LVDS_A_DATA_P<3>
96 79 184 LVDS_LTX3 70 197 R8500
PNL_BL_EN 25 MXM_PNL_BL_EN 79 71 198 100K 2
C 96 79
96 79
MXM_LVDS_B_CLK_N
MXM_LVDS_B_CLK_P
169
171
LVDS_UCLK*
LVDS_UCLK PNL_BL_PWM 27 MXM_PNL_BL_PWM 84 100
76
77
203
204
77 MXM_DETECT_L 1
MF-LF 5% 1/16W
402
C
GND GND PULLED TO GROUND ON MXM
96 79 MXM LVDS B DATA N<0> 193 LVDS_UTX0* PNL_PWR_EN 23 MXM PNL PWR EN 79 82 209 WE DON’T USE CARD DETECT
96 79 MXM_LVDS_B_DATA_P<0> 195 LVDS_UTX0 77 76 64 21 6 =PP3V3_S0_MXM 83 210 R8501
RSVD0 10
88 215
1
100K 2
96 79 MXM_LVDS_B_DATA_N<1> 187 LVDS_UTX1* RSVD1 159 TP_MXM_N_TDO NOSTUFF 77 MXM_DETECT_R
89 216
96 79 MXM LVDS B DATA P<1> 189 LVDS_UTX1 RSVD2 12 R85791 MF-LF 5% 1/16W
SYSTEM MANAGEMENT
94 221 402
RSVD3 161 TP_MXM_N_TDI 4.7K
96 79 MXM_LVDS_B_DATA_N<2> 181 LVDS_UTX2* 5% 95 222
RSVD4 163 TP_MXM_N_TCK 1/16W
96 79 MXM_LVDS_B_DATA_P<2> 183 LVDS_UTX2 MF-LF 100 228
RSVD5 165 TP_MXM_N_TMS 402 2
101 244
96 79 MXM_LVDS_B_DATA_N<3> 175 LVDS_UTX3* RSVD6 167 TP_MXM_N_TRST_L
106 E3
96 79 MXM_LVDS_B_DATA_P<3> 177 LVDS_UTX3 RSVD7 227 MXM_A_TESTEN
107 250 =PM_MXM_PGOOD_PULLUP 64
RSVD8 229 TP_MXM_A_TRST_L
NOSTUFF 112 251
100 64 PM_MXM_EN 8 PWR_EN RSVD9 231 TP_MXM_A_TDO SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,
POWER/THERMAL
1
100 77 64 PM_MXM_PGOOD 6 PWRGOOD RSVD10 233 TP_MXM_A_TDI R8580 113 256
OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR
4.7K
MANAGEMENT
118 257
47 MXM_PWR_LEVEL 18 PWR_LEVEL RSVD11 235 TP_MXM_A_TMS 5%
1/16W 119 262
RSVD12 237 TP_MXM_A_TCK MF-LF
49 =SMB_MXM_THRM_SCL 34 SMB_CLK 402 2 124 263 R8503
RSVD13 238
49 =SMB_MXM_THRM_SDA 32 SMB_DAT 125 268
2
10K 1
RSVD14 239 100 77 64 PM_MXM_PGOOD
133 269
47 MXM_ALERT_L 22 TH_ALERT* RSVD15 240 MF-LF 5% 1/16W
134 275
47 MXM_OVERT_L 20 TH_OVERT* RSVD16 241 402
139 282
TP MXM TH PWM 24 TH_PWM RSVD17 242
140 283
RSVD18 243
E4
ANALOG DISPLAY
TP_MXM_VGA_DDC_CLK 160 VGA_DDC_CLK RSVD19 245

TP_MXM_VGA_DDC_DAT 158 VGA_DDC_DAT RSVD20 247
RSVD21 249
TP_MXM_VGA_BLUE 172 VGA_BLUE
RSVD22 14
B TP_MXM_VGA_GREEN
TP_MXM_VGA_HSYNC
170
164
VGA_GREEN
VGA_HSYNC
RSVD23 16 B
PRSNT_L* 281 MXM DETECT L 77
TP_MXM_VGA_RED 168 VGA_RED
PRSNT_R* 2 MXM DETECT R 77
TP_MXM_VGA_VSYNC 162 VGA_VSYNC
WAKE* 4 TP_MXM_WAKE_L

PAGE TITLE
MXM I/O
DRAWING NUMBER SIZE

REVISION
R
10.1.0
85 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MXM TX CAPS MXM RX CAPS

93 9 PEG R2D C P<0> MXM C8600 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<15> 76 93 MXM C8632 0.1UF 1
IN OUT
93 76 IN
MXM PCIE D2R P<15> 2 10% 16V X5R 402 PEG D2R N<0> OUT 9 93
93 9
PEG R2D C N<0> MXM C8601 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D N<15> 76 93 MXM C8633 0.1UF 1
MXM PCIE D2R N<15> PEG D2R P<0>
D
IN OUT
93 76 IN
2 10% 16V X5R 402
OUT 9 93
D
93 9 IN
PEG R2D C N<1> MXM C8602 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<14> OUT 76 93 93 76 IN
MXM PCIE D2R P<14> MXM C8634 0.1UF 1 2 10% 16V X5R 402 PEG D2R N<1> OUT 9 93
PEG R2D C P<1> MXM C8603 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D N<14> MXM PCIE D2R N<14> MXM C8635 0.1UF 1 2 10% 16V X5R 402 PEG D2R P<1>
93 9 IN OUT 76 93 93 76 IN OUT 9 93
93 9 IN
PEG R2D C N<2> MXM C8604 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<13> OUT 76 93 93 76 IN
93 9 IN
PEG_R2D_C_P<2> MXM C8605 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<13> OUT 76 93 93 76 IN
MXM_PCIE_D2R_N<13> MXM C8637 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<2> OUT 9 93
93 9 IN
PEG R2D C P<3> MXM C8606 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<12> OUT 76 93 93 76 IN
93 9 IN
PEG_R2D_C_N<3> MXM C8607 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<12> OUT 76 93 93 76 IN
93 9
PEG R2D C N<4> MXM C8608 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<11> 76 93 MXM C8640 0.1UF 1
IN OUT
93 76 IN
MXM_PCIE_D2R_P<11> 2 10% 16V X5R 402 PEG_D2R_N<4> OUT 9 93
93 9
PEG R2D C P<4> MXM C8609 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D N<11> 76 93 MXM C8641 0.1UF 1
IN OUT
93 76 IN
MXM PCIE D2R N<11> 2 10% 16V X5R 402 PEG D2R P<4> OUT 9 93
93 9 PEG R2D C N<5> MXM C8610 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<10> 76 93 MXM C8642 0.1UF 1
IN OUT
93 76 IN
MXM_PCIE_D2R_P<10> 2 10% 16V X5R 402 PEG_D2R_N<5> OUT 9 93
PEG R2D C P<5> MXM C8611 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D N<10>
93 9 IN OUT 76 93
93 76 IN
MXM PCIE D2R N<10> MXM C8643 0.1UF 1 2 10% 16V X5R 402 PEG D2R P<5> OUT 9 93
93 9 IN
PEG R2D C P<6> MXM C8612 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<9> OUT 76 93
C MXM C8613 0.1UF 1 MXM PCIE D2R P<9> MXM C8644 0.1UF 1 2 10% 16V X5R 402 PEG D2R N<6> C
93 9 IN
PEG R2D C N<6> 2 10% 16V X5R 402 MXM PCIE R2D N<9> OUT 76 93
93 76 IN OUT 9 93
93 76 IN
93 9 IN
PEG R2D C N<7> MXM C8614 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<8> OUT 76 93
MXM PCIE D2R P<8> MXM C8646 0.1UF 1 2 10% 16V X5R 402 PEG D2R N<7>
93 9 IN
PEG R2D C P<7> MXM C8615 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D N<8> OUT 76 93
93 76 IN OUT 9 93
93 76 IN
93 9 IN
PEG R2D C N<8> MXM C8617 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D N<7> MXM PCIE D2R P<7> MXM C8648 0.1UF 1 2 10% 16V X5R 402 PEG D2R N<8>
93 9 IN OUT 76 93 93 76 IN OUT 9 93
93 76 IN
93 9 IN
93 9 IN OUT 76 93 93 76 IN OUT 9 93
93 76 IN
93 9 IN
PEG_R2D_C_N<10> MXM C8620 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<5> OUT 76 93
PEG R2D C P<10> MXM C8621 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D N<5>
93 9 IN OUT 76 93
93 76 IN
93 76 IN
93 9 IN
PEG R2D C N<11> MXM C8622 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<4> OUT 76 93
PEG R2D C P<11> MXM C8623 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D N<4> MXM PCIE D2R P<4> MXM C8654 0.1UF 1 2 10% 16V X5R 402 PEG D2R N<11>
93 9 IN OUT 76 93 93 76 IN OUT 9 93
93 76 IN
B 93 9 IN
B
93 9 IN OUT 76 93 93 76 IN OUT 9 93
MXM PCIE D2R N<3> MXM C8657 0.1UF 1 2 10% 16V X5R 402 PEG D2R P<12>
93 76 IN OUT 9 93
93 9
PEG R2D C N<13> MXM C8626 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D P<2> 76 93 MXM C8658 0.1UF 1
IN OUT
93 76 IN
MXM PCIE D2R P<2> 2 10% 16V X5R 402 PEG D2R P<13> OUT 9 93
93 9
IN OUT
93 76 IN
MXM PCIE D2R N<2> 2 10% 16V X5R 402 PEG D2R N<13> OUT 9 93
PEG_R2D_C_P<14> MXM C8628 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<1>

93 9 IN OUT 76 93
93 76 IN
MXM PCIE D2R P<1> MXM C8662 0.1UF 1 2 10% 16V X5R 402 PEG D2R P<14> OUT 9 93
PEG R2D C N<14> MXM C8629 0.1UF 1 2 10% 16V X5R 402 MXM PCIE R2D N<1>
93 9 IN OUT 76 93
93 76 IN
MXM PCIE D2R N<1> MXM C8663 0.1UF 1 2 10% 16V X5R 402 PEG D2R N<14> OUT 9 93
93 9 PEG_R2D_C_N<15> MXM C8630 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<0> 76 93 MXM C8660 0.1UF 1
IN OUT
93 76 IN
MXM PCIE D2R P<0> 2 10% 16V X5R 402 PEG D2R N<15> OUT 9 93
93 9
IN OUT
93 76 IN
MXM PCIE D2R N<0> 2 10% 16V X5R 402 PEG D2R P<15> OUT 9 93
A SYNC MASTER=K62 SYNC DATE=N/A A

PAGE TITLE
MXM PCIE CAPS

DRAWING NUMBER SIZE

REVISION
R
10.1.0
86 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes

(NONE)
D BOM options provided by this page:

(NONE)
D
T29 CONN POWER AND CONTROL ALIAS
MXM ALIAS 6 =PP3V3_SW_DPAPWR PP3V3_SW_DPAPWR 85 98
76 MXM_DP_A_ML_P<0..3> DP_EXTA_ML C_P<0..3> 85 96

76 MXM_DP_A_ML_N<0..3> DP_EXTA_ML_C_N<0..3> 85 96 6 =PP3V3_SW_DPBPWR PP3V3_SW_DPBPWR 87 98
76 MXM_DP_A_AUX_P DP_EXTA_AUXCH_C_P 79 85 96
MAKE_BASE=TRUE NO_TEST=TRUE 100 36 33 19 PCIE_WAKE_L =T29_WAKE_L 85 87
76 MXM DP A AUX N DP EXTA AUXCH C N 79 85 96
96 76 MXM_DP_B_ML_P<0..3> DP_T29SNK1_ML C_P<0..3> 89 99
76 MXM DP A HPD DP EXTA HPD 85 MAKE_BASE=TRUE NO_TEST=TRUE
96 76 MXM_DP_B_ML_N<0..3> DP_T29SNK1_ML C_N<0..3> 89 99
96 76 MXM DP B AUX P DP T29SNK1 AUXCH C P 89 99
77 MXM_DP_E_ML_P<0..3> DP_EXTB_ML_C_P<0..3> 87 96 MAKE_BASE=TRUE NO_TEST=TRUE
96 76 MXM_DP_B_AUX_N DP_T29SNK1_AUXCH_C_N 89 99
77 MXM_DP_E_ML_N<0..3> DP_EXTB_ML_C_N<0..3> 87 96 MAKE_BASE=TRUE NO_TEST=TRUE
76 MXM_DP_B_HPD DP_T29SNK1_HPD 89
77 MXM_DP_E_AUX_P DP_EXTB_AUXCH C_P 79 87 96 MAKE_BASE=TRUE NO_TEST=TRUE
77 MXM DP E AUX N DP EXTB AUXCH C N 79 87 96
96 76 MXM_DP_D_ML_P<0..3> DP_T29SNK0_ML C_P<0..3> 89 99
77 MXM_DP_E_HPD DP_EXTB_HPD 87
MAKE_BASE=TRUE NO_TEST=TRUE 96 76 MXM DP D ML N<0..3> DP T29SNK0 ML C N<0..3> 89 99
96 76 MXM DP D AUX P DP T29SNK0 AUXCH C P 89 99

C 96 76 MXM_DP_D_AUX_N DP_T29SNK0_AUXCH_C_N
89 99 C
DDC/AUX ALIAS 76 MXM DP D HPD DP T29SNK0 HPD
89
96 85 79 DP_EXTA_AUXCH_C_P DP_EXTA_DDC_CLK 85
96 85 79
MAKE_BASE=TRUE
DP_EXTA_AUXCH_C_N DP_EXTA_DDC_DATA 85
UNUSED MXM CONTROL SIGNALS
MAKE_BASE=TRUE
96 87 79 DP_EXTB_AUXCH_C_P DP_EXTB_DDC_CLK 87
MAKE_BASE=TRUE 77 MXM_PNL_BL_EN NC_MXM_PNL_BL EN
96 87 79 DP_EXTB_AUXCH_C_N DP_EXTB_DDC_DATA 87 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
77 MXM_PNL_PWR_EN NC_MXM_PNL_PWR_EN
NO_TEST T29 & DP DC BIAS
I81
T29_A BIAS_R2D_P0 85 86 I99
T29_B BIAS_R2D_P2 87 88
NO_TEST=TRUE NO_TEST=TRUE
I82
T29_A BIAS_R2D_N0 85 86 I100
T29_B BIAS_R2D_N2 87 88
I83
T29_A_BIAS_R2D_P1 85 86 I101
T29_B_BIAS_R2D_P3 87 88
I84
T29_A_BIAS_R2D_N1 85 86 I102
T29_B_BIAS_R2D_N3 87 88
I93
T29_A_BIAS 83 85 86 I103 T29_B_BIAS 83 87 88 99
NO_TEST=TRUE 99 NO_TEST=TRUE
I109
T29_A_BIAS_P1 86 I110
T29_B_BIAS_P3 88
I111 T29_A_BIAS_N1 86 I112 T29_B_BIAS_N3 88
I89
DP_A_BIAS_P_0 85 86 I104
DP_B_BIAS_P_0 87 88
I90
DP_A_BIAS_N_0 85 86 I105
DP_B BIAS N_0 87 88
I92
DP_A_BIAS_P_2 85 86 I107
DP_B BIAS P_2 87 88
B I91
I94
DP_A_BIAS_N 2
NO_TEST=TRUE
DP_A_BIAS
85 86
85 99
I106
I108
DP_B_BIAS_N_2
NO_TEST=TRUE
DP_B_BIAS
87 88
87
B
Unused MXM Interfaces

96 77 MXM_LVDS_A_DATA_N<3> NC_MXM_LVDS_A DATA_N<3>
96 77 MXM_LVDS_A_DATA_P<3> NC_MXM_LVDS_A DATA_P<3>
96 77 MXM LVDS B CLK N NC MXM LVDS B CLK N
96 77 MXM_LVDS_B_CLK_P NC_MXM_LVDS_B CLK_P
96 77 MXM_LVDS_B_DATA_N<0> NC_MXM_LVDS_B_DATA_N<0>
96 77 MXM_LVDS_B_DATA_P<0> NC_MXM_LVDS_B_DATA_P<0>
96 77 MXM_LVDS_B_DATA_N<1> NC_MXM_LVDS_B DATA_N<1>
96 77 MXM_LVDS_B_DATA_P<1> NC_MXM_LVDS_B_DATA_P<1>
96 77 MXM LVDS B DATA P<2> NC MXM LVDS B DATA P<2>
A 96 77 MXM_LVDS_B_DATA_P<3> NC_MXM_LVDS_B_DATA_P<3>
PAGE TITLE
DP ALIAS
DRAWING NUMBER SIZE

REVISION
R
10.1.0
87 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GreenCLK Implementation Notes: System RTC Power Source & 32kHz / 25MHz Clock Generator
VBAT: Alias as appropriate (see note below & Desktop Example)
+V3.3A: Alias as appropriate (see note below)
VDD_25M: 3.3V matching ’highest’ VDDIO power state (ENET)
VDDIO_25M_A: SB power rail for XTAL circuit.

VDDIO_25M_B: Ethernet power rail for XTAL circuit.
VDDIO_25M_C: T29 power rail for XTAL circuit.
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.
D For Cougar Point Desktop: VDDIO = VCCVRM

For Cougar Point Mobile: VDDIO = VCCVRM
(1.8V), Vclk = 1.1V Max, Divider: 604 / 1000
(1.5V), Vclk = 1.1V Max, Divider: 332 / 1000
D
For Caesar-IV (BCM57765): VDDIO = XTALVDDH (3.3V), Vclk = 3.3V Max. No Divider Necessary
6 =PP3V3 S3 SYSCLK
Coin-Cell & G3Hot: 3.42V G3Hot

Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5
C 80 37 36 =PP3V3_S3_ENET_PHY_FET
C
R8812 1 0
80 37 36 =PP3V3_S3_ENET_PHY_FET 2 98 PPVDDIO_25M_B
5% MIN NECK WIDTH=0 2 mm
1/16W VOLTAGE=3 3V
MF LF 98 PPVBAT_G3_SYSCLK_R
402 MIN LINE WIDTH=0 3 mm
R8806 0 NOSTUFF MIN NECK WIDTH=0 2 mm
24 18 6 =PP1V05_S0_PCH 1 2 VOLTAGE=3 3V
1
5% R8808
1/16W 10K
MF LF 5%
402 1/16W
MF-LF
R8807 1 0 2 402
80 24 6 =PP1V8R1V5_S0_PCH_VCCVRM 2 98 PPVDDIO_25M_A
1/16W VOLTAGE=1 05V No bypass necessary R8825
MF LF
402 40.2 (1.1V)
1 2 PCH_CLK25M_XTALIN OUT 18 27 94
+3.42V 13
1%
VDD_25M 5
+V3.3A 2
1/16W
1
T29 MF LF
R8826
402
R8810 1 0 VBAT and +V3.3A are 140
90 89 81 6 =PP3V3_T29_RTR 2 98 PPVDDIO_25M_C 1%
internally ORed to 1/16W
5% T29 MF LF
1/16W create VDD_RTC_OUT. 402
MF LF
402
C8824 1
C8822 1
C8820 1 1
C8802 2
0 NOSTUFF
0.1UF
20%
0.1UF
20%
0.1UF
20%
1UF
10%
U8800 +V3.3A should be first
80 24 6 =PP1V8R1V5 S0 PCH VCCVRM R8809 1 2 10V
CERM 2
10V
CERM 2
10V
CERM 2 2
6 3V
CERM SLG3NB148V available ~3.3V power
402 402 402 402 TQFN to reduce VBAT draw.
1/16W VOLTAGE=3 3V CRITICAL
MF LF
402 11 VDDIO_25M_A 32KHZ_A 12 TP_SYSCLK_CLK32K_RTC
6 VDDIO_25M_B
14 9 R8843 T29
C8805 VDDIO_25M_C 25MHZ_A 99 SYSCLK_CLK25M_SB
R8815 33 R8845
B 2
12PF
1 99 SYSCLK_CLK25M_X2 1
0
2 99 SYSCLK_CLK25M_X2_R 3 X2
25MHZ_B
25MHZ_C
8
15
99
99
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_T29_CLK
1
5%
2
1
47
2
ENET_CLK25M_XTALI_OSC
SYSCLK_CLK25M_T29 (1 8V) OUT 89 99
(3 3V) OUT 36 99
B
1/16W
5% NOSTUFF 4 X1 For SB RTC Power MF LF 5%
5% 1/16W 402 1/16W
50V
CRITICAL MF LF 1
VDD_RTC_OUT 1 TP_PPVRTC_G3_OUT MF LF
R8816
1
CERM 402 402

402 NC Y8805 1M
2
5% GND THRM
NC 25.000MHZ-12PF-20PPM 1/16W
PAD 1
C8810
4
10
16
17
C8806 MF LF
3
1UF
7
SM 3 2X2 5MM 402
2 10%
12PF 6 3V
2 CERM
1 2 99 SYSCLK_CLK25M_X1 402
5%
NOTE: 30 PPM crystal required
50V
CERM
402
A SYNC_MASTER=K62_AARON SYNC_DATE=N/A A
PAGE TITLE
GREEN CLOCK
DRAWING NUMBER SIZE

REVISION
R
10.1.0
88 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP3V3_T29_P3V3T29FET (3.3V FET Input) Supervisor & CLKREQ# Isolation
- =PP3V3_T29_FET (3.3V FET Output)
- =PP3V3_S0_T29PWRCTL 6 =PP3V3_S0_T29PWRCTL
- =PP1V05_T29_P1V05T29FET (1.05V FET Input)
- =PP1V05_T29_FET (1.05V FET Output)
T29 =PP3V3 T29 RTR 6 80 81 89 90
1
Signal aliases required by this page: R8906 1 C8900
10K 0.1UF
- =T29_CLKREQ_L 5%
10%
1/16W
- T29_RESET_L MF LF 2
25V
X5R
D BOM options provided by this page:

402
2 402 T29
CRITICAL 1
T29
R8907
D
1
(NONE) VDD 100K
Platform (PCIe) Reset 5%
U8900 1/16W
MF LF
100 27 T29 RESET L 402
IN SLG4AP016V 2
TDFN =PP1V05_T29 6
=PP3V3_T29 RTR 6 80 81 89 90
R8903 2 + SENSE 2
10K - 0.7V
T29 CLKREQ# ISOLATION T29 5%
1/16W
T29 R8904 2 Open-Drain GPIO
MF LF
402 DLY
10K 1
Q8950 5% RESET* 4 T29_RESET_RTR_L OUT 89 100
G 1
SSM3K15FV 1/16W 94 21 15 IN T29_SW_RESET_L 3 MR*
MF LF DLY = 60 ms +/- 20%
SOD-VESM-HF 402
1
6 EN
=T29_CLKREQ_L 89
S
T29 CLKREQ L T29_CLKREQ_FET_L 8 OUT IN
94 21 15 OUT (OD) IN 7 T29_CLKREQ_ISOL_L
2
MAKE BASE=TRUE
Pull-up provided by SB page. THRM
GND PAD
9
3.3V T29 Switch
U8910
C 6 =PP3V3_S0_P3V3T29FET
A2
TPS22924
CSP
A1
PP3V3_T29_FET 6 C
Max Current = 1.7A (85C)
B2 VIN VOUT B1
T29
T29 CRITICAL U8910
C8910 1 C2 ON
1UF GND Part TPS22924C
10%
C1
6 3V
CERM 2 Type Load Switch
402
R(on) 18 mOhm Typ
50 mOhm Max
Max Output: 2A
64 63 6 =PP12V S0 PWRCTL
T29
1 C8930
0.1UF
10%
CRITICAL 2 16V
X5R
1.05V T29 Switch Q8930 402
BSZ035N03MSG
P-TSDSON-8
T29 PP1V05_T29_FET 6
=PP1V05 S0 P1V05T29FET
3
6
2
D
S
1
=PP3V3 S0 PWRCTL
G
74 64 63 6
B B
P1V05_S0_T29_EN 4
T29
1
1
R8930 VCC
10K
5%
1/16W
MF-LF
U8930
2 402
SLG5AP001
5D TDFN
ON 2
7G CRITICAL S6
8 PG T29
PM_PGOOD_P1V05_S0_T29_FET NC 3
THRM
PAD GND
4
100 18 IN T29_PWR_EN
A SYNC_MASTER=K62_AARON SYNC_DATE=(MASTER) A
PAGE TITLE
T29 POWER
DRAWING NUMBER SIZE

REVISION
R
10.1.0
89 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP12V_S0_LCD
- =PP3V3_S0_VIDEO

INTERNAL DP INTERFACE INTERNAL DP POWER
(NONE)
BOM options provided by this page:
D IG, MXM, MLB_PNL_PWR, LCD_PNL_PWR CRITICAL

J9002
518S0778 D
CRITICAL
CABLINE-CA
F-RT-SM J9001
R9050 53780-8606
M-RT-SM
SMB_BLC_TCON_SDA 1
0 2
31
7
97 49 6 OUT
5%
1/16W 1 518S0787
I2C MASTER ON TCON 1
R9051 MF-LF
402 97 I2C_TCON_SDA 2
SMB_BLC_TCON_SCL 1
0 2 97 I2C_TCON_SCL 3
2
97 49 6 BI 3
5% 4
1/16W I2C SLAVE ON TCON 4
MF-LF NOSTUFF SMB_DP_TCON_SLA_SDA 5
NOSTUFF 49 IN 5
402 6
1 C9010 1 C9011 49 BI SMB_DP_TCON_SLA_SCL 6
47PF 47PF 7
5% 5%
50V 50V 8
2 CERM 2 CERM 100 84 OUT DP INT SPDIF AUDIO 8
402 402 TP_OPTION1 9
100 84 DP_INTPNL_HPD 10
OUT
11
12
L9000
96 84 BI DP_INTPNL_AUX_N FERR-250-OHM
96 84 DP_INTPNL_AUX_P 13 6 =PP12V S0 LCD
BI 1 2 98 PP12V_LCD
14 VOLTAGE=12V
SM MIN_LINE_WIDTH=0.5MM
DP INTPNL ML P<0> 15 MIN_NECK_WIDTH=0.25MM 1 C9020 1 C9001
96 84 IN NO_TEST
96 84 DP INTPNL ML N<0> NO_TEST 16 10UF 0.001uF
IN 10% 20%
17 16V 50V
2 X5R CERM 2 CERM
18 0805 402
96 84 IN DP_INTPNL_ML_P<1> NO_TEST
96 84 DP_INTPNL_ML_N<1> NO_TEST 19
IN
20
DP_INTPNL_ML_P<2> 21
C 96 84
96 84
IN
IN DP_INTPNL_ML_N<2>
NO_TEST
NO_TEST 22 C
23
96 84 DP INTPNL ML P<3> NO_TEST 24

IN
96 84 DP_INTPNL_ML_N<3> NO_TEST 25
IN
26
100 82 VIDEO_ON 27
OUT
R9010 TP_OPTION2 28
0 29
100 6 VSYNC_DP_CONN 100 1 2 VSYNC_DP
5% 30
1/10W
MF LF
603
33
34
35
36
37
38
39
40
41
32
B B
BACKLIGHT CONTROL SUPPORT

guarantee backlight is
only on when Panel has valid video
82 6 =PP3V3_S0_DP
82 6 =PP3V3 S0 DP
1 C9006
0.1UF 5 VIDEO_ON_L
OUT
20%
10V
1 C9005
2 CERM 22UF
402 used by diag LED 20%
6 3V
2 CERM
805
5 U9000 5 U9000
74AUP2G14GM
SOT886
D9000
SOT23
74AUP2G14GM
SOT886 R9011
VIDEO ON 1 6 1 3 VIDEO ON L DLY 3 4 LCD BKL ON DLY 1
47 2 BL EN OUT
100 82 6 100
5%
BAT54XG 1/16W
MF-LF
402
A 2
R9009
19.1K2
2
1 PAGE TITLE
1%
1/16W
Display: Int DP Connector
MF-LF DRAWING NUMBER SIZE
402
REVISION
R
10.1.0
90 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3V3(DP)/2V9(T29) PORTA SUPPLY 12V T29 PORTA SUPPLY

D9101
PP3V3R2V9_DPAPWR_D
POWERDI-123
1 2
PP3V3R12V_SW_DPAPWR 83 86
MIN LINE WIDTH=0 6MM VOLTAGE=12V
=PP5V_S3_P3V3R2V9_REG_A MIN NECK WIDTH=0 2MM DFLS260 MIN NECK WIDTH=0 20 MM NOSTUFF
6 VOLTAGE=3 3V
12 VOLTS NEED TO UPDATE TABLE BELOW LATER
1 C9122 1
R9121 1 C9124 1 C9125 1
R9150 Nominal Min Max
10UF
10%
20K 10UF
10%
10UF
10%
2.2K =PP12V S5 T29 A 12 WATTS MAX PER PORT IFLT 885mA 876mA 894mA (*)
1/16W 5% 1/10W 5% 6
D 1 C9120
10UF CRITICAL
2 16V
X5R-CERM
0805
2
MF-LF 402
C9123
1
1
R9124
2 16V
X5R-CERM
0805
2 16V
X5R-CERM
0805
2
MF-LF 603
ILIM
TFLT
935mA 925mA 944mA (*)
18.3ms 13.4ms 26.7ms
D
10% 330PF
11.5K
16V
2 X5R-CERM U9101 10% 50V 2
<RA> 1/16W 1%
MF-LF 402
T29 TSD 470ms 235ms 724ms
0805 402 CERM
ISL80101A R9116 1 (*) U9410 tolerance unknown T29
9
DFN
1
2 15K D9105
DSN2
5%
1/16W 1 CRITICAL
10 VIN VOUT 2 MF LF 10 98 PP3V3R12V SW DPAPWR D 1 2 PP3V3R12V_SW_DPAPWR 83 86
402 2 T29 MIN LINE WIDTH=0 38 MM MIN LINE WIDTH=0 38 MM
T29_DP_PORTA_PWR_EN_REG 3V3R2V9_DPAPWR_ADJ 2 T29 11 T29 MIN NECK WIDTH=0 20 MM MIN NECK WIDTH=0 20 MM
7 ENABLE ADJ 3
100 98 3 VIN VOUT
100 83
12
VOLTAGE=12V NSR20F20NXT5G VOLTAGE=12V
3V3R2V9_SS_A 6 SS C9110 1
4
1
C9111
PG 4
=PP3V3_S3_P3V3R2V9_REG_A 0.1UF 0.1UF
80101A1_ISET
6
8 ISET
1
R9123 10%
50V
2
U9110 2
10%
50V
THRM 2.05K X7R SN1010017 X7R
GND PAD 603 1 QFN 603 1
<RB2> 1/16W 1%
1 16 EN* FLT* 15
R9122 DPAPWRSW HVEN L R TP DPAPWRSW FLT L
5
11
MF-LF 402 NOSTUFF 100
(IPU Weak!)
1 C9121 100K 2
1 6 RTRY* ILIM 7
0.022UF
10%
1/16W 5%
MF-LF 402 R9125 T29 100 DPAPWRSW_ILIM
16V 15.0K CRITICAL 9 CT
2 CERM-X5R 1
R9130 <RB1> 1/16W 1% 100 DPAPWRSW_CT IFLT 8 100 DPAPWRSW_IFLT
402 25.5K PM_PGOOD_P3V3_2V9_A 2 MF-LF 402 D9103 NOSTUFF T29 GND THRM T29 T29
1/16W 1% 2 MMBZ5227BLT1H R9117 1
1
R9112 PAD
R9110 1
1
3
MF-LF 402 SOT23 R9111
5
13
14
17
100 13K 0
DP_A_PWRDWN_INV
2 5% 5% 100K 174K
1/16W 1/16W 1% 1%
=PP3V3_S3_PWRCTL
VO=0.5*(1+ RA/RB) MF LF
402
2 2
MF LF
402
1/16W
MF LF
402 2
1/16W
MF LF
2 402
1
83 74 64 6
1
NOSTUFF VO=3.304V T29
Q9115 <CT> <RFLT> <RLIM>
R9126 SSM3K15FV D 3
=PP3V3_S5_P3V3R2V9_A 10K SOD VESM HF IFLT = 200K / RFLT = 2A

6 5%
1/16W
MF-LF ILIM = 201K / RLIM = 1.155A.
1 C9150 2 402
0.1UF
3 TFLT = CCT * 38900
C 10%
16V
2 X5R
DP_A_PWRDWN_FET_R D
NOSTUFF
Q9120
2N7002DW-X-G 100 85 T29 A HV EN
1 G S 2
TSD = CCT * 100000 C
402 6 IN
SOT 363
5 G S
NOSTUFF
D
Q9120
5 MC74VHC1G08 2N7002DW-X-G
94 T29_DP_PORTA_PWR_EN 1 4
20
25
SOT23-5-HF T29_A_BIAS 2 G S
SOT 363
100 4 T29_DP_PORTA_PWR_EN_REG 99 86 85 79
83 PM_PGOOD_P5V_S3_REG 2
U9120 83 100
LO: 3V3 FOR DP
63 HI: 2V9 FOR T29 1
71
100 2V9 MEASURED AT CDR
3
3V3(DP)/2V9(T29) PORTB SUPPLY 12V T29 PORTB SUPPLY

D9131
POWERDI-123 PP3V3R12V_SW_DPBPWR 83 88
PP3V3R2V9_DPBPWR_D 1 2
NET_PHYSICAL_TYPE=POWER MIN LINE WIDTH=0 38 MM
MIN LINE WIDTH=0 6MM VOLTAGE=12V 12 VOLTS
6
=PP5V_S3_P3V3R2V9_REG_B VOLTAGE=3 3V
DFLS260 MIN NECK WIDTH=0 20 MM
NOSTUFF Nominal Min Max
=PP12V S5 T29 B 12 WATTS MAX PER PORT
1 C9132 1
R9131 1 C9134 1 C9135 1
R9151 6 IFLT 885mA 876mA 894mA (*)
10UF 20K 10UF 10UF 2.2K ILIM 935mA 925mA 944mA (*)
10% 1/16W 5% 10% 10% 1/10W 5%
2 16V MF-LF 402 1 2 16V 2 16V MF-LF 603 TFLT 18.3ms 13.4ms 26.7ms
1 C9130 X5R-CERM
0805 C9133 1
X5R-CERM
0805
X5R-CERM
0805
10UF CRITICAL R9134 TSD 470ms 235ms 724ms
B 10%
16V
U9131
2 330PF
10% 50V 2
11.5K
2
(*) U9410 tolerance unknown T29 B
2 X5R-CERM
0805 402 CERM
<RA> 1/16W 1%
MF-LF 402 T29 D9106
ISL80101A 1 (IPU Weak!)
1
DSN2
DFN 2 R9146 CRITICAL 10 PP3V3R12V SW DPBPWR D 1 2 PP3V3R12V_SW_DPBPWR 83 88
9 1 15K 2 MIN LINE WIDTH=0 38 MM MIN LINE WIDTH=0 38 MM
T29 11
10 VIN VOUT 2 5% T29 VIN VOUT MIN NECK WIDTH=0 20 MM MIN NECK WIDTH=0 20 MM
1/16W 3 T29 VOLTAGE=12V NSR20F20NXT5G VOLTAGE=12V
MF LF C9140 1 12 1
C9141
T29_DP_PORTB_PWR_EN_REG 3V3R2V9_DPBPWR_ADJ 402 4
83
7 ENABLE ADJ 3
100
2 0.1UF 0.1UF
3V3R2V9_SS_B 6 SS
10%
50V U9140 10%
50V
=PP3V3_S3_P3V3R2V9_REG_B 2 2
PG 4 6
1
X7R SN1010017 X7R
R9133 603 1 QFN 603 1

80101A2_ISET
8 ISET
THRM
PAD
2.05K 100 DPBPWRSW_HVEN_L_R 16 EN* FLT* 15 TP_DPBPWRSW_FLT_L
GND
<RB2> 1/16W 1%
(IPU Weak!)
1 C9131 1
R9132 6 RTRY* ILIM 7
5
11
MF-LF 402 100 DPBPWRSW_ILIM

0.022UF 2 NOSTUFF
10%
100K 1 T29
16V
2 CERM-X5R
1/16W 5%
MF-LF 402
R9135 CRITICAL
100 DPBPWRSW CT 9 CT IFLT 8 100 DPBPWRSW IFLT
15.0K T29 GND THRM
402 1
R9129 2 <RB1> 1/16W 1% D9104 NOSTUFF 1
PAD T29 T29
R9140 1
1
25.5K PM_PGOOD_P3V3_2V9_B MF-LF 402
MMBZ5227BLT1H R9142 R9141
5
13
14
17
R9147 1 0 100K 174K
3
1/16W 1% 2 SOT23
MF-LF 402 13K 5% 1% 1%
100 5% 1/16W 1/16W 1/16W
DP B PWRDWN INV
2 1/16W MF LF MF LF MF LF
T29 MF LF
2 402 402 2 2 402
402 2
Q9145 <CT> <RFLT> <RLIM>
1
=PP3V3_S3_PWRCTL SSM3K15FV D 3
83 74 64 6
NOSTUFF SOD VESM HF
1
R9136
10K
5%
1/16W
MF-LF 1 G S 2
2 402
=PP3V3_S5_P3V3R2V9_B 6
3
100 87 T29 B HV EN
NOSTUFF IN
DP_B_PWRDWN FET R D
A 1 C9151 6
Q9130
2N7002DW-X-G
SOT 363
0.1UF NOSTUFF 5 G S PAGE TITLE
10%
2 16V
X5R
402
D
Q9130
2N7002DW-X-G 4
2V9/3V3/12V POWER SWITCH
T29_B_BIAS 2 G S
SOT 363 DRAWING NUMBER SIZE
99 88 87 79
LO: 3V3 FOR DP Apple Inc. 051-8442 D

5 MC74VHC1G08 HI: 2V9 FOR T29
T29_DP_PORTB_PWR_EN 1 SOT23-5-HF
1 REVISION
94 25 20 2V9 MEASURED AT CDR R
4 T29_DP_PORTB_PWR_EN_REG 10.1.0
PM_PGOOD_P5V_S3_REG 2
U9130 83
83 71 63
91 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R9223
0 PP1V5 S0 DP R
6 =PP1V5 S0 DP 2 1 84 98
5%
VOLTAGE=1.5V
1/16W
NOSTUFF MIN_LINE_WIDTH=0.4MM
MF-LF
1
C9273 MIN_NECK_WIDTH=0.2MM
402 0.1uF
10% =PP3V3_S0_INTDPMUX 6 84
16V
2 X5R
402
A2
J4
C9268 1 1
C9269 1
C9209
0.1uF 0.1uF 1UF
96 76 MXM DP C ML P<0> B4 DIN1_0+ VDD CRITICAL 10% 10% 10%
IN 16V 16V 10V
2 2
96 76 MXM_DP_C_ML_N<0> A4 DIN1_0- X5R X5R 2 X5R
IN
D PP1V5_S0_DP_R 96 76 IN MXM_DP_C_ML_P<1> B5 DIN1_1+ U9200

402 402 402 1
C9201 1 2
10% 16V
D
98 84 0.1uF
DIN1_1- CBTL06142CEEG
X5R 402
96 76 MXM DP C ML N<1> A5
IN C9202 1 2
TFBGA
10% 16V
R9240 1 1
R9242 96 76 IN MXM_DP_C_ML_P<2> B6 DIN1_2+ 0.1uF X5R 402
470K 470K 96 76 MXM_DP_C_ML_N<2> A6 DIN1_2-
5% 5% IN
1/16W 1/16W
A8 B2
C9203 1 2
MF LF MF LF 96 76 IN MXM_DP_C_ML_P<3> DIN1_3+ DOUT_0+ 96 DP_INTCONN_ML_C_P<0> 10% 16V DP_INTPNL_ML_P<0> OUT 82 96
402
2 2
402 0.1uF X5R 402
96 76 MXM_DP_C_ML_N<3> A9 DIN1_3- DOUT_0- B1 96 DP_INTCONN_ML_C_N<0> DP_INTPNL_ML_N<0> 82 96
IN C9204 1 2 OUT
96 76 BI MXM_DP_C_AUX_P C9213 1 2
H9 10% 16V
10% 16V 96 MXM_DP_C_AUX_R_P DAUX1+ 0.1uF X5R 402
0.1uF X5R 402
96 MXM_DP_C_AUX_R_N
J9 DAUX1-
96 76 MXM_DP_C_AUX_N C9214 1 2
DOUT_1+ D2 96 DP_INTCONN_ML_C_P<1> DP_INTPNL_ML_P<1> 82 96
BI C9205 1 2 OUT
10% 16V
0.1uF X5R 402
H8 DDC_CLK1 DOUT_1- D1 96 DP_INTCONN_ML_C_N<1> 10% 16V DP_INTPNL_ML_N<1>
NC 0.1uF X5R 402
OUT 82 96
J8 DDC_DAT1
NC C9206 1 2
10% 16V
76 MXM_DP_C_HPD J2 HPD_1 0.1uF X5R 402
OUT E2 DP_INTCONN_ML_C_P<2> DP_INTPNL_ML_P<2>
DOUT_2+ 96
OUT 82 96
DOUT_2- E1 96 DP_INTCONN_ML_C_N<2> DP_INTPNL_ML_N<2> 82 96

C9207 1 2 OUT
1 DP_T29SRC_ML_C_P<0> B8 DIN2_0+
R9228 99 84 IN 0.1uF
10%
X5R
16V
402
100K 99 84 DP T29SRC ML C N<0> B9 DIN2_0-
IN C9208 1 2
5% F2
PP1V5_S0_DP_R 1/16W
D8 DOUT_3+ 96 DP_INTCONN_ML_C_P<3> 10% 16V DP_INTPNL_ML_P<3> OUT 82 96
98 84 MF LF 99 84 IN DP_T29SRC_ML_C_P<1> DIN2_1+ F1
0.1uF X5R 402
402
D9 DOUT_3- 96 DP_INTCONN_ML_C_N<3> DP_INTPNL_ML_N<3> OUT 82 96
T29 T29 2 99 84 IN DP_T29SRC_ML_C_N<1> DIN2_1-
R9244 1 1
R9245 DP_T29SRC_ML_C_P<2> E8 C9210 1 2
470K 470K 99 84 IN DIN2_2+
5% 5% 99 84 IN DP_T29SRC_ML_C_N<2> E9 DIN2_2- AUX+ H2 96 DP_INTCONN_AUXCH_C_P 0.1uF
10%
X5R
16V
402 84 6 =PP3V3_S0_INTDPMUX
1/16W 1/16W
MF LF MF LF AUX- H1 96 DP_INTCONN_AUXCH_C_N C9215 1 2
NOSTUFF
402 2 402 99 84 DP_T29SRC_ML_C_P<3> F8 DIN2_3+ 10% 16V
2 IN
R9248 1
1
T29 0.1uF X5R 402 R9249
99 84 DP_T29SRC_ML_C_N<3> F9 DIN2_3-
IN 470K 100K
99 89 BI DP_T29SRC_AUXCH_C_P C9211 1 2
H6
5% 5%
10% 16V 99 DP_T29SRC_AUXCH_R_C_P DAUX2+ 1/16W 1/16W
C 99 89 BI DP_T29SRC_AUXCH_C_N C9212
0.1uF
1
X5R
2
10% 16V
402
99 DP_T29SRC_AUXCH_R_C_N J6 DAUX2-
HPDIN J1 DP_INTPNL_HPD 82 100
MF LF
402 2
2
MF LF
402
DP_INTPNL_AUX_P 82 96
C
H5 IN BI
0.1uF X5R 402 (For each pair) NC DDC_CLK2
DP_INTPNL_AUX_N BI 82 96
T29 =PP3V3 S0 INTDPMUX J5 DDC_DAT2
84 6
NC NOSTUFF 1 NOSTUFF
DP_T29SRC_HPD H3 R9250 1 R9251
89 OUT HPD_2 R9227 1 100K 470K
100K 5% 5%
1 5% 1/16W
R9220 1/16W
1/16W
MF LF MF LF
10K 94 84 61 18 DP_GPU_T29_SEL A1 GPU_SEL DDC_AUX_SEL C2 MF LF 402 2 2 402
IN 402
5% 2
1/16W B7
MF LF XSD* TST0 G2
402
2
GND
DP INTMUX XSD
B3
C8
G8
H4
H7
1
R9237
10K 84 6 =PP3V3_S0_INTDPMUX
5%
1/16W T29
MF LF
402 2
1
C9272
0.1uF
10%
T29 2
16V
X5R
402
U9210
74LVC1G157
SOT487
5
VCC
100 82 IN
DP INT SPDIF AUDIO 1 I1
MUX Y 4 AUD_SPDIF_IN_CODEC OUT 56 100
100 94 60 IN AUD SPDIF IN 3 I0 SELECTOR
OUTPUT
S GND
2
B 98 84
PP1V5 S0 DP R 94 84 61 18 IN DP GPU T29 SEL

LB # 820-2828-A Schematic Diagram_S

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LB # 820-2828-A Schematic Diagram_S

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8 7 6 5 4 3 2 1

LAST_MODIFIED=Tue Feb 8 15:20:30 2011

D Page Contents Sync Page Contents Sync D

A 100 PM RESETS ENABLES PGOOD CONST

Apple Inc. 051-8442 D

ANALOG VIDEO OUTPUT

DIGITAL VIDEO OUTPUT

DIGITAL VIDEO OUTPUT

SD CARD PCI HDA

System Block Diagram

Apple Inc. 051-8442 D

FireWire Mini PCI-E Conns 10.1.0

PP0V75_S0 THE INFORMATION CONTAINED HEREIN IS THE

BOM Variants COMMON

D 085-1226 PCBA,MLB,DEV,K62 DEVELOPMENT,DEV_GROUP

639-2131 PCBA,MLB,K62,3.1G,4C,PRQ,P1_ODD,NO_DBG K62,3P1GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P1,NO_DBG

639-2130 PCBA,MLB,K62,3.4G,4C,PRQ,P1_ODD,NO_DBG K62,3P4GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P1,NO_DBG

CPU SOCKET & ILM SUB-BOMS 051-8442 1 SCH,MLB,K62 SCH1 K62

511S0071 1 SOCKET,LGA1155,CPU-LF U1000 CRITICAL TYCO_SOCKET

604-1474 1 ASSY,PURCHASED,ILM,TYCO ILM CRITICAL TYCO_SOCKET

511S0073 1 SOCKET,LGA1155,CPU-LF U1000 CRITICAL MOLEX_SOCKET

604-1161 1 ASSY,PURCHASED,ILM,MOLEX ILM CRITICAL MOLEX_SOCKET

B K62 ALTERNATE PARTS B

085-2450 SUB ASSY,CPU SOCKET,K62,MOLEX MOLEX_SOCKET 128S0298 128S0293 ALL 330UF

371S0679 371S0652 ALL PIN DIODE

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

085-2450 085-2451 SKT_ILM MOLEX ALTERNATE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

S5 Led ALL_SYS_PWRGD Led MXM PWR GOOD Led VIDEO ON Led

100 64 32 IN ALL SYS PWRGD R 5 G S SOT 363

PROTO DEBUG LEDS ARE SHOWN BELOW

"S0" RAILS PP3V3_S5 PP3V3_S5_REG

PS ON =PP1V05 S0 CK505 26 =PP5V S0 LPCPLUS 48 =PP3V3 S5 P3V3R2V9 A 83

1 C607 G 2N7002DW-X-G F-RT-SM

21 SYNC MASTER=K62 AARON SYNC DATE=12/30/2010 A

CPU Heatsink DIMM CONNECTOR NUTS

PCH HEATSINK MTG HOLES (NON-PLATED HOLE ON PCB ONLY)

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

860-1430 6 STANDOFF,MLB,K60/K62 SDF0713 SDF0714 SDF0715 SDF0717 SDF0718 SDF0719 COMMON

21 TP_PCIE_CLK100M_PE7P NC_PCIE_CLK100M_PE7P 19 TP_DP_IG_B_MLN<3..0> NC_DP_IG_B_MLN<3..0>

10 TP_PE_TX_P<3..0> NC_PE_TXP<3..0> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

12 TP_MEM_B_DQ_CB<7..0> NC_MEM_B_DQ_CB<7..0> 20 TP_USB_3N NC_USB_3N

A 20 TP_USB_12N NC_USB_12N 18 TP_PCH_CLKOUT_DPP NC_PCH_CLKOUT_DPP

PEG Slot Support

=PEG D2R N<0..15>

21 IN PEG_CLKREQ_L MXM CLKREQ_L OUT 76 100

76 MXM_RESET_L PEG_RESET_L 27 100

PLACEMENT NOTE=PLACE CLOSE TO U1800 5%

A SYNC MASTER=K62 SIJI SYNC DATE=09/11/2010 A

Apple Inc. 051-8442 D

FLEXIBLE DISPLAY INTERFACE

PCI EXPRESS -- GRAPHICS

0 TP_PE_RX_N<0> P4 PEG_TX_7* =PEG_R2D_C_N<7> OUT 9

8 TP_PE_RX_P<1> R2 PE_RX_1 PEG_TX_13* M7 =PEG_R2D_C_N<13> 9

8 TP_PE_TX_N<0> P7 PE_TX_0* PEG_TX_0 C13 =PEG_R2D_C_P<0> 9

PEG_TX_9 G10 =PEG_R2D_C_P<9> OUT 9

PEG_TX_12 J5 =PEG R2D C P<12> 9

PEG_TX_14 L6 =PEG_R2D_C_P<14> OUT 9

Apple Inc. 051-8442 D

=PPVCCIO S0 CPU 100 19 OUT CPU_PROC_SEL K32 PROC_SEL

JTAG & BPM

0 100 PLT_RESET_LS1V05_L F36 RESET* TDO L39 XDP_CPU_TDO OUT 25 93

100 25 21 IN CPU_PWRGD J40 UNCOREPWRGOOD

BPM[1]* H38 XDP_BPM_L<1> BI 25 93