J59 820-2997 APPLE THUNDERBOLT 27_ Display_LS

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
C 0001188998 PRODUCTION RELEASED 2011-07-22
D
J59
(7/22/2011) D
( csa) Date
Page Contents Sync

1 08/22/2010
1 Table of Contents DRB
2 N/A
2 J59 BLOCK DIAGRAM MASTER
3 N/A
3 Power Block Diagram MASTER
4 N/A
4 BOM Configuration & Misc MASTER
6 N/A
5 DC POWER IN MASTER
8 N/A
6 Power Aliases MASTER
9 N/A
7 Signal Aliases MASTER
10 N/A
8 FAN CNTRL & TSENSE MASTER
11 N/A
9 LED BL DRIVER MASTER
12 N/A
10 CAMERA/ALS MASTER
13 08/22/2010
11 DEBUG, MISC & JTAG K59
14 11/18/2010
12 PNX0161 CODEC AUDIO
C 13
15
16
AUDIO DC-DC REGULATORS AUDIO
11/18/2010
11/18/2010
C
14 SIGMA DSP AUDIO
17 11/18/2010
15 LEFT SPEAKER AMP AUDIO
18 11/18/2010
16 RIGHT SPEAKER AMP AUDIO
19 11/18/2010
17 SUBWOOFER SPEAKER AMP AUDIO
20 11/18/2010
18 AUDIO CONNECTORS AUDIO
23 N/A
19 POWER SW CONTROL MASTER
26 08/22/2010
20 LPC2144 & PERIPHERALS K59
27 08/22/2010
21 DP FC & INTERFACE K59
28 03/17/2011
22 T29 Clocking T29 D
36 11/01/2010
23 T29 Primary (1 of 2) T29 D
37 03/17/2011
24 T29 Primary (2 of 2) T29 D
38 09/16/2010
25 CAESAR IV SUPPORT K62
39 10/01/2010
26 ETHERNET PHY (CAESAR IV) TONY
40 09/16/2010
27 Ethernet Connector K62
41 09/09/2010
28 FireWire LLC/PHY (FW643) K62
42 09/23/2010
29 FireWire: 1394B MISC K62
43 09/23/2010
30 FIREWIRE CONNECTOR
B 31
45
USB 7-PORT HUB
K62
K59
11/01/2010 B
46 N/A
32 USB 2.0 Host Controller MASTER
49 08/22/2010
33 USB EXTERNAL CONNS K59
50 03/17/2011
34 Tethered Cable MCU T29 D
52 N/A
35 J59 & T29 SMBUS CONNECTIONS MASTER
70 N/A
36 1.05V VREG MASTER
71 03/17/2011
37 Power: T29 15V Boost T29 D
73 N/A
38 Power: USB (1.0V S3) MASTER
77 N/A
39 5V/3.3V SUPPLY MASTER
79 09/30/2010
40 Power: Enables & PGOODs T29 D
90 03/17/2011
41 Tethered Cable Connector T29 D
93 11/01/2010
42 T29 A PORT MICROCONTROLLER T29 D
94 N/A
43 DisplayPort/T29 A Connector MASTER
100 11/17/2010
44 CONSTRAINTS: T29 TONY
103 11/17/2010
45 CONSTRAINTS: AUDIO & MISC TONY
105 11/17/2010
46 CONSTRAINTS:ENET, FIREWIRE & USB TONY
109 11/17/2010
47 T29 PCB Rule Definitions TONY
A 48
110
J59 ICT/FCT MASTER
N/A
A
DRAWING TITLE
SCH,J59,MLB
DRAWING NUMBER SIZE
Apple Inc. 051-8774 D

REVISION
R
C.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 48
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8 7 6 5 4 3 2 1
D D
C C
B B
A SYNC_MASTER=MASTER SYNC_DATE=N/A A
PAGE TITLE
J59 BLOCK DIAGRAM

DRAWING NUMBER SIZE

REVISION
R
C.0.0
2 OF 110
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Device Function: Dr.B Mr.Dev Mr.Dev Mr.Dev Display ENET FW SATA DPIn
Power Source: Self Self Bus Bus Self Bus Bus Bus Bus
Wake Support: Yes Yes Yes No Yes Yes No No No
mDP Tethered Q7560 24V FW FW FW FW FW FW N/A FW N/A N/A

(420mA / 10W) (420mA) (420mA) (420mA) (420mA) (420mA)
D 3.0-26.4V FET
D
U7000 3.3V S5 MCU MCU N/A N/A MCU N/A N/A N/A N/A
(10mA) (10mA) (10mA)
TPS51980
MagSafe 1.05V T29 RTRx2,FW,SATA RTR,FW,SATA RTR,FW,SATA RTR,FW,SATA RTRx2,FW RTR RTR,FW RTR,SATA RTR
15-18.5V
3.3V T29 RTRx2,FW,SATA RTR,FW,SATA RTR,FW,SATA RTR,FW,SATA RTRx2,FW RTR RTR,FW RTR,SATA RTR,mDP
UB500 5V S3 USB N/A N/A N/A N/A N/A N/A N/A N/A
(2.1A)
TPS51980
3.3V S4 mDPx2 mDPx2 N/A N/A mDP N/A N/A N/A N/A
(1A) (1A) (1A)
U7200 1.2V ENET DP++ DP++ N/A N/A DP++ N/A N/A N/A N/A
C SC194A
(440mA) (440mA) (440mA) C
U7300 1.5V USB PLX (USB) PLX (USB) N/A N/A PLX (USB) N/A N/A N/A N/A
(210mA) (210mA) (210mA)
SC194A
L7435 1.2V ENET N/A N/A ENET N/A N/A ENET N/A N/A N/A
(400mA?) (400mA?)
(U3900)
U7600 1.8V SATA SATA SATA SATA SATA N/A N/A N/A SATA N/A
(250mA) (250mA) (250mA) (250mA) (250mA)
SC194A
3.3V MCU N/A N/A MCU MCU N/A MCU MCU MCU MCU
(10mA) (10mA) (10mA) (10mA) (10mA) (10mA)
U7700
LP2951
B U???? 12V S5 B
?????
U???? 24V S0
?????
A T29 Bus-Powered Device Power States: DP/T29 Display-Specific Power States: SYNC_MASTER=MASTER SYNC_DATE=N/A A
PAGE TITLE
S4: Device negotiation, SRC_PWR = 3.0-3.6V (MCU function only) (In addition to S5-S0 states for T29 Self-Powered Device) Power Block Diagram
S3: Device sleep, SRC_PWR = 5.0-26.4V (optional wake functions supported) D5: Display standby, no cables attached DRAWING NUMBER SIZE
S0: Device running, SRC_PWR = 21.6-26.4V (run functions supported) D3: Display sleep, DP cable detached or no source power, USB VBus present (USB wake supported)
D2: Display low-power, DP cable attached and source powered, source asleep per AUX command to TCON (USB wake supported) REVISION
NOTE: Devices not supporting wake function would not implement S3 state. R
D0: Display ready, DP cable attached and source powered C.0.0
NOTEs:
T29 Self-Powered Device Power States: - D5 implies S5, S0 implies D0.
S5: Device standby, no cable attached (MCU function & DP port power only) - If only native DP source is attached, any Dx state can be supported while T29 is in S5.
S3: Device sleep, cable attached (optional wake functions supported)
3 OF 110
NOTE: D2 not supported on Dr.B as there is no direct connection from panel TCON III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
S0: Device running, cable attached (run functions supported)
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8 7 6 5 4 3 2 1
BOM NUMBER BOM NAME BOM OPTIONS

639-1575 PCBA,MLB,J59 BASIC
Module Parts
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
085-2422 PCBA,MLB,DEV,J59 DEVELOPMENT
338S0945 1 IC,T29-PRQ,220 FCBGA,15X15MM U3600 CRITICAL
D 338S0753 1 IC FW643 E 1394B PHY/OHCI LINK/PCI E 12 U4100 CRITICAL D

343S0549 1 IC ASIC GBIT ENET QFN 48 6X6 BCM57761 B0 U3900 CRITICAL
338S0977 1 PCI EXPRESS TO USB 2 0 HOST CONTROLLER(REV B) U4600 CRITICAL
BOM GROUP BOM OPTIONS

BASIC COMMON,ALTERNATE,T29HV:P12V,BIT_BANG_I2C,ENET_WAKE:PCIE,PIUSB_REV:B,PRODUCTION
FLASH PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
RAW: 335S0550 341T0376 1 IC EEPROM J59 PRIMARY SPI 32KBIT MLP8 U3690 CRITICAL
RAW: 335S0800 341T0331 1 ENET FLASH C IV NO SD J59 U3990 CRITICAL
RAW: 335S0559 341T0375 1 IC EEPROM FW643 E2 GUID I2C 2KBIT MLP8 U4290 CRITICAL
RAW: 337S4115 341T0385 1 IC MCU 32B LPC1114 32KB/8KB HVQFN33 J59 U5000 CRITICAL
RAW: 337S4115 341T0385 1 IC PRGRMD LPC1114 T29 SUPER MCU HVQFN33 U9330 CRITICAL
RAW: 337S3558 341T0378 1 IC PRGRMD LPC2144 J59 SYSTEM MCU U2617 CRITICAL
RAW: 353S2320 341T0369 1 IC PRGRMD PNX0161 AUDIO/HID TFBGA88 U1400 CRITICAL
C C
ALTERNATES
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
376S0977 376S0859 ALL DIODESINC ALT FET
376S0972 376S0612 ALL ROHM ALT FET
377S0107 377S0066 ALL ON SEMI ALT RCLAMP
155S0431 155S0289 L1204 ALTERNATE CM CHOKE
376S1029 376S0953 ALL ALTERNATE DC/DC FET
376S1030 376S0801 ALL ALTERNATE DC/DC FET
376S1017 376S0612 ALL ALTERNATE TOSH SS FET
377S0124 377S0057 ALL ALTERNATE VARISTOR
152S1483 152S1376 ALL ALTERNATE INDUCTOR
155S0691 155S0183 ALL ALT BEAD FOR BL FILT
128S0262 128S0220 ALL ADDS KEMET TO SANYO
138S0684 138S0660 ALL ADDS MURATA TO TAIYO
B 155S0571 155S0309 ALL ALTERNATE FERRITE B

353S3477 353S3207 ALL ALTERNATE FAB U9410
Schematic / PCB / EEEE #’s

820-2997 1 PCBF MLB J59 PCB1 CRITICAL
051-8774 1 SCH MLB J59 SCH1 CRITICAL
825-7122 1 MLB LABEL 48 0MM X 4 8MM [EEEE_DHMY] CRITICAL
PAGE TITLE
BOM Configuration & Misc

DRAWING NUMBER SIZE

REVISION
R
C.0.0
4 OF 110
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PP610
1P0-BOT
SM
1
PP
DC_24VIN
PP611
1P0-BOT
SM
1
PP
D DC_24VIN
CRITICAL D
CRITICAL
PP605
1P0-BOT
DC 24.5VOLT POWER IN Q609
SM PP24V_BLC_PREFILT PP24V_BLC_FET 6
J603 1
PP CRITICAL PP603
1P0-BOT
PP24V S5 BLCFET SUD50P0615L MIN_LINE_WIDTH=1.0MM MIN_LINE_WIDTH=1.0MM
5569-12A2S-225 DC_24VIN
L623
ACM1211-SM1 SM
MIN_LINE_WIDTH=1.0MM
MIN_NECK_WIDTH=0.5MM
TO-252 MIN_NECK_WIDTH=0.5MM
VOLTAGE=24.5V
CRITICAL MIN_NECK_WIDTH=0.5MM
VOLTAGE=24.5V
M-RT-TH
700-OHM-8A 1
PP VOLTAGE=24.5V FL601
7 1 PP24V_S5 PREFILT C639 2 3 DC_24VIN 600OHM-100MHZ-0.2V
MIN_LINE_WIDTH=1.0MM 10UF
4
8 2 MIN_NECK_WIDTH=0.5MM 1 2
VOLTAGE=24.5V 1 2 C641 C645 PP604 PP620
D
9 3 2K-HR 2K-HR 1206-1
2
1 4 1P0-BOT 1P0-BOT
10 4 20% SM CRITICAL CRITICAL R624 SM
SWI_INV
2
CRITICAL
GND_ACDC24 35V 1 1
C648 1
C650 1 C620 1 C621 1 C622 1 1 C600
G
11 5 MIN_NECK_WIDTH=0.5MM X7R
1210 0.1UF
SYM_V R
DC_24VIN 0.01UF
PP
100UF 100UF 0.01UF 180K
5% 0.47UF 0.47UF SWI_INV PP
0.1UF FL602
1
MIN LINE_WIDTH=1.0MM SWI_INV 600OHM-100MHZ-0.2V
NC_DCIN
NO TEST TRUE
12 6 VOLTAGE=0V DC_24VIN 10%
50V
10%
50V
DC_24VIN 20%
2 35V
20%
2 35V
10%
50V
2 X7R
1/10W
MF-LF
10%
2 50V
10%
2 50V
PP621
1P0-BOT
10%
50V
2 X7R
X7R 1 C643 X7R ELEC ELEC 603-1 603 CERM
1206
CERM
1206 SM 603-1
1 2
1
603-1 603-1 6.3X8-SM-HF 6.3X8-SM-HF 1
DC_CONNIN DC_24VIN 0.01UF DC_24VIN DC_24VIN DC_24VIN SWI_INV GATE_Q0309 PP
SWI_INV 1206-1
PP606
1P0-BOT
10%
50V
2 X7R SWI_INV MIN_NECK_WIDTH=0.2MM
SWI_INV
SM CRITICAL
220K 2
SWI_INV SWI_INV SWI_INV MIN_LINE_WIDTH=0.6MM
R627
603-1 1
1
C651 VOLTAGE=0V
1/10W
MF-LF
PP
DC_24VIN
603
PP612 100UF
5%
DC_24VIN 1P0-BOT 20%
SM 2 35V
1 ELEC
1
PP 6.3X8-SM-HF GATE_Q0309_R SWI_INV
DC_12VIN DC_24VIN
PP613
1P0-BOT R625 3
SM
1
PP
1 C673 PWR_INV_ON 1 10K 2 BASE_Q0308 1 Q608
DC_12VIN 10UF 20 9 IN MMBT3904G
20% SOT23
PP607
1P0-BOT
DC 12 VOLT POWER IN 2 35V
X7R
1210
5%
1/16W
MF-LF R626 2 SWI_INV
SM
1
402
1
10K 2
SWI_INV
PP
PP601 5%
DC_12VIN 1P0-BOT
SM 1/16W
1 PP MF-LF
402
C C640
DC_12VIN
PP12V_S5_ACDC 6 SWI_INV
C
10UF C642 C646 PP602
1
2
1 2 1P0-BOT
SM NOSTUFF NOSTUFF
1
20% PP CRITICAL CRITICAL
0.1UF 0.01UF 1 1
35V
X7R 10% 10% DC_12VIN C647 C649
1210 50V 50V 220UF 220UF
DC_12VIN X7R X7R 20% 20%
603-1 603-1 2 16V 2 16V
PP608
1P0-BOT
DC_12VIN
DC_12VIN
ELEC
SM-CASE-C1-HF
ELEC
SM-CASE-C1-HF
SM DC_12VIN DC_12VIN
1
PP
DC_12VIN
8 6 =PP3V3_S5_FAN
B B
1
R647
100K
1%
1/16W
MF-LF
402
2DC_CONNIN
L622
FERR-120-OHM-3A R602
1 2
FAN_ON_IN_FILT_L
1
10K 2
FAN_ON_L
FAN ON IN L OUT 20
0603 5%
DC_CONNIN 1/16W
MF-LF
402
1 C604
DC_CONNIN 100PF
5%
2 50V
CERM
402
DC_CONNIN
A SYNC MASTER=MASTER SYNC DATE=N/A A

PAGE TITLE
DC POWER IN
DRAWING NUMBER SIZE

REVISION
R
C.0.0
6 OF 110
8 7 6 5 4 3 2 1
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S5 Rails S0 RAILS
PP12V_S5 PP12V_S5_ACDC 5 PP24V_S0_BLC PP24V_BLC_FET 5

MIN LINE WIDTH=0 4 mm MIN LINE WIDTH=1 0MM
MIN NECK WIDTH=0 2 mm MIN NECK WIDTH=0 5MM
VOLTAGE=12V VOLTAGE=24 5V
MAKE BASE=TRUE MAKE BASE=TRUE
D
=PP12V_S5_FANFET
=PP12V_S5_5V3V_VREG
19
39
=PP24V_BLC_LEDS 9
D
PPVIN_SW_T29BST 37 =PP12V_S5_AUDIOFET 19
VOLTAGE=12V
=PP12V S5 LCDFET 19
=PP12V S5 P12VS0FET 40
=PPVIN SW T29BST 6 37 PP12V S0 =PP12V S0 FET 40

MIN LINE WIDTH=0 4 mm
MIN NECK WIDTH=0 2 mm
VOLTAGE=12V
MAKE BASE=TRUE
=PP12V S0 FW 30
=PP12V_S0_P1V05S0_VREG 36
PP5V S5 PP5V S5 REG 39

VOLTAGE=5V
MAKE BASE=TRUE
=PP5V_S5_USB 33
=PP5V_S5_AUDIOFET
=PP5V_S5_CAMFET
19
10
PP3V3 S0
=PP3V3 S0 FET 40 T29 PORT POWER VOLTAGE
=PP5V_S5_P1V05S0_VREG VOLTAGE=3 3V
36
MAKE BASE=TRUE
=PP3V3_S0_DEVRESET 7 1000 MA
=PP3V3 S0 CK505 22
PP15VR12V_S3 =PP15V_T29_REG 37
=PP3V3 S0 T29P 7 11 23 24 MIN LINE WIDTH=0 4 mm
=PP3V3_S0_I2C_UC 35 VOLTAGE=15V
MAKE BASE=TRUE
=PP3V3_S0_FWPHY 28 29 30
PP3V3 S5 PP3V3 S5 REG =PPHV_SW_DPAPWRSW 43 500 MA
39 =PPVDDIO_S0_T29P_CLK 22
C MIN NECK WIDTH=0 2 mm

VOLTAGE=3 3V
MAKE BASE=TRUE
=PP3V3 S4 DEVRESET 7
=PP3V3_S0_TCPWRSW
=PP3V3_S0_ENET_PHY
40 41
20 26 CRITICAL
C
T29HV:P12V
=PP3V3 S5 FANBUF =PP3V3_S0_TCON
19 400 mA?
=PP3V3 S0 I2C T29
21 35
37 6 =PPVIN_SW_T29BST R890
=PP3V3_S5_FAN 5 8
35
1
0.0012
=PP3V3_S5_USB 31 32 33
1%
=PP3V3_S5_LPC 20 35 1W
MF
=PP3V3_S5_AUDIOFET 19 T29HV:P12V 0815-HF
R895
2
=PP3V3_S5_TCON 21
=PP3V3_S5_JTAG 11
0
5%
=PP3V3 S5 BLC 9 1/16W
MF-LF
=PP3V3_S5_ALS PP1V05_S0 PP1V05_S0_REG 402
1
35 36
=PP3V3_S5_P3V3S3FET 40 MIN NECK WIDTH=0 2 mm
VOLTAGE=1 05V
=PP3V3_S5_P3V3S0FET 40 MAKE BASE=TRUE
T29BST_PWREN_DIV_L OUT 37
=PP3V3_S4_DPAPWRSW 7 43 =PP1V05_S0_CK505 22
=PP3V3_S5_T29P =PP1V05_S0_T29P 24
RT800
1
0 2 PP3V3_S4_MCU =PP3V3_S4_MCU 11 34 750 MA
5% MIN NECK WIDTH=0 2 mm
1/10W VOLTAGE=3 3V PP3V3_SW_TCPWR =PP3V3_S0_TCPWR_FET 41
MF-LF MAKE BASE=TRUE MIN LINE WIDTH=0 4 mm
603 MIN NECK WIDTH=0 2 mm
VOLTAGE=3 3V
MAKE BASE=TRUE
=PP3V3_S0_TCCONN 41 750 MA
S3 RAILS
B Digital Ground B
GND
PP3V3_S3 =PP3V3_S3_FET 40 MIN LINE WIDTH=0 6MM
MIN LINE WIDTH=0 4 mm MIN NECK WIDTH=0 2MM
MIN NECK WIDTH=0 2 mm VOLTAGE=0V
VOLTAGE=3 3V
MAKE BASE=TRUE
< 2100 mA
=PP3V3 S3 ENET PHY 20 25
=PP3V3_S3_USB 7 32 35
=PP3V3_ENET_SYSCLK 22
=PP3V3_S3_P1V0S3REG 38
=P1V0S3_EN 38
PP1V0_S3 PP1V0_S3_REG 38
VOLTAGE=1V
MAKE BASE=TRUE
=PP1V0_S3_USB 32
PAGE TITLE
Power Aliases
DRAWING NUMBER SIZE

REVISION
R
C.0.0
8 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCIe Assignments Power-Up Reset Generation
INTERNAL DP PANEL SOURCE MUX BYPASS
23 IN PCIE_T29_R2D_C_P<0> PCIE_USB_R2D_C_P OUT 32 46 =PP3V3_S4_DEVRESET Q0910.3 POWERED BY S4 TO ENSURE
MAKE BASE=TRUE 23 IN DP T29SRCA ML C P<0> DP INT ML C P<0> OUT 7 44
6
MAKE BASE=TRUE =PP3V3_S0_DEVRESET no glitch when S0 powers-up.
23 IN PCIE_T29_R2D_C_N<0> PCIE_USB_R2D_C_N OUT 32 46
6
MAKE BASE=TRUE 23 IN DP_T29SRCA_ML_C_N<0> DP_INT_ML_C_N<0> OUT 7 44
MAKE BASE=TRUE
23 OUT PCIE_T29_D2R_P<0> PCIE_USB_D2R_P IN 32 46

1
MAKE BASE=TRUE R913
23 OUT PCIE_T29_D2R_N<0> PCIE_USB_D2R_N IN 32 46 100K
MAKE BASE=TRUE 23 IN DP_T29SRCA_ML_C_P<1> DP_INT_ML_C_P<1> OUT 7 44 5%
MAKE BASE=TRUE 1/16W
MF LF
23 IN T29_PCIE_RESET_L<0> USB_RESET_L OUT 32 23 IN DP_T29SRCA_ML_C_N<1> DP_INT_ML_C_N<1> OUT 7 44
2
402
MAKE BASE=TRUE MAKE BASE=TRUE
D S0 RESET L
MAKE BASE=TRUE
I330
T29 RESET L OUT 23 D
23 IN PCIE_T29_R2D_C_P<1> PCIE_ENET_R2D_C_P OUT 26 46 2
MAKE BASE=TRUE 23 IN DP_T29SRCA_ML_C_P<2> DP_INT_ML_C_P<2> OUT 7 44 R912
MAKE BASE=TRUE 470K 6
23 IN PCIE T29 R2D C N<1> PCIE ENET R2D C N OUT 26 46
5%
MAKE BASE=TRUE 23 DP_T29SRCA_ML_C_N<2> DP_INT_ML_C_N<2> 7 44
IN
MAKE BASE=TRUE
OUT 1/16W D Q910
R910 1
MF LF
23 OUT PCIE T29 D2R P<1> PCIE ENET D2R P IN 26 46
402
1 DMB53D0UV
MAKE BASE=TRUE 100K SOT-563
5%
23 PCIE_T29_D2R_N<1> PCIE_ENET_D2R_N 26 46 23 DP_T29SRCA_ML_C_P<3> DP_INT_ML_C_P<3> 7 44 1/16W S0_RESET 2 G
OUT IN IN OUT
MAKE BASE=TRUE MAKE BASE=TRUE MF LF
402
DP_T29SRCA_ML_C_N<3> DP_INT_ML_C_N<3> 2
23 IN OUT 7 44
23 IN T29 PCIE RESET L<1> ENET RESET L OUT 26 MAKE BASE=TRUE 3
MAKE BASE=TRUE
DEVRESET_P3V3_RC 5 Q910 S
PCIE T29 R2D C P<2> PCIE FW R2D C P
23 BI DP_T29SRCA_AUXCH_C_P DP_INT_AUXCH_C_P BI 7 44
100ms delay DMB53D0UV
23 IN OUT 28 46 MAKE BASE=TRUE SOT-563 1
MAKE BASE=TRUE
PCIE_T29_R2D_C_N<2> PCIE_FW_R2D_C_N
23 BI DP T29SRCA AUXCH C N DP INT AUXCH C N BI 7 44 C910 1
4
23 IN OUT 28 46 MAKE BASE=TRUE
MAKE BASE=TRUE
1UF
10%
6 3V
CERM 2
23 OUT PCIE_T29_D2R_P<2> PCIE_FW_D2R_P IN 28 46
23 DP T29SRCA HPD DP INT HPD 21 402
MAKE BASE=TRUE OUT IN
MAKE BASE=TRUE
23 OUT PCIE_T29_D2R_N<2> PCIE_FW_D2R_N IN 28 46
MAKE BASE=TRUE
23 IN T29_PCIE_RESET_L<2> FW_RESET_L OUT 28

MAKE BASE=TRUE
MISC T29 ALIAS CONNECTIONS
23 IN PCIE_T29_R2D_C_P<3> NC_PCIE_T29_R2D_C_P3 Wake Sources Power State Isolation
MAKE BASE=TRUE NO TEST=TRUE 41 34 IN T29 LSX R2P =T29 LSX R2P OUT 34
MAKE BASE=TRUE
23 IN PCIE_T29_R2D_C_N<3> NC_PCIE_T29_R2D_C_N3
MAKE BASE=TRUE NO TEST=TRUE 41 34 T29 LSX P2R =T29 LSX P2R 34
OUT IN
MAKE BASE=TRUE ENSURES THAT DEVICES OFF IN S3 DO NOT DRAG DOWN TBLT_WAKE_L.
23 OUT PCIE_T29_D2R_P<3> NC_PCIE_T29_D2R_P3
MAKE BASE=TRUE NO TEST=TRUE TP_T29_A_BIAS T29_A_BIAS 42 26 25 =PP3V3_S3_ENET_PHY_FET
IN
PCIE T29 D2R N<3> NC PCIE T29 D2R N3 MAKE BASE=TRUE
23 OUT
MAKE BASE=TRUE NO TEST=TRUE
C 23 IN T29_PCIE_RESET_L<3> NC_T29_PCIE_RESET_L3 R909 R950 1

Q950
SSM3K15FV
C
1
0 2
SOD VESM HF
43 6 IN =PP3V3_S4_DPAPWRSW DPAPWRSW_EN 100K
1
MAKE BASE=TRUE 5%
5%
G
1/16W
INTERNAL DP PANEL AC COUPLING CAPS 1/16W
MF-LF =DPAPWRSW EN OUT 43
MF LF
402
402 2
D
26 IN =ENET_WAKE_L TBLT_WAKE_L OUT 34 42
C900
3
MAKE BASE=TRUE
2
ENET_WAKE_L
1
44 7 IN DP_INT_ML_C_P<0> DP_INT_ML_P<0> OUT 21 44 48 U5000 IS SLAVE MCU - U9330 IS MASTER

=TCMCU_ADDR MAKE BASE=TRUE
OUT 34
0.1UF 10% 16V X5R 402 (SEE REFERENCE DESIGN)
C901
1
44 7 IN DP_INT_ML_C_N<0> DP_INT_ML_N<0> OUT 21 44 48
0.1UF 10% 16V X5R 402 35 32 6 =PP3V3_S3_USB
C902 CLOCKS Q952

1
DP_INT_ML_C_P<1> DP_INT_ML_P<1>
R952 1
44 7 IN OUT 21 44 48
SSM3K15FV
0.1UF 10% 16V X5R 402 SOD VESM HF
PCIE_CLK100M_PCIBR_P PCIE_CLK100M_USB_P 100K
1
22 IN OUT 32 46
5%
MAKE BASE=TRUE
C903
G
1/16W
1
44 7 IN DP_INT_ML_C_N<1> DP_INT_ML_N<1> OUT 21 44 48 22 IN PCIE_CLK100M_PCIBR_N PCIE_CLK100M_USB_N OUT 32 46

MF LF
402
MAKE BASE=TRUE 2
0.1UF 10% 16V X5R 402
D
PCIBR_CLKREQ_L PCIE_CLKREQ4 32 IN =USB_WAKE_L
C904 22 7 OUT
3
2
MAKE BASE=TRUE USB_WAKE_L
1
44 7 IN DP_INT_ML_C_P<2> DP_INT_ML_P<2> OUT 21 44 48

MAKE BASE=TRUE
0.1UF 10% 16V X5R 402
PCIE_CLK100M_T29S_P NC_PCIE_CLK100M_SRC6P
22 IN
C905 PCIE_CLK100M_T29S_N NC_PCIE_CLK100M_SRC6N
1
44 7 IN DP_INT_ML_C_N<2> DP_INT_ML_N<2> OUT 21 44 48

22 IN
0.1UF 10% 16V X5R 402
22 OUT T29S_CLKREQ_L PCIE_CLKREQ6
C906 MAKE BASE=TRUE
1
44 7 IN DP_INT_ML_C_P<3> DP_INT_ML_P<3> OUT 21 44 48
B 0.1UF 10% 16V X5R 402

22 IN PCIE_CLK100M_SLOT_P NC_PCIE_CLK100M_SRC1P
T29 GPIO TO DETECT ERRANT PASSIVE DP CABLE CONNECTION B
C907
1
44 7 IN DP_INT_ML_C_N<3> DP_INT_ML_N<3> OUT 21 44 48 22 IN PCIE_CLK100M_SLOT_N NC_PCIE_CLK100M_SRC1N

0.1UF 10% 16V X5R 402
22 PCIESLOT_CLKREQ_L PCIE_CLKREQ1 24 23 11 7 6
=PP3V3_S0_T29P
OUT
C908 MAKE BASE=TRUE
1
44 7 IN DP_INT_AUXCH_C_P DP_INT_AUXCH_P OUT 21 44 48
0.1UF 10% 16V X5R 402
PCIE_CLK100M_SATA_P NC_PCIE_CLK100M_SRC9P R9001 Q900

C909 22 IN
SSM3K15FV
1
44 7 DP_INT_AUXCH_C_N DP_INT_AUXCH_N 21 44 48
IN OUT 10K SOD VESM HF
0.1UF 10% 16V X5R 402 22 IN PCIE_CLK100M_SATA_N NC_PCIE_CLK100M_SRC9N 5%
1
MAKE BASE=TRUE NO TEST=TRUE 1/16W
G
MF LF
402
22 SATA_CLKREQ_L PCIE_CLKREQ9 2
OUT
MAKE BASE=TRUE
D
23 IN T29_GPIO<1> DP_A_PWRDWN OUT 7 42
FW CLK24P576M NC FW CLK24P576M
3
22
2
IN
Misc Ethernet Aliases MAKE BASE=TRUE NO TEST=TRUE
26 OUT ENET LOW PWR TP ENET LOW PWR 22 IN PS161 CLK27M R NC CLK27M
MAKE BASE=TRUE MAKE BASE=TRUE NO TEST=TRUE
22 IN PCI CLK33M PCIBR NC PCI0 CLK33M

Misc FireWire Aliases MAKE BASE=TRUE NO TEST=TRUE
22 IN PCI CLK33M NECUSB NC PCI2 CLK33M

28 IN FW_PME_L TP_FW_WAKE_L MAKE BASE=TRUE NO TEST=TRUE UNUSED T29 ROUTER GPIOS
MAKE BASE=TRUE
R901 =PP3V3_S0_T29P 6 7 11 23 24
T29 GPIO<2> 1
10K 2
T29 NOCONNECTS DUE TO SINGLE PORT AND NO DPOUT 23 BI
PCIE CLKREQ ENABLING UNUSED T29S GREENCLK
5%
1/16W
MF-LF
402
A R902 SYNC_MASTER=MASTER SYNC_DATE=N/A A
DP_A_PWRDWN NC_DP_A_PWRDWN PCIBR_CLKREQ_L 1
0 2
R990 PAGE TITLE
42 7 IN 22 7 IN 0
MAKE BASE=TRUE NO TEST=TRUE MAKE BASE=TRUE
5%
1 2 =PPVDDIO_S0_T29S_CLK
OUT 22 Signal Aliases
1/16W 5%
MF-LF DRAWING NUMBER SIZE
1/16W PPVDDIO_S0_T29S_CLK
402 MF-LF
402 MAKE BASE=TRUE Apple Inc. 051-8774 D
R908 R903 REVISION
0 R
C.0.0
4.7K 2 22 IN T29 CLKREQ L 1 2
42 34 OUT PM_DPO_EN 1 MAKE BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH
5%
5% 1/16W
1/16W MF-LF 22 SYSCLK_CLK25M_T29S NC_SYSCLK_CLK25M_T29S THE INFORMATION CONTAINED HEREIN IS THE
MF-LF 402 IN PROPRIETARY PROPERTY OF APPLE INC.
MAKE BASE=TRUE NO TEST=TRUE THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402
9 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
19 =PP12V_FAN_MOTOR
D D
R1057
1.5K 2
R1055
1.5K 2
MF-LF
1/4W
1206
MF-LF
5%
1/4W
1206
5%
1
1
19 =PP3V3_FAN_MOTOR FAN0 4 8
FAN0
R1056
1
3.9K 2 CRITICAL
FAN0_VDIV8R5 FAN0_GATESLOWDN 3 MICROFET (MOLEX)
5% FDMA510PZ
1/8W FAN0 CRITICAL
R1053
R1054
MF-LF 1 C1000 Q1022 J1013
2
805 (COLOR=BLACK,GOLD-PIN)
0.47UF
1/16W
MF-LF
1/16W
MF-LF
10K
10K
53780-8604
402
402
10%
5%
5%
16V M-RT-SM (HF-PART)
2 X7R 1 2 5 6 7
FAN0 VOLTAGE=12V 5
805
MIN LINE WIDTH=0 5MM
1
(SECOND ENTERY 3806K F04N 23R)
MIN NECK WIDTH=0 2MM
FAN0 FAN0 3
48 FAN0_PWR 1 MOTOR CONTROL
Q1021
MMBD914XG
2 TACH
2N7002E-X-G
D1002
CRITICAL 3 GND
3
1
PWM_FAN0 SOT23-3 1
C1078
SOT23
20 IN 4 12V DC
100UF
2 20%
1
2 16V
ELEC 6
6.3X5.5-SM3
3K-HR
R1052
C 20 IN TACH0 1
47K 2 48 FAN_TACH0 C
5%
1/16W
MF-LF
402
CURRENT LIMIT TO PROTECT UC

PP3V3_S5 FAN F CRITICAL
MIN NECK_WIDTH=0.2MM
VOLTAGE=3.3V
L1038
FERR-120-OHM-1.5A =PP3V3_S5_FAN
C1061 1
1 2
5 6
0.1UF
10% 0402
50V
CRITICAL X7R 2 TSENSE
603-1
J1011 TSENSE
8 TSENSE
53780-8603
M-RT-SM V+
4
U1018
1 R1071 1 1.5K 2 1 DX1
TMP422 7
48 45 TDX1_P 45 DX1_P SOT23-8 SCL =I2C_TMP_SCL 35
BLOWER TEMPERATURE 2 48 45 TDX1_N 1% 2 DX2 CRITICAL SDA 6 =I2C_TMP_SDA 35

3
1/16W
MF-LF
1 C1060 3 DX3
NC 402 100PF
TSENSE 5% 4 DX4
50V
2 CERM
5
R1072 1 1.5K 2 45 402 DX1 N GND TMP422 ADDR IS $98 AS CONFIGURED
TSENSE 1% TSENSE 5
1/16W
MF-LF
402
TSENSE
B J1012
CRITICAL
B
SM-2MT-HF
3
1 48 45 TDX2 P R1073 1 1.5K 2 45 DX2 P

PSU TEMPERATURE 2 48 45 TDX2 N 1%
1/16W
MF-LF
1 C1062
402 100PF
4 TSENSE 5%
2 50V
CERM
TSENSE R1074 1 1.5K 2 402 45 DX2 N
1% TSENSE
1/16W
MF-LF
402
TSENSE

PAGE TITLE
FAN CNTRL & TSENSE

DRAWING NUMBER SIZE

REVISION
R
C.0.0
10 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TP1182
1 TP1180
A 1
TH-TP50 HV9982 A
TH-TP50 HV9982 PP8V_BLC_VREG 9
R1153 R1154 MIN LINE WIDTH=1MM
DAC_OUT 1
3.32K2 1
3.32K2 VOLTAGE=8V =PP24V_BLC_LEDS 6
45 20 NET PHYSICAL TYPE=POWER
1% 1% CRITICAL
1/16W 1/16W CRITICAL
MF-LF
402
MF-LF
402
TP1181
1
L1143 1 5MM
D1108
A 100UH-2.1A 2MM
HIGH VOLTAGE DO-214AB STR0_+ 9 48
TH-TP50
C1102 R1155 HV9982 1 2 BL LFD01 2 MIN LINE WIDTH=1MM
0.1UF CRITICAL HIGH VOLTAGE
DAC_DIV 100K 2 CDRH127-SMMIN NECK WIDTH=0 2MM STR0 NET SPACING TYPE=1 5MM
1 2 1
1 C1155 1 C1157 1 C1158 1 C1161 4
S310 1 C1106
1 C1191
1% 1.0UF STR0_-
10% 1/16W 0.1UF 0.1UF 0.1UF 0.1UF 0.022UF
NO STUFF 10%
100V MIN LINE WIDTH=1MM
9 48
16V MF-LF 10% 10% 10% 10% 10% 2 PEN MIN NECK WIDTH=0 2MM
D
X7R-CERM
402 HV9982
402
MIN LINE WIDTH=1MM
50V
2 X7R
603-1
2 50V
X7R
603-1
2 50V
X7R
603-1
2 50V
X7R
603-1
D CRITICAL
Q1125
2 100V
CERM
0805
9863-ECW
STR0
HIGH VOLTAGE
NET SPACING TYPE=1 5MM D
BL_GATE0 G FDD3860
9
R1189
1
S TO-252
R1125
STR0 1.00M2
P1V024_VREF 1.00M2 BL_OVP_STR0 1 4
HV9982 9 PP8V BLC VREG 1
9
1%
1 C1182
3 MIN NECK WIDTH=0 2MM 1000PF
R1111 R1112 1%
1/8W STR0
R1123 R1195 R1192 1/8W STR0
MF-LF
NO STUFF
10%
100V
D CRITICAL
=PP3V3_S5_BLC 1.5K 2 4.7K 2 MF-LF 27.4K2 27.4K2 805 2 X7R
9 6
1 V_CREF0 1 805
BL_FS0 1
0.39 2 1 1
603 Q1126
1% 1% BL CS0 1% 1% BL FLT0 1 G FDD3860
1 C1148 1/16W
MF-LF
1 C1160 1/16W
MF-LF
9
1%
1/4W
1/8W
MF-LF
1/8W
MF-LF 1 C1101
9
S TO-252
STR0
402 0.1UF 402 1 MF 805 805
0.1UF 10% NO STUFF C1199 1206 1000PF
10% 50V 10%
50V
2 X7R
2 X7R
603-1
150PF
5% R1124
STR0 100V
2 X7R 3 R1194
R1191 2 1.24 2
603-1
1.5K 2
PP1112
1P0-BOT
50V
CERM 1
0.39 2 603
STR0
9 BL_FDBK0 1
(24VOLT) 402
1
R1101 R1102 1
SM
PP STR0 1%
1%
1/4W
1%
1/16W 1
1.5K 2 V_CREF1 1
4.7K 2 HV9982 1/4W
MF ADC_STR0_V
MF-LF
1206
OUT 20 45
P2V0 MF-LF 1206
402
HV9982
1%
1/16W 1 C1170 1%
1/16W
PP1113
1P0-BOT
STR0 NET SPACING TYPE=MICROCTLR STR0
MF-LF MF-LF SM
402 0.1UF 402 1 CRITICAL
10% PP CRITICAL
3 6 CRITICAL
TLV341 R1190 2 50V
X7R
NO STUFF HV9982 L1141 1 5MM
D1106
V+ SOT563 100UH-2.1A 2MM STR1_+ 9 48
4
5.23K2
1 TP1125
1
603-1
1 2
HIGH VOLTAGE DO-214AB
1 2
MIN LINE WIDTH=1MM
U1103 A BL LFD1 MIN NECK WIDTH=0 2MM
1% TH-TP50 R1103 R1104 CRITICAL CDRH127-SMMIN NECK WIDTH=0 2MM CRITICAL
HIGH VOLTAGE
NET SPACING TYPE=1 5MM
45 39 P5VP3V3_VREF 2 1/16W HV9982 1.5K 2 4.7K 2
IN V- 5 MF-LF
402
1 V CREF2 1 1 C1188 4 S310STR1 1 C1108 1 C1193
1
TP1124 1% 1% 1.0UF 0.022UF 1.0UF STR1_- 9 48
1
A 1/16W 1 C1171 1/16W 10%
100V D CRITICAL
NO STUFF
10% 10% MIN LINE WIDTH=1MM
R1122 MF-LF
TH-TP50 HV9982 402 0.1UF
10%
MF-LF
402
2 PEN
9863-ECW Q1123 2 100V
CERM
100V
2 PEN MIN NECK WIDTH=0 2MM
HIGH VOLTAGE
1
10K 2
HV9982 50V NO STUFF 0805 9863-ECW NET SPACING TYPE=1 5MM
2 X7R 9 BL_GATE1 1 G FDD3860 STR1
1%
1/10W
603-1
R1197 S TO-252
STR1 R1128
1.00M2
33
30
C PWR_INV_ON MF-LF
R1107 1.00M2 BL_OVP_STR1 1
C
8
IN 9 4
603
10K HV9982 9 PP8V BLC VREG 1
BL_FS1 3 MIN LINE WIDTH=0 5MM 1%
1 C1183
NO STUFF1000PF
VDD1
1 2
VDD
VDD2
VDD3
VIN
1%
1%
1/8W STR0
R1126 R1106 R1100 1/8W STR1
MF-LF 10%
100V
D CRITICAL
MF-LF 27.4K2 27.4K2 805 2 X7R
6 =PP3V3_S5_BLC
1/10W
MF-LF HV9982
805
1
0.39 2 1 1
603 Q1127
9
PWM_STR0
603 0
R1135 BL CS1 1% 1% BL FLT1 1 G FDD3860
20 IN 1 2 PWMD1 17 PWMD1 GATE1 40 BL_GATE0 9
9
1% 1/8W 1/8W
9
TO-252
PWM_STR1 603 1
0
2 R1132 PWMD2 18 PWMD2 C1105 1
1/4W MF-LF MF-LF 1 C1107 S
1 C1100 20 IN
PWM_STR2 603 1
0
2 R1133 PWMD3 19 PWMD3 CRITICAL
CS1 3 BL CS0 9
150PF
MF
1206
805 805
1000PF
10%
STR1
0.1UF 20 IN
5% 100V 3 R1105
10%
2 16V
603
R1196 OVP1 7 BL_OVP_STR0 9 50V 2 R1127
STR1 2 X7R
1.24 2
X7R-CERM
402
R1110 10K HV9982 6 REF1 U1115 CERM
402 1
0.39 2 603
STR1
9 BL_FDBK1 1
1
10K 2
HV9982 1 2
HV9982 FLT1 2 BL_FLT0 9
STR1 1%
13 REF2 1% 1/4W
1% QFN 1/4W MF-LF
5
1% 1/10W 25 REF3 FDBK1 5 BL_FDBK0 9 MF ADC_STR1_V 1206
20 IN BL_ONOFF 1 SN74LVC1G08
SOT23-5 R1134 1/10W
MF-LF
MF-LF
603 1206 OUT 20 45
(4)
STR1
0 603
STR1
NET SPACING TYPE=MICROCTLR
DP_VIDEO_ON 2
U1101 4 RBL_EN1
603
2 BL_EN 10 EN GATE2 35 BL_GATE1 9
20 IN
21 HV9982 CS2 37 BL_CS1 9
CRITICAL
CRITICAL
3 HV9982
STR_CLK 23 CLK L1142 1 5MM
D1107
OVP2 14 BL_OVP_STR1 9 100UH-2.1A 2MM
HIGH VOLTAGE DO-214AB
STR2_+ 9 48
MIN LINE WIDTH=1MM
COMP1 4 COMP1 1 2 BL_LFD2 1 2 MIN NECK WIDTH=0 2MM
FLT2 36 BL_FLT1 9 HIGH VOLTAGE
COMP2 12 COMP2 CDRH127-SMMIN NECK WIDTH=0 2MM NET SPACING TYPE=1 5MM
NOSTUFF CRITICAL
COMP3 BL_FDBK1 4 S310
R1109
27 COMP3 FDBK2 38 9
STR2
1 C1109 1 C1195 STR2_-
0.022UF 1.0UF 9 48
STRCLK1 1
0 2 SKIP BL_GATE2
D CRITICAL 10% 10% MIN LINE WIDTH=1MM
20 IN 15 SKIP GATE3 31 9
2 100V 100V
2 PEN HIGH VOLTAGE
5% Q1124 CERM
0805 9863-ECW NET SPACING TYPE=1 5MM
1/10W
MF-LF
1 C1118 1 C1119 1 C1120 1 C1156 20 S1
CS3 28 BL_CS2 9
9 BL_GATE2 1 G FDD3860 STR2
603 33NF 33NF 33NF 2200PF S TO-252 R1131
HV9982 10%
2 25V
10%
2 25V
10%
2 25V
5%
2 50V
21 S2 OVP3 24 BL_OVP_STR2 9 R1108 STR2 1.00M2
CERM CERM CERM CERM 1.00M2 BL_OVP_STR2 1 4
402 402 402 603 FLT3 29 BL_FLT2 9
9 PP8V_BLC_VREG 1
3 MIN LINE WIDTH=0 5MM
9
1% STR2
1 C1184
R1160 HV9982 HV9982 HV9982 RAMP 16 RAMP 1% MIN NECK WIDTH=0 2MM
R1121 R1119 1/8W NO STUFF1000PF
10% D
B 1
10K 2
HV9982 FDBK3 26 BL_FDBK2 9
1/8W STR0
MF-LF BL_FS2 R1129 STR2 27.4K2 27.4K2
MF-LF
805 100V
2 X7R
CRITICAL
B
22 805 0.39 2 1 1 Q1128
39 GND1
GND2
32 GND3
NC 603
1% NC 1
G
11 GND
THRM 9 BL_CS2 1% 1% 9 BL_FLT2 1 FDD3860

1/10W
MF-LF PAD 1%
1/4W
1/8W
MF-LF
1/8W
MF-LF
1 C1115 S TO-252
603
C1113 1 MF 805 805 1000PF
41
10% STR2
C1159
34
1 1206
150PF 100V
2700PF 5%
50V R1130
2 X7R
603
3 R1120
5% CERM 2 STR2 1.24 2
HV9982 50V
2 CERM 402 1
0.39 2 STR2 9 BL_FDBK2 1
805 1%
STR2 1% ADC_STR2_V OUT 20 45 STR2 1/4W
1/4W MF-LF
MF NET SPACING TYPE=MICROCTLR 1206
1206
20 OUT STR0 SENSE

R1113 R1116
1
1.5K 2 3.32K2
1
1% HV9982 1% HV9982
1/16W 1/16W
MF-LF MF-LF
20 OUT STR1_SENSE 402 402
CRITICAL
R1114 R1117
1
1.5K 2 3.32K2
1
J1115
4530K-F12N-01X
1% HV9982 1% F-RT-SM
1/16W 1/16W HV9982 9 PAD 14
MF-LF MF-LF
20 OUT STR2_SENSE 402 402
STR0_+ 1
R1115 R1118 48 9
2
1
1.5K 2 3.32K2
1
48 9 STR0C
48 9 STR1_+ 3
1% 1% HV9982
1/16W HV9982 1/16W 48 9 STR1C 4
MF-LF MF-LF
402 402 STR2 + 5
A (ENTERY,2.0MM PITCH)
(GOLD-PIN, BLACK)
48 9
48 9 STR2C 6 SYNC MASTER=MASTER SYNC DATE=N/A A

48 9 STR0C 7 PAGE TITLE
48 9 STR0_- 8
9
LED BL DRIVER
48 9 STR1C DRAWING NUMBER SIZE
48 9 STR1_- 10
48 9 STR2C 11 REVISION
R
48 9 STR2_- 12 C.0.0
9 PAD 13 THE INFORMATION CONTAINED HEREIN IS THE
11 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D 48 PP5V_CAM_FILT CRITICAL D
J1204
VOLTAGE=5V 53261-8607
M-RT-SM
8
L1204
120-OHM
CAMERA
CAMERA L701-SM
SYM_VER 1 1
46 31 USB_CAMERA_DM 3 4 48 46 CAM_DM 2
IN
48 46 CAM_DP 3
4
46 31 USB_CAMERA_DP 2 1
IN 5
6
7
PP5V_CAM_FET L1205
FERR-120-OHM-1.5A
VOLTAGE=5V 1 2
0402
CAMERA 1 C1208 1 C1207
1 2 5 6 7 0.1UF 100PF
10% 5%
CRITICAL 2 16V 2 50V
X7R-CERM CERM
402 402
Q1204 CAMERA CAMERA
FDMA510PZ
35 CAM_GATE 3 MICROFET
OUT
C 1
C
R1206 R1207 4 8 CAMERA =PP5V S5 CAMFET 6
10K 1
100K 2
5%
1/16W STUFF R1210 AND R1214 FOR FW CONTROL
MF-LF 5%
402 1/16W CAMERA STUFF C1214, R1212, Q1206, R1211 FOR HW CONTROL
2CAMERA MF-LF
CAM SW GATE
402 1 C1209
10UF
20%
10V
2 X5R
3
805
Q1205 CAMERA
2N7002E-X-G
SOT23-3 1
CAMERA
2
R1214
0
CAM_ON_GATE2 1 2 PWR_CAM_ON IN 20
5%
1/16W
1
R1210 MF-LF
402
100K
5%
1/16W
MF-LF
2 402 CAMERA
PP1202
1P0-BOT
B SM
PP
1 B
PP1203
1P0-BOT
SM
1
PP
L1206
FERR-120-OHM-0.3A
35 =I2C_ALS_SDA 1 2 45 I2C_FALS_SDA
BI
CAMERA 0402
L1207
FERR-120-OHM-0.3A
35 =I2C_ALS_SCL 1 2 45 I2C_FALS_SCL
IN
0402
CAMERA

PAGE TITLE
CAMERA/ALS
DRAWING NUMBER SIZE

REVISION
R
C.0.0
12 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
T29 JTAG AND DEBUG
AUDIO ALIASES SYSTEM MICRO JTAG

11 6 =PP3V3_S5_JTAG
D I20
DEVELOPMENT
34 6 =PP3V3 S4 MCU D
20 IN AUDIO SHDN_L GPIO_SHUTDOWN_L 18
DEVELOPMENT
MAKE_BASE=TRUE
J1310
1 C1311 DEVELOPMENT
I89 STMM-110-02-T-D-SM-K-TR 0.1UF J1350 1
R1350
M-ST-SM
10% FTSH-105-01-LM-DV-K 10K
19 IN AUD_USB_VBUS USB_VBUS 12 2 16V
X7R-CERM
M-ST-SM 5%
MAKE_BASE=TRUE 1 2 402 1 2 1/16W
TCMCU SWDIO BI MF LF 34
20 LPC2144_JTAG_TRST_L 3 4 JTAG 3 4 2
402
TCMCU SWCLK OUT 34
LPC2144 JTAG TDI 5 6 5 6
20 TCMCU_PROG_SWO
20 LPC2144 JTAG TMS 7 8 7 8
I23 NC
LPC2144_JTAG_TCK 9 10 9 10
20 IN UART MLB2AUDIO UART_RXD 18
20 TCMCU_RESET_L OUT 34
MAKE_BASE=TRUE 20 LPC2144_JTAG_RTCK 11 12
I24 20 LPC2144_JTAG_TDO 13 14
20 IN UART_AUDIO2MLB AUD_161_UART_TXD 12 18
20 LPC2144_RESET_UC_L 15 16
MAKE_BASE=TRUE
17 18
I25 NC
19 20
21 IN I2S SD0 ADAV4601 SDIN0 14 NC
MAKE_BASE=TRUE
I26
21 IN I2S_WS ADAV4601_LRCLK0 14
MAKE_BASE=TRUE
I27
21 I2S_MCLK TP_AUD_161_I2SI_MCLK
PP1301
1P0-BOT
IN
MAKE_BASE=TRUE SM
I86
1
PP PLACE TOP SIDE
NEAR U1400 AUDIO JTAG
11 6 =PP3V3_S5_JTAG
21 IN I2S SCLK ADAV4601 BCLK0 14 =PP3V3_S0_T29P
MAKE_BASE=TRUE 24 23 7 6
1K PU FOR TDO OPEN DRAIN DRIVER
DEVELOPMENT
I28 NOSTUFF
21 20 IN AUDIO_ON
MAKE_BASE=TRUE
DP_AUDIOON 14 18
J1320
1 C1321
0.1UF
C I29
STMM-110-02-T-D-SM-K-TR
M-ST-SM
10%
16V
2 X7R-CERM
R1360
10K
1 1
R1361 R1362
10K 1K
1 1
R1363
10K
C
1 2 402 5% 5% 5% 5%
21 IN AUDIO_MUTE_L DP_MUTE_L 14 18
1/16W 1/16W 1/16W 1/16W
MAKE_BASE=TRUE 18 12 AUD_161_JTAG_TRST_L 3 4 JTAG MF LF MF LF MF LF MF LF
402 402 402 402
I40 12 AUD_161_JTAG_TDI 5 6 2 2 2 2
46 31 IN USB_AUDIO_DM USB_DM 12 AUD_161_JTAG_TMS 7 8

12
MAKE_BASE=TRUE
12 AUD 161 JTAG TCK 9 10 42 34 JTAG TBLT TCK JTAG T29P TCK OUT 23
I43 IN
MAKE BASE=TRUE
TP_AUD_161_JTAG_RTCK 11 12
46 31 IN USB_AUDIO_DP USB_DP 12
MAKE_BASE=TRUE 12 AUD_161_JTAG_TDO 13 14 42 34 JTAG_TBLT_TDI JTAG_T29P_TDI OUT 23
IN
MAKE BASE=TRUE
18 12 AUD_161_RSTN_IN 15 16
17 18 JTAG_TBLT_TDO JTAG_T29P_TDO
NC 42 34 OUT
MAKE BASE=TRUE
IN 23
19 20
NC
JTAG_TBLT_TMS JTAG_T29P_TMS OUT 23
MAKE BASE=TRUE
34 IN =JTAG_TBLTTC_TMS
42 IN =JTAG_TBLTA_TMS
B MOUNTING HOLES J9000 TETHERED CABLE CLAMP STANDOFFS B
CRITICAL
SD1300
ZT1301 ZT1307 STDOFF-5.8OD3.52H-TH-0.90-1.82
8P0R4P5-NSP TH CRITICAL
1
1 1
SD1302
SL-5.5X4.5-8CIR-NSP STDOFF-5.8OD3.52H-TH-0.90-1.82
APN: 860-1449 1
ZT1302 ZT1303
8P0R4P5-NSP TH
1 1
SL-5.5X4.5-8CIR-NSP
ZT1300 ZT1304 CRITICAL

8P0R4P5-NSP
1
TH SD1301
1 STDOFF-5.8OD3.52H-TH-0.90-1.82 CRITICAL
SL-5.5X4.5-8CIR-NSP
1
SD1303
ZT1305 STDOFF-5.8OD3.52H-TH-0.90-1.82
TH
1 1
SL-5.5X4.5-8CIR-NSP
ZT1306
TH
1
A SL-5.5X4.5-8CIR-NSP
SYNC MASTER=K59 SYNC DATE=08/22/2010 A
PAGE TITLE
DEBUG, MISC & JTAG

DRAWING NUMBER SIZE

REVISION
R
C.0.0
13 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUD_161_CORE_VDD 12
12.000 MHZ CRYSTAL VOLTAGE=1 8V
APN 197S0264
L1400
USB AUDIO CODEC L1401
AUD_161_XTALH_IN 12 AUD_161_XTALH_OUT 12 FERR-220-OHM

VOLTAGE=3 3V
APN 353S2320 PLACE C1406 NEAR FLASH_VDD_HV PIN FERR-220-OHM
CRITICAL 1 2 1 2
19 18 14 13 12 =PP3V3_AUDIO_DIGITAL AUD_161_IO_VDD PP1V8_AUDIO_DIGITAL 12 13 14
Y1400
SM-3.2X2.5MM
0402 0402
12.000MHZ-30PPM-10PF 1 C1400 1 C1401 1 C1402 1 C1403 1 C1404 1 C1405 1 C1406 1 C1407

1 3
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF
20% 10% 10% 10% 10% 10% 10% 20%
2 4 10V 16V 16V 16V 16V 16V 16V 6.3V
2 X5R 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X5R
1 C1428 1 C1429 L1405
805 402 402 402 402 402 402 603
D13
A10
22PF 22PF VOLTAGE=3 3V
E1
N8
L1
FERR-1000-OHM MIN LINE WIDTH=0 20MM
L1408
D
5%
50V
2 CERM
5%
50V
2 CERM 14
PP3V3_AUDIO_ANALOG 1 2
MIN NECK WIDTH=0 15MM VOLTAGE=3 3V
MIN LINE WIDTH=0 40MM FERR-1000-OHM D
VDDE0
VDDE1
VDDE2
VDDI0
VDDI1
402 402 12 MIN NECK WIDTH=0 20MM
13
17 16 15 0402 NOSTUFF AUD_161_DAC_VDD 1 2 PP3V3_AUDIO_ANALOG 12 13 14 15 16 17
1 C1434 1 C1435 OMIT_TABLE
NOSTUFF 0402
10UF 0.1UF 1 C1410 1 C1411
20% 10% AUD_161_XTALH_IN J1 XTALH_IN CRITICAL XTALL_IN G1
10V
2 X5R
16V
2 X7R-CERM
12
10UF 0.1UF
12 AUD_161_XTALH_OUT H1 XTALH_OUT U1400 XTALL_OUT F1 TP_AUD_161_XTALL_OUT NC 20% 10%
805 402 2 10V 2 16V
H2 E2 X5R X7R-CERM
TIE PNX0161_PSU_STOP LOW
15 14 13 12
18 17 16
GND_AUDIO_CODEC 12 AUD_161_XTAL_VDD XTALH_VDDA18 PNX0161 XTALL_VDDA18 AUD_161_XTAL_VDD 12
805 402
IF USING INTERNAL 1.8 &

L1406 VOLTAGE=1 8V
K2 XTALH_VSSA TFBGA XTALL_GNDA G2 GND AUDIO CODEC 12 13 14 15 16 17 18
MIN NECK WIDTH=0 20MM VOLTAGE=3 3V
3.3 V SUPPLIES, HIGH IF AUD_161_JTAGSEL_ARM M3 JTAGSEL_ARM C13 AUD_161_I2C_SDA
14 13 12 PP1V8_AUDIO_DIGITAL 1 2 18
M4 JTAG_TDI
I2C_SDA
C12
12 45 MIN LINE WIDTH=0 20MM
MIN NECK WIDTH=0 15MM R1417
USING EXTERNAL SUPPLIES 0402 11 AUD_161_JTAG_TDI I2C_SCL AUD_161_I2C_SCL 12 45 240
N2 JTAG_TCK AUD_161_DAC_VREF 1 2 PP3V3_AUDIO_ANALOG 12 13 14 15 16 17
11 AUD 161 JTAG TCK NOSTUFF
1 C1424 1 C1425 AUD 161 JTAG TMS N3 JTAG_TMS UART_TXD K12 AUD_161_UART_TXD 11 18 CRITICAL 5%
1/16W
10UF 0.1UF 11
UART_RXD J12 AUD_161_UART_RXD 18
1
C1408 1 C1409 MF-LF
20% 10% AUD 161 JTAG TRST L M1 JTAG_TRST_N 402
6.3V
2 X5R
16V
2 X7R-CERM
18 11
47UF 0.1UF
11 AUD_161_JTAG_TDO M5 JTAG_TDO DAC_VDDA33 B10 20% 10%
603 402 16V
A9 2 6.3V 2 X7R-CERM
DAC_VREFP TANT-POLY
AUD 161 ADC MIC A4 ADC_MIC CASE-A4 402
L1407 VOLTAGE=3 3V
NC
18
TP AUD 161 ADC VINL A2 ADC_VINL

DAC_VREFN B9 GND_AUDIO_CODEC 12 13 14 15 16 17 18
MIN NECK WIDTH=0 20MM HP_OUTL A5 AUD_161_HP_OUTL 12
NC TP_AUD_161_ADC_VINR A1 ADC_VINR PP3V3_AUDIO_ANALOG 12 13 AUD_161_HP_VREF 12
17 16 15 14 13 12 PP3V3_AUDIO_ANALOG 1 2 HP_OUTR A7 AUD_161_HP_OUTR 12 14 15 16 17 MIN LINE WIDTH=0 20MM
12 AUD_161_ADC_VREF B1 ADC_VREF NOSTUFF MIN NECK WIDTH=0 15MM
0402 NOSTUFF HP_FCL B5 AUD_161_HP_FCL 12
1 C1426 1 C1427
C2 ADC_VREFN
HP_FCR A8 AUD 161 HP FCR
1 C1418 1 C1419 1 C1420 1 C1421
AUD_161_ADC_VREFP A3 ADC_VREFP
12
10UF 0.1UF 33PF 0.68UF
10UF 0.1UF D1 HP_VDDA33 B6 20%
10V
10%
16V
5%
50V
10%
6.3V
20% 10% AUD_161_ADC_VDDA18 ADC_VDDA18 2 X5R 2 X7R-CERM 2 CERM 2 CERM
2 10V 2 16V HP_GNDA B7
X5R X7R-CERM AUD_161_ADC_VDDA33 C1 ADC_VDDA33 805 402 402 402
805 402
HP_OUTC A6 TP_AUD_161_HP_OUTC NC GND_AUDIO_CODEC 12 13 14 15 16 17 18
18 17 16 15 14 13 12 GND AUDIO CODEC D2 ADC_GNDA
HP_VREF B8 AUD_161_HP_VREF 12
19 18 13 =PP5V_AUDIO_DIGITAL N9 PSU_VBUSA N1 MIN LINE WIDTH=0 20MM R1424

N12 DAI_DATA AUD 161 I2SI DATA 12 MIN NECK WIDTH=0 15MM 100
PSU_VBUSB N4
1 2 USB_VBUS IN 11
C 1 C1416
0.1UF
1 C1417
0.1UF
=PP3V3_AUDIO_DIGITAL
NC
M13
TP AUD 0161 LX VOUT33N10
PSU_VOUT33
PSU_LX_VOUT33
DAI_WS
DAI_BCK N6
AUD_161_I2SI_WS
AUD_161_I2SI_BCLK
12
12
5% 1/16W
MF-LF 402
R1423
C
10%
16V
2 X7R-CERM
10%
16V
2 X7R-CERM
1 C1422 M9 PSU_VSS1 DAO_DATA N7 AUD 161 I2SO DATA 1
1.5K 2
USB DP PU 3 D S 2 =PP3V3 AUDIO DIGITAL
0.1UF 12 12 13 14 18 19
402 402 10% M10 PSU_VSS2 DAO_WS M7 AUD_161_I2SO_WS 12 1% 1/16W
16V
2 X7R-CERM
402 NC TP_AUD_161_LX_VOUT18 N11 PSU_LX_VOUT14 DAO_BCK M6 AUD_161_I2SO_BCLK 12
MF-LF 402
G
Q1400
14 13 12 PP1V8_AUDIO_DIGITAL N13 PSU_VOUT14 DAO_CLK N5 AUD_161_I2SO_MCLK 12
NTR1P02L
1 SOT23-3-HF
L12 PSU_CLEAN
1 C1423 M11 PSU_GND
USB_VBUS A13 AUD_161_USB_VBUS
0.1UF USB_CONNECT_N B13 AUD_161_USB_CONNECT_L
10% L13 PSU_PLAY
16V
2 X7R-CERM USB_DP
46 A12 AUD_161_USB_DP
AUD 161 PSU STOP K13
402 PSU_STOP
USB_DM
46 A11 AUD_161_USB_DM R1421
K1 18
RSTN_IN J13
1 2 USB_DP BI 11
J2 GPIO_0 AUD_161_GPIO_0 18
NC TP_AUD_161_CLK_OUT CLK_OUT G12 AUD_161_GPIO_1
1% 1/16W
MF 402
GPIO_1 18
AUD_161_CORE_VDD E12 H13 AUD_161_GPIO_2

AUD_161_RSTN_IN
12 FLASH_VDD_HV GPIO_2
G13
18
R1422
18 11 IN B2 GPIO_3 AUD_161_GPIO_3 18
1
18 2
H12 USB_DM BI 11
B12 GPIO_4 AUD_161_GPIO_4 18
F13 1% 1/16W
M2 GPIO_5 AUD_161_GPIO_5 18 MF 402
NOSTUFF N/A
GPIO_6 F12 AUD_161_GPIO_6
R14301 1
R1431 M12
GPIO_7 E13 AUD_161_GPIO_7
12 18
0 100K 12 18
5% 5%
1/16W 1/16W MIC_VREFSUP B4 AUD_161_ADC_VREF 12
MF-LF MF-LF MIN LINE WIDTH=0 20MM
PLACE C1412 & C1413 NEAR XTALL_VDDA18 PIN 402 2 2 402 MIC_OUTSUP B3 AUD 161 MIC OUTSUP 18 MIN NECK WIDTH=0 15MM
VSSE0
VSSE1
VSSE2
VSSI0
VSSI1
PLACE C1414 NEAR XTALH_VDDA18 PIN MIN NECK WIDTH=0 20MM
L1402 VOLTAGE=1 8V 1 C1436 1 C1437

MIN NECK WIDTH=0 20MM 0.1UF 0.1UF
F2
M8
D12
L2
B11
14
12 PP1V8_AUDIO_DIGITAL 1 2 AUD_161_XTAL_VDD 12
10% 10%
13 16V 16V
2 X7R-CERM 2 X7R-CERM
B 0402
1 C1412 1 C1413 1 C1414
402 402 B
10UF 0.1UF 0.1UF
20% 10% 10% GND AUDIO CODEC 12 13 14 15 16 17 18
6.3V 16V 16V
2 X5R 2 X7R-CERM 2 X7R-CERM
603 402 402
PLACE C1436 NEAR MIC_VREFSUP PIN (B4)
PLACE C1437 NEAR ADC_VREF PIN (B1) CRITICAL
C1432
330PF
12 AUD_161_HP_FCL 1 2
5%
50V
COG
402
AUD_161_HP_OUTL OUT 12
=PP3V3_AUDIO_DIGITAL 12 13 14 18 19
CRITICAL
C1433
330PF
BIT_BANG_I2C BIT_BANG_I2C 1 2
AUD_161_HP_FCR
R14251 1
R1426 R14001 1
R1401 =PP3V3_AUDIO_DIGITAL 12 13 14 18 19
12
47K 47K 1.5K 1.5K 5%

5% 5% 1% 1% 50V
1/16W 1/16W 1/16W 1/16W 1 1 1 COG
MF-LF MF-LF MF-LF MF-LF R1414 R1415 R1416 402
402 2 2 402 INTERNAL_I2C 402 2 2 402 47K 47K 47K AUD_161_HP_OUTR OUT 12
5% 5% 5%
R1402 =PP3V3_AUDIO_DIGITAL 12 13 14 18 19 1/16W 1/16W 1/16W
33 MF-LF MF-LF MF-LF
45 12 AUD_161_I2C_SDA 1 2 I2C_SDA BI 14 18 45 R1407 2 402 2 402 2 402
5% 1/16W
1
R1411 1
R1412 1
R1413 33
MF-LF 402 12 AUD_161_I2SO_DATA 1 2 ADAV4601_SDIN2 OUT 14
47K 47K 47K
5% 5% 5% 5% 1/16W
BIT_BANG_I2C 1/16W 1/16W 1/16W MF-LF 402
A R1404 MF-LF MF-LF MF-LF
18 12 AUD_161_GPIO_6 1
33 2
2 402 2 402 2 402 R1408
33 PAGE TITLE
A
AUD 161 I2SI DATA 12 12 AUD 161 I2SO WS 1 2 ADAV4601 LRCLK2 14
IN OUT
5% 1/16W
MF-LF 402 5% 1/16W
MF-LF 402
PNX0161 CODEC
INTERNAL_I2C DRAWING NUMBER SIZE
R1403 R1409 051-8774 D
33 AUD_161_I2SI_WS AUD_161_I2SO_BCLK 1
33 2 ADAV4601_BCLK2
Apple Inc. REVISION
45 12 AUD 161 I2C SCL 1 2 I2C SCL OUT 14 18 45 IN 12 12 OUT 14
R
5% 1/16W 5% 1/16W
MF-LF 402
C.0.0
MF-LF 402
NOSTUFF NOTICE OF PROPRIETARY PROPERTY: BRANCH
BIT_BANG_I2C R1410 THE INFORMATION CONTAINED HEREIN IS THE
R1405 1
33 2
AUD_161_I2SI_BCLK IN 12 12 AUD_161_I2SO_MCLK ADAV4601_MCLKI OUT 14 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
33
18 12 AUD_161_GPIO_7 1 2 5% 1/16W
MF-LF 402
14 OF 110
5% 1/16W SHEET
MF-LF 402 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.8 V REGULATOR PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

APN 353S2847
353S2847 1 HF MAX8860EUA18+G65 U1500
CRITICAL
VOLTAGE=1 8V
U1500 MIN LINE WIDTH=0 50MM R1504
MAX8860EUA18+ MIN NECK WIDTH=0 20MM
UMAX 0
19 18 14 13 12 =PP3V3 AUDIO DIGITAL 2 IN OUT1 1 MAX8860 OUT 1 2 PP1V8 AUDIO DIGITAL 12 14
D R1500
1K MAX8860_SHDNB 7
OMIT
SHDN*
OUT2 4 R1507 5%
1/10W
VOLTAGE=1 8V
MIN LINE WIDTH=0 50 MM
MIN NECK WIDTH=0 20 MM
D
1 2 100K 2 MF-LF
FAULT* 8 MAX8860_FAULTB 1 603
5% 5 SET
1/16W
MF-LF
CC 6 MAX8860_CC 1%
1/16W
402 1
R1501 GND MF-LF 1 C1503
C1500 1 C1501 1 10K 3 402
2.2UF
2.2UF 0.1UF 5% 1 C1502 20%
20%
10V
10%
16V 1/16W 33NF 2 10V
X5R-CERM
X5R-CERM 2 X7R-CERM 2 MF-LF 10% 402
402 402 2 402 25V
2 CERM
402
6/16 IT’S UNCLEAR IF ANALOG 3.3 V NEEDS TO COME UP WITH DIGITAL 3.3 V,
OR IF IT CAN COME UP INDEPENDENTLY (WITH 5.0 V)
ANALOG 3.3 COMES UP WITH DIGITAL 3.3 --> POPULATE R1506
ANALOG 3.3 COMES UP INDEPENDENTLY --> POPULATE R1502 3.3 V REGULATOR
APN 353S2147
L1500
FERR-120-OHM-1.5A
19 18 12 =PP5V_AUDIO_DIGITAL 1 2 CRITICAL
NOSTUFF 0402
U1501
C R1502
1
1K 2
VOLTAGE=5V
MAX8510EXK33+G65
SC70-5
VOLTAGE=3 3V
R1505
0
C
5%
MAX8510_IN 1 IN OUT 5 MAX8510_OUT 1 2 PP3V3_AUDIO_ANALOG 12 14 15 16 17
VOLTAGE=3 3V
1/16W 5% MIN LINE WIDTH=0 50 MM
MF-LF 1/10W MIN NECK WIDTH=0 20 MM
MAX8510_SHDN_L 3 SHDN* BP 4 MAX8510_BP
402
C1506 C1507 1 MF-LF
603
R1506 0.01UF 1UF
1K 1 1 2 10%
19 18 14 13 12 =PP3V3_AUDIO_DIGITAL 1 2 C1504 1 C1505 1 R1503 GND 10V 2
X5R
1UF 0.1UF 10K 2 10% 402-1
5% 5%
1/16W 10% 10% 1/16W 25V
MF-LF 10V 16V X7R
NOSTUFF X5R 2 X7R-CERM 2 MF-LF 402
402
402-1 402 2 402
R1508
0
1 2 GND_AUDIO_CODEC 12 14 15 16 17 18
VOLTAGE=0V
5% MIN LINE WIDTH=0 50MM
1/16W MIN NECK WIDTH=0 20MM
MF-LF
402
XW1501
SM
1 2 GND_AUDIO_SPKRAMP 15 16 17 18 48
VOLTAGE=0V
NET SPACING TYPE=AUDIO
B B
A A
PAGE TITLE
AUDIO DC-DC REGULATORS

DRAWING NUMBER SIZE

REVISION
R
C.0.0
15 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO SIGNAL PROCESSOR
APN 337S3285
L1601
FERR-220-OHM
ADAV4601_CORE_VDD 1 2 PP1V8_AUDIO_DIGITAL 12 13
0402
D 1 C1609
0.1UF
1 C1610
0.1UF
1 C1611
0.1UF
1 C1612
0.1UF
1 C1613
0.1UF
1 C1614
10UF
D
10% 10% 10% 10% 10% 20%
16V 16V 16V 16V 16V 6.3V
2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X5R
402 402 402 402 402 603
PLACE C1601 NEAR PIN 4 (ADC POWER SUPPLY)

PLACE C1602 & C1603 NEAR PINS 68 & 71, RESPECTIVELY (DAC POWER SUPPLIES)
L1600 ADAV4601_AVDD
PLACE
PLACE
C1604 & C1605 NEAR PIN 59 (HEADPHONE POWER SUPPLY)
C1606, C1607, & C1608 NEAR PIN 53 (PLL POWER SUPPLY) L1602
FERR-220-OHM 14 FERR-220-OHM
17 16 15 13 12 PP3V3_AUDIO_ANALOG 1 2 ADAV4601_IO_VDD 1 2 =PP3V3_AUDIO_DIGITAL 12 13 18 19
0402 0402
NOSTUFF
C1600 1 C1601 1 C1602 1 C1603 1 C1604 1 C1605 1 C1606 1 C1607 1 C1608 1 1 C1615 1 C1616
10UF 0.1UF 0.1UF 0.1UF 10UF 0.1UF 10UF 0.1UF 1000PF 0.1UF 10UF
20% 10% 10% 10% 20% 10% 20% 10% 5% 10% 20%
10V 16V 16V 16V 10V 2 16V 10V 2 16V 25V 2 16V 2 10V
X5R 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X5R X7R-CERM 2 X5R X7R-CERM 2 NP0-C0G 2 X7R-CERM X5R
805 402 402 402 805 402 805 402 402 402 805
GND_AUDIO_CODEC
53
59
68
71
14
21
31
40
51
29
18 17 16 15 14 13 12
4
PLACE R1604 AS CLOSE AS POSSIBLE TO U1601 PIN 33 AVDD DVDD ODVDD
NOSTUFF CRITICAL
R1604 U1601
1
0 2 ADAV4601
12 IN ADAV4601_MCLKI
TP ADAV4601 ADC INL 78 AUXIN1L LQFP AUXOUT1L 72 ADAV4601 TWTOUT L OUT 15
5% NC
TP_ADAV4601_ADC_INR 79 AUXIN1R AUXOUT1R 73 ADAV4601_TWTOUT_R
1/16W
MF-LF R1606 NC OUT 16
402 0 25
CRITICAL 18 11 IN DP AUDIOON 1 2 ADAV4601 SDIN3 SPDIF_IN0/SDIN3 AUXOUT3L 62 ADAV4601 WFROUT L OUT 15
C1632 5%
DP AUDIO CLOCKS 11 IN ADAV4601 LRCLK0 26 SPDIF_IN1/LRCLK0 AUXOUT3R 63 ADAV4601 WFROUT R OUT 16
18PF 1/16W
MF-LF ADAV4601 BCLK0 27
11 IN SPDIF_IN2/BCLK0
1 2 402
36 AUXOUT4L 64 ADAV4601_SUBOUT_L OUT 17
C 5%
50V
NC
NC
NO TEST
NO TEST
NC_ADAV4601_LRCLK1
NC_ADAV4601_BCLK1 35
SPDIF_IN3/LRCLK1
SPDIF_IN4/BCLK1
AUXOUT4R 65 TP_ADAV4601_SUBOUT_R
NC C
CERM CRITICAL 12 ADAV4601_LRCLK2 18 SPDIF_IN5/LRCLK2 HPOUT1L 57 TP_ADAV4601_HPOUT1L
402 IN NC
1
Y1600 USB AUDIO CLOCKS 12 IN ADAV4601_BCLK2 19 SPDIF_IN6/BCLK2 HPOUT1R 58 TP_ADAV4601_HPOUT1R
NC
24.576M
HC49-USMD ADAV4601_RESETB 50 RESET* PWM1A 42 NC_ADAV4601_PWM1A NO TEST
CRITICAL 2
18 IN
43 NC_ADAV4601_PWM1B
NC C1617 1 1 C1618 C1619 1 1 C1620 C1621 1 1 C1622
C1633 ADAV4601 XIN 33 MCLKI/XIN
PWM1B
44
NO TEST
NC 0.01UF
10%
0.01UF
10%
0.01UF
10%
0.01UF
10%
0.01UF
10%
0.01UF
10%
18PF PWM2A NC_ADAV4601_PWM2A NO TEST
NC 25V 25V 25V 25V 25V 25V
1 2 TP_ADAV4601_XOUT 34 45 NC_ADAV4601_PWM2B X7R 2 2 X7R X7R 2 2 X7R X7R 2 2 X7R
XOUT PWM2B NO TEST
NC 402 402 402 402 402 402
PWM3A 46 NC_ADAV4601_PWM3A NO TEST
5% 45 ADAV4601_I2C_SDA 16 SDA NC
50V PWM3B 47 NC ADAV4601 PWM3B NO TEST GND AUDIO CODEC 12 13 14 15 16 17 18
CERM NC
402 R1600 45 ADAV4601_I2C_SCL 17 SCL PWM4A 48 NC_ADAV4601_PWM4A NO TEST
NC
I2C_SDA 1
33 2 49 NC_ADAV4601_PWM4B
45 18 12 IN 37 SDO0/AD0 PWM4B NO TEST
NC
TP_ADAV4601_SDO0
5% NC
1/16W
15 PWM_READY 39 TP_ADAV4601_PWM_READY
NC
MF-LF ADAV4601_MUTEB MUTE*
402
22 SPDIF_OUT/SDO1 38 TP_ADAV4601_SDATA_OUT1
NC
ADAV4601_SDIN0
R1601 DP AUDIO DATA 11 IN
23
SDIN0
33 ADAV4601_SDIN1 SDIN1 MCLK_OUT 30 TP_ADAV4601_MCLK_OUT
NC
45 18 12 I2C_SCL 1 2
BI ADAV4601_SDIN2 24
USB AUDIO DATA 12 IN SDIN2
5% FILTD 67 ADAV4601_FILTD
1/16W
MF-LF 5
402
6 FILTA 1 ADAV4601_FILTA
R1603 7 VREF 2 ADAV4601_VREF
DP_MUTE_L 1
0 2 8
18 11 IN
9 ISET 80 ADAV4601_ISET
5%
1/16W NOSTUFF
MF-LF 10 PLL_LF 54 ADAV4601_PLL_LF
402
11
1
R1623 1
C1624 1 C1625 1
C1626 1 C1627 1 C1628 1 C1629
20.0K 47UF 0.1UF 47UF 0.1UF 10UF 0.1UF
R1605 12 NC 1% 20% 10%
16V 20% 10%
16V
20%
6.3V
10%
16V
0 1/16W 2 6.3V 2 X7R-CERM 2 6.3V 2 X7R-CERM 2 X5R 2 X7R-CERM
B 1
5%
2 60
61
MF-LF
2 402
TANT-POLY
CASE-A4 402
TANT-POLY
CASE-A4 402 603 402 B
1/16W
MF-LF 66 GND_AUDIO_CODEC 12 13 14 15 16 17 18
402
74
75
76
77
AGND DGND ODGND
3
55
56
69
70
13
20
32
41
52
28
18 17 16 15 14 13 12 GND_AUDIO_CODEC
CRITICAL
C1630 1 1 C1631
1000PF 0.1UF
5% 10%
25V 16V
NP0-C0G 2 2 X7R-CERM
402 402
XW1600
SHORT_L2_SM
TP_ADAV4601_PLL_FILT NC
1 2 1
R1602
2.0K
1%
NOSTUFF 1/16W
MF-LF
R1607 2 402
1
0 2
ADAV4601_AVDD 14
5%
1/16W
MF-LF
402
A NOSTUFF A
PAGE TITLE
R1608
1
0 2
SIGMA DSP
DRAWING NUMBER SIZE
5%
1/16W
MF-LF Apple Inc. 051-8774 D
402 REVISION
R
GND CONNECTIONS WERE ADDED TO ADDRESS EMI CONCERNS ON K59

C.0.0
16 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LEFT SPEAKER AMP PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
APN 353S2042 PART NUMBER
GAIN = 7.36 V/V (+17.33 DB) 155S0698 155S0554 L1700
FC = ~774 HZ (TWEETER), ~12 HZ (WOOFER)
155S0698 155S0554 L1701
155S0698 155S0554 L1702

19 17 16 =PP12V_AUDIO_DIGITAL
155S0698 155S0554 L1703
C1700 1 C1701 1 C1702 1 C1703 1 D
D 220UF
20%
220UF
20%
0.1UF
10%
25V
0.1UF
10%
25V
16V 2 16V 2 X5R 2 X5R 2
ELEC ELEC
SM-CASE-C1-HF SM-CASE-C1-HF 402 402
48 18 17 16 15 13 GND_AUDIO_SPKRAMP
AUD_LCHAMP_VS
16
27
30
VS PVDD AUD LCHAMP CPP
CRITICAL
U1700 1 C1709 L1700
MAX9736BETJ+ 0.1UF 220-OHM-25%-2.5A
MIN LINE WIDTH=0 20MM 10%
15 REG 22 50V
AUD LCHAMP VREG TQFN C1P MIN NECK WIDTH=0 15MM 2 X7R 1 2 SPKRAMP_LTWT_OUT_P
MIN LINE WIDTH=0 20MM 21 603-1 OUT 18 45 48
MIN NECK WIDTH=0 15MM 5 FBL CRITICAL C1N AUD LCHAMP CPN NET SPACING TYPE=AUDIO
15 AUD_TWTAMP_FBL 0603 MIN LINE WIDTH=0 6MM
IN
6 INL 3 MIN LINE WIDTH=0 20MM MIN NECK WIDTH=0 2MM
15 IN AUD_TWTAMP_INL BOOT AUD_LCHAMP_BOOT MIN NECK WIDTH=0 15MM CRITICAL
AUD_LCHAMP_COM 12 COM OUTL1+ 31 AUD_LTWT_P

L1701
45
220-OHM-25%-2.5A
MIN NECK WIDTH=0 15MM OUTL1- 1 MIN NECK WIDTH=0 20MM
15 AUD_WFRAMP_INL 18 INR 1 2 SPKRAMP_LTWT_OUT_N 18 45 48
IN OUT
19 FBR 32 MIN LINE WIDTH=0 60MM 0603 NET SPACING TYPE=AUDIO
15 IN AUD_WFRAMP_FBL OUTL2+ MIN NECK WIDTH=0 20MM MIN LINE WIDTH=0 6MM
2 MIN NECK WIDTH=0 2MM
20 OUTL2- 45 AUD_LTWT_N
17 16 14 13 12 PP3V3 AUDIO ANALOG MOD CRITICAL
4 MONO OUTR1+ 25 45 AUD LWFR P L1702
10 SHDN* OUTR1- 23 MIN LINE WIDTH=0 60MM
220-OHM-25%-2.5A
L1705 9 MUTE*
OUTR2+ 26
1 2 SPKRAMP_LWFR_OUT_P OUT 18 45 48
FERR-1000-OHM 11 REGEN 0603
OUTR2- 24 45 AUD LWFR N MIN NECK WIDTH=0 2MM
18 AUD_SPKRAMP_SHDN_L 1 2 MIN LINE WIDTH=0 60MM CRITICAL
IN
0402 NC1 7 L1703
C L1706
NC2
NC3
8
17 1 C1710
220-OHM-25%-2.5A
1 2 SPKRAMP LWFR OUT N 18 45 48
C
OUT
FERR-1000-OHM 0.1UF NET SPACING TYPE=AUDIO
R17001 R1701 C1704
1
100PF
1 1 C1705 C1706 1
100PF 1UF
1 C1707
1UF
1 C1708
1UF THM
10%
18 IN AUD_SPKRAMP_MUTE_L 1 2 100K 100K 2 50V
X7R
5% 5% 5%
50V
5%
50V
10%
10V
10%
10V
10%
10V AGND PGND PAD 603-1
0402 1/16W 1/16W CERM 2 2 CERM X5R 2 2 X5R 2 X5R
13
14
28
29
33
MF-LF MF-LF 402 402 402-1 402-1 402-1
402 2 2 402 CRITICAL CRITICAL CRITICAL CRITICAL
17 16 OUT AUD_SPKRAMP_SHDN_L_FILT C1711 1 1 C1712 C1713 1 1 C1714
17 16 OUT AUD_SPKRAMP_MUTE_L_FILT 1000PF 1000PF 1000PF 1000PF
5% 5% 5% 5%
25V 25V 25V 25V
NOSTUFF NP0-C0G 2 2 NP0-C0G NP0-C0G 2 2 NP0-C0G
402 402 402 402
R1750
0
18 17 16 14 13 12 GND_AUDIO_CODEC 1 2 GND_AUDIO_SPKRAMP 13 15 16 17 18 48
5%
1/16W
MF-LF
402
R1734 R1724
1
21K 2 1
21K 2
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 402
CRITICAL CRITICAL
C1734 C1724
120PF 120PF
1 2 1 2
B 5%
50V
CERM
5%
50V
CERM
B
402 402
C1730 R1731 C1720 R1721

1UF 0.015UF
2 1 1
13.7K2 1 2 13.7K2
1
14 IN ADAV4601 WFROUT L AUD WFRAMP L C AUD WFRAMP INL OUT 15 AUD WFRAMP FBL OUT 15 14 IN ADAV4601 TWTOUT L AUD TWTAMP L C AUD TWTAMP INL OUT 15 AUD TWTAMP FBL OUT 15
1% 1%
10% 1/16W 10% 1/16W
10V MF-LF 16V MF-LF
X5R 402 X7R 402
402-1 402
A A
PAGE TITLE
LEFT SPEAKER AMP

DRAWING NUMBER SIZE

REVISION
R
C.0.0
17 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RIGHT SPEAKER AMP PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
GAIN = 7.36 V/V (+17.33 DB) 155S0698 155S0554 L1800
FC = ~774 HZ (TWEETER), ~12 HZ (WOOFER)
155S0698 155S0554 L1801
155S0698 155S0554 L1802

155S0698 155S0554 L1803
C1800 1 C1801 1 C1802 1 C1803 1 D
D 220UF
20%
220UF
20%
0.1UF
10%
25V
0.1UF
10%
25V
16V 2 16V 2 X5R 2 X5R 2
ELEC ELEC
AUD_RCHAMP_VS
16
27
30
VS PVDD AUD RCHAMP CPP
CRITICAL
U1800 1 C1809 L1800
MAX9736BETJ+ 0.1UF 220-OHM-25%-2.5A
15 REG 22 50V
AUD RCHAMP VREG TQFN C1P MIN NECK WIDTH=0 15MM 2 X7R 1 2 SPKRAMP_RTWT_OUT_P
MIN LINE WIDTH=0 20MM 21 603-1 OUT 18 45 48
MIN NECK WIDTH=0 15MM 5 FBL CRITICAL C1N AUD RCHAMP CPN NET SPACING TYPE=AUDIO
16 AUD_TWTAMP_FBR 0603 MIN LINE WIDTH=0 6MM
IN
6 INL 3 MIN LINE WIDTH=0 20MM MIN NECK WIDTH=0 2MM
16 IN AUD_TWTAMP_INR BOOT AUD_RCHAMP_BOOT MIN NECK WIDTH=0 15MM CRITICAL
AUD_RCHAMP_COM 12 COM OUTL1+ 31 AUD_RTWT_P

L1801
45
220-OHM-25%-2.5A
MIN NECK WIDTH=0 15MM OUTL1- 1 MIN NECK WIDTH=0 20MM
16 AUD_WFRAMP_INR 18 INR 1 2 SPKRAMP_RTWT_OUT_N 18 45 48
IN OUT
19 FBR 32 MIN LINE WIDTH=0 60MM 0603 NET SPACING TYPE=AUDIO
16 IN AUD_WFRAMP_FBR OUTL2+ MIN NECK WIDTH=0 20MM MIN LINE WIDTH=0 6MM
2 MIN NECK WIDTH=0 2MM
20 OUTL2- 45 AUD_RTWT_N
17 15 14 13 12 PP3V3 AUDIO ANALOG MOD CRITICAL
4 MONO OUTR1+ 25 45 AUD RWFR P L1802
17 15 AUD_SPKRAMP_SHDN_L_FILT 10 SHDN* OUTR1- 23 MIN LINE WIDTH=0 60MM
220-OHM-25%-2.5A
IN
17 15 AUD_SPKRAMP_MUTE_L_FILT 9 MUTE* 1 2 SPKRAMP_RWFR_OUT_P 18 45 48
IN 26 OUT
11 OUTR2+ 0603
REGEN 24 MIN LINE WIDTH=0 6MM
OUTR2- 45 AUD RWFR N MIN NECK WIDTH=0 2MM
MIN LINE WIDTH=0 60MM CRITICAL
NC1 7 L1803
C NC2
NC3
8
17 1 C1810
220-OHM-25%-2.5A
1 2 SPKRAMP RWFR OUT N 18 45 48
C
OUT
C1804 1 1 C1805 C1806 1 1 C1807 1 C1808 0.1UF 0603 MIN LINE WIDTH=0 6MM
10% MIN NECK WIDTH=0 2MM
100PF 100PF 1UF 1UF 1UF THM 2 50V
5% 5% 10% 10% 10% AGND PGND PAD X7R
50V 50V 10V 10V 10V 603-1
CERM 2 2 CERM X5R 2 2 X5R 2 X5R
13
14
28
29
33
402 402 402-1 402-1 402-1
CRITICAL CRITICAL CRITICAL CRITICAL
C1811 1 1 C1812 C1813 1 1 C1814
1000PF 1000PF 1000PF 1000PF
5% 5% 5% 5%
25V 25V 25V 25V
NOSTUFF NP0-C0G 2 2 NP0-C0G NP0-C0G 2 2 NP0-C0G
402 402 402 402
R1850
0
18 17 15 14 13 12 GND_AUDIO_CODEC 1 2 GND_AUDIO_SPKRAMP 13 15 16 17 18 48
5%
1/16W
MF-LF
402
R1834 R1824
1
21K 2 1
21K 2
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 402
CRITICAL CRITICAL
C1834 C1824
120PF 120PF
1 2 1 2
B 5%
50V
CERM
5%
50V
CERM
B
402 402
C1830 R1831 C1820 R1821

1UF 0.015UF
2 1 1
13.7K2 1 2 13.7K2
1
14 IN ADAV4601 WFROUT R AUD WFRAMP R C AUD WFRAMP INR OUT 16 AUD WFRAMP FBR OUT 16 14 IN ADAV4601 TWTOUT R AUD TWTAMP R C AUD TWTAMP INR OUT 16 AUD TWTAMP FBR OUT 16
1% 1%
10% 1/16W 10% 1/16W
10V MF-LF 16V MF-LF
X5R 402 X7R 402
402-1 402
A A
PAGE TITLE
RIGHT SPEAKER AMP

DRAWING NUMBER SIZE

REVISION
R
C.0.0
18 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SUBWOOFER SPEAKER AMP PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
GAIN = 7.36 V/V (+17.33 DB) 155S0698 155S0554 L1900
FC = ~12 HZ
155S0698 155S0554 L1901
C1900 1 C1901 1 C1902 1 C1903 1 D

D 220UF
20%
220UF
20%
0.1UF
10%
25V
0.1UF
10%
25V
16V 2 16V 2 X5R 2 X5R 2
ELEC ELEC
AUD_SUBAMP_VS
16
27
30
VS PVDD AUD SUBAMP CPP
U1900 1 C1909
MAX9736BETJ+ 0.1UF
15 REG 22 50V
AUD SUBAMP VREG TQFN C1P MIN NECK WIDTH=0 15MM 2 X7R
MIN LINE WIDTH=0 20MM 21 603-1
MIN NECK WIDTH=0 15MM 5 FBL CRITICAL C1N AUD SUBAMP CPN CRITICAL
AUD_SUBAMP_FBL
17 IN
AUD_SUBAMP_INL 6 INL BOOT 3 AUD_SUBAMP_BOOT
MIN LINE WIDTH=0 20MM L1900
17 IN MIN NECK WIDTH=0 15MM 220-OHM-25%-2.5A
AUD_SUBAMP_COM 12 COM OUTL1+ 31 45 AUD_SUB_P 1 2 SPKRAMP SUB_OUT_P 18 45 48
OUT
MIN LINE WIDTH=0 20MM 1 MIN LINE WIDTH=0 60MM 0603 NET_SPACING_TYPE=AUDIO
MIN NECK WIDTH=0 15MM 18 INR OUTL1- MIN NECK WIDTH=0 20MM MIN_LINE_WIDTH=0.6MM
17 IN AUD_SUBAMP_INR MIN_NECK_WIDTH=0.2MM
17 AUD_SUBAMP_FBR 19 FBR OUTL2+ 32
IN
OUTL2- 2
16 15 14 13 12 PP3V3 AUDIO ANALOG 20 MOD
4 MONO OUTR1+ 25
10 23 CRITICAL
AUD_SPKRAMP_SHDN_L_FILT SHDN* OUTR1-
16 15 IN
AUD_SPKRAMP_MUTE_L_FILT 9 MUTE*
L1901
16 15 IN
OUTR2+ 26 220-OHM-25%-2.5A
11 REGEN
OUTR2- 24 45 AUD SUB N 1 2 SPKRAMP SUB OUT N 18 45 48
OUT
0603
NET_SPACING_TYPE=AUDIO
7 MIN NECK WIDTH=0 20MM MIN_LINE_WIDTH=0.6MM
NC1 NC MIN_NECK_WIDTH=0.2MM
C NC2
NC3
8
17
NC
1 C1910 CRITICAL CRITICAL
C
NC
C1904 1 1 C1905 C1906 1 1 C1907 1 C1908 0.1UF C1911 1 1 C1912
10%
100PF 100PF 1UF 1UF 1UF THM 2 50V 1000PF 1000PF
5% 5% 10% 10% 10% AGND PGND PAD X7R 5% 5%
50V 50V 10V 10V 10V 603-1 25V 25V
CERM 2 2 CERM X5R 2 2 X5R 2 X5R NP0-C0G 2 2 NP0-C0G
13
14
28
29
33
402 402 402-1 402-1 402-1 402 402
GND_AUDIO_SPKRAMP 13 15 16 17 18 48
NOSTUFF
R1950
0
18 16 15 14 13 12 GND_AUDIO_CODEC 1 2
5%
1/16W
MF-LF
402
R1934 R1924
1
21K 2 1
21K 2
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 402
CRITICAL
C1934
120PF
1 2
B 5%
50V
CERM
B
402
C1930 R1931 R1921

1UF
2 1 1
13.7K2 1
21K 2
14 IN ADAV4601 SUBOUT L AUD SUBAMP L C AUD SUBAMP INR OUT 17 AUD SUBAMP FBR OUT 17 17 IN AUD SUBAMP FBR AUD SUBAMP INL OUT 17 AUD SUBAMP FBL OUT 17
1% 1%
10% 1/16W 1/16W
10V MF-LF MF-LF
X5R 402 402
402-1
A A
PAGE TITLE
SUBWOOFER SPEAKER AMP

DRAWING NUMBER SIZE

REVISION
R
C.0.0
19 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
L2001
FERR-1000-OHM
MIC CONNECTOR
APN 518S0666
18 17 16 15 14 13 12 GND_AUDIO_CODEC 1 2 CRITICAL
NOSTUFF 0402 J2007
R2003 53261-8603
R2035 1K M-RT-SM
0 12 AUD_161_ADC_MIC 1 2 AUD_MIC_IN_P_C 4
18 12 11 AUD_161_RSTN_IN 1 2 MIN LINE WIDTH=0 50MM
5% MIN NECK WIDTH=0 20MM
5%
1/16W
1/16W
MF-LF R2005 48 AUD MIC IN N CONN 1
MF-LF 402
1
0 2 2
402
C2000 1 MIN LINE WIDTH 0 40MM 48 GND_AUD_MIC_CONN
0.001UF
C2001 1
5%
VOLTAGE=0V 48 AUD_MIC_IN_P_CONN 3
10% 1UF 1/16W MIN LINE WIDTH=0 50MM
50V 10% MF-LF MIN NECK WIDTH=0 20MM
CERM 2 10V
R2036 X5R 2
402
D 19 18 14 13 12 =PP3V3_AUDIO_DIGITAL 1
0 2 JTAG_TRST_N_INP
402 402-1
L2000
5
D
5% R2004 FERR-1000-OHM
1/16W
AUD 161 MIC OUTSUP
2.2K 2 AUD MIC IN P L 1 2
BAT54XV2T1
MF-LF 12 1
D2000
R20011 1
R2034 5% 0402
SOD-523
2
1/16W CRITICAL
4.7K 10K MF-LF
402
CRITICAL 2 2
CRITICAL
5% 5%
1/16W 1/16W
C2002 1 1 C2005 C2003 1 DZ2001 DZ2000
1
MF-LF MF-LF
402 2 6.8V-100PF 6.8V-100PF
2 402 33PF 2.2UF 33PF 402 402
5% 20% 5%
50V 10V 50V
CERM 2 2 X5R-CERM CERM 2
402 402 402 1 1
12 AUD_161_JTAGSEL_ARM AUD_161_JTAG_TRST_L 11 12
18 17 16 15 14 13 12 GND_AUDIO_CODEC
1 C2004 C2005 & R2004 SHOULD BE PLACED NEAR J2007
0.22UF
10%
10V
2 CERM
402 LEFT SPEAKER CONNECTOR
APN 518S0688
CRITICAL
I2C DEBUG CONNECTORS J2003

53261-8605
APN 518-0349 6
M-RT-SM
DEVELOPMENT UART DEBUG CONNECTOR

J2012 APN 518S0667 SPKRAMP_LWFR_OUT_P 1
HB3903U-L 48 45 15 IN
M-ST-TH 48 45 15 SPKRAMP LWFR OUT N 2
IN
45 14 12 I2C SCL 1 DEVELOPMENT NC J1701 3 NO TEST=TRUE 3
BI
2 CRITICAL 4
48 45 15 IN SPKRAMP LTWT OUT P
3 J2002 5
C 45 14 12 OUT I2C_SDA
53261-8604
M-RT-SM
48 45 15 IN SPKRAMP_LTWT_OUT_N
C
5 48 18 17 16 15 13 GND_AUDIO_SPKRAMP 7
=PP5V_AUDIO_DIGITAL 1
FIXME!!! 3-PIN VERSION NOT RELEASED IN AGILE? 19 13 12
12 11
IN
IN AUD_161_UART_TXD 2
ROW, ROW, ROW YOUR BOAT, GENTLY DOWN THE STREAM. 18
18 12 IN AUD 161 UART RXD 3
HA HA, FOOLED YOU, I’M A SUBMARINE. 4 SUBWOOFER CONNECTORS

APN 518S0665 CRITICAL
6
J2005
53261-8602
M-RT-SM
3
DEVELOPMENT
J2011 SPKRAMP_SUB_OUT_P 1
HB3902U-L 48 45 17 IN
M-ST-TH R2007 48 45 17 IN SPKRAMP_SUB_OUT_N 2
1 2 GPIO1_PULL_UP 1
4.7K 2 =PP3V3_AUDIO_DIGITAL 12 13 14 18 19
5% 48 18 17 16 15 13 GND_AUDIO_SPKRAMP 4
1/16W INTERNAL_I2C
MF-LF INTERNAL_I2C
402
R20121 1
R2013 R20311 1
R2032
47K 47K 47K 10K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 2 2 402 402 2 2 402
R2020
4.99K2
11 GPIO_SHUTDOWN_L 1 AUD_161_RSTN_IN 11 12 18
1%
1/16W R2021 RIGHT SPEAKER CONNECTOR
MF-LF 0
14 ADAV4601_RESETB 402 1 2 AUD_161_GPIO_0 12 APN 518S0667
B R2022 5% 1/16W
MF-LF 402
B
NC_GPIO1 1
0 2 AUD_161_GPIO_1 12
NC NO TEST=TRUE CRITICAL
5% 1/16W
MF-LF 402 R2023 J2004
0
15 AUD_SPKRAMP_SHDN_L 1 2 AUD_161_GPIO_2 12 53261-8604
M-RT-SM
R2024 5% 1/16W
MF-LF 402 5
0
15 AUD SPKRAMP MUTE L 1 2 AUD 161 GPIO 3 12
SPKRAMP_RWFR_OUT_P 1
5% 1/16W
MF-LF 402 R2025 48 45 16 IN
0 48 45 16 IN SPKRAMP_RWFR_OUT_N 2
14 11 DP AUDIOON 1 2 AUD 161 GPIO 4 12
48 45 16 SPKRAMP_RTWT_OUT_P 3
IN
R2026 5% 1/16W
MF-LF 402 48 45 16 IN SPKRAMP_RTWT_OUT_N 4
1
0 2
14 11 DP_MUTE_L AUD_161_GPIO_5 12
5% 1/16W 48 18 17 16 15 13 GND AUDIO SPKRAMP 6

MF-LF 402
AUD_161_GPIO_6 12
AUD_161_GPIO_7 12
18 12 11 AUD_161_UART_TXD
R2030
0
11 UART RXD 1 2 AUD 161 UART RXD 12 18
5% 1/16W
MF-LF 402
R20181 R20141 1
R2015 R20161 1
R2017
47K 47K 47K 47K 10K
A 5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
A
402 2 402 2 PAGE TITLE
2 402 402 2 2 402
AUDIO CONNECTORS
DRAWING NUMBER SIZE

REVISION
R
C.0.0
20 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP12V_LCD_FET
PP2314
1P0-BOT
VOLTAGE=12V
MAKE BASE=TRUE
SM
1
6 =PP12V S5 LCDFET
PP
=PP12V LCD PANEL 21
PP2322
1P0-BOT
NOSTUFF 1 SW1_VLCD 1
SM
C2320 1 1 2 5 6 7 R2300 PP
0.047UF
10% CRITICAL
10K
1%
PP2315
1P0-BOT SWI_VAUD
1
25V
X5R 2 Q2318 1/10W
1
SM PP2323
1 C2317 R2353 0402
MF-LF
2 603
PP 1P0-BOT
SM PP12V_AUDIO_FET
0.47UF 100K FDMA510PZ 1
PP MIN LINE WIDTH=0 6MM
10% 5% 3 MICROFET SW1_VLCD MIN NECK WIDTH=0 2MM
2 16V 1/16W SWI_VAUD VOLTAGE=12V
X7R MF-LF SW1_VLCD MAKE BASE=TRUE
805
2 402
D
GATE_12VLCD
4 8
SWI_VAUD
=PP12V AUDIO DIGITAL 15 16 17 D
R2315
RT2306
2
6 =PP12V_S5_AUDIOFET 5 6 7 8
1/10W
MF-LF
0
68K
603
2 VCC12V_AUD_S
5%
1
1
1
5%
D CRITICAL R2379
PWR_PANEL_ON_DIV R2332 1/4W 10K
1
SW1_VLCD
PWR_PANEL_ON_INV
1 C2324 68K
MF-LF
1206
Q2319 1%
1/10W
0.47UF 5% FDS4465_G MF-LF
10% 1/10W GATE_12VAUDIO 4 G
16V SOI-HF 2 603
R2327 3 2 X7R SWI_VAUD MF-LF
2 603
S
SWI_VAUD
PWR_PANEL_ON 1
10K 2 1
Q2304 805 SWI_VAUD
20 IN MMBT3904G VDIV_GATE
5% SOT23 SWI_VAUD 1 2 3
1 1
1/16W
MF-LF
R2301 2 SW1_VLCD R2378 R2331
402 220K 499K
SW1_VLCD
1
10K 2
5% 1%
1/10W 1/10W
MF-LF MF-LF
5%
1/16W 2 603
SWI_VAUD 2 603
MF-LF PWR_AUDIO12V_ON_INV
402
SW1_VLCD
AUD USB VBUS 11
R2328 3
PWR_AUDIO12V_ON 1
10K 2 PWR_AUDIO12V_ON_DIV 1
Q2310
P4_PWR_INV_DIV
20 IN MMBT3904G
5% SOT23
1/16W SWI_VAUD
3 2
P4_PWR_INV
R2382 MF-LF
402 R2329
1
10K 2 1 Q2354 1
R2384 SWI_VAUD 1
10K 2
2N3906 100K
5% SOT23-HF 5% 5%
1/16W AUDIO_VB 1/16W 1/16W
MF-LF 2 MF-LF MF-LF
402 402
2 402
AUDIO_VB R2383 AUDIO_VB SWI_VAUD
1
100K 2
MIN LINE WIDTH=0 6MM CRITICAL PP5V AUDIO FET 19
5% MIN NECK WIDTH=0 2MM MIN LINE WIDTH=0 6MM
C 1/16W
MF-LF
402 AUDIO_VB
6 =PP5V S5 AUDIOFET
SWI_VAUD5
RT2350
Q2350
SI3443CDV
VOLTAGE=5V
MAKE BASE=TRUE
C
0 TSOP-6
PP5V AUDIO FET 19 1 2 VCC5V_AUD_S
6
=PP5V_AUDIO_DIGITAL
R2380 3
5%
12 13 18
10K Q2355
2 5
1
31 P4_PWR 1 2 P4_PWR_DIV 1
MMBT3904G
1 C2370 R2370 1/4W
MF-LF
D
IN
4
SOT23 0.1UF 100K 1206
5% 5%
1
1/16W AUDIO_VB 10% 1/16W
MF-LF
402 R2381 2 1 C2380 2 50V
X7R MF-LF
0.1UF 2 402
G
10K 603-1
AUDIO_VB 10%
1 2
50V
GATE_5VAUDIO 1
2 X7R SWI_VAUD5 R2385
3
5% SWI_VAUD5
603-1 1 10K
1/16W
MF-LF AUDIO_VB
SWI_VAUD5 R2371 1%
402 10K 1/10W
1% MF-LF
AUDIO_VB 1/10W 2 603
PP2319
1P0-BOT
PP2318
1P0-BOT
MF-LF
SM SM 2 603
1 1 PWR_AUDIO5V_ON_INV
PP PP
SWI_FAN3 SWI_FAN3
R2373 3
PWR_AUDIO5V_ON 1
10K 2 PWR_AUDIO5V_ON_DIV 1
Q2351
PP3V3_FAN_BUF
20 19 IN MMBT3904G
PWR_FAN_ON_INV2_DIV MIN LINE WIDTH=1 0MM 5% SOT23
MIN NECK WIDTH=0 25MM 1/16W
2
3
VOLTAGE=3.3V
MAKE_BASE=TRUE
MF-LF
402 R2372 SWI_VAUD5
PWR_FAN_ON_INV2 R2330 1
10K 2
SWI_VAUD5
1
10K 2 1 Q2307 5%
2N3906 =PP3V3_FAN_MOTOR 8 1/16W
5% SOT23-HF MF-LF
FAN SWITCH 1/16W
MF-LF
402
2
SWI_FAN3
=PP3V3_S5_FANBUF 6
402
SWI_VAUD5
SWI_FAN3 R2303
1
100K 2
B 5%
1/16W
MF-LF 1 C2319 MIN LINE WIDTH=0 6MM
B
402 SWI_FAN3 PP2316
1P0-BOT 0.1UF SWI_VAUD3
CRITICAL PP3V3 AUDIO FET
1
SM 10%
50V =PP3V3_S5_AUDIOFET
Q2352 MIN NECK WIDTH=0 2MM
R2320 3
PP 2 X7R
603-1
6
RT2351 SI3443CDV VOLTAGE=3 3V
MAKE BASE=TRUE
0
10K PWR_FAN_ON_DIV2 Q2306 SWI FAN12 SWI_FAN3 1 2 VCC3V3_AUD_S TSOP-6
6
1 2 1
MMBT3904G PP2317 5% =PP3V3_AUDIO_DIGITAL 12 13 14 18
2 5
SOT23 1
5%
1/16W SWI_FAN3
1P0-BOT
SM 1 C2371 R2374 1/4W
MF-LF
D
4
MF-LF
R2321 2 1
PP 0.1UF 100K 1206
402 5%
1
SWI_FAN3 10K 10% 1/16W
1 2 SWI_FAN12 2 50V
X7R MF-LF
2 402
G
5% 603-1
1/16W PP12V_FAN_FET 48 GATE_3VAUDIO
MF-LF MIN LINE WIDTH=1 0MM
3
402 MIN NECK WIDTH=0 25MM SWI_VAUD3 SWI_VAUD3
1
SWI_FAN3
VOLTAGE=12V
MAKE_BASE=TRUE R2368 SWI_VAUD3 R2375
10K 10K
20 19 PWR AUDIO5V ON 1 2 1%
IN 1/10W
5% MF-LF
6 =PP12V_S5_FANFET 1 2 5 6 7 =PP12V_FAN_MOTOR 8 1/16W 2 603
MF-LF PWR5V_AUDIO_FET_DLY_INV
402
CRITICAL
NOSTUFF
1 C2318
1
R2302 Q2300 R2376 3
0.1UF 5%
100K FDMA510PZ
PWR AUDIO3V ON 1
10K 2 PWR5V AUDIO FET DLY 1
Q2353
10% 1/16W GATE_12VFAN 3 MICROFET 20 IN MMBT3904G
2 50V
X7R MF-LF SWI_FAN12 5% SOT23
1/16W
603-1 2 402 2 SWI_VAUD3
MF-LF
402 R2377
1
10K 2
4 8 SWI_VAUD3
SWI_FAN12 SWI_FAN12
5%
R2319
1/16W
100K 2
MF-LF
1/10W
MF-LF
402
603
5%
A SWI_VAUD3
NOSTUFF SYNC MASTER=MASTER SYNC DATE=N/A A
1
SWI_FAN12
PWR FAN ON INV 1 C2372 PAGE TITLE
R2316 3
0.1UF
10%
50V
POWER SW CONTROL
2 X7R DRAWING NUMBER SIZE
PWR_FAN_ON 1
10K 2 PWR_FAN_ON_DIV 1
Q2305 603-1 051-8774 D
20 IN MMBT3904G SWI_VAUD3 Apple Inc.
SWI_FAN12 5% SOT23 REVISION
1 1/16W SWI_FAN12
C2316 2
R
C.0.0
0.018UF
MF-LF
402 R2317
10%
1
10K 2
16V SWI_FAN12
X7R 2 THE INFORMATION CONTAINED HEREIN IS THE
402 5% PROPRIETARY PROPERTY OF APPLE INC.
1/16W THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF-LF
402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
23 OF 110
SWI_FAN12 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
35 20 6 =PP3V3_S5_LPC
MICRO_WRL
=PP3V3_S3_ENET_PHY
CRITICAL CRITICAL 25 6
C2632 1
MICRO_WRL
L2632 L2633 0.1UF
10%
R2601
FERR-120-OHM-1.5A FERR-120-OHM-1.5A
2
=PP3V3_S5_LPC =PP3V3_S5_LPC 6 16V
X7R-CERM 2
NOSTUFF
35 20 6 20 35
1/16W
MF-LF
10K
1 2 FILT_VDDA3V3_UC FILT VREF_UC 1 2 402
402
5%
0402 VOLTAGE=3.3V VOLTAGE=3.3V 0402
MIN LINE WIDTH=0 6MM MIN NECK WIDTH=0 25MM
1
C2629 1 C2682 1 C2683 1 C2684 1 C2630 MIN NECK WIDTH=0 25MM MIN LINE WIDTH=0 6MM
R2616
LATCH 1 (WR)
1
100UF 10UF 10UF 100PF 0.1UF 1 C2670 1 C2687 1 C2688 MICRO_WRL1 10K
20% 20% 20% 5% 10% 2
0.1UF 10UF 10UF
20
2 16V
ELEC
10V
2 X5R
10V
2 X5R
50V
2 CERM
16V
2 X7R-CERM 10% 20% 20% U2622 5% 402
D
6.3X5.5-SM3
MICRO_F1
805
MICRO_F1
805
MICRO_F1 402
MICRO_F1
402
MICRO_F1
=PP3V3_S5_LPC 35
6
20
16V
2 X7R-CERM
402
2 10V
X5R
805
2 10V
X5R
805 2 D1
VCC
Q1 19 USB_BUSPWR_SW OUT 31
1/16W MF-LF
D
MICRO MICRO
3 D2 Q2 18 PWR_AUDIO3V_ON OUT 19
1 C2625 4 D3 TSSOP Q3 17 I2C TCON ENAB 21
SN74LVC573A
OUT
0.1UF 5 D4 Q4 16 ENET PWR EN
SIGNAL_MODEL=EMPTY
OUT 25
10% USB_UC_DP_PU 20
16V 6 D5 15 PWR CAM ON
2 X7R-CERM Q5 OUT 10
402 7 D6 Q6 14 WP_L
C2627 1
1 C2669 1 C2600 1 C2622 1 C2623 1 C2624 MICRO
=PP3V3_S5_LPC 8 D7 Q7 13
20
AUDIO_SHDN_L OUT
R2600
10UF 10UF 0.1UF 0.1UF 0.1UF 6 20 35 11
23
43
51
63
49
2
100K
7
0.1UF 20% 20% 10% 10% 10% 9 D8 Q8 12 WALL_CHRG_ON OUT 31 33
10% 10V 10V 16V 16V 16V 5% MICRO_WRL
2 X5R 2 X5R 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM
C2628 C2699
R2624
R2623
16V 1 1 1/16W
1.5K 2
2
X7R CERM 2 805 805 402 402 402 VDD VDDA VREF VBAT MF-LF
0.1UF 0.1UF
1/16W
MF-LF
1/16W
MF-LF
10K
402 WR_LATCH1 LATCH_OE_L 402
MICRO MICRO OMIT_TABLE 20 11 LE OE* 1 20
402
402
10% 10%
1%
5%
MICROG1 MICRO MICRO MICRO CRITICAL
2 16V
X7R-CERM
16V
2 X7R-CERM
5 74LVC1G08 U2617 GND
R2622
402 402
10
2
SOT553
1
FAN_ON_L 1 MICROG1 MICROG1 MICRO
20 5 IN LPC2144FBD64
1/16W
MF-LF
10K
MICRO_WRL
402
4
5%
U2605 11 UART_MLB2AUDIO 19 P0_0/TXD0/PWM1
LQFP =PP3V3 S0 ENET PHY 6 26
USB_CHG_WAKE_L 2 OUT
33 IN 08 5 74LVC1G08 UART_AUDIO2MLB 21 P0_1/RXD0/PWM3/EINT0 =PP3V3_S5_LPC
SOT553 11 6
1
FO A UCW 1 IN 10 USB UC DP
3 22 D+ IN 31 46 20 MICRO
45 21 OUT I2C_LPCREM_SCL P0_2/SCL0/CAP0_0 11
35
4 LPC2144 WAKE L USB UC DM
U2606 20
I2C_LPCREM_SDA 26 P0_3/SDA0/MAT0_0/EINT1
D- IN 31 46
2 08
45 21 BI
27 16
1 C2671
R2613
R2615
WR_LATCH0 IOB_D0
100K 2
P0_4/SCK0/CAP0_1/AD0_6 P1_16/TRACEPKT0
NOSTUFF
20
29 12
0.1UF
1/16W
MF-LF
1/16W
MF-LF
3 10%
10K
ADC_USB5V P0_5/MISO0/MAT0_1/AD0_7 P1_17/TRACEPKT1 IOB_D1
45 33
LATCH 0 (WR)
402
402
IN 16V
5%
5%
30 8 2 X7R-CERM
P0_6/MOSI0/CAP0_2/AD1_0 P1_18/TRACEPKT2 IOB D2
20
=PP3V3_S5_LPC 9 PWM STR0 31 P0_7/SSEL0/PWM2/EINT2 P1_19/TRACEPKT3 4 IOB D3
402
U2621
1
35 20 6 OUT
PWM_STR1 33 48 IOB_D4 VCC
9 OUT P0_8/TXD1/PWM4/AD1_1 P1_20/TRACESYNC MICRO_WRL MICRO_WRL
34 44 2 D1 Q1 19 PWR_INV_ON OUT 5 9
9 OUT PWM_STR2 P0_9/RXD1/PWM6/EINT3 P1_21/PIPESTAT0 IOB_D5 TSSOP Q2 18 PWR AUDIO12V ON
OMIT_TABLE 35 40 3 D2 OUT 19
5 20 LATCH_OE_L P0_10/RTS1/CAP1_0/AD1_2 P1_22/PIPESTAT1 IOB_D6
SN74LVC1G02 4 D3 Q3 17 ENET VMAIN CTRL 26
SN74LVC573A
USB_DEV_VBUS_LS 1 I2C_LPCLOC_SCL 37 36 IOB_D7 OUT
31 IN SOT553-5 45 35 20 OUT P0_11/CTS1/CAP1_1/SCL1 P1_23/PIPESTAT2
5 D4 Q4 16 PWR AUDIO5V ON
ENET_WOL_ENABLE_L 38 32 OUT 19
4 RUSB_UPSTREAM5V_L RD_LATCH1_L
U2608 20 20 P0_12/DSR1/MAT1_0/AD1_3 P1_24/TRACECLK 20
C 42 40 35 34 20 IN PM_S3_EN 2 02
45 35 20
20 WR_LATCH1
I2C LPCLOC SDA
39
41
P0_13/DTR1/MAT1_1/AD1_4
P0_14/DCD1/EINT1/SDA1
P1_25/EXTIN0
P1_26/RTCK
28
24
DP_RX_INT_L
LPC2144 JTAG RTCK 11 20
IN 21
6
7
D5
D6
Q5
Q6
15
14
DPRESET
PWR_FAN_ON
OUT 21
OUT 19
C
3 BI PWR_PANEL_ON OUT 19
45 64 8 D7 Q7 13
21 IN VSYNC P0_15/RI1/EINT2/AD1_5 P1_27/TDO LPC2144 JTAG TDO 11 20
46 60 9 D8 Q8 12 USB_HUB_RESET_L OUT 31
20 LPC2144_WAKE_L P0_16/EINT0/MAT0_2/CAP0_2 P1_28/TDI LPC2144_JTAG_TDI 11 20
9 BL_ONOFF 47 P0_17/CAP1_2/SCK1/MAT1_2 P1_29/TCK 56 LPC2144_JTAG_TCK 11 20

OUT WR_LATCH0
53 52 20 11 LE OE* 1
42 40 35 34 20 IN PM_S3_EN P0_18/CAP1_3/MISO1/MAT1_3 P1_30/TMS LPC2144_JTAG_TMS 11 20
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 9 STRCLK1 54 P0_19/MAT1_2/MOSI1/CAP1_2 P1_31/TRST* 20 LPC2144_JTAG_TRST_L 11 20 GND
OUT
10
42 40 35 34 25 PM_S0_EN 55 P0_20/MAT1_3/SSEL1/EINT3
311S0394 1 SINGLE NAND GATE SOT553-5 U2608 CRITICAL MICRO_WRL
8 PWM_FAN0 1 P0_21/PWM5/AD1_6/CAP1_3 RESET* 57 20 11 LPC2144_RESET_UC_L =PP3V3_S5_LPC 6 20
OUT 35
NOTE NOR GATE FOR OLD SYSTEM UC SLEEP NAND GATE FOR DEEP SYSTEM UC SLEEP SLEEP 8 TACH0 2 P0_22/AD1_7/CAP0_0/MAT0_0
WARNING DEV CONNECTOR WAKE WILL NO LONGER WORK WITH THIS CONFIGURATION!!! IN
31 IN VBUS_UC 58 P0_23/VBUS XTAL1 62 XTAL1_UC LATCH 2 (RD)
20
9 61
35 20 6 =PP3V3_S5_LPC
SOT23-3-HF
45 9 OUT DAC_OUT
13
P0_25/AD0_4/AOUT XTAL2 XTAL2_UC U2620 1 C2631
NTR1P02L 45 9 IN ADC_STR2_V P0_28/AD0_1/CAP0_2/MAT0_2 VCC 0.1UF
2
Q2665 45 9 IN ADC_STR0_V 14 P0_29/AD0_2/CAP0_3/MAT0_3 RTXC1 3 RTCX1_UC 19 Q1 D1 2 FAN_ON_L 5 20
10%
16V
2 X7R-CERM
ADC_STR1_V 15 P0_30/AD0_3/EINT3/CAP0_0 RTXC2 5 RTCX2_UC 18 Q2 D2 3 DP_VIDEO_ON
45 9 TSSOP 9 21
R2665
IN IN 402
NOSTUFF
S
1 USB_UC_DP_PU_EN 17 P0_31/UP_LED/CONNECT 17 Q3 D3 4 RUSB_UPSTREAM5V_L IN 20 MICRO_RDL
SN74LVC573A
1/16W
MF-LF
G
402
5%
16 5 AUDIO_ON
0
Q4 D4
C2677
2 CERM
IN 11 21
50V
402
15 6 STR0_SENSE
5%
Q5 D5 IN 9
D 22PF
1
12.000MHZ-30PPM-10PF
CRITICAL 14 Q6 D6 7 STR1_SENSE IN 9
1
3 NOTE DON’T PULLDOWN P0 31 OR JTAG GETS DISABLED!! 13 Q7 D7 8 STR2_SENSE
VSS VSSA IN 9
MICRO 12 Q8 D8 9 DP_PWR_UP_L IN 21
USB_UC_DP_PU
6
18
25
42
50
59
20
SM-3.2X2.5MM
Y2604
20 RD_LATCH1_L 1 OE* LE 11
CRITICAL
4
GND
10
C2678
1
CRITICAL MICRO_RDL
MICRO
B B
22PF
2 CERM
50V
402
5%
=PP3V3 S5 LPC 6 20 35
1
C2675
20 11 OUT LPC2144_JTAG_RTCK MICRO
22PF
R2670
2 CERM
LPC2144_JTAG_TRST_L
2
3
50V
402
20 11 OUT
5%
CRITICAL
1/16W
MF-LF
10K
20 11 LPC2144_JTAG_TDI
VCC
402
OUT
5%
R2621
1
LPC2144_JTAG_TMS
20 11 OUT 4.7K 1 U2618 1 C2626
4.1X1.5X.9-SM
20 11 LPC2144 JTAG TCK 2
0.1UF
1
OUT
CRITICAL
32.768K
Y2603
MICRO MICRO MAX6328 10%
C2676
JTAG 5%
2
1/16W 16V
2 2 X7R-CERM
20 11 LPC2144_JTAG_TDO MF-LF
OUT RESET 402
22PF
402
20 11 LPC2144_RESET_UC_L MICRO
2 CERM
OUT CRITICAL
50V
402
5%
35 20 6 =PP3V3 S5 LPC GND
MAX6328URT23+G65
1
1
6=PP3V3_S5_LPC MICRO MICRO CRITICAL
20
R2625
R2606
35
100K 2
100K 2 SYSTEM EEPROM

R2603
R2604
1/16W
MF-LF
1
4.7K 2
4.7K 2
C2638 1
402
5%
8
1/16W
MF-LF
1/16W
MF-LF
JTAG 5%
0.1UF =PP3V3 S5 LPC
402
402
5%
5%
1/16W 35 20 6
MF-LF 10% VCC
1
16V
402
X7R-CERM 2 U2616 MICRO
R2641
R2626
100K 2
1
402 AT24C04B
SYSEE
1/16W
MF-LF
100K 2 SYSEE SYSEE SOI
402
1 A0 SDA 5
5%
1 SYS_A0 =I2C_SYS_SDA 35
JTAG 5% SYS_A1 2 A1 CRITICALSCL 6 =I2C_SYS_SCL 35
1/16W
1
MF-LF SYS_A2 3 A2 MICRO
402
R2627 WP 7 SYS WP ENET WOL ENABLE L
A 20
A
R2605
100K 2 GND SYNC MASTER=K59 SYNC DATE=08/22/2010

2
1
4 I2C_LPCLOC_SCL 20 35 45
PAGE TITLE
3
DEVELOPMENT
LPC2144 & PERIPHERALS
0
JTAG 5%
1/16W
MF-LF
CRITICAL I2C_LPCLOC_SDA 20 35 45 3 Q2640
402 J2610 Q2600 2N7002E-X-G DRAWING NUMBER SIZE
1
HB3903U-L 2N7002E-X-G ENET_WOL_ENABLE 1 SOT23-3 051-8774 D

R2628 M-ST-TH
1 SOT23-3
26 IN
Apple Inc.
1
100K 2 1 20 WP_L REVISION
SYSEE
2
R2640 2 R
C.0.0
JTAG 5%
R2637 2 100K 2
1/16W 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF-LF 3
1
100K 2
402 5% THE INFORMATION CONTAINED HEREIN IS THE
1/16W PROPRIETARY PROPERTY OF APPLE INC.
5% MF-LF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1/16W 402
SHORT PINS 2 & 3 FOR JTAG BOOT MODE MF-LF
402
26 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
L2740
FERR-120-OHM-3A
19 =PP12V_LCD_PANEL 1 2
0603
CRITICAL
21 6 =PP3V3_S5_TCON R2746 R2747 PP3V3_DPL_TCON
L2741
R2754 R2769 0 0 FERR-120-OHM-3A
CRITICAL
10K 1 2 PP3V3_BUF 1 2
1 2
10K 1 2 I2S_SWWS 21 MIN LINE WIDTH=0 4MM 48 PP12V_PANEL_FC
J2726
1 2 SWVIDEO ON 21 5% MIN NECK WIDTH=0 2MM 5% MIN LINE WIDTH=1 0MM
0603
5%
5%
1/16W
1/16W
MF-LF
VOLTAGE=3 3V 1/16W
MF-LF
VOLTAGE=12V
53780-8606
1/16W MF-LF 402 402 M-RT-SM
MF-LF 402 NOSTUFF 7
402
R2777 1 C2701
R2755 R2771 0.1UF R2775
D 1
100K 2 DP_VIDEO_ON 9 20 21 1
10K 2 I2S_SWSD0 21
1
100K 2 10%
16V
2 X7R-CERM 1
100K 2
1
2
D
5%
5% 5% 1/16W 402 3
1/16W 1/16W MF-LF 5%
MF-LF
402
MF-LF
402
402 U2702 1/16W
MF-LF
4
74LVC1G125DBVG4 5
402 5
R2756 20 OUT DP RX INT L 4 2 SWDP RX INT L NOSTUFF 6
10K SWVSYNC
R2776
1 2 21
10K SOT23-5 1
L2746
5% 1 2 SWAUDIO_MUTE_L 21 PP2705 3 FERR-120-OHM-0.3A 8
1/16W 1P0-BOT
MF-LF 5% SM 1 2K29TC NC_I2S_MCLK_FC
402 1/16W 1 NO TEST
MF-LF PP 0402
R2757 402
CRITICAL
100K 2
1 RVSYNC 21 L2703 J2725
5% FERR-120-OHM-0.3A 20474-040E-11
R2745
11
12
13
1/16W F-RT-SM
MF-LF 22 1 2K29TC
48 INT FC L 41 K29TC
402 11 OUT I2S_MCLK 1 2
GND 0402 42
22 2
5% OE* DIR
R2759 1/16W
MF-LF
L2705
10K 402 R2741 RI2S_MCLK 10 14 21 I2S_SWMCLK FERR-120-OHM-0.3A 1
1 2 SWAUDIO ON 21
I2S_SCLK
K29TC 1
22 2 AUDIO_ON
A8 B8
21 SWAUDIO_ON 1 2K29TC
48 AUDIO_ON_FC 2
11 OUT OUT 9 15
5% A7 B7 3
1/16W 5% AUDIO_MUTE_L 21 SWAUDIO_MUTE_L 0402
MF-LF 1/16W
11 OUT 8 16
R2742 A6 B6
402 MF-LF RI2S_SCLK 7 U2701 17 21 I2S_SWSCLK L2706 4
402 22 A5 B5 FERR-120-OHM-0.3A 5
R2763 11 OUT I2S WS 1 2 RI2S WS 6 18 21 I2S SWWS
A4 B4 2K29TC
10K 5% RI2S SD0 5 19 21 I2S SWSD0 1 48 AUDIO MUTE FC L 6
1 2 I2S_SWSCLK 21 1/16W
R2743 A3 B3 7
MF-LF DP_VIDEO_ON 4 20 21 SWVIDEO_ON 0402
5% 402 22 OUT
A2 B2 8
1/16W 11 OUT I2S_SD0 1 2 21 RVSYNC 3 TSSOP 21 21 SWVSYNC
MF-LF A1 SN74LVC8T245PW B1
402 5% 9
1/16W
R2709 10
R2762 22
MF-LF
402 L2708
10K I2S_SWMCLK 20 OUT VSYNC 1 2 VCCA VCCB FERR-120-OHM-0.3A 11
C 1 2 21
12
C
23
24
5% K29TC
5% 1/16W 1 2K29TC
48 I2S_SCLK_FC
1/16W MF-LF 13
MF-LF 402 21 6 =PP3V3_S5_TCON PP3V3_DPL_TCON 21 0402
402 K29TC L2709 14
FERR-120-OHM-0.3A 15
1 2K29TC
48 I2S_WS_FC 16
PP2702
1P0-BOT
1 C2772 1 C2776 0402 17
=PP3V3 S5 TCON SM 0.1UF L2710
21 6
1 10% 0.1UF FERR-120-OHM-0.3A NC_DP_SPDIF 18
PP =PP3V3_S5_TCON 16V 10% NO TEST
21 6 2 X7R-CERM 16V 19
402 2 X7R-CERM 1 2K29TC
NC_DP_OPTION1
48 I2S_SD0_FC NO TEST
402 48 DP_INT_HPD_FC 20
1 0402
20 OUT DP PWR UP L R2744 48 21
21 PP3V3_DPL_TCON
CRITICAL 10K 44
21 22
MIN LINE WIDTH=1 0MM 5% 7 DP_INT_AUXCH_N
VOLTAGE=3 3V Q2718 1/16W
MF-LF
44
7 DP_INT_AUXCH_P 23
SI3443CDV 2 402
L2737 21
48 24
PP2701 TSOP-6 FERR-120-OHM-0.3A
6
48
DP_INT_ML_P<0> 25
1P0-BOT R2739 2K29TC 7
5
SM 1 48 VIDEO_ON_FC 44
1 100K 2 DP_PWR_UP_GATE 7 DP_INT_ML_N<0> 26
D
PP
2
1 3 0402 44
48 27
Q2710
1
1
R2738 5%
1/16W PP2703 L2739
48
44
7 DP_INT_ML_P<1> 28
100K MF-LF 2N7002E-X-G 1P0-BOT FERR-120-OHM-0.3A
G
5% 402 3 SM 48
DP_INT_ML_N<1> 29
SOT23-3 1 1 7
1/16W NO STUFF 2K29TC
44
MF-LF Q2712 PP 1 48 VSYNC_FC 30
3
48
2 402 K29TC 2N7002E-X-G 0402 44
DP_INT_ML_P<2> 31
2 7
R2740 R2724 SOT23-3 1 DPRESET IN 20
48
7 DP_INT_ML_N<2> 32
DPL_GATE 1
0 2 1
5.1M 2 44
33
5% 5%
2 K29TC R2725 L2702 48
DP_INT_ML_P<3> 34
K29TC FERR-120-OHM-0.3A 7
1/16W 1/16W 5.1M 2 44
35
MF-LF MF-LF 1
2K29TC
DP_INT_ML_N<3>
402 402
5% K29TC
PP2704
1P0-BOT
1 48 DP_PWR_UP_FC
7
44
48 36
21 6 =PP3V3_S5_TCON 1/16W SM 0402
MF-LF 1 37
402 PP
B COMBINED IN SERIES WITH 47 OHM ON PANEL

R2720
120
LIMITS CURRENT TO 20MA NC_DP_OPTION2
NO TEST
38
39
B
DP_INT_HPD
1 C2775 7 1 2 40
0.1UF 5% K29TC
R2764 10%
16V
1/16W
MF-LF 43
10K I2C_TCON_ENAB_R 2 X7R-CERM 402
20 IN I2C_TCON_ENAB 1 2
402
5%
L2712 44
1/16W FERR-120-OHM-0.3A
MF-LF
402 J2710 1 2K29TC 48 45 DDC SDA FC
8
HB3902U-L V+ 0402 L2713

M-ST-TH SDA_SWREM
1 1 7 IN1 IN2 3
45
FERR-120-OHM-0.3A
1 R2780 R2781 U2704 1 2K29TC
2
4.7K 4.7K TS5A23166 45 SCL_SWREM 48 45 DDC_SCL_FC
5% 5% 2 COM1 US8
1/16W 1/16W COM2 6 0402
MF-LF MF-LF
2 402 2 402 CRITICAL L2715
DEVELOPMENT 1 NO1 NO2 5
FERR-120-OHM-0.3A
35 =I2C DP628 SDA 1 2K29TC 48 45 SDA FC
GND BI
0402 L2716
4
CAMERA FERR-120-OHM-0.3A
35 =I2C_DP628_SCL 1 2K29TC 48 45 SCL_FC
IN
J2712 J2711 0402
HB3902U-L HB3902U-L
M-ST-TH M-ST-TH
1 1
2 2 35 6 =PP3V3_S0_TCON
45 20 IN I2C_LPCREM_SCL 1
DEVELOPMENT DEVELOPMENT
R2722
45 20 IN I2C_LPCREM_SDA 100K
J2713 5%
1/16W
A HB3902U-L
M-ST-TH
MF-LF
2 402 SYNC MASTER=K59 SYNC DATE=08/22/2010 A
1 PAGE TITLE
2 48 44 21 7 DP_INT_AUXCH_N
DP FC & INTERFACE
48 44 21 7 DP_INT_AUXCH_P DRAWING NUMBER SIZE
DEVELOPMENT
1 REVISION
R2723 R
C.0.0
100K
5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/16W
MF-LF THE INFORMATION CONTAINED HEREIN IS THE
2 402 PROPRIETARY PROPERTY OF APPLE INC.
27 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BYPASS Properties:
L2860
FERR-120-OHM-1.5A U2850 50 53 5 mm U2850 1 3 4 mm
6 =PP3V3_S0_CK505 U2850 60 63 5 mm U2850 54 56 4 mm
U2850 67 66 3 mm U2850 4 7 5 mm
1 2 PP3V3_S0_CK505_VDD
MIN LINE WIDTH=0 5mm
PCI_GEN_SEL SRC_OUTPUTS 0402 MIN NECK WIDTH=0 2mm
VOLTAGE=3 3V
C2860 1 1
C2861 1
C2862 1
C2863 1
C2854 1
C2855 1
C2856
0 Gen 1 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10% 10% 10% 10%
6 3V 16V 16V 16V 16V 16V 16V
1 Gen 2 X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 402 402 402 402 402 402
U2850 11 16 8 mm U2850 44 47 5 mm
D PCI_SEL PIN 65
U2850 29 32 6 mm
U2850 37 32 8 mm =PP1V05_S0_CK505 6
D
0 24.576MHz
C2870 1
C2871 1
C2872 1
C2873 1
0.1UF 0.1UF 0.1UF 0.1UF

1 33MHz R2880 1 R2882 1 R2884 1 R2886 1 R2888 1 R2890 1 10% 10% 10% 10%
16V 16V 16V 16V
10K 10K 10K 10K 10K 10K X5R 2 X5R 2 X5R 2 X5R 2
5% 5% 5% 5% 5% 5% 402 402 402 402
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
GCLK_SEL PIN 5 PIN 6 MF LF MF LF MF LF MF LF MF LF MF LF
402 402 402 402 402 402
2 2 2 2 2 2
0 DOT_96+ DOT_96-
50
60
67
54
11
29
37
44
1
4
1 1 1 1 1
VDD_PCI
VDD_27
1 27M 27M w/SS
VDD_CORE
VDD_24
VDD_48
VDD_REF
VDD_SRC
VDD_CPU
R2881 R2883 R2885 R2887 R2889
10K 10K 10K 10K 10K One 0.1uF per power pin (place at pin).
5% 5% 5% 5% 5%
FS_C FS_B FS_A CPU MHz 1/16W 1/16W 1/16W 1/16W 1/16W One 10uF cap per filtered rail.
MF LF MF LF MF LF MF LF MF LF
402 402 402 402 402
2 2 2 2 2
0 0 0 266.6
40 IN CK505_PWRGD 68 CKPWRGD/PWRDWN* CPU_0 46
NC
0 0 1 133.3
CPU_0* 45
NC
0 1 0 200.0 58 CPU_STOP* U2850 43
SLG8SP568 CPU_1 NC
QFN CPU CLKs Unused
0 1 1 166.6 CPU_1* 42
7 IN PCIESLOT_CLKREQ_L 8 CLKREQ_1* CRITICAL NC
Frequency strapped to 133MHz for lowest
1 X X RSVD 7 IN T29_CLKREQ_L 17 CLKREQ_3* CPU_2_ITP/SRC_10 41
NC lowest power. CPU_STOP* must be enabled
7 IN PCIBR CLKREQ L 20 CLKREQ_4* CPU_2_ITP*/SRC_10* 40
NC via I2C to stop CPU_x outputs.
26 IN ENET CLKREQ L 23 CLKREQ_5*
SRC_0 9
7 IN T29S_CLKREQ_L 26 CLKREQ_6* NC Unused 100MHz (no CLKREQ#)
SRC_0* 10
NC
28 IN FW_CLKREQ_L 35 CLKREQ_8*
7 IN SATA_CLKREQ_L 36 CLKREQ_9* SRC_1 12 PCIE_CLK100M_SLOT_P OUT 7
PCIe x4 Slot 100MHz
SRC_1* 13 PCIE_CLK100M_SLOT_N OUT 7
CK505_PCI_STOP_L 57 PCI_STOP*
C 7 PCI CLK33M PCIBR R2895 33 1 2 PCI CLK33M PCIBR R 59 PCIF_0/ITP_EN
SRC_2
SRC_2*
14
15
NC
NC
Unused 100MHz (no CLKREQ#) C
OUT
5% 1/16W MF LF 402
SRC_3 18 PCIE CLK100M T29 P OUT 23 44
CK505_PCIE_GEN2_SEL 61 PCI_0/PCIE_GEN_SEL (IPD) T29 Primary 100MHz
SRC_3* 19 PCIE_CLK100M_T29_N OUT 23 44
CK505_24P576M_L 62 PCI_1/PCI_SEL
7 OUT PCI_CLK33M_NECUSB R2896 33 1 2 PCI_CLK33M_NECUSB_R 64 PCI_2/GCLK_SEL SRC_4 21 PCIE_CLK100M_PCIBR_P OUT 7
5% 1/16W MF LF 402 PCI Bridge 100MHz
7 OUT FW CLK24P576M R2897 33 1 2 CK505 CLK24P576M FSB 65 PCI_3/24.576M/FS_B SRC_4* 22 PCIE CLK100M PCIBR N OUT 7
5% 1/16W MF LF 402
SRC_5 24 PCIE_CLK100M_ENET_P OUT 26 46

CK505_CLK48M_FSA 2 48M/FS_A Caesar-IV PCIe 100MHz
SRC_5* 25 PCIE_CLK100M_ENET_N OUT 26 46
CK505_FSC 55 REF/FS_C
SRC_6 27 PCIE_CLK100M_T29S_P OUT 7
T29 Secondary 100MHz
R2891 1 R2893 1 35 IN =I2C_CK505_SCL 48 SCL SRC_6* 28 PCIE_CLK100M_T29S_N OUT 7
10K 10K 35 BI =I2C_CK505_SDA 49 SDA

5% 5% SRC_7 30
1/16W 1/16W
NC Unused 100MHz (no CLKREQ#)
MF LF MF LF SRC_7* 31
402 402 CK505_CLK14M_XTAL_IN 52 XTAL_IN NC
2 2
CK505_CLK14M_XTAL_OUT 51 XTAL_OUT SRC_8 34 PCIE_CLK100M_FW_P OUT 28 46
CRITICAL FireWire PCIe 100MHz
SRC_8* 33 PCIE_CLK100M_FW_N OUT 28 46
1
R2892 1
R2894 Y2850
10K 10K 14.31818 SRC_9 39 PCIE_CLK100M_SATA_P 7
1 2 OUT
5% 5% SATA 100MHz
1/16W 1/16W SRC_9* 38 PCIE_CLK100M_SATA_N OUT 7
MF LF MF LF
5X3 2 SM
402 402
2 2
C2850 1 1
C2851 DOT_96/27M 5 PS161_CLK27M_R OUT 7 PS161 27MHz Non-Spread
18pF 18pF 69 THRM_PAD DOT_96*/27M_SS 6 Unused 27MHz Spread
5% 5% NC
50V 50V
CERM 2 2 CERM
VSS_CORE
402 402
VSS_PCI
VSS_REF
VSS_SRC
VSS_CPU
VSS_24
VSS_48
VSS_27
NEED TO CHECK CAP VALUE
B B
53
63
66
56
16
32
47
3
7
System 25MHz Clock Generator
GreenClk 25MHz Power 6 =PP3V3_ENET_SYSCLK
Ethernet XTAL Power 25 =PPVDDIO ENET CLK

T29S XTAL Power 7 =PPVDDIO S0 T29S CLK
T29P XTAL Power 6 =PPVDDIO_S0_T29P_CLK
C2824 1
C2822 1
C2820 1 1
C2802
2
0.1UF 0.1UF 0.1UF 1UF

VDD
VDDIO_A
VDDIO_B
VDDIO_C
20% 20% 20% 10%

10V 10V 10V 6 3V
CERM 2 CERM 2 CERM 2 2 CERM
402 402 402 402
U2800
SLG3NB146V
A C2805
12PF R2805
0
TDFN
CRITICAL
SYNC_MASTER=T29_D SYNC_DATE=03/17/2011 A
2 1 SYSCLK CLK25M X2 1 2 SYSCLK CLK25M X2 R 10 XOUT PAGE TITLE
5%
5%
1/16W
NO STUFF 1 XIN
25MHZ_A 5 SYSCLK_CLK25M_T29S OUT 7 T29 Clocking
50V
CRITICAL MF LF 1
R2806 25MHZ_B 4 SYSCLK_CLK25M_ENET DRAWING NUMBER SIZE
1
OUT 25
CERM 402
402 NC Y2805 1M 25MHZ_C 8 SYSCLK_CLK25M_T29 051-8774 D
2
23
NC 25.000MHZ-12PF-20PPM
5%
1/16W
OUT
Apple Inc. REVISION
4
C2806 MF LF R
C.0.0
3
GND
SM 3 2X2 5MM 402

12PF 2 THRM
PAD NOTICE OF PROPRIETARY PROPERTY: BRANCH
1 2 SYSCLK_CLK25M_X1
9
11

5%
NOTE: 30 PPM crystal required PROPRIETARY PROPERTY OF APPLE INC.
50V
CERM
402
28 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
OMIT_TABLE
PCIE_T29_D2R_P<0> V19 V21 PCIE_T29_R2D_C_P<0>
7 IN PER_0_P U3600 PET_0_P OUT 7
PCIE_T29_D2R_N<0> T19 T21 PCIE_T29_R2D_C_N<0>

7 IN PER_0_N T29 PET_0_N OUT 7
FCBGA
(SYM 1 OF 2)
PCIE GEN2
PCIE_T29_D2R_P<1> P19 P21 PCIE_T29_R2D_C_P<1>
7 IN PER_1_P PET_1_P OUT 7
PCIE T29 D2R N<1> M19 M21 PCIE T29 R2D C N<1>
7 PER_1_N PET_1_N 7
RECEIVE
IN OUT
TRANSMIT
PCIE T29 D2R P<2> K19 K21 PCIE T29 R2D C P<2>
7 PER_2_P PET_2_P 7
D 7
IN
IN PCIE T29 D2R N<2> H19
PER_2_N PET_2_N H21 PCIE T29 R2D C N<2>
OUT
OUT 7 D
=PP3V3_S0_T29P 6 7 11 23 24
PCIE T29 D2R P<3> F19 F21 PCIE T29 R2D C P<3> 1
7 IN PER_3_P PET_3_P OUT 7
R3651
PCIE T29 D2R N<3> D19 D21 PCIE T29 R2D C N<3>
7 IN PER_3 N PET_3_N OUT 7 10K
5%
1/16W
MF LF
NO STUFF 2
402
TP_T29_MONDC0 R3610 1 2 T29_MONDC0 B21

MONDC0 F1
5% 1/16W MF LF 402 WAKE* T29 PCIE WAKE L
DEBUG For monitoring current/voltage 0
R3611 A20 U3600 not powered in sleep, WAKE# input unusable.
TP_T29_MONDC1 1 2 T29_MONDC1 MONDC1 E6
5% 1/16W MF LF 402 PERST* T29_RESET_L IN 7
0
NO STUFF
E14 T29_RSENSE
RSENSE
TP T29 MONOBSP C3615 1 2
T29 MONOBSP K17
MONOBSP
10% 16V X5R 402
DEBUG For monitoring clock 0.1uF
TP_T29_MONOBSN C3616 1 2 T29_MONOBSN M17
MONOBSN R3655 1
10% 16V X5R 402 1.0K
0.1uF 0 5%
=PP3V3 S0 T29P 6 7 11 23 24 1/16W
MF LF
603
2
E16 T29_RBIAS
RBIAS
1 1
C3690 1
R3692 1 R3623 1 1
R3620
R3690 R3691 1UF 3.3K 10K 10K CLKREQ# not
3.3K 3.3K 10%
5% 5% 5%
POWER ON RESET
6 3V
5% 5% CERM 2 1/16W 1/16W 1/16W functional in
1/16W 1/16W 402 CRITICAL MF LF MF LF MF LF K1
MF LF MF LF 402 402 402 endpoint mode. PCIE_RST_0* T29_PCIE_RESET_L<0> OUT 7
OMIT_TABLE 2 2
Pull-ups required on 2
CLK REQUEST
402 2 2 402 8 J2
P3 PCIE_RST_1* T29 PCIE RESET L<1> OUT 7
VCC GPIO1 & 2 if unused. T29_PCIE_CLKREQ_L PCIE_CLKREQ_0* K3
N4 PCIE_RST_2* T29 PCIE RESET L<2> OUT 7
1 T29_GPIO<1> PCIE_CLKREQ_1*
(T29_SPI_MOSI) 5 D U3690 Q 2 (T29_SPI_MISO) R3693 7 BI
PCIE_RST_3* J4 T29 PCIE RESET L<3> 7
3.3K T29_GPIO<2> M3 OUT
7 BI PCIE_CLKREQ_2*
C (T29_SPI_CLK) 6 C
M95160
2KX8-1.8V
5%
1/16W T29_RSVD L4
PCIE_CLKREQ_3* TDI T3 JTAG_T29P_TDI IN 11 C
MISC
MF LF =PP3V3_S0_T29P 6 7 11 23 24
JTAG
R4 JTAG T29P TMS
MLP
2 402 P1 TMS IN 11
(T29_SPI_CS_L) 1 S_L 44 T29_SPI_MOSI EE_DI R2 JTAG T29P TCK
EEPROM
M1 TCK IN 11
44 T29_SPI_MISO EE_DO T1
1
R3698
T29ROM_WP_L 3 W_L N2 TDO JTAG_T29P_TDO OUT 11
44 T29_SPI_CS_L EE_CS* 10K
L2 5%
T29ROM_HOLD_L 7 HOLD_L 44 T29_SPI_CLK EE_CLK REFCLK_100_IN_P H17 PCIE_CLK100M_T29_P IN 22 44 1/16W
G16 MF LF
VSS THM A2 REFCLK_100_IN_N PCIE CLK100M T29 N IN 22 44 402
R3695
PAD TP_T29_THERM_DP THERM_DP 2
CLOCKS
P17 806
4 9
E4 XTAL_25_IN SYSCLK_CLK25M_T29_R 1 2 SYSCLK_CLK25M_T29 IN 22
T29_TEST_EN TEST_EN
TEST PORT
R16 TP_T29_XTAL25OUT
P5 XTAL_25_OUT 1%
TP_T29_TEST_POINT_0 TEST_POINT_0 1/16W
1 TP_T29_TEST_POINT_1 N6
TEST_POINT_1 TMU_CLK_OUT U2 T29_TMU_CLK_OUT R3696 1 MF LF
R3625 1K
402
TP_T29_TEST_POINT_2 M5 E2 T29_TMU_CLK_IN
0 TEST_POINT_2 TMU_CLK_IN 5%
5% L6 1/16W
1/16W T29_TEST_POINT_3 TEST_POINT 3 NO STUFF MF LF
MF LF 402 2
1
2
402 R3699
10K
5%
AA4 1/16W
R3629 1 TP_DP_T29SNK0_MLP<3> DPSNK0_ML_LANE_3P MF LF
402
0 TP_DP_T29SNK0_MLN<3> Y3 2
DPSNK0_ML_LANE_3N
5%
1/16W AA6
MF LF TP_DP_T29SNK0_MLP<2> DPSNK0_ML_LANE_2P
402 2 Y5
TP_DP_T29SNK0_MLN<2> DPSNK0_ML_LANE_2N
SINK PORT 0
TP_DP_T29SNK0_MLP<1> AA8
DPSNK0_ML_LANE_1P
TP_DP_T29SNK0_MLN<1> Y7 AA18 DP_T29SRCA_ML_C_P<3>
DPSNK0_ML_LANE_1N DPSRC0_ML_LANE_3P OUT 7
Y17 DP_T29SRCA_ML_C_N<3>
AA10 DPSRC0_ML_LANE_3N OUT 7
TP_DP_T29SNK0_MLP<0> DPSNK0_ML_LANE_0P
TP_DP_T29SNK0_MLN<0> Y9 AA16 DP_T29SRCA_ML_C_P<2>
DPSNK0_ML_LANE_0N DPSRC0_ML_LANE_2P OUT 7
V1 DPSRC0_ML_LANE_2N OUT 7
TP_DP_T29SNK0_AUXCHP
SOURCE PORT 0
DPSNK0_AUX_CHP
B TP_DP_T29SNK0_AUXCHN W2
DPSNK0_AUX_CHN DPSRC0_ML_LANE_1P AA14 DP_T29SRCA_ML_C_P<1> OUT 7
B
DISPLAY
V5 DPSRC0_ML_LANE_1N OUT 7
TP DP T29SNK0 HPD DPSNK0_HOT_PLUG_DET
AA12 DP T29SRCA ML C P<0>
DPSRC0_ML_LANE_0P OUT 7
DPSRC0_ML_LANE_0N OUT 7
V9
NC DPSNK1_ML_LANE_3P W16
U8 DPSRC0_AUX_CHP DP T29SRCA AUXCH C P BI 7
NC DPSNK1_ML_LANE_3N U16
DPSRC0_AUX_CHN DP T29SRCA AUXCH C N BI 7
V11 100pF SRF > 40MHz
NC DPSNK1_ML_LANE_2P V3
U10 DPSRC0_HOT_PLUG_DET DP_T29SRCA_HPD IN 7
NC DPSNK1_ML_LANE_2N BYPASS=U3600.Y19::2mm
SINK PORT 1
V13 Y19 BYPASS=U3600.Y19::5.08mm
NC DPSNK1_ML_LANE_1P DP_ATEST T29 DP ATEST
U12 Y21
NC DPSNK1_ML_LANE_1N DP_RES_0
AA20
V15 DP_RES_1 T29_DP_RES C3685 1 1
C3686
NC DPSNK1_ML_LANE_0P 100PF 0.01UF
U14 5% 10%
NC DPSNK1_ML_LANE_0N 1 1 50V 50V
R3685 R3632 CERM 2 2 X7R
V7 402 402
NC DPSNK1_AUX_CHP 14.0K 100K
U6 1% 5%
NC DPSNK1_AUX_CHN 1/16W 1/16W
T29_R2C_LSEO<0> =T29_R2C_LSEO<0> 34 MF LF MF LF
23
U4 402 402
MAKE BASE=TRUE DPSNK1_HOT_PLUG_DET 2 2
23 T29 C2R LSEO<0> =T29 C2R LSEO<0> 34 NC
MAKE BASE=TRUE
23 T29 LSEO<0> =T29 LSEO<0> 42

CABLE PORT - LINK 0 MDP PORT A - LINK 0
MAKE BASE=TRUE
T29_LSOE<0> =T29_LSOE<0> T29_R2C_C_P<0> A6 A14 T29_R2D_C_P<0>
23 42 44 41 OUT PRT0_T29T_P PRT2_T29T_P OUT 42 44
MAKE BASE=TRUE A4 A12
44 41 OUT T29_R2C_C_N<0> PRT0_T29T_N PRT2_T29T_N T29_R2D_C_N<0> OUT 42 44
PORT2
PORT0
T29 C2R P<0> C4 C12 T29 D2R P<0>

44 41 IN PRT0_T29R_P PRT2_T29R_P IN 42 44
44 41 IN T29_C2R_N<0> C2
J6
PRT0_T29R_N
PORTS PRT2_T29R_N C10
G4
T29_D2R_N<0> IN 42 44
T29 R2C LSEO<0> T29 LSEO<0>

A NOTE: C2R = Cable to Router
23
23
OUT
IN T29 C2R LSEO<0> K5
T29_0_LSEO
T29_0_LSOE
T29_2_LSEO
T29_2_LSOE H3 T29 LSOE<0>
OUT
IN
23
23 SYNC_MASTER=T29_D SYNC_DATE=11/01/2010 A
CABLE PORT - LINK 1 MDP PORT A - LINK 1 PAGE TITLE
R2C = Router to Cable
44 41 OUT T29_R2C_C_P<1> A10
PRT1_T29T_P PRT3_T29T_P A18 T29_R2D_C_P<1> OUT 42 44 T29 Primary (1 of 2)
T29_R2C_C_N<1> A8 A16 T29_R2D_C_N<1>
44 41 OUT PRT1_T29T_N PRT3_T29T_N OUT 42 44 DRAWING NUMBER SIZE
051-8774 D
PORT1
PORT3
44 41 IN T29 C2R P<1> C8

PRT1_T29R_P PRT3_T29R_P C16 T29 D2R P<1> IN 42 44 Apple Inc. REVISION
T29_C2R_N<1> C6 C14 T29_D2R_N<1>
44 41 PRT1_T29R_N PRT3_T29R_N 42 44 R
IN IN
C.0.0
G6 G2
34 OUT T29_R2C_LSEO<1> T29_1_LSEO T29_3_LSEO T29_LSEO<1> OUT 42 NOTICE OF PROPRIETARY PROPERTY: BRANCH
T29 C2R LSEO<1> H5 H1 T29 LSOE<1>
34 IN T29_1_LSOE T29_3_LSOE IN 42 THE INFORMATION CONTAINED HEREIN IS THE
44 35 BI I2C_T29_SDA F3
T29_SDA I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
36 OF 110
I2C_T29_SCL F5
44 35 OUT T29_SCL III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D CRITICAL
=PP3V3 S0 T29P 6 7 11 23 D
135 mA (Single-Port)
6 =PP1V05_S0_T29P OMIT_TABLE 152 mA (Dual-Port)
H9 H7 1 1 1 1 1
2100 mA (Single Port) VCC1P0 U3600 VCC3P3 C3744 C3743 C3745 C3746 C3747 EDP: 200 mA
2250 mA (Dual Port) H11
VCC1P0 VCC3P3 M7 1UF 1UF 1UF 10UF 10UF
T29 10% 10% 10% 20% 20%
H13 K7 6 3V 6 3V 6 3V 6 3V 6 3V
EDP: 3000 mA C3700 1 1
C3705 1
C3706 1
C3707 1
C3708 1
C3709 VCC1P0 FCBGA VCC3P3 CERM 2 CERM 2 CERM 2 2 X5R 2 X5R
10UF 1UF 1UF 1UF 1UF 1UF K9
VCC1P0 (SYM 2 OF 2) 402 402 402 603 603
20% 10% 10% 10% 10% 10% G10
6 3V 6 3V 6 3V 6 3V 6 3V 6 3V K11 VCC3P3_T29
X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM VCC1P0 G12
603 402 402 402 402 402 K13 VCC3P3_T29
VCC1P0
M9
VCC1P0
M11
VCC1P0 P7
M13 VCC3P3_DP_RX1
VCC1P0 R6
VCC3P3_DP_RX1
C3701 1 1
C3710 1
C3711 1
C3712 1
C3713 1
C3714 H15 1 1 1 1
10UF 1UF 1UF 1UF 1UF 1UF VCC1P0_PE P9 C3753 C3752 C3751 C3750
VCC3P3_DP_TXRX
VCC
20% 10% 10% 10% 10% 10% K15
VCC1P0_PE 1UF 1UF 1UF 1UF
6 3V 6 3V 6 3V 6 3V 6 3V 6 3V P11 10% 10% 10% 10%
X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM M15 VCC3P3_DP_TXRX 6 3V 6 3V 6 3V 6 3V
603 402 402 402 402 402 VCC1P0_PE CERM 2 CERM 2 CERM 2 CERM 2
E8 402 402 402 402
VCC1P0_PE
E10
VCC1P0_PE
E12
VCC1P0_PE
G14
VCC1P0_PE
R8 P13
VDD1P0_DP_RX1 VDD3P3DP_PLL
R10
VDD1P0_DP_TXRX
R12
1 C3720 1 C3721 1 C3722 VDD1P0_DP_TXRX C3760 1
1UF 1UF 1UF 1UF
10% 10% 10% 10%
6 3V 6 3V 6 3V 6 3V
2 CERM 2 CERM 2 CERM CERM 2
402 402 402 402
C L3770
C
R3730 FERR-120-OHM-1.5A
4.7 R14 P15 1 2
1 2 PP1V05_S0_T29P_VDD_DPPLL VDD1P0_DP_PLL VCC3P3_DP_TXRXBIAS PP3V3_S0_T29P_DPBIAS
MIN LINE WIDTH=0 4 mm MIN LINE WIDTH=0 4 mm
5% MIN NECK WIDTH=0 2 mm MIN NECK WIDTH=0 2 mm 0402
1/16W VOLTAGE=1 05V VOLTAGE=3 3V
MF LF
402
1
C3730 C3770 1
10UF G8
VSS VSSDP T5 2.2UF
20% 20%
6 3V J8 T7 6 3V
2 CERM X5R VSS VSSDP CERM 2
0402 1 J10 T9 402 LF
VSS VSSDP
J12 T11
VSS VSSDP
J14 T15
VSS VSSDP
L8 T17
VSS VSSDP
L10 V17
VSS VSSDP
L12 W4
VSS VSSDP
L14 W6
VSS VSSDP
N8 W8
VSS VSSDP
N10 W10
VSS VSSDP
N12 W12
VSS VSSDP
N14 W14
VSS VSSDP
Y1
VSSDP
AA2
VSSDP
B1
VSSPE T13
B3 VSSDP_PLL
VSSPE
GND
B5 F9
VSSPE VSSPE
B7 F11
VSSPE VSSPE
B9 F13
VSSPE VSSPE
B B11
B13
VSSPE
VSSPE
VSSPE
VSSPE
F15
F17
B
B15 G18
VSSPE VSSPE
B17 G20
VSSPE VSSPE
B19 J16
VSSPE VSSPE
C18 J18
VSSPE VSSPE
C20 J20
VSSPE VSSPE
D1 L16
VSSPE VSSPE
D3 L18
VSSPE VSSPE
D5 L20
VSSPE VSSPE
D7 N16
VSSPE VSSPE
D9 N18
VSSPE VSSPE
D11 N20
VSSPE VSSPE
D13 R18
VSSPE VSSPE
D15 R20
VSSPE VSSPE
D17 U18
VSSPE VSSPE
E18 U20
VSSPE VSSPE
E20 W18
VSSPE VSSPE
F7 W20
VSSPE VSSPE
A SYNC_MASTER=T29_D SYNC_DATE=03/17/2011 A
PAGE TITLE
T29 Primary (2 of 2)
DRAWING NUMBER SIZE

REVISION
R
C.0.0
37 OF 110
Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CAESAR IV 1.2V INT.VR CMPTS CAESAR IV POWER ENABLE CIRCUIT CAESAR IV ACTIVITY LED
I298 26 25 7 =PP3V3 S3 ENET PHY FET
CRITICAL =PPVDDIO_ENET_CLK 22
L3800 PLACEMENT_NOTE=PLACE L3800 CLOSE TO U3900
4.7UH-0.8A =PP3V3 S3 ENET PHY FET 7 25 26
NOSTUFF
D
1
PCAA031B-SM
2 ENET_SR_LX
26
R3856
0
1
DEVELOPMENT
R3815
D
MIN_NECK_WIDTH=0.2MM 20 6 =PP3V3_S3_ENET_PHY 1 2 PP3V3_S3 ENET PHY_FET 330
VOLTAGE=1.2V MAKE_BASE=TRUE 5%
5% MIN_LINE_WIDTH=1.0 MM 1/16W
SWITCH NODE=TRUE 1/8W MIN_NECK_WIDTH=0.2 MM MF-LF
DIDT=TRUE 1 MF LF VOLTAGE=3.3V
R3853 Q3850 805 NET_SPACING_TYPE=SWITCHNODE 2 402
10K FDC606P_G ENET_ACT
5%
SOT-6
6
1/16W A
ENET_SR_VFB 26
MF-LF DEVELOPMENT
5
MIN_LINE_WIDTH=1.0MM 2 402 LED3800
D
4
2
VOLTAGE=1.2V GREEN 3 6MCD
2 0X1 25MM SM
1
K
=PP1V2 S3 ENET PHY 1 SILKSCREEN:ENET ACT

26 R3855
G
10K 1
C3853
5%
3
1/16W 0.1UF
MF-LF 10%
2 402
16V
PP1V2 S3 ENET INTREG 2 X7R CERM C3852
MAKE_BASE=TRUE R3852 402 0.1UF 26 IN ENET TRAFFICLED L ENET LED ACT L
MIN_LINE_WIDTH=1.0MM 100K MAKE_BASE=TRUE
1 MIN_NECK_WIDTH=0.2MM 1 2 ENET_PWR_ENABLE_L 1 2
C3825 1 C3827 1 C3828 1 C3829 1 C3830 1 C3831 1 C3826 VOLTAGE=1.2V
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 5%
10%
20% 10% 10% 10% 10% 10% 10% 1/16W
6.3V 16V 16V 16V 16V 16V 16V MF LF X5R
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 402 16V
603-2 402 402 402 402 402 402 ENET PWR EN L 402
3
PLACEMENT_NOTE=PLACE CLOSE TO L3800
PLACEMENT_NOTE=PLACE CLOSE TO L3800 D
R3801 Q3851
0 1 2N7002
20 IN ENET PWR EN 1 2 ENET PWR EN R G S SOT23-HF1
5%
1/16W 2
MF LF
402
C C
3
D
R3802 Q3852
0 1 2N7002
42 40 35 34 20 PM_S0_EN 1 2 PM_S0_EN_R G S
IN SOT23-HF1
5%
1/16W 2
MF LF
402
ADDED TO PREVENT SYSTEM UC WATCHDOG EVENT FROM POWERING DOWN ENET
I295
26 IN ENET CLK25M XTALO TP ENET XTALO
MAKE_BASE=TRUE
I297
B 26 ENET_CLK25M_XTALI SYSCLK_CLK25M_ENET
MAKE_BASE=TRUE
22
B
A SYNC MASTER=K62 SYNC DATE=09/16/2010 A

PAGE TITLE
CAESAR IV SUPPORT
DRAWING NUMBER SIZE

REVISION
R
C.0.0
38 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
=PP1V2_S3_ENET_PHY 25
281mA (1000base-T max power, Caesar IV) R3901
0 396mA (1000base-T, Caesar II)
26 25 7 =PP3V3_S3_ENET_PHY_FET 1 2 ENET_3V3_S3_SR_IN
SWITCH NODE=TRUE
5%
1/16W
DIDT=TRUE
NET SPACING TYPE=SWITCHNODE
1 C3980 1 C3981
MF LF
402
MIN LINE WIDTH 0 4 MM
MIN NECK WIDTH 0 2 MM
0.1UF 0.1UF
VOLTAGE 3 3V 10% 10%
16V 16V ENET_SR_LX
CRITICAL 2 X5R 2 X5R 25
1 C3979 402 402 Internal 1.2V Switching Regulator pins.
4.7UF L3900 CRITICAL
20% FERR-600-OHM-0.5A R3900 ENET_SR_VFB 25
6.3V L3920
2 CERM 0
1 2 PP3V3_S3_ENET_PHY_XTALVDDH ENET_XTALVDDH FERR-600-OHM-0.5A
D
603
SM
VOLTAGE=3 3V C3900 1
1
5%
1/16W
2
VOLTAGE=3 3V
PP1V2_S3_ENET_PHY_AVDDL 1 2
D
MF LF MIN LINE WIDTH=0 4 mm
0.1UF MIN NECK WIDTH=0 2 mm SM
402
10% VOLTAGE=1 2V
16V
2 1 1
X7R CERM
402
C3921 C3920
CRITICAL 0.1UF 4.7UF
10% 10%
L3905 16V
2 2
6 3V
CRITICAL
FERR-600-OHM-0.5A X7R CERM X5R CERM
402 603
L3925
1 2 PP3V3_S3_ENET_PHY_BIASVDDH FERR-600-OHM-0.5A
SM MIN NECK WIDTH=0 2 mm 1 2
VOLTAGE=3 3V 1 C3905 PP1V2 S3 ENET PHY PCIEPLL
0.1UF MIN NECK WIDTH=0 2 mm SM
10% VOLTAGE=1 2V
16V
2 X7R CERM
402
C3926 1 1
C3925
CRITICAL 0.1UF 4.7UF
10% 10%
L3910 16V
2 2
6 3V
CRITICAL
FERR-600-OHM-0.5A X7R CERM X5R CERM
R3942 IS A LEAKAGE PATH, SO RESISTOR 402 603
L3930
VALUE IS SMALL. 1 2 PP3V3 S3 ENET PHY AVDDH FERR-600-OHM-0.5A
20 6 =PP3V3_S0_ENET_PHY SM MIN NECK WIDTH=0 2 mm PP1V2_S3_ENET_PHY_GPHYPLL 1 2
VOLTAGE=3 3V R3910 1 1
C3910 1
C3911 MIN LINE WIDTH=0 4 mm
0.1UF 0.1UF MIN NECK WIDTH=0 2 mm SM
4.7K 10% 10% VOLTAGE=1 2V
5% 16V 16V
1/16W 2 X7R CERM 2 X7R CERM C3931 1 1 C3930
R3942 1 MF LF
402
402 402
0.1UF 4.7UF
Current 4.7K 2
10% 10%
Limiting 5% 16V
2 2
6 3V
1/16W X7R CERM X5R CERM
Resistor MF LF 402 603
402
2
NOSTUFF
R3998
R3940 1
1
0 R3941 1
C3917 1
C3918 C3915 1 1
C3916
ENET_VMAIN_CTRL 1 2 4.7K 4.7K 0.1UF 0.1UF 4.7UF 0.1UF
30
36
BIASVDDH 25
XTALVDDH 12
VDDO 42
SR_VDDP 10
SR_LX 11
27
33
39
18
21
GPHY_PLLVDDL 24
15
41
20 IN 1 1
10% 10% 10% 10% C3936 C3935
SR_VDD 9
SR_VFB 8
5% 5%
5% 1/16W
16V 16V 6 3V 16V
1/16W 2 2 2 2 0.1UF 10UF
C 1/16W MF LF MF LF
X7R CERM
402
X7R CERM
402
X5R CERM
603
X7R CERM
402 10% 10%
C
PCIE_PLLVDDL
MF LF 402 402 AVDDH AVDDL VDDC
402 2 2 16V 6 3V
X7R CERM 2 2 X5R
402 805
C3950
0.1uF
1 2
OMIT_TABLE
46 7 OUT PCIE_ENET_D2R_N
10%
U3900
16V C3951 ENET_VMAIN_PRSNT 40 VMAIN_PRSNT(IPD ENET) BCM57761A0KMLG TRD0_P 28 ENETCONN_MDI_P<0> BI 27 46
X5R
0.1uF QFN 29
402
1 2
TRD0_N ENETCONN_MDI_N<0> BI 27 46
46 7 OUT PCIE_ENET_D2R_P
46 PCIE_ENET_D2R_C_N 16 PCIE_TXD_N TRD1_P 32 ENETCONN_MDI_P<1> BI 27 46
10% 46 PCIE_ENET_D2R_C_P 17 PCIE_TXD_P TRD1_N 31 ENETCONN_MDI_N<1> BI 27 46
16V
X5R
TRD2_P 34 ENETCONN_MDI_P<2>
C3955 402 46 PCIE_ENET_R2D_P 22 PCIE_RXD_P BI 27 46
0.1uF TRD2_N 35 ENETCONN_MDI_N<2> 27 46

46 PCIE_ENET_R2D_N 23 BI
1 2
PCIE_RXD_N 38
46 7 IN PCIE_ENET_R2D_C_P TRD3_P ENETCONN_MDI_P<3> BI 27 46
46 22 IN PCIE_CLK100M_ENET_P 20 PCIE_REFCLK_P TRD3_N 37 ENETCONN_MDI_N<3> BI 27 46

10%
16V C3956 46 22 IN PCIE_CLK100M_ENET_N 19 PCIE_REFCLK_N
X5R
0.1uF
402
6 GPIO_0 3 ENET_WOL_ENABLE OUT 20
(IPD
46 7 IN PCIE_ENET_R2D_C_N 1 2
7 IN ENET_RESET_L PERST* (IPD)
ENET_WAKE:PCIE 7
10% ENET_CLKREQ_L CLKREQ*
R3943 16V
22 OUT (OD)
0 X5R
26 7 =ENET_WAKE_L 1 2 402 ENET_WAKE_R_L 1 WAKE* (OD)
ENET_WAKE:GPIO
OUT
R3999
(See note) 5%
0
1/16W 1 2
ENET_LOW_PWR 2 =ENET_WAKE_L OUT 7 26
MF LF 7 IN LOW_PWR (IPD)
WAKE# 402
5%
1/16W
Must isolate from PCIe WAKE# if PHY ENET_SMB_CLK 4 SMB_CLK MF LF
402
is powered-down in S3/S5. Standard ENET SMB DATA 5 SMD_DATA (IPD ENETM)
N-channel FET isolation suggested. 46

26 ENET_SCLK SCLK/SPD1000LED*
B If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.
26
BI
IN ENET_MISO 44 SI*/EEDATA B
(IPU
26 BI ENET MOSI 45 SO*/LINKLED*
26 BI ENET CS L 43 CS*/EECLK
TP_ENET_SPD100LED_L 48 SPD100LED* (OD)
25 OUT ENET TRAFFICLED L 47 TRAFFICLED* (OD)
25 IN ENET CLK25M XTALI 13 XTALI

25 OUT ENET_CLK25M_XTALO 14 XTALO
ENET RDAC 26 RDAC

THRM_PAD
PHY Non-Volatile Memory
49
1
R3965
ROM contains MAC address, PCIe config 1.24K
1%
info as well as code for Bonjour proxy. 1/16W
MF LF
Avoids need for EFI to program at startup. 2 402
(Required ROM size 1 Mbit)
26 25 7 =PP3V3_S3_ENET_PHY_FET
R3993 1 R3992 1
6
4.7K 4.7K 1
C3990
5% 5%
1/16W 1/16W
VCC 0.1UF
10%
MF LF
402
2
MF LF
402
2 U3990 2
16V
X7R CERM
R3904 M45PE10 402
0 SOIC
26 IN ENET_SCLK 1 2 ENET_SCLK R 2 C OMIT_TABLE D 1 ENET_MOSI IN 26
A 26 ENET_CS_L
5% 402
1/16W
MF LF 4 S*
SYNC_MASTER=TONY SYNC_DATE=10/01/2010 A
IN PAGE TITLE
Q 8 ENET_MISO OUT
ENET_SWP_L 5 W*
NOSTUFF
26
ETHERNET PHY (CAESAR IV)
DRAWING NUMBER SIZE
ENET SRESET L 3 RESET* 1
R3990
1
R3997
VSS 4.7K 4.7K Apple Inc. 051-8774 D
5% 5% REVISION
7
NOTE: Pull-down on SO plus internal pull-ups on 1/16W 1/16W R

MF LF MF LF C.0.0
other 3 SPI pins configures ENET for the 2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Atmel AT45DB011D (1Mbit) ROM. If a different THE INFORMATION CONTAINED HEREIN IS THE
ROM is used then the straps must change. PROPRIETARY PROPERTY OF APPLE INC.
NOTE: ENETM requires SI pull-down instead of SO. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 39 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CRITICAL
T4000
LFE9249APF
SOI
1 TCT1 MCT1 24 ENETCONN_MCT0
2 TD1+ 1CT:1CT MX1+ 23

C 46 26 BI ENETCONN_MDI_P<0> ENETCONN_MDI_T_P<0> BI 27 46
C
46 26 ENETCONN_MDI_N<0> 3 TD1- MX1- 22 ENETCONN_MDI_T_N<0> BI 27 46
CRITICAL
BI
J4000
4 TCT2 MCT2 21 ENETCONN_MCT1
RJ45-J59
F-ANG-TH
ENET_MDI
46 26 BI ENETCONN_MDI_N<1> 5 TD2+ 1CT:1CT MX2+ 20 ENETCONN_MDI_T_N<1> BI 27 46 46 27 BI ENETCONN_MDI_T_P<0> 1
TRAN_P0
46 27 BI ENETCONN_MDI_T_N<0> 2
TRAN_N0
46 26 BI ENETCONN_MDI_P<1> 6 TD2- MX2- 19 ENETCONN_MDI_T_P<1> BI 27 46 46 27 BI ENETCONN_MDI_T_P<1> 3
TRAN_P1
46 27 ENETCONN_MDI_T_P<2> 4
BI TRAN_P2
7 TCT3 MCT3 18 ENETCONN MCT2 46 27 BI ENETCONN MDI T N<2> 5
TRAN_N2
TRAN_N1
46 26 BI ENETCONN_MDI_P<2> 8 TD3+ 1CT:1CT MX3+ 17 ENETCONN_MDI_T_P<2> BI 27 46
46 27 ENETCONN_MDI_T_P<3> 7
BI TRAN_P3
TRAN_N3
46 26 BI ENETCONN_MDI_N<2> 9 TD3- MX3- 16 ENETCONN_MDI_T_N<2> BI 27 46
9
10 TCT4 MCT4 15 ENETCONN_MCT3 SHIELD
10 PINS
46 26 BI ENETCONN_MDI_N<3> 11 TD4+ 1CT:1CT MX4+ 14 ENETCONN_MDI_T_N<3> BI 27 46
514-0779
46 26 BI ENETCONN_MDI_P<3> 12 TD4- MX4- 13 ENETCONN_MDI_T_P<3> BI 27 46
157S0071
B B
PLACE C4001/2/3/4 CLOSE TO PINS 1/4/7/10 ON T4000!!
1 1 1 1
ENETCONN_TCT R4000 R4001 R4002 R4003
75 75 75 75
5% 5% 5% 5%
1 C4001 1 C4002 1 C4003 1 C4004 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 2 402 2 402 2 402 2 402
2 10V
CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
402 402 402 402
ENETCONN_MCT_BS
NOSTUFF
1 C4000
NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps. 1000PF
10%
2 2KV
CERM
1206
NOTE: BOB SMITH TERMINATION FOR EMC.

PAGE TITLE
Ethernet Connector
DRAWING NUMBER SIZE

REVISION
R
C.0.0
40 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_S0_FWPHY 6 28 29 30
7 mA I/O
138 mA
1 1 1 1 1
C4120 C4121 C4122 C4123 C4124
1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
6 3V 6 3V 6 3V 6 3V 6 3V
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
402 402 402 402 402
CRITICAL
L4130
120-OHM-0.3A-EMI
D 114 mA FireWire PHY
PP3V3_FW_FWPHY_VDDA 1 2
D
MIN NECK WIDTH=0 2 MM 0402 LF
VOLTAGE=3 3V
C4130 1
C4131 1
C4132 1
1UF 1UF 1UF

10% 10% 10%
6 3V 6 3V 6 3V
CERM 2 CERM 2 CERM 2
402 402 402
K18 has 0.475-ohm upstream of L4110
CRITICAL CRITICAL
L4110 L4135
29 =PP1V0_S0_FWPHY 120-OHM-0.3A-EMI 120-OHM-0.3A-EMI
1 2
25 mA PCIe SerDes 17 mA PCIe SerDes 1 2
135 mA PP1V0_FW_FWPHY_AVDD PP3V3_FW_FWPHY_VP25
MIN LINE WIDTH=0 4 MM MIN LINE WIDTH=0 4 MM
0402 LF MIN NECK WIDTH=0 2 MM MIN NECK WIDTH=0 2 MM 0402 LF
VOLTAGE=1 0V VOLTAGE=3 3V
1 C4110 1 C4111 C4135 1 C4136 1
1UF 1UF 1UF 1UF

10% 10% 10% 10%
6 3V 6 3V 6 3V 6 3V
2 CERM 2 CERM CERM 2 CERM 2
402 402 402 402
110 mA Digital Core 0 mA VReg PWR
1
C4100 1
C4101 1
C4102 1
C4103 1
C4104 1
C4105 1
C4106 C4141 1 1
C4140
1UF 1UF 1UF 1UF 1UF 1UF 1UF 0.1UF 1UF
10% 10% 10% 10% 10% 10% 10% 20% 10%
6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 10V 6 3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 2 CERM
402 402 402 402 402 402 402 402 402
C PLACEMENT NOTE=Place C4170 close to U1800

PLACEMENT NOTE=Place C4171 close to U1800
C
C4170
B12
C13
E10
H12
M12
N11
C12
G12
L11
A12
L10
K12
APN: 338S0753 -> 1 2 16V PCIE_FW_R2D_C_N
A1
B1
E2
H2
K2
L1
N3
C1
F1
J1
L3
M2
D5
D6
D8
L5
L6
L9
IN 7 46
0.1UF10% X5R 402
VDD10 VDD33 VDDH VP VP25 VREG_PWR C4171 1 2 16V PCIE_FW_R2D_C_P IN 7 46
OMIT_TABLE 0.1UF10% X5R 402
B13 ATBUSB PCIE_RXD0N N8 46 PCIE FW R2D N
NC CRITICAL
NC
A13 ATBUSH PCIE_RXD0P N7 46 PCIE_FW_R2D_P
U4100 C4175 1 2 16V
NC A11 ATBUSN PCIE_TXD0N N5 46 PCIE_FW_D2R_C_N PCIE_FW_D2R_N OUT 7 46
0.1UF10% X5R 402
FW643 PCIE_TXD0P N6 46 PCIE_FW_D2R_C_P
29 IN FW PHY DS0 F12 DS0 (IPD) NT-19 C4176 1 2 16V
BGA
PCIE_FW_D2R_P OUT 7 46
29 IN FW_PHY_DS1 E12 DS1 (IPD) NT-20 0.1UF10% X5R 402
REFCLKN N9 PCIE_CLK100M_FW_N IN 22 46
29 IN FW_PHY_DS2 E13 DS2 (IPD) NT-21 PCI EXPRESS PHY PLACEMENT NOTE=PLACE C4175 CLOSE TO U4100
REFCLKP N10 PCIE_CLK100M_FW_P IN 22 46 PLACEMENT NOTE=PLACE C4176 CLOSE TO U4100
29 BI FW_P0_TPA_N B8 TPA0N
29 BI FW_P0_TPA_P A8 TPA0P
NT-4 (IPU) TCK M4 TP_FW643_TCK
NT-3 (IPU) TDI N2 TP_FW643_TDI
29 BI FW_P1_TPA_P A5 TPA1P TEST CONTROLLER =PP3V3_S0_FWPHY 6 28 29 30
(IPU) TDO M1 TP_FW643_TDO
NT-1 (IPU) TMS M3 TP_FW643_TMS
29 BI FW_P2_TPA_P A3 TPA2P 1394 PHY NOSTUFF
R4165 1
FW_P0_TPB_N B9 N1 FW643_TRST_L 1
29 BI TPB0N NT-2 (IPU) TRST* R4166
29 BI FW_P0_TPB_P A9 TPB0P 10K 10K
5% 5%
29 BI FW P1 TPB N B6 TPB1N 1/16W 1/16W
MF LF MF LF
FW_P1_TPB_P A6 TPB1P NT-10 (IPD) 402 2
2 402
29 BI
WAKE* C2 FW_PME_L OUT 7
29 BI FW_P2_TPB_N B4 TPB2N NT-12 (IPD)
30 PPVP_FW_PHY_CPS FIXME!!! TYPO IN SYMBOL REGCTL REGCLT D13 FW643_REGCTL
29 BI FW_P2_TPB_P A4 TPB2P
PLACEMENT NOTE=Place close to U4100 B10 POWER MANAGEMENT VAUX_DETECT E1 FW643 VAUX DETECT
R4160 1 29 BI FW_P0_TPBIAS B7 TPBIAS0 FIXME!!! TYPO IN SYMBOL VAUX ENABLE VAUX_DISABLE D2 TP_FW643_VAUX_ENABLE
B 200K
1%
1/16W
29
29
BI
BI
FW_P1_TPBIAS
FW_P2_TPBIAS
C3
A2
TPBIAS1
TPBIAS2
NT-13 (OD) CLKREQN L2 FW_CLKREQ_L OUT 22
1
R4164
10K
B
MF LF 5%
402 1/16W
2 FW643 R0 B11 R0 MF LF
FW643_TPCPS B10 TPCPS 2 402
NT-16 (IPD) SCIFCLK G2 TP_FW643_SCIFCLK
SCIF NT-14 (IPD) SCIFDAIN G1 TP FW643 SCIFDAIN
C4150 TP_FW643_NAND_TREE K1 NAND_TREE NT-OUT
R4150 NT-17 SCIFDOUT H1 TP FW643 SCIFDOUT
22PF FW643_REXT L8 REXT
1 2
412 NOTE: NT-xx notes show NT-15 (IPD) SCIFMC F2 TP FW643 SCIFMC
FW_CLK24P576M_XO 1 2 FW_CLK24P576M_XO_R F13 XO
NAND tree order.
5%
1% FW_CLK24P576M_XI G13 XI NT-9
50V
CRITICAL 1/16W
MF LF
1
CERM
402 NC Y4150 402 TP_FW643_SE M13 SE (IPD)
R4161 1 1
R4170 SERIAL EEPROM NT-7 SCL N12 FW643 SCL
2
OUT 29
NC 24.576MHZ TP_FW643_SM N13 SM (IPD) CONTROLLER
2.94K 191 NT-6 SDA M11 FW643_SDA
4
C4151 SM 3 2X2 5MM

1% TP_FW643_MODE_A J2 MODE_A (IPD) NT-18
BI 29
3
1%
22PF 1/16W 1/16W
MF LF MF LF TP FW643 CE L13 CE (IPD)
1 2
402 402
2 2 TP FW643 FW620 L D12 FW620* (IPU) MISCELLANEOUS
5% TP FW643 JASI EN D1
50V
JASI_EN (IPD) NT-11
CERM TP_FW643_AVREG A10 AVREG CHIP RESET NT-5 PERST* N4 FW_RESET_L 7
402 IN
TP_FW643_VBUF H13 VBUF
FW643_PU_RST_L K13 FW_RESET* (IPU) NT-8
29 FW643_OCR10_CTL J12 OCR_CTL_V10

R4162 1 1
C4162 J13 OCR_CTL_V12 (Reserved)
External power-on reset (IPU 100K): 470K NC
5%
0.33UF
Per LSI, R4162 and C4162 can be NOSTUFF -> 1/16W 10% VSS VREG_VSS
6 3V
MF LF 2
L12
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
CERM X5R
402 402
2

PAGE TITLE
FireWire LLC/PHY (FW643)

DRAWING NUMBER SIZE

REVISION
R
C.0.0
41 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Termination
FW643 1.0V GENERATION Place close to FireWire PHY
D CRITICAL
Q4200
28 FW_P0_TPBIAS
VOLTAGE=1.86V
D
BCP6916DG
SOT223-4
2 PP1V0 S0 FW VDD
NET_SPACING TYPE=POWER
=PP1V0 S0 FWPHY 28
1 C4250 R42501 1
R4251
MAX_NECK_LENGTH=3MM 0.33UF 56.2 56.2
MAKE_BASE=TRUE 10% 1% 1%
30 29 28 6 =PP3V3_S0_FWPHY 3 4 1 C4210 1 C4211 1 C4212 1 C4213 MIN_LINE_WIDTH=0.6MM
2 6.3V
CERM-X5R 1/16W
MF-LF
1/16W
MF-LF
0.1UF 0.1UF 10UF 10UF VOLTAGE=1.0V 402
402 2
20% 20% 20% 20% 2 402
1 10V
2 CERM 2 10V 2 6.3V 2 6.3V
CERM CERM CERM
1 C4200 1 C4201 402 402 805-1 805-1
2.2UF 2.2UF
20% 20% NOTE: MULTIPLE VIAS TO DGND
2 6.3V
CERM
6.3V
2 CERM NOTE: Q4200 COLLECTOR CONNECT TO CAPS WITH 0.4 SQ-IN HEAT SINK
402-LF 402-LF
28 FW P0 TPA P FW_PORT0_TPA_P 30 46
MAKE BASE=TRUE
28 FW_P0_TPA_N FW_PORT0_TPA_N 30 46
MAKE BASE=TRUE
28 FW_P0_TPB_P FW_PORT0_TPB_P 30 46
MAKE BASE=TRUE
28 FW_P0_TPB_N FW_PORT0_TPB_N 30 46
MAKE BASE=TRUE
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY 1
R4200 R42521 R4253
75 56.2
28 FW643_OCR10_CTL 1 2 FW_OCR10_CTL_R 56.2 1%
NET_SPACING_TYPE=SWITCHNODE NET_SPACING_TYPE=SWITCHNODE 1% 1/16W
MIN_LINE_WIDTH=0.25MM 5% MIN_LINE_WIDTH=0.25MM 1/16W MF-LF
MIN_NECK_WIDTH=0.2MM 1/16W MIN_NECK_WIDTH=0.2MM MF-LF
DIDT=TRUE MF-LF DIDT=TRUE 402 2 2 402
402
C FW643 GUID ROM

FW_P0_TPA_C
C
1
R4254
C4254 1
1%
4.99K
=PP3V3_S0_FWPHY 6 28 29 30
220PF 1/16W
1 1 5%
R4298 R4299 25V MF-LF
4.7K 4.7K CERM 2 2 402
402
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402
8
VCC 1
OMIT_TABLE R4290
5 SDA E2/NC2 3 10K
28 FW643_SDA 5%
E1/NC1 2 1/16W
MF LF
28 FW643_SCL 6 SCL E0/NC0 1 402 2
U4290 WC* 7 FWROM_WC_L

M24C02-WMN6TPHF
SO8
VSS
4
2ND & 3RD TPA/TPB PAIR UNUSED
28 FW P1 TPBIAS NC FW PORT1 TPBIAS
MAKE BASE=TRUE
NO TEST=TRUE
28 FW_P1_TPA_P NC_FW_PORT1_TPA_P
MAKE BASE=TRUE
NO TEST=TRUE
28 FW_P1_TPA_N NC_FW_PORT1_TPA_N
MAKE BASE=TRUE
B 1394 PHY DATA/STROBE OPTIONS NO TEST=TRUE
B
28 FW P1 TPB P NC FW PORT1 TPB P
MAKE BASE=TRUE
NO TEST=TRUE
30 29 28 6 =PP3V3_S0_FWPHY 28 FW_P1_TPB_N NC_FW_PORT1_TPB_N
MAKE BASE=TRUE
NO TEST=TRUE
NOSTUFF 28 FW_P2_TPBIAS NC_FW_PORT2_TPBIAS

1 MAKE BASE=TRUE
R4255 1R4256 1R4257 NO TEST=TRUE
10K 10K 10K FW_P2_TPA_P NC_FW_PORT2_TPA_P
5% 5% 5% 28
1/16W 1/16W 1/16W MAKE BASE=TRUE
MF-LF MF-LF MF-LF NO TEST=TRUE
2 402 2 402 2 402 28 FW_P2_TPA_N NC_FW_PORT2_TPA_N
MAKE BASE=TRUE
NO TEST=TRUE
28 FW_PHY_DS0
28 FW_P2_TPB_P NC_FW_PORT2_TPB_P
28 FW PHY DS1 MAKE BASE=TRUE
THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT NO TEST=TRUE
28 FW_PHY_DS2 IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE, FW643 28 FW_P2_TPB_N NC_FW_PORT2_TPB_N
MAKE BASE=TRUE
HAS INTERNAL 100K PULL-DOWNS, ONLY PULL-UPS NECESSARY. NO TEST=TRUE
1 NOTE: AGERE’S RECOMMENDATION FOR UNUSED PORTS

R4258
10K
5%
1/16W
MF-LF
2 402

PAGE TITLE
FireWire: 1394B MISC

DRAWING NUMBER SIZE

REVISION
R
C.0.0
42 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
INRUSH RESETABLE PTC

CRITICAL PLACEMENT NOTE=PLACE CLOSE TO D4300
POUR COPPER TO SINK HEAT
CRITICAL
F4301 XW4300
1 2 PPVP_FW_PHY_CPS
0.3AMP-60V OUT 28
12 VOLTS Q4350 1 2 SM
FDC610PZ VOLTAGE=12V
14 WATTS MAX PER PORT SSOT6

CRITICAL
SMD030F-SM
POUR COPPER TO SINK HEAT
6
R4300 CRITICAL CRITICAL
CRITICAL CRITICAL
L4300
5
0.33 2 Q4300 F4300
=PP12V_S0_FW PP12V_S0_VG_OK P12V_FW_R D4300 D
4
1
FERR-250-OHM
D 30 6
2
5%
MIN LINE WIDTH=1 7MM FDC610PZ SM 3AMP-32V
MIN NECK WIDTH=0 5MM MIN NECK WIDTH=0 5MM
P12V_FW_CL P12V_FW_D FW_PORT0_VP_F FW_PORT0_VP
1
VOLTAGE=12V 1W VOLTAGE=12V 1 2 1 2 1 2
MF SSOT6
MIN LINE WIDTH=1 7MM MIN LINE WIDTH=1 7MM MIN LINE WIDTH=1 7MM MIN LINE WIDTH=1 7MM
2512 MIN NECK WIDTH=0 5MM MIN NECK WIDTH=0 5MM MIN NECK WIDTH=0 5MM SM MIN NECK WIDTH=0 5MM
6
VOLTAGE=12V CRS08-1.5A-30V VOLTAGE=12V 603 VOLTAGE=12V VOLTAGE=12V
2 5
1 FAST NON-RESETABLE FUSE
4
R4351 NOSTUFF
1K C4351 1 THIS FUSE WILL NOT BLOW
1 C4300
0.01UF
1
5%
1/16W
0.001UF 3
NOSTUFF IT IS HERE FOR SAFETY ONLY 10%
MF LF
20% 50V SHOULD BE DONE AS A POWER STRIP(SUBPLANE)
50V
2 402 CERM 2
402
Q4301 5.1V 3 D4305 2 X7R
603-1
3
MMBT2907AXG D4301 1 MMBD914XG
60V-600MA SOT23
FWPWR_ON_L SOT23 MMBZ5231BXG 1
SOT23
3
1
R4355
1K R4352
5% 51.1K2
1/16W
MF LF
1 30 FW CURRENT LIMIT
402 1%
2 1
1/16W R4301 PORT 0
FWPWR_EN_L
MF-LF 10K FW_TURN_ON_V

402
5%
1/16W 1
1394B
MF-LF
2 402
R4302 1R4303
15K 20K CRITICAL
5% 5%
FW_CURRENT_LIMIT_Q 1/10W
MF-LF
1/16W
MF-LF
J4300
2 603 2 402
FWB-PL-J59
3 3 F-ANG-TH
D Q4302 1 FW_FET_LINEAR_LIMIT_OUT FW_PORT0_TPB_N 1 TPB TPB(R)
Q4351 MMBT2222A7F IN 30
46 30 29 BI
9
2N7002 SOT23 FW FET LINEAR LIMIT IN OUT 30
1 G S SOT23-HF1 2 PLACE CLOSE TO COMPARATOR 46 30 29 BI FW_PORT0_TPB_P 2 TPB+ VP
1 8
2 1 C4302 R4307 7
20K
C 0.01UF
20%
16V
5%
1/16W
NC
6
SC/NC
C
2 CERM MF-LF 46 30 29 BI FW_PORT0_TPA_N 3 TPA VG
402 2 402
FW_PORT0_TPA_R 5
46 30 29 BI FW_PORT0_TPA_P 4 TPA+ TPA(R)
10
SHIELD
NOSTUFF 11 PINS
R4304 D4302 C4332 1

100K 2 BAS40XG 514-0778
1 FW_FET_LINEAR_LIMIT_FB 1 3 0.001UF
10%
50V
5% AREF needs to be isolated from all CERM 2
1/16W SOT23 402
MF-LF 30 6 =PP12V_S0_FW local grounds per 1394b spec
402
When a billingual device is connected to a
beta-only device, there is no DC path
1 C4304 between them (to avoid ground offset issue)
CRITICAL 8 0.1UF
10% R43351 1 C4335
V+ 2 16V
X7R-CERM BREF should be hard-connected to logic 1M 0.1UF
10%
U4300 402
ground for speed signaling and connection 1%
1/16W 2 50V
LM393 X7R
MF-LF 603-1
5.1V 6 SOI-HF 402 2
7
D4303 5 NC
R4305 SOT23
FW_CURRENT_LIMIT 100K 2 3 1 2
30 IN 1 FW_CURRENT_LIMIT_R FW_CURRENT_LIMIT_RD 1 FW_FET_LINEAR_LIMIT_OUT OUT 30
5% 30 FW FET LINEAR LIMIT IN 3
1/16W IN
MF-LF MMBZ5231BXG
402 GND
4
B PLACE CLOSE TO COMPARATOR
C4305 1
1
R4306 B
200K
2.2UF 5%
10% 1/16W
16V 2 MF-LF
X5R 2 402
603
ACTIVE "LATE VG" + ESD PROTECTION

29 28 6
=PP3V3_S0_FWPHY
C4350 1
0.1UF
10%
16V
PLACEMENT NOTE=PLACE U4350 CLOSE TO J4300 X7R-CERM 2
402
1
VCC
U4350
TPD4S1394
TP_FW_LATEVG_VCLMP 3 VCLMP LLP 8
CRITICAL D1+ FW_PORT0_TPA_P BI 29 30 46
FWPWR_EN D1- 7 FW_PORT0_TPA_N BI 29 30 46
A NOSTUFF
4 FWPWR_EN
D2+ 6 FW_PORT0_TPB_P BI 29 30 46
SYNC MASTER=K62 SYNC DATE=09/23/2010 A
PAGE TITLE
1 D2- 5 FW_PORT0_TPB_N
R4350
100K
GND BI 29 30 46
FIREWIRE CONNECTOR
2
5% DRAWING NUMBER SIZE

1/16W
MF-LF
2 402 REVISION
R
C.0.0
43 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
L4526 VOLTAGE=3.3V
FERR-120-OHM-3A MIN LINE WIDTH=0 6MM
33 32 31 6 =PP3V3_S5_USB 1 2 VDDPLL3V3_H1
0603
1 C4511 1 C4599 1 C4500 1 C4512 =PP3V3_S5_USB 6 31 32 33
0.01UF 100PF 10UF 0.1UF
10% 5% 20% 10%
25V 50V 6.3V 16V
1
C4559 2 X7R 2 CERM 2 X5R 2 X7R-CERM 1 C4502 1 C4503 1 C4505 1 C4506
100UF 402 402 603 402
0.1UF 0.1UF 0.01UF 0.01UF
20% 10% 10% 10% 10%
2 16V 2 16V 16V 2 25V 2 25V
ELEC
6.3X5.5-SM3
L4527 VOLTAGE=3.3V
X7R-CERM
402
2 X7R-CERM
402
X7R
402
X7R
402
FERR-120-OHM-3A
D 1 2
VDDA3V3_H1 D
0603
1 C4513 1 C4501 1 C4518 1 C4514 1 C4515 1 C4516 1 C4517 MIN LINE WIDTH=0 6MM
0.01UF 100PF 10UF 0.1UF 0.1UF 0.1UF 0.1UF MIN NECK WIDTH=0 25MM
10% 5% 20% 10% 10% 10% 10% VOLTAGE=1.8V
25V
2 X7R
50V
2 CERM
6.3V
2 X5R
16V
2 X7R-CERM
16V
2 X7R-CERM
16V
2 X7R-CERM
16V
2 X7R-CERM
VDD1V8 H1
VOLTAGE=1.8V
402 402 603 402 402 402 402 MIN LINE WIDTH=0 6MM
VDD1V8PLL_H1
1 C4504 1 C4509 1 C4507 1 C4508
10
52
57
VDD33PLL 64
VDD33CR 24
VDD33 46
VDD18 25
VDD18PLL 62
5
CRITICAL 33 32 31 6 =PP3V3_S5_USB 0.1UF 1UF 0.1UF 1UF
10% 10% 10% 10%
Y4500 VDDA33 2 16V
X7R-CERM 2 6.3V
CERM 2 16V
X7R-CERM 2 6.3V
CERM
24.000M-60PPM-16PF 402 402 402 402
1 2 NOSTUFF 1
R45011 R4504
5X3 2X1 4 SM 10K 100K
1 C4575 1 C4577 PP4503 5% 5%
1/16W
5%
18PF
5%
18PF 1P0-BOT
SM
1/16W
MF-LF MF-LF U4500
50V 50V PP
1 402 2 2 402 USB2517
2 CERM 2 CERM 1 USBDN1_H1_DM
402 R4573 402 19 TEST LLP USBDN1_DM/PRT_DIS_M1
2
OUT 33 46
1
1.0M 2 USBDN1_DP/PRT_DIS_P1 USBDN1_H1_DP OUT 33 46
20 USB HUB RESET L 43 RESET* CRITICAL

5% IN 3 USBDN2_H1_DM
USBDN2_DM/PRT_DIS_M2 OUT 33 46
1/10W
MF-LF XTAL1_H1 61 XTAL1/CLKIN USBDN2_DP/PRT_DIS_P2 4 USBDN2_H1_DP 33 46
603 OUT
CRITICAL XTAL2_H1 60 XTAL2
=PP3V3_S5_USB USBDN3_DM/PRT_DIS_M3 6 USBDN3_H1_DM 33 46
33 32 31 6 OUT
USB_NON_REM0 45 SUSP_IND/LOCAL_PWR/NON_REM0 USBDN3_DP/PRT_DIS_P3 7 USBDN3_H1_DP 33 46
OUT
40 8 USB AUDIO DM
R4577
SDA/SMBDATA/NON_REM1 USBDN4_DM/PRT_DIS_M4 11 46
R4575
OUT
NO STUFF
NO STUFF
2
2
USBDN4_DP/PRT_DIS_P4 9 USB_AUDIO_DP
1/16W
MF-LF
10K
OUT 11 46
41
1/16W
MF-LF
10K
=PP3V3_S5_USB
R4520
402
SCL/SMBCLK/CFG_SEL0
5%
R4510
6 31 32 33
402
NO STUFF
5%
2
NOSTUFF 8 CRITICAL USB_CFG_SEL1 42 HS_IND/CFG_SEL1 11 USB_CAMERA_DM 10 46 100K 2

USBDN5_DM/PRT_DIS_M5 OUT
1/16W
MF-LF
10K
1
13 12
402
USB CFG SEL2 USB CAMERA DP

5%
1
VCC CFG_SEL2 10 46
C4521 C
1
OUT
C 3 E2/NC2
SDA 5 NC
51 LED_A1*/PRT_SWP1
USBDN5_DP/PRT_DIS_P5
53
NC
5%
1/16W
MF-LF
1 C4520
0.1UF
1
0.1UF
1
2 E1/NC1 USBDN6_DM/PRT_DIS_M6 402 10%

1 1 49 54 10% 16V
1 E0/NC0 SCL 6 R4502 R4503 NC LED_A2*/PRT_SWP2 USBDN6_DP/PRT_DIS_P6 NC 16V 2 X7R-CERM
NO STUFF
47 2 X7R-CERM 402
1 C4510 10K 10K NC LED_A3*/PRT_SWP3 55 402
WP_H1 7 WC* U4512 I2C PULLUPS ON P52 5% 5% 33 USB_UC_DM OUT 20 46
0.1UF 1/16W 1/16W LED_A4*/PRT_SWP4 USBDN7_DM/PRT_DIS_M7
10% M24C02-WMN6TPHF MF-LF MF-LF NC 56 USB_UC_DP 20 46
31 USBDN7_DP/PRT_DIS_P7 OUT 5
16V
2 X7R-CERM SO8
VSS
402 2 2 402 NC
17
LED_A5*/PRT_SWP5
29 PRTPWR_H1
U4520
1
74LVC1G32
402
4
NC
15
LED_A6*/PRT_SWP6 PRTPWR1
26
SOT553-5
4
U4521
1
5 SN74LVC1G132
NC LED_A7*/PRT_SWP7 PRTPWR2 NC SC70-5
PRTPWR3 23 33 20 WALL_CHRG_ON 2 32 4 VBUS_DISCHARGE OUT 33
50 LED_B1*/BOOST0 NC IN
NC PRTPWR4 20 P4_PWR OUT 19 2
48 LED_B2*/BOOST1 3
NC PRTPWR5 30
CFG_SEL[1:0] 34 LED_B3*/GANG_EN NC 3
NC PRTPWR6 39
01 - EXTERNAL MASTER 32 LED_B4* NC
11 - EXTERNAL ROM NC
18 LED_B5*
PRTPWR7 36 VBUS_UC OUT 20 PP4502
1P0-BOT
00 - NO ROM NC SM
=I2C_USBHUB_SCL 16 LED_B6* OCS1* 28 OC_H1_L 1
35 IN NC IN 33 PP
14 LED_B7* OCS2* 27
35 BI =I2C_USBHUB_SDA NC NC
OCS3* 22
NC
OCS4* 21 VBUS_DNSTREAM_ENAB
NC OUT 33
OCS5* 35
=PP3V3_S5_USB
NC
OCS6* 38
33 32 31 6
NC CRITICAL
37
OCS7* NC R4579 R4506
63 RBIAS_H1 1
12K 2 100K 2
RBIAS 1
C4540 1 1 C4542 VBUS_DET 44 VBUS DET
1%
1/16W 5%
1/16W
0.1UF 0.1UF MF
402 MF-LF
10% 10% 58 402
16V 16V USBUP_DM USB_HUB_UP_DM 31 46
X7R-CERM 2 2 X7R-CERM
402 402 USBUP_DP 59 USB_HUB_UP_DP 31 46 R4507
100K 2
B THRML_PAD 1
5%
B
65
1/16W
5 74LVC1G08 MF-LF
USB_BUSPWR_SW 1 SOT553 5 402
20 IN
4 1
74LVC1G32
U4540 UC_OR_HOST_BUSPWR SOT553-5
USB_HOST_BUSPWR_EN 2 08 4 (VBUS DET)
32 IN
2
U4542
3 32
USB DEV CONNECTOR DEVELOPMENT CONNECTOR USB MUX

DEVELOPMENT R45601 0 2
PRODUCTION
J4590 DEVELOPMENT
MF-LF 5%
402
1/16W =PP3V3_S5_USB 6 31 32 33
UH51543-S7-7F USB DEV VBUS LS
F-RT-SM L4580 DEVELOPMENT OUT 20 31
R45611 0 2PRODUCTION
6 FERR-120-OHM-3A R4580 R4581 MF-LF 5% 1/16W DEVELOPMENT
7 USB_DEV_VBUS_F 27K 33K
1 2 1 2 1 2 402
C4560 1
9
0603 5% 5% 0.1UF
1 1/16W 1/16W VCC 10%
VBUS USB_DEV_VBUS MF-LF MF-LF 16V
402 402 X7R-CERM 2
2 46 USB DEV DM 46 32 USB HOST DP 5 M+ DEVELOPMENT Y+ 1 USB HUB UP DP 31 46 402
D- IN
D+
3 46 USB DEV DP L4585
120-OHM
46 32 IN USB HOST DM 4 M- Y- 2
U4560 USB HUB UP DM 31 46
NC
NC
NC
NC
A ID
GND
4
5
NC L701-SM
SYM_VER 1
46 31 USB_DEV_F_DP 7 D+
PI3USB102ZLE
TQFN
SEL=1 : DEVELOPMENT CABLE SYNC MASTER=K59 SYNC DATE=11/01/2010 A
2 5 3 4 4 3 USB_DEV_F_DM 31 46
USB_DEV_F_DM 6 D- SEL=0 : HOST PAGE TITLE
NC
IO
NC
IO
8
NC
6 VBUS 2 5 3 4
46 31
USB 7-PORT HUB
NC
IO
NC
IO
9 1 2 USB_DEV_F_DP 31 46 USB_MUX_OE_L 8 OE* SEL 10 USB_DEV_VBUS_LS 20 31

DRAWING NUMBER SIZE
1 GND 6 VBUS
DEVELOPMENT GND Apple Inc. 051-8774 D
1 GND REVISION
3
R
U4580
KEEP R4581 REGARDLESS FOR OR GATE INPUT PULLDOWN
R4562
C.0.0
RCLAMP0502N 10K NOTICE OF PROPRIETARY PROPERTY: BRANCH
SLP1210N6 U4581 1 2
DEVELOPMENT RCLAMP0502N 5%
1/16W THE POSESSOR AGREES TO THE FOLLOWING: PAGE
SLP1210N6
DEVELOPMENT
MF-LF
402
45 OF 110
DEVELOPMENT SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
35 32 7 6 =PP3V3_S3_USB L4650
60-OHM-EMI =PP1V0_S3_USB 6
PP1V0_S3_USB_AVDD 2 1
1
C4630 1
C4631 1 1
C4632 1
C4633 1
C4634 1
C4635 1
C4636 1
C4637 MIN NECK WIDTH=0 2 MM SM
USB_WAKE OPEN DRAIN BUFFER TO BLOCK BACK DRIVE FROM ENET_WAKE
VOLTAGE=1 05V
CRITICAL 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF THIS AVOIDS ACTIVATING THE RESUME CIRCUIT DURING WOL
20%
6 3V
20%
6 3V
10%
16V
10%
16V
10%
16V
10%
16V
10%
16V
10%
16V C4650 1 1
C4651 1
C4652 1
C4653 1
C4654
L4640 X5R 2 X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 10UF 0.1UF 0.1UF 0.1UF 0.1UF =PP3V3_S3_USB
=USB_WAKE_L
OUT 7
35 32 7 6
60-OHM-EMI 603 603 402 402 402 402 402 402 20% 10% 10% 10% 10%
SM 6 3V 16V 16V 16V 16V
X5R 2 2 X5R 2 X5R 2 X5R 2 X5R
603 402 402 402 402 PULLUP NEEDED IF PME L IS OPEN DRAIN 1
R46011 R4600
2 10K 200
5%
5%
1/16W
PP3V3_S3_USB_VDDA 1/16W
MF LF 3
MF LF
D
VOLTAGE=3 3V
402
2
402
2
D Q4600 D
2N7002DW-X-G
SOT-363
USB_PME_OD 5 G S
C4640 1
C4641 1 1
C4642 1
C4643 1
C4644 1
C4645 1
C4646 1
C4647 1
C4648 1
C4649 C4660 1 1
C4661 1
C4662 1
C4663 1
C4664 1
C4665 1
C4666
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 20% 10% 10% 10% 10% 10% 10%
6 3V 6 3V 16V 16V 16V 16V 16V 16V 16V 16V 6 3V 16V 16V 16V 16V 16V 16V
X5R 2 X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 402 402 402 402 402 402 402 402 603 402 402 402 402 402 402
6
D
Q4600
2N7002DW-X-G
2 SOT-363
32 USB_PME_L G S
115
121
122
128
105
112
100
109
111
83
90
91
97
54
33
67
40
46
49
60
22
35
81
8
AVDDH 1
VDDA VDDR AVDD VDDC
46 7 IN PCIE_USB_R2D_C_P C4600 1 2
10% 16V 46 PCIE_USB_R2D_P 37 PERP DP1 124 USB_HOST_DP BI 31 32 46

0.1uF X5R 402 OMIT_TABLE
46 PCIE USB R2D N 38 PERN DM1 123 USB HOST DM BI 31 32 46
46 7 IN PCIE_USB_R2D_C_N C4601 1 2
CRITICAL
10% 16V
0.1uF X5R 402
U4600 DP2 117
NC
PCIE_USB_D2R_P C4602 1 2 PI7C9X440SL DM2 116
46 7 OUT
10% 16V LQFP NC
0.1uF X5R 402 46 PCIE_USB_D2R_C_P 41 PETP USB DEVICE RESUME DURING D3 DRIVER
35 32 7 6 =PP3V3 S3 USB
46 7 OUT PCIE_USB_D2R_N C4603 1 2 46 PCIE_USB_D2R_C_N 42 PETN DP3 93
NC
PCI EXPRESS INTERFACE

10% 16V
0.1uF X5R 402 DM3 92
NC 35 32 7 6 =PP3V3_S3_USB
1
R4641
PCIE CLK100M USB P C4604 1 2 46 PCIE CLK100M USB C P 51 REFCLKP DP4 85 100K 2
46 7 IN
10% 16V
NC 5%
0.1uF PCIE CLK100M USB C N 52 84 1/16W
USB INTERFACE
X5R 402 46 REFCLKN DM4 NC S
=PP3V3_S3_USB 6 7 32 35
MF LF
46 7 IN PCIE_CLK100M_USB_N C4605 1 2 2 402
10% 16V OCIx requires pull-up if unused.
0.1uF X5R 402 USB_HOST_BUSPWR_EN
32 USB_RESET_MASKED_L 104 PERST* OCI1 4 PIUSB_OCI1_L R4671 402 10K 1 2 1/16W
OUT 31 32 USB_PME_DELAY_L 1
5% MF LF
USB PME L 113 PME* OCI2 5 PIUSB OCI2 L R4672 402 10K 1 2 1/16W G S0T23-3-HF
C
32
OCI3 6 PIUSB OCI3 L R4673 402 10K 5%

1 2 1/16W
MF LF
3
BSS84
Q4660 C
Active-Low
PIUSB_REXT 57 REXT 5% MF LF D
OCI4 7 PIUSB_OCI4_L R4674 402 10K 1 2 1/16W
Q4640 3
5% MF LF
1
2N7002E-X-G USB HOST DM PU
R4604 POE1 10 PIUSB_POE1_L 1 SOT23-3
1.43K SIGNAL_MODEL=EMPTY1
1% POE2 11 TP_PIUSB_POE2_L
1/16W 2 R4660
MF LF POE3 12 TP_PIUSB_POE3_L 1.5K
402
2 13 TP_PIUSB_POE4_L 5%
POE4 1/16W
PIUSB REXTRET 56 REXT_GND MF LF
402
2
RREF1 126 PIUSB_RREF1 R4681 6.04K 1 2
1% 1/16W MF LF 402
1% 1/16W MF LF 402 46 32 31 USB_HOST_DM
MINIMIZE STUBS ON BUS IN LAYOUT!!!
NC
20 LEG_EMU_EN 1% 1/16W MF LF 402 46 32 31 USB_HOST_DP
SIGNALS
R4605 330 1 2 PIUSB_IO_HIT_I 3 IO_HIT_I
LEGACY
1% 1/16W MF LF 402
5% 1/16W MF LF 402 SIGNAL_MODEL=EMPTY 1
R4606 330 1 2 PIUSB_IRQ1_I 16 IRQ1_I R4665
5% 1/16W MF LF 402
NC
18 IRQ1_O 35 32 7 6 =PP3V3_S3_USB 200
5%
R4607 330 1 2 PIUSB_IRQ12_I 17 IRQ12_I 1/16W
5% 1/16W MF LF 402 MF LF
19 IRQ12_O
NC
14
R46661 402
2
NC SMI_O 10K USB_HOST_DP_PD
5%
1/16W
35 32 7 6 =PP3V3_S3_USB MUST BE TIED TO S3 IN ORDER TO WAKE FROM SLEEP =PP3V3_S3_USB 6 7 32 35
MF LF 6
402
2
R4610 4.7K 1 2 PIUSB_MAIN_DETECT 24 MAIN_DETECT TEST1 1 PIUSB_TEST1 R4691 402 330 1 2 1/16W D
Q4665
5% 1/16W MF LF 402 5% MF LF
=PP3V3_S3_USB TEST3 65 PIUSB_TEST3 R4693 402 4.7K 1 2 1/16W 2N7002DW-X-G
35 32 7 6
R4612 4.7K 1 2 PIUSB_EECLK 99 EECLK TEST4 77 PIUSB_TEST4 R4694 402 330

5%
1 2 1/16W MF LF
D4600 2 G S
SOT-363
5% 1/16W MF LF 402 5% MMBD914XG
R4613 4.7K PIUSB_EEDATA 98 114 PIUSB_TEST5 R4695 402 4.7K 1 2 1/16W MF LF USB_PME_DELAY
1 2 EEPD TEST5 3 1
5% 1/16W MF LF 402 5%
1/16W MF LF
1
66 PIUSB_TEST6 R4696 402 4.7K 1 2
MISCELLANEOUS SIGNALS
TEST6 3
5% MF LF
35 =I2C_USBHOST_SCL 21 SMBCLK (IPD) SOT23
IN
=I2C USBHOST SDA 64
R4603
D Q4665
B 35 BI SMBDATA
2
NC 32
USB_PME_L 1
100K 2
32 USB_PME_DELAY_L 5 G S
2N7002DW-X-G
SOT-363 B
TP_PIUSB_GPIO0 69 GPIO0 30 PIUSB_MODE0 R4697 330 1 2
5% 1/16W MF LF 402 1%
TP_PIUSB_GPIO1 70 GPIO1 31 PIUSB_MODE1 R4698 330 1 2 1/16W 1 C4606 4
5% 1/16W MF LF 402 MF-LF
TP_PIUSB_GPIO2 71 GPIO2 32 PIUSB_MODE2 R4699 330 1 2 402 0.15UF
5% 1/16W MF LF 402 10%
TP_PIUSB_GPIO3 72 GPIO3 43 10V
NC 2 X5R
TP_PIUSB_GPIO4 73 GPIO4 44
NC 402
R4635 330 1 2 TP_PIUSB_GPIO5 74 GPIO5 47

NC
5% 1/16W MF LF 402
R4636 330 1 2 TP PIUSB GPIO6 75 GPIO6 48
NC
SMB ADDR = $68 | GPIO[7:5] R4637 330 5% 1/16W MF LF 402
USB PCIE RESET MASK DURING/AFTER SLEEP TO SUPPORT USB WAKE FROM SLEEP
1 2 TP PIUSB GPIO7 76 GPIO7 55
NC
5% 1/16W MF LF 402 35 32 7 6 =PP3V3_S3_USB
58
NC NC
R4624 330 1 2 PIUSB_SCAN_EN 15 SCAN_EN 59
NC 35 32 7 6 =PP3V3_S3_USB PIUSB_REV:B
5% 1/16W MF LF 402
R4625 330 1 2 PIUSB_JTAG_TRST_L 29 TRST* 62
NC PIUSB_REV:B C4659 1
5% 1/16W MF LF 402
R4626 330 1 2 PIUSB_JTAG_TMS 27 TMS 63
NC C4658 1 0.1UF
10%
5% 1/16W MF LF 402
TP_PIUSB_JTAG_TCK 26 TCK 78 0.1UF 16V
2
NC 33 31 6 =PP3V3_S5_USB 10% X5R
TP_PIUSB_JTAG_TDI 28 79 16V 402
TDI NC X5R 2
CRITICAL 402
TP PIUSB JTAG TDO 25 TDO 80
8
Y4620 NC
88
12.000M NC 5 PIUSB_REV:B VCC 5 PIUSB_REV:B
1 2
PIUSB_CLK12M_XI 102 XI 107
NC TCMCU_DP_HPD_OUT 1
74LVC1G32 U4652 USB_RESET_L 1
74LVC1G32
PIUSB_CLK12M_XO_R 103 108
34 IN SOT553-5 SN74LV2G74 32 7 IN SOT553-5
XO NC 4 7 VSSOP-HF1 4
SPM HPD OR U4651 USB RESET MASKED L
11.4X4.7X4.2-SM VSS THRM U4650 PRE*
32
1 C4620 R4621 1 C4621 PAD 42 IN DP A EXT HPD 2 32 PIUSB_REV:B
1 1 Q
5 USB RESET MASK 2 32
20PF 20PF CLK
101
106
110
118
120
125
127
129
1M R4655
23
34
36
39
45
50
53
61
68
82
86
89
94
96
9
5% 1 2 5% PIUSB_REV:B 3 PIUSB_REV:B 3
2 50V 2 50V C4657 1 10K 2
CERM 5% CERM 5% D 3
402 1/16W 402 0.1UF 1/16W Q* NC
MF-LF 10% MF-LF 6
402 16V
2 402 2 CLR*
X5R GND
402 MASK_CLR_L
4
A PIUSB_REV:B
C4655 1 SYNC_MASTER=MASTER SYNC_DATE=N/A A
PAGE TITLE
1UF
XTAL OSCILLATOR CIRCUIT FROM LAZARUS BOARD 10%
6 3V
2
USB 2.0 Host Controller
CERM
402 DRAWING NUMBER SIZE
PIUSB_REV:C Apple Inc. 051-8774 D

REVISION
R4650 R
C.0.0
0
32 7 USB_RESET_L 1 2 USB_RESET_MASKED_L 32 NOTICE OF PROPRIETARY PROPERTY: BRANCH
5% THE INFORMATION CONTAINED HEREIN IS THE
1/16W PROPRIETARY PROPERTY OF APPLE INC.
MF-LF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402
STUFF AROUND RESET MASK WHEN PERICOM FIXES PCIE RESET IN REV C
46 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_S5_USB
PP4906
1P0-BOT
CRITICAL
33 32 31 6
1
SM L4928 VOLTAGE=5V
PP VOLTAGE=5V
FERR-120-OHM-3A MIN NECK WIDTH=0 25MM
HUB1_VBSW MIN LINE WIDTH=0 6MM 1 2 MIN LINE WIDTH=0 6MM
=PP3V3_S5_USB
PP4907
R4985
33 32 31 6
HUB1
2
1P0-BOT 0603
NOSTUFF HUB1_DN1
1/16W
MF-LF
10K
SM
C4987 C4988 C4989 Q4904
402
1 1 1 1 1
C4967
5%
PP
0.001UF 10UF 100UF 0.1UF BSS84V VOLTAGE=3.3V
HUB1_VBSW 10% 20% 20% 10% SOT-563 MIN LINE WIDTH=0 5MM
1
CRITICAL 2 50V
CERM 2 10V
X5R 2 6.3V 2 16V
X7R-CERM MIN NECK WIDTH=0 2MM R4904
6 =PP5V S5 USB 402 805
POLY-TANT
402 HUB1_DN1
R4990 CASE-B2-SM1
4 S D 3 3.48K2 USBDN1_H1_DP
0.0082
HUB1_DN1 HUB1_DN1 HUB1_DN1 J4906 PUDP1 1 31 33 46
1 PP5V1_USB_VBUS USB-ST-TAIL-J59 Q4904 1%

OC_H1_L
L4919 HUB1_DN1 F-ANG-TH 1/16W
1%
1W
VOLTAGE=5V
31 OUT 120-OHM-90MA
DLP0NS G BSS84V MF-LF
402
D
MF-LF
2512
CRITICAL 46
31 IN USBDN1_H1_DM 4
SYM_VER 1
3 46
VB1
DM1
1
2
VBUS
DATA-
5 HUB1_DN1
SOT-563 HUB1_DN1
R4905 D
HUB1_VBSW 33
46 DP1 3 1 S D 6 PUDM11
10K 2 USBDN1_H1_DM
DATA+ 31 33 46
U4912 46 1 2
4
GND 1
1%
TPS2561DR 31
33 IN USBDN1_H1_DP
HUB1_DN1 R4903 G
1/16W
MF-LF
SON 2 5 3 4
5
100K 402
HUB1_DN1 HUB1_DN1
NC
IO
NC
IO
2 IN_0 5%
OUT1 9 33 VBUS1
6 VBUS 6 1/16W 2 MIN LINE WIDTH=0 5MM
3 IN_1 MF-LF MIN NECK WIDTH=0 2MM
OUT2 8 7 2 402 VOLTAGE=3.3V
CRITICAL 1 GND HUB1_DN1
1
C4904 1 C4912 10 FAULT1* ILIM 7 1 C4910 1 C4911 CRITICAL PUG1
330UF 0.1UF 6 FAULT2* 0.1UF 0.01UF
20% 20% 20% 20%
10V 10V 16V 6
PLACE U4990 CLOSE TO R4950! 2 6.3V
POLY-TANT
2 CERM
402
4 EN1 2 CERM
402
2 CERM
402
U4901
CASE-D3L-SM1
HUB1_VBSW HUB1_VBSW 5 EN2
THRM HUB1_VBSW HUB1_VBSW
RCLAMP0502N
SLP1210N6
D
Q4903
PAD 2N7002DW-X-G
HUB1_VBSW GND 2 SOT-363
31 20 WALL CHRG ON G S
IN
11
U4990 ILIM12
1
INA216
WCSP-4
A1 B2 1
PP4908
IN+ CRITICAL OUT R4912 1P0-BOT
SM
A2 23.2K 1
PP
IN- 1%
1/16W HUB1_VBSW
MF-LF
GND 2 402 PP4909
1P0-BOT
B1 HUB1_VBSW 1
SM CRITICAL
PP
VOLTAGE=5V L4929 VOLTAGE=5V Q4906
HUB1_VBSW
FERR-120-OHM-3A MIN NECK WIDTH=0 25MM BSS84V
1 2 MIN LINE WIDTH=0 6MM SOT-563 VOLTAGE=3.3V
NOSTUFF
0603
MIN NECK WIDTH=0 2MM R4907
HUB1_DN2 S D 3.48K2 USBDN2_H1_DP
1 C4990 1 C4991
1
C4968 1 C4992
4 3 PUDP2 1 31 33 46
C USB ADC REF 10%

0.001UF 10UF
20%
100UF
20%
2 6.3V
0.1UF
10% Q4906
1%
1/16W
MF-LF
C
2 50V 2 10V POLY-TANT 2 16V G BSS84V 402
CERM X5R CASE-B2-SM1 X7R-CERM
402 805 402 SOT-563 HUB1_DN2
1 HUB1_DN2 5 HUB1_DN2
R4991 33 VBUS2 HUB1_DN2 HUB1_DN2 HUB1_DN2 R4908
CRITICAL HUB1_VBSW
24.3K
1% U4991 J4907 1 S D 6 PUDM2 1
10K 2
USBDN2_H1_DM
31 33 46
2 USB-ST-TAIL-J59
1/16W
MF-LF 4
LMC7211 1 1
L4921 HUB1_DN2 F-ANG-TH 1%
2 402 V+ SM-HF C4920 C4921 120-OHM-90MA
1 HUB1_DN2 1/16W
HUB1_VBSW 1 0.1UF
20% 20%
0.01UF DLP0NS
SYM_VER 1 VB2 1
VBUS
R4906 G MF-LF
402
10V 16V 4 3 2
100K
3 2 CERM 2 CERM 46 33 31 IN USBDN2_H1_DM 46 DM2 DATA- 5% 2 HUB1_DN2
USB_CHG_VREF V- 402 402 1/16W MIN NECK WIDTH=0 2MM
46 DP2 3 MF-LF VOLTAGE=3.3V
5 HUB1_VBSW HUB1_VBSW DATA+
4 2 402
46 33 31 USBDN2_H1_DP 1 2 GND HUB1_DN2
1 IN PUG2
R4992 HUB1_DN2
51.1K 2 5 3 4 5
6
NC
IO
NC
IO
1%
1/16W NOSTUFF 6
6 VBUS
MF-LF
2 402
R4999 7
D
Q4905
0 1 GND CRITICAL
2N7002DW-X-G
HUB1_VBSW 1 2 SOT-363
2 G S
5% HUB1_VBSW
1/16W
MF-LF 1
402 U4902
20 OUT USB_CHG_WAKE_L RCLAMP0502N
SLP1210N6
1
R4993 PP4910
33.2K CRITICAL 1P0-BOT
1% SM
1/16W HUB1_VBSW 1
PP
MF-LF
2 402 CRITICAL U4934 PP4911
HUB1_VBSW 1
C4902 1 C4963 TPS2557DRB
HUB1_VBSW
1P0-BOT Q4908
B ADC_USB5V
150UF
20% 20%
0.1UF SON 1
SM
PP CRITICAL
BSS84V
SOT-563 VOLTAGE=3.3V
B
OUT 20 45
2 6.3V
POLY-TANT
10V
2 CERM 2 IN_0 OUT1 6 33 VBUS3 HUB1_VBSW
VOLTAGE=5V
L4930 VOLTAGE=5V
MIN LINE WIDTH=0 5MM R4910
CASE-B2-SM 402 3 IN_1 OUT2 7 MIN NECK WIDTH=0 25MM
FERR-120-OHM-3A MIN NECK WIDTH=0 25MM
3.48K2
HUB1_VBSW HUB1_VBSW MIN LINE WIDTH=0 6MM MIN LINE WIDTH=0 6MM 4 S D 3 PUDP3 1 USBDN3_H1_DP 31 33 46
1 1 2
R4994 8 FAULT* ILIM 5
48.7K NOSTUFF
0603 Q4908 1%
1/16W
1% 4 EN 1 G BSS84V MF-LF
1/16W
MF-LF
31 IN VBUS_DNSTREAM_ENAB 1 C4930 1 C4931 1 C4993 1 C4994 C4969 1 C4995 SOT-563
402
HUB1_DN3
2 402 THRM 0.1UF 0.01UF 0.001UF 10UF 100UF 0.1UF 5 R4911
20% HUB1_DN3
HUB1_VBSW GND PAD 20% 20% 10% 20% 2 6.3V 10%
S D 6 10K
2 10V
CERM 2 16V
CERM 2 50V
CERM 2 10V
X5R
POLY-TANT 2 16V
X7R-CERM
1 PUDM31 2 USBDN3_H1_DM 31 33 46
ILIM34 CASE-B2-SM1
1
402 402 402 805 402 1%

HUB1_DN3 1
HUB1_VBSW HUB1_VBSW HUB1_DN3 HUB1_DN3 HUB1_DN3 R4909 G
HUB1_DN3 1/16W
MF-LF
1
R4934 J4905 100K 402
5% HUB1_DN3
PP4901
1P0-BOT 1%
44.2K L4923 HUB1_DN3
USB-ST-TAIL-J59
F-ANG-TH
1/16W
MF-LF
SM 1/16W 120-OHM-90MA VOLTAGE=3.3V
1 MF-LF DLP0NS 2 402
PP VB3 1
2 402
SYM_VER 1
VBUS HUB1_DN3
4 3
PUG3
HUB1_VBSW 46 33 31 USBDN3_H1_DM 46 DM3 2
IN DATA-
46 DP3 3
DATA+ 6
4
1 2 GND
VBUS1 33 VBUS2 33 VBUS3
46 33 31
33
IN USBDN3_H1_DP D
Q4907
2 5 3 4 5
2N7002DW-X-G
SOT-363
2 G S
NC
IO
NC
IO
6
1 1 6 VBUS
1
R4949 R4950 R4951 7 1
1K 1K CRITICAL
1K 5% 5% 1 GND
5% 1/16W 1/16W
1/16W MF-LF MF-LF
MF-LF 2 402 2 402
2 402
HUB1_DN1
HUB1_DN2 HUB1_DN3 U4903
VB2DIS VB3DIS RCLAMP0502N
VB1DIS
A 3 3
SLP1210N6
HUB1_DN3 SYNC MASTER=K59 SYNC DATE=08/22/2010 A
3 PAGE TITLE
D
Q4903
D
Q4905
2N7002DW-X-G
D
Q4907
2N7002DW-X-G USB EXTERNAL CONNS
2N7002DW-X-G 5
SOT-363
5
SOT-363 DRAWING NUMBER SIZE
SOT-363 G S G S
31 IN VBUS_DISCHARGE 5 G S
4 4 REVISION
4 R
C.0.0
49 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCU Pull-ups/downs
T29 host/device has 10K pull-up on LSX_R2P.
Dual-plug cable has cross-over for P2R/R2P.
Device micro (U5000) senses pull-up to

detect host. Cable may be powered-off
34 11 6 =PP3V3_S4_MCU
until host pull-up is detected.
P2R = Plug to Receptacle 41 7 T29_LSX_P2R R5079 1M 1 2

5% 1/16W MF LF 402
R2P = Receptacle to Plug 41 7 T29_LSX_R2P R5080 10K 1 2
5% 1/16W MF LF 402
D 34 TCMCU_DP_CONFIG1 R5085 10K 1 2

D
5% 1/16W MF LF 402
34 TCMCU_DP_CONFIG2 R5086 10K 1 2

5% 1/16W MF LF 402
NOSTUFF
0
R5088 1/16W
34 7 =T29_LSX_P2R 1 2
5% MF LF
402
34 TCMCU HPD IN R5087 10K 1 2

5% 1/16W MF LF 402
42 34 7 TBLT_WAKE_L R5081 10K 1 2

5% 1/16W MF LF 402
34 11 6 =PP3V3_S4_MCU
2.5-3.3V
C5000 1 1
C5001 1
C5002 TCMCU_ADDR:
10UF 0.1UF 0.1UF
20% 10% 10%
6 3V 16V 16V VDD : Master
X5R 2 2 X5R 2 X5R
603 402 402 2/3 VDD : Slave 3
1/3 VDD : Slave 2
29
GND : Slave 1
6
R5000
10K
VDD
C CRITICAL
OMIT_TABLE
U5000
TCMCU_ADDR
MAKE BASE=TRUE
1
5%
1/16W
2 =TCMCU_ADDR
Alias to power or ground as

IN 7
C
MF LF
42 34 7 BI TBLT WAKE L LPC1114FHN33-301 402 appropriate to set address.
MAKE BASE=TRUE HVQFN
11 IN TCMCU_RESET_L 2
RESET*/PIO0_0 R/PIO1_0/AD1/CT32B1_CAP0 22 TCMCU_DP_CONFIG1 34
42 BI MCU_CA_DET 3
PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_1/AD2/CT32B1_MAT0 23 TCMCU_DP_CONFIG2 34
23 IN =T29 R2C LSEO<0> 8

PIO0_2/SSEL0/CT16B0_CAP0 R/PIO1_2/AD3/CT32B1_MAT1 24 TP TCMCU HV EN
42 40 35 25 20 OUT PM_S0_EN 9
PIO0_3 SWDIO/PIO1_3/AD4/CT32B1_MAT2 25 TCMCU_SWDIO BI 11
35 IN =I2C_TCMCU_SCL 10
PIO0_4/SCL PIO1_4/AD5/CT32B1_MAT3/WAKEUP 26 TCMCU_DP_HPD_OUT 32
35 BI =I2C_TCMCU_SDA 11
PIO0_5/SDA PIO1_5/RTS*/CT32B0_CAP0 30 TBLT_AC_PRESENT IN 42
34 TCMCU_HPD_IN 15
PIO0_6/SCK0 PIO1_6/RXD/CT32B0_MAT0 31 =T29_LSX_P2R IN 7 34
TP_TCMCU_T29_BIAS 16
PIO0_7/CTS* PIO1_7/TXD/CT32B0_MAT1 32 =T29_LSX_R2P OUT 7
23 OUT =T29_C2R_LSEO<0> 17
PIO0_8/MISO0/CT16B0_MAT0 PIO1_8/CT16B1_CAP0 7 T29_R2C_LSEO<1> IN 23
23 OUT T29_C2R_LSEO<1> 18
PIO0_9/MOSI0/CT16B0_MAT1 PIO1_9/CT16B1_MAT0 12 I2C_MCU_SCL OUT 35 42 45
11 IN TCMCU_SWCLK 19
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_10/AD6/CT16B1_MAT1 20 I2C_MCU_SDA BI 35 42 45
42 BI TBLT_PWR_REQ_L 21
R/PIO0_11/AD0/CT32B0_MAT3 PIO1_11/AD7 27 PM_DPO_EN IN 7 42
JTAG_TBLT_TDI OUT 11 42
42 40 35 20 OUT PM_S3_EN 1
PIO2_0/DTR* PIO3_2 28 JTAG_TBLT_TCK OUT 11 42
PIO3_4 13 =JTAG_TBLTTC_TMS OUT 11

4
XTALIN 14 JTAG_TBLT_TDO
5 PIO3_5 IN 11 42
NC XTALOUT
VSS Note: = prefix on some nets
are for Dr.B support.
33
1
R5001
10K
5%
1/16W
MF-LF
2 402
B B
PAGE TITLE
Tethered Cable MCU

DRAWING NUMBER SIZE

REVISION
R
C.0.0
50 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
T29 IC I2C Connections

LPC I2C CONNECTIONS 6 =PP3V3_S0_I2C_T29
35 20 6 =PP3V3_S5_LPC
=PP3V3_S5_LPC
R5220 1
35 20 6 1
T29 Primary IC R5221 T29 Device uC
PP5221
1P0-BOT 4.7K 4.7K
U3600 SM 5% 5% U5000
1 1 1/16W 1/16W
R5253 (MASTER) PP (WRITE: 0X28 READ: 0X29)
R5251 C5250
1 1 1 1 MF LF MF LF
MicroController R5250 R5252 J59 SYS EEPROM 402 2 402
D U2617
4.7K
5% 5%
4.7K 0.1UF
20%
10V
4.7K
5%
4.7K
5%
1/16W
(PAGE 0 - WRITE: 0XA4 READ: 0XA5)
(PAGE 1 - WRITE: 0XA6 READ: 0XA7) 44 23 I2C_T29_SCL
2
=I2C_TCMCU_SCL 34
D
18
1/16W 1/16W CERM 2 1/16W MF LF MAKE BASE=TRUE
(MASTER) MF LF MF LF 402 MF LF
402
402 2 2 402 402 2 2 I2C_T29_SDA =I2C_TCMCU_SDA
VDD 44 23 34
MAKE BASE=TRUE
45 20 I2C_LPCLOC_SDA 17 SDA SD0 3 45 I2C_LPC1_SDA =I2C_SYS_SDA 20 PP5220
MAKE BASE=TRUE CRITICAL MAKE BASE=TRUE 1P0-BOT
SC0 4 SM
45 20 I2C_LPCLOC_SCL
MAKE BASE=TRUE 16 SCL
U5250 INT0* 2 PM S3 EN 20 34 35 40 42
45 I2C_LPC1_SCL
MAKE BASE=TRUE
=I2C_SYS_SCL 20
PP
1
IN
PCA9544A
QFN T29 Port A MCU
TP_I2CLPCMUX_INT_L 15 INT* SD1 6
U9330
SC1 7
(WRITE: 0X26 READ: 0X27)
INT1* 5 PM_S0_EN IN 20 25 34 35 40 42 J59 TEMP SENSOR
(WRITE: 0X98 READ: 0X99) =I2C TBLTAMCU SCL 42
SD2 10
=I2C_TBLTAMCU_SDA 42
SC2 11
I2C MUX Address: 1 A2 INT2* 9 SPARE INT2 L 35 =I2C TMP SDA 8
WRITE: 0XEE? READ: 0XEF? 20 A1

=I2C_TMP_SCL 8
19 A0 SD3 13
SC3 14
INT3* 12 SPARE_INT3_L 35 PLACE ALL I2C PROBE POINTS ON TOP SIDE

VSS TH_PAD J59 USB HUB
21
(WRITE: 0X58 READ: 0X59)
T29 MCU I2C CONNECTIONS
=I2C_USBHUB_SDA 31
6 =PP3V3_S0_I2C_UC
=I2C_USBHUB_SCL 31
C 6 =PP3V3_S5_ALS R5200
4.7K
1 1
R5201
4.7K
C
MicroController 5% 5% DP/T29 Plug CDRs
SOT23-3-HF 1/16W 1/16W
U5000 OR U9330 2x GN2033: J9000
35 20 6 =PP3V3_S5_LPC NTR1P02L MF LF
402
MF LF
402
2 Q5250 (MASTER) 2 2 (See Tables)
S
1 CAM GATE 10
45 42 34 I2C_MCU_SDA =I2C_PLUGCDRS_SDA 41
G IN MAKE BASE=TRUE
45 42 34 I2C_MCU_SCL =I2C_PLUGCDRS_SCL 41
MAKE BASE=TRUE
D
NOSTUFF1 NOSTUFF1 3
R5260 R5261 R52621 R52631 DEVELOPMENT
4.7K 4.7K 4.7K 4.7K
5% 5% 5% 5% PUSCL J5250
1/16W
MF LF
1/16W
MF LF
1/16W
MF LF
1/16W
MF LF
VOLTAGE=3.3V
MIN LINE WIDTH=0 5MM HB3902U-L CK505 (Clk Gen)
402 2 402 2 402 2 402 2 MIN NECK WIDTH=0 2MM M-ST-TH SLG8SP568: U2850
1 (Write: 0xD2 Read: 0xD3)
42 40 35 34 20 PM_S3_EN 2
PM_S0_EN =I2C_CK505_SDA
42 40 35 34 25 20
R5270 1 1
R5271 22
35 SPARE_INT2_L 4.7K 4.7K
35 SPARE_INT3_L 5% 5%
J59 ALS =I2C_CK505_SCL 22
1/16W 1/16W
MF LF MF LF
402 2
2
402
(WRITE: 0X52 READ: 0X53) B117 PLUG CDRS (POR)
FAR DP ML<0>/T29 LINK 0 - (WRITE: 0X48 READ: 0X49)
PLACE ALL PROBE POINTS ON TOP SIDE 48 45 I2C_ALS_SDA =I2C_ALS_SDA 10
FAR DP ML<2>/T29 LINK 1 - (WRITE: 0X4A READ: 0X4B)
MAKE BASE=TRUE
NEAR DP ML<0>/T29 LINK 0 - (WRITE: 0X4C READ: 0X4D)
48 45 I2C_ALS_SCL =I2C_ALS_SCL 10
NEAR DP ML<2>/T29 LINK 1 - (WRITE: 0X4E READ: 0X4F)
MAKE BASE=TRUE
B117 I2C ROM - (WRITE: 0XA0 READ: 0XA1)
7 6 =PP3V3_S3_USB
32
B B
R5272 1
1
R5273 J59 USB HOST
4.7K 4.7K
5% 5%
1/16W 1/16W
MF LF MF LF (WRITE: 0XD0 READ: 0XD1)
402 2 2
402
45 I2C_USBHOST_SDA =I2C_USBHOST_SDA 32
MAKE BASE=TRUE
45 I2C_USBHOST_SCL =I2C_USBHOST_SCL 32
MAKE BASE=TRUE
6 =PP3V3_S0_TCON
21 TCON HAS PULLUPS
NOSTUFF NOSTUFF
R5274 1
1
R5275 J59 DP628
4.7K 4.7K
5% 5%
A 1/16W
MF LF
402 2 2
1/16W
MF LF
402
(WRITE: 0X1A READ: 0X1B) SYNC_MASTER=MASTER SYNC_DATE=N/A A
PAGE TITLE
45 I2C DP628 SDA
MAKE BASE=TRUE
=I2C DP628 SDA 21
J59 & T29 SMBUS CONNECTIONS
45 I2C_DP628_SCL =I2C_DP628_SCL 21
DRAWING NUMBER SIZE
MAKE BASE=TRUE
REVISION
R
C.0.0
52 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
6 =PP12V S0 P1V05S0 VREG
CRITICAL
1
C7010 1 C7011 1 C7012 1 C7013 1 C7014
270UF 10UF 10UF 1UF 1UF
2 20% 10% 10% 10% 10%
16V 16V 16V 16V
CRITICAL 2 16V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R
ELEC
0805 0805 402 402
6 =PP5V S5 P1V05S0 VREG Q7000 8X9-TH1
R7003 RJK0214DPA
C7000 1
R7004 P1V05 REG UGATE R 1
0 2 P1V05 REG UGATE 1 WPAK2
1UF 0 NET_PHYSICAL_TYPE=POWER NET_PHYSICAL_TYPE=POWER
10% P1V05 REG VBST R 1 2 NET_SPACING_TYPE=VR_CONTROL 5% NET_SPACING_TYPE=VR_CONTROL
10V 2 NET_PHYSICAL TYPE=POWER 1/10W 7
X5R 5% MF-LF
402-1 NET_SPACING_TYPE=VR_CONTROL
VBST 10
1/10W 603
C
V5IN 7
MF-LF
C 1
R7002
603
P1V05 REG VBST P1V05 REG LGATE 6
100K NET_PHYSICAL TYPE=POWER NET_PHYSICAL_TYPE=POWER
5% NET_SPACING_TYPE=VR_CONTROL NET_SPACING_TYPE=VR_CONTROL
1/16W
U7000 MF-LF MAX CURRENT = 7.0A
PWM FREQ = 380KHZ
R7005 TPS51218 2 402 3 4 5
1K DSC C7001 1
40 IN =P1V05S0 EN 1 2 P1V05S0 EN R 3 EN PGOOD 1 P1V05S0 PGOOD OUT 40
0.1UF CRITICAL
10%
5%
1/16W 4 VFB DRVH 9
25V
X5R 2 L7000 PP1V05_S0_REG
MF-LF 402 1.5UH-9A 6
402
P1V05_REG_TRIP 2 TRIP SW 8 P1V05_REG_PHASE 1 2
DIDT=TRUE IHLP2525EZ
5 RF NET_SPACING_TYPE=SWITCHNODE
P1V05_REG_RF DRVL 6 NOSTUFF NET_PHYSICAL_TYPE=POWER CRITICAL NOSTUFF NOSTUFF
CRITICAL R70201 NOSTUFF 1
R7050 1
C7050 1 C7051 1 C7052 1 C7053 1 C7054
1 1 1 C7055 1 7.15K 330UF-0.006OHM 10UF 10UF 1UF 1UF
R7000 R7001 THRM 5% 10PF 1% 20% 20%
6.3V
20%
6.3V
10%
6.3V
10%
6.3V
23.7K 100K PAD 1/10W 5% 1/16W 2 2V
POLY
2 X5R 2 X5R 2 X5R 2 X5R
1% 1% MF-LF 50V MF-LF 603 603 402 402
11
1/16W 1/16W 603 2 CASE-D2-SM

CERM 2 2 402
MF-LF MF-LF 402
402 2 402 2
P1V05 REG_SNUB
DIDT=TRUE
NOSTUFF NET_PHYSICAL_TYPE=POWER
NET_SPACING_TYPE=SWITCHNODE
C7020 1
0.001UF
20% 1
50V
CERM 2
R7051
Connect RF to GND = auto-skip 402 15.0K
1%
Connect RF to PGOOD = forced continuious 1/16W
MF-LF
R79XX sets switching frequency 2 402
P1V05_REG_VFB
B B

PAGE TITLE
1.05V VREG
DRAWING NUMBER SIZE

REVISION
R
C.0.0
70 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes SI8409DB:
Power aliases required by this page: CRITICAL

Vds(max):
Vgs(max):
-30V
+/-12V
T29 15V Boost Regulator
- =PPVIN_SW_T29BST (8-13V Boost Input) T29BST CRITICAL
8-13V Input Vgs(th): -1.4V
- =PP15V_T29_REG (15V Boost Output) Q7180 T29BST
Changes required Rds(on): 46mOhm @ 4.5V Vgs
SI8409DB L7195
Signal aliases required by this page: for 2S. BGA Id(max): 3.7A @ 70C 10UH-4A-68-MOHM
(NONE) 1 2
3
6 =PPVIN_SW_T29BST 6 PPVIN_SW_T29BST T29BST_BOOST
MIN LINE WIDTH=0 5 mm MIN LINE WIDTH=0 5 mm
D
4
2
BOM options provided by this page: MIN NECK WIDTH=0 25 mm T29BST T29BST PCMB063T 100MS MIN NECK WIDTH=0 25 mm
SWITCH NODE=TRUE
T29BST - Stuffs 15V boost regulator T29BST Voltage not specified here C7190 1
C7191 1
DIDT=TRUE
T29BST add property on another page
10UF 10UF
R7180 1 T29BST_SNS1
G
1
C7180 T29BST 10%
25V
10%
25V CRITICAL
470K 2 2 T29BST
D 5%
1/16W
0.1UF
10% R7191
1 X5R
805
X5R
805
R7189 1 1
T29BST
D
1
50V
D7195
27
20
21
38
MF LF 2 X7R
200K
402
2 603 1 1% 0 POWERDI 123
1/16W VIN 5%
DFLS230L
MF LF SW 1/16W
6 T29BST PWREN DIV L 402
2
CRITICAL MF LF 2
402
2
T29BST <R1> 25 T29BST
T29BST_EN_UVLO EN/UVLO SNS1 6
1 T29BST SNS2
R7181 U7190
330K SNS2 3
5%
LT3957 XW7195
1/16W T29BST_INTVCC 28 INTVCC QFN SM
MF LF
402 2 1 PLACE NEAR=C7195 1 2 mm
2
30
1 T29BST_VSNS
T29BST_PWREN_L T29BST_VC VC 2 T29BST
T29BST T29BST
T29BST T29BST T29BST NC 10
NC C7188 R7195 1
D 3
C7192 1 1
C7187 R7193 1 T29BST RT 33 RT 35
1
137K
Q7105 10K 10PF 1% =PP15V_T29_REG 6
SSM3K15FV 4.7UF 47PF 1% 36 5%
1/16W
10% 5% 50V
1/16W 2 MF LF
SOD VESM HF 10V
X5R 2 2
50V
CERM MF LF
T29BST_SS 32
CERM
402 402
2
Vout = 15.47V
805 402 402 SS T29BST T29BST
2
<Ra>
T29BST_VC_RC 31 T29BST_FBX
1
C7195 1
C7197 Max Current = 1A
1 G S 2
FBX 4.7UF 4.7UF
T29_A_HV_EN
T29BST T29BST 34
SYNC T29BST 10%
50V
10%
50V Freq = 300KHz
43 42 IN 1
T29BST 1
T29BST NO STUFF 1
2 X7R CERM 2 X7R CERM
R7192 1
C7193 R7194 1
C7194 1
C7189 R7196 1206 1206
73.2K 0.033UF 41.2K 0.33UF 100PF 15.8K
1%
10%
1%
10%
SGND GND 5%
1% T29BST T29BST T29BST
1/16W 1/16W 1/16W
MF LF 2
16V
MF LF 2
6 3V
2
50V
MF LF C7196 1
C7198 1 1
C7199
23
24
37
12
13
14
15
16
17
X5R CERM X5R CERM
4
2
402 402 402
2 402 402 402 2 4.7UF 4.7UF 0.001UF
<R2>
GND_T29BST_SGND
<Rb> 10%
50V
10%
50V
10%
50V
X7R CERM 2 X7R CERM 2 2 X7R
MIN LINE WIDTH=0 5 mm 1206 1206 402
UVLO(falling) = 1.22 * (R1 + R2) / R2 MIN NECK WIDTH=0 25 mm
VOLTAGE=0V
UVLO(rising) = UVLO(falling) + (2uA * R1)
SGND shorted to
UVLO = 4.55V (falling), 4.95 (rising) Vout = 1.6V * (1 + Ra / Rb)
GND inside package,
C no XW necessary. C
B B
PAGE TITLE
Power: T29 15V Boost

DRAWING NUMBER SIZE

REVISION
R
C.0.0
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 71 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
1.0V Switcher
C CRITICAL
C
L7300
6.0UH-1.4A-0.26OHM PP1V0_S3_REG 6
U7300 P1V0S3_SW 1 2
SC194A
2520
Vout = 1.0V
6 =PP3V3 S3 P1V0S3REG MLP10 SWITCH NODE=TRUE
1 10
DIDT=TRUE
XW7301
Max Current = 0.325A
VIN LX
SM
=P1V0S3_EN 4 CRITICAL 5 P1V0S3_FB 1 2

f = 1MHZ
6 IN EN VOUT
PLACE NEAR=L7300 2 1 mm
3
SYNC/PWM
6
VID0 VID1 VID0 Vout
7
1
C7301
VID1 0 0 1.0V 22UF
20%
2
0 1 1.2V 6 3V
MODE 2 X5R CERM 1
C7300 1
THRM
1 0 1.5V 603
22UF GND PGND PAD 1 1 1.8V
20%
11
6 3V
X5R CERM 1 2
603
353S2719
B B
PAGE TITLE
Power: USB (1.0V S3)

DRAWING NUMBER SIZE

REVISION
R
C.0.0
73 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5V_S3/3.3V_S5 POWER SUPPLY

D D
VOUT = (2 * RA / RB) + 2
VOUT = (2 * RC / RD) + 2

376S0927 1 FDMC3020DC Q7760 CRITICAL
376S0928 1 FDMC2514SDC Q7761 CRITICAL <RA> <RB> <RD> <RC>

R7767 R7768 R7769 R7770
15.4K 10K 10K 6.81K
1% 1% 1% 1%
XW7703 1/16W 1/16W 1/16W 1/16W XW7704
MF LF MF LF MF LF MF LF
SM 402 402 402 402 SM
2 1 5V S3 VFB XW7203 1 2 1 2 1 2 1 2 3V3S5 VFB R7270 2 1
PLACE NEAR=L7260 1 1 MM
PLACE NEAR=L7220 2 1 MM
XW7705
SM
2 1
PLACE NEAR=C7251 1 1 MM
C 39 6 =PP12V S5 5V3V VREG

C
XW7702 1
C7772
R7705 NOSTUFF 0
SM 1UF
10% 1 2
2 1 25V
2 402 5% 1/16W MF LF
X5R
PLACE NEAR=C7291 1 1 MM 603 1 P5VP3V3 TONSEL
R7703 0
1 2
402 5% 1/16W MF LF
39 6 =PP12V_S5_5V3V_VREG P5VP3V3 VREF

OUT 9 45
1
NOSTUFF
2 =PP12V_S5_5V3V_VREG 6 39
CRITICAL CRITICAL NOSTUFF MF LF 1
C7770
5% 402
1 1 CRITICAL
R7790 1UF NOSTUFF CRITICAL
C7784 C7783 1
C7782 1
C7780
1
C7781 10 2MF LF
20% 1 1
CRITICAL
1
270UF 270UF 0.001UF 1UF P5VS3 SKIPSEL 5% 402
10V C7741 C7740
1
C7742 C7744
39UF 0 027OHM 2
20% 20% 10% 1 R7791 CERM 1UF 270UF
2 16V 2 16V
20% 20%
25V C7771 603
39UF 0 027OHM 0 001UF
16
50V 10% 20% 20%
3
ELEC ELEC 2 2 16V 2 20%
CERM POLY
X5R
C7760 0.22UF VIN VREF 2
25V
2
50V
2 16V
8X9-TH1 8X9-TH1 402 B1A-SM
603 1 10% X5R
16V
POLY
2
CERM ELEC
5
0.1UF 2
10V 14
SKIPSEL VREG3 8
P5VP3V3 REG3
603 1
B1A-SM
402
8X9-TH1
10% CERM
402
2
OMIT TABLE 16V
CRITICAL D X5R R7760 4
TONSEL VREG5 17
P5VP3V3 REG5 R7720 C7720 10% CRITICAL
402 402 5% 1/16W MF LF 402 5% 1/16W MF LF 16V
Q7760 0 0 0.1UF X5R D1 Q7720
RJK03E1DNS G 4 2 1 P5VS3 VBST R 1 2 P5VS3 VBST
22
VBST1 CRITICAL
VBST2 9
P3V3S5 VBST 1 2 P3V3S5 VBST R 2 1 402
MIN LINE WIDTH 0 6 MM DIDT TRUE

D DT TRUE U7700 MIN LINE WIDTH 0 6 MM
DIDT TRUE
RJK0384DPA
HWSON 8 DID TRUE
WPAK
MIN NECK WIDTH 0 2 MM MIN NECK WIDTH 0 2 MM
P5VS3 DRVH
21
DRVH1 DRVH2 10 MIN NECK WIDTH 0 2 MM
P3V3S5 DRVH
1 G1
QFN
MIN LINE WIDTH 0 6 MM DIDT TRUE MIN LINE WIDTH 0 6 MM
CRITICAL S MIN NECK WIDTH 0 2 MM 20 11 MIN NECK WIDTH 0 2 MM
DIDT TRUE
S1/D2 7
CRITICAL
PWM FREQ. = 375 KHZ
TPS51125
P5VS3 LL LL1 LL2 P3V3S5 LL
L7760 MIN LINE WIDTH 0 6 MM DIDT TRUE
MIN LINE WIDTH 0 6 MM L7720
3.3UH-20%-11A-12MOHM 3 2 1
P5VS3 DRVL
19
DRVL1 DRVL2 12
P3V3S5 DRVL
MIN NECK WIDTH 0 2 MM DIDT TRUE
3.3UH-20%-11A-12MOHM MAX CURRENT = 7.0A
MAX CURRENT = 7.0A 1 2 MIN LINE WIDTH 0 6 MM
DIDT TRUE
6 G2 1 2
24 7
P5VS3 VO1 VO1 VO2 P3V3S5 VO2
B PWM FREQ. = 300 KHZ
PP5V S5 REG
PIC1004H-SM
P5VS3 VFB
2
VFB1 VFB2 5
P3V3S5 VFB S2
PIC1004H-SM
B
6 5
PP3V3 S5 REG 6
5
1 6
OMIT TABLE
P5VS3 ENTRIP ENTRIP1 ENTRIP2 P3V3S5 ENTRIP
CRITICAL D MIN LINE WIDTH 0 6 MM 18

VCLK CRITICAL
Q7761 MIN NECK WIDTH 0 2 MM NC
1
C7793 1
C7790 1
C7791 RJK03E0DNS G 4 DIDT TRUE 1
C7751
1
C7750
23
0.001UF 10UF 220UF HWSON 8 1
PGOOD 1 R7772 150UF 10UF
1
C7753
20% 20% 20%
R7771 1
C7773 20%
20% 0.001UF
50V 10V 13 75K 6 3V 20%
2
CERM
2 X5R 2 6 3V 75K EN0 NC 10UF 1% 2 6 3V 2 X5R 50V
402 603
ELEC
D1A-SM
S 1%
GND THRM_PAD 20% 1/16W
POLY
B1A-SM
603 2
CERM
1/16W 6 3V MF-LF 402
MF LF
15
25
2 X5R 402
402 603 2
CRITICAL 2
3 2 1
GND 5V3V3S5 SGND 1 2
VOLTAGE 0V
XW7701
SM
PLACE NEAR=U7200 25 1 MM
P5V3V3S5 PGOOD OUT 40

PAGE TITLE
5V/3.3V SUPPLY
DRAWING NUMBER SIZE

REVISION
R
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3
C.0.0
77 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
T29 / Device Rails Power Goods
42 35 34 20 IN PM_S3_EN =P3V3S3_EN OUT 40

MAKE BASE=TRUE
P5V3V3S5_PGOOD TP_5V3V3S5_PGOOD
D R7905 1
39 IN
MAKE BASE=TRUE D
2.2K
5%
1/16W
MF LF REF DESIGN REQ 2.2K FOR QTY 2 MCUS
402
2
PM S0 EN =P12VS0 EN 36 IN P1V05S0_PGOOD CK505_PWRGD OUT 22

42 35 34 25 20 IN OUT 40
MAKE BASE=TRUE S0 PGOOD
=P3V3S0_EN OUT 40
MAKE BASE=TRUE
1
R7906 =P1V05S0_EN OUT 36
2.2K
5%
1/16W
MF LF
402
2
41 6 =PP3V3_S0_TCPWRSW
=TCCONN_PWR_EN OUT 41
C C
3.3V S0 FET
3.3V S3 FET RT7990
CRITICAL
CRITICAL 0 Q7990
6 =PP3V3_S5_P3V3S0FET 1 2 PP3V3_S5_P3V3S0FET SIA427DJ
RT7980 Q7980 4557 MA 5%
+1700 MA MIN NECK WIDTH=0 2MM SC70 6L
0 SIA427DJ 1/4W VOLTAGE=3 3V =PP3V3_S0_FET 6
=PP3V3_S5_P3V3S3FET PP3V3_S5_P3V3S3FET
7
6 1 2 MF LF
SC70 6L
4753 mA MIN LINE WIDTH=0 4MM 1206 4557 MA
S
=PP3V3_S3_FET
D
4
1
5% 6
7
1/4W VOLTAGE=3 3V +1700 MA
4753 mA NOSTUFF
D
MF LF
4 Q7810
1
1206
R7992 1 C7991 1
0.033UF
Q7980
G
C7981 47K
R7982 1 1
5%
10%
16V Part SiA427DJ
0.033UF 1/16W 2
G
47K 10% MF LF
X5R
3
5% 16V Part SiA427DJ 402
402
Type P-Ch 8V/5V
1/16W 2 2
MF LF
X5R
C7990
3
402
402
2
Type P-Ch 8V/5V R7990 0.01UF Rds(ON) 26 mOhm @1.8V
C7980 33K
R7980 0.01UF Rds(ON) 26 mOhm @1.8V P3V3S0_EN_L 1 2 P3V3S0_SS 1 2
33K Max Current 12 A @ 1.8V

5%
P3V3S3_EN_L 1 2 P3V3S3_SS 1 2
1/16W 10%
Max Current 12 A @ 1.8V MF LF 16V
Q7989 5%
10% Q7999 D 3
402 CERM
1/16W 402
16V
SSM3K15FV D 3 MF LF
402 CERM SSM6N37FEAPE
402 SOT563
SOD-VESM-HF
B 5 G S 4
B
1 G S 2 40 IN =P3V3S0_EN
40 IN =P3V3S3_EN
12V S0 FET
CRITICAL
Q7995
RT7995 SI8409DB
0 BGA
6 =PP12V_S5_P12VS0FET 1 2 PP12V_S5_P12VS0FET =PP12V_S0_FET 6
3
2100 mA 5% MIN NECK WIDTH=0 2MM 2100 mA
D
1/4W VOLTAGE=12V
2
MF LF
1206
Q7995
R7996 1
G
1
C7996
47K 0.033UF Part Si8409DB
5%
10%
1/16W
1
16V
MF LF 2 X5R C7995 Type P-Ch 30V/12V
402
2 R7995 402
0.01UF
33K Rds(ON) 46 mOhm @4.5V
P12VS0_EN_DIV_L 1 2 P12VS0_SS 1 2
5%
10%
Max Current 3.7 A @ 70C
1/16W
R7997 1 MF LF 16V
402 CERM
4.7K 402
5%
1/16W
MF LF Tweak R/C values as necessary!
402
2
A P12VS0_EN_L SYNC_MASTER=T29_D SYNC_DATE=09/30/2010 A

PAGE TITLE
Q7999 D 6 Power: Enables & PGOODs

SSM6N37FEAPE DRAWING NUMBER SIZE
SOT563

REVISION
R
2 G S 1
C.0.0
40 IN =P12VS0_EN THE INFORMATION CONTAINED HEREIN IS THE
79 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Cable 3.3V Power Switch

CRITICAL
U9080
6 =PP3V3_S0_TCPWR_FET TPS2065DBV =PP3V3_S0_TCPWRSW 6 40
SOT23
1 5
1A Max Continuous OUT IN
TP_TCPWRSW_OC_L 3 OC* EN 4 =TCCONN_PWR_EN 40

IN
GND
2
D C9086 1 1
C9085 C9081 1 1
C9080
CRITICAL
1
CRITICAL
C9087
D
10UF 0.1UF 0.1UF 22UF 100UF
20% 20% 20% 20% 20%
6 3V 10V 10V 6 3V 6 3V
X5R 2 2 CERM CERM 2 2 X5R CERM 1 2
POLY TANT
603 402 402 603 CASE B2 SM
C C
L9000
Tethered (Thunderbolt-Only) Cable Connector
6 =PP3V3 S0 TCCONN FERR-120-OHM-3A R9000
0
1 2 PP3V3_SW_TCCONN_F 1 2
0603 MIN NECK WIDTH=0 20 MM 5%
VOLTAGE=3 3V 1/10W
C9000 1 MF LF
603
0.01UF
10%
50V C9005
X7R 2
R9002 GND VOID=TRUE
R9005 0.01UF
402 GND VOID=TRUE
12 12
1 2 GND_TCCONN_2 For J9000 T29 SMT pads TCCONN_1 1 2 TCCONN_1_R 1 2
NOTE: C2R = Cable to Router MIN LINE WIDTH=0 38 MM (3 5 15 & 17) MIN LINE WIDTH 0 38 MM MIN LINE WIDTH 0 38 MM
10% 50V
5% MIN NECK WIDTH=0 20 MM MIN NECK WIDTH 0 20 MM 5% MIN NECK WIDTH 0 20 MM
X7R 402
R2C = Router to Cable 1/16W VOLTAGE=0V VOLTAGE 3 3V 1/16W VOLTAGE 3 3V
GND VOID=TRUE MF LF MF LF GND VOID=TRUE
402 CRITICAL 402
C9040 1 2 C9050 1 2
T29_C2R_P<0> 44 T29_C2R_C_P<0> 44 T29_R2C_P<0> T29_R2C_C_P<0>

44 23 OUT 0.22UF
20%
X5R
6 3V
402
J9000 0.22UF
20%
X5R
6 3V
402
IN 23 44
44 23 OUT T29_C2R_N<0> 44 T29_C2R_C_N<0> MDP-J59 44 T29_R2C_N<0> T29_R2C_C_N<0> IN 23 44

C9041 1 2
F-RT-THSM
C9051 1 2
20% 6 3V 20% 6 3V
0.22UF X5R 402 0.22UF X5R 402
GND VOID=TRUE GND VOID=TRUE

BOT ROW TOP ROW
C9006
R9003 GND VOID=TRUE
TH PINS SM PINS R9006 0.01UF
12 2 1 GND VOID=TRUE 12
1 2 GND_TCCONN_8 HOT_PLUG_DETECT GND TCCONN_7 1 2 TCCONN_7_R 1 2
4 3 GND VOID=TRUE
MIN LINE WIDTH=0 38 MM CONFIG1 ML_LANE0P MIN LINE WIDTH 0 38 MM MIN LINE WIDTH 0 38 MM
10% 50V
5% MIN NECK WIDTH=0 20 MM MIN NECK WIDTH 0 20 MM 5% MIN NECK WIDTH 0 20 MM
1/16W VOLTAGE=0V 6 5 GND VOID=TRUE 1/16W X7R 402
NO STUFF MF LF
CONFIG2 ML_LANE0N VOLTAGE 3 3V
MF LF
VOLTAGE 3 3V
402 8 7 402
R9030 1 2 GND GND
35 =I2C_PLUGCDRS_SDA 5% 1/16W I2C_TCCONN_SDA 10 ML_LANE3P 9 T29_LSX_R2P 7 34
BI 0 ML_LANE1P IN
MF LF 402
B 35 IN =I2C_PLUGCDRS_SCL
R9031
0
1 2
5% 1/16W
I2C_TCCONN_SCL 12
14
ML_LANE3N
GND
ML_LANE1N
GND
11
13
T29_LSX_P2R OUT 7 34
B
MF LF 402
R9004 16 15 GND VOID=TRUE
LSX pulls on TCMCU page.
12
GND VOID=TRUE AUX_CHP ML_LANE2P
NO STUFF 18 17 GND VOID=TRUE
1 2 GND_TCCONN_14 AUX_CHN ML_LANE2N
5%
MIN NECK WIDTH=0 20 MM 20 DP_PWR 19 GND VOID=TRUE
R9007
1/16W VOLTAGE=0V RETURN 12
MF LF GND TCCONN 13 1 2
402 MIN LINE WIDTH=0 38 MM
SHIELD PINS MIN NECK WIDTH=0 20 MM 5%
VOLTAGE=0V 1/16W
GND VOID=TRUE MF LF GND VOID=TRUE
22 21 402
C9042 1 2 C9052 1 2
44 23 OUT T29_C2R_P<1> 20% 6 3V 44 T29_C2R_C_P<1> 44 T29_R2C_P<1> 20% 6 3V T29_R2C_C_P<1> IN 23 44

0.22UF X5R 402 0.22UF X5R 402
44 23 OUT T29 C2R N<1> 44 T29 C2R C N<1> 44 T29 R2C N<1> T29 R2C C N<1> IN 23 44
C9043 1 2 C9053 1 2
20% 6 3V 20% 6 3V
0.22UF X5R 402 0.22UF X5R 402

C9001 L9008
0.01UF R9001 FERR-120-OHM-3A
12
2 1 TCCONN_20_RC 1 2 GND_TCCONN_19 1 2
MIN LINE WIDTH=0 38 MM MIN LINE WIDTH=0 38 MM
MIN NECK WIDTH=0 20 MM 5% MIN NECK WIDTH=0 20 MM 0603
10% 1/16W
VOLTAGE=3 3V VOLTAGE=0V
50V MF LF
X7R 402
402 R9008
12
1 2
5%
1/16W
MF LF
402
PAGE TITLE
Tethered Cable Connector

DRAWING NUMBER SIZE

REVISION
R
C.0.0
90 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GND VOID=TRUE
C9370 1 2
T29 A High-Speed Signals
(C9370/C9371)
44 23 OUT T29_D2R_N<0> 10% 6 3V T29_D2R_C_P<0> IN 43 44
0.22UF CERM X5R
44 23 OUT T29_D2R_P<0> 402 T29_D2R_C_N<0> IN 43 44
C9371 1 2
OVERSIZE PAD=0 875 mm^2 10% 6 3V

0.22UF CERM X5R
(Both L’s) 402
(C9372.2) GND VOID=TRUE
T29: TX_0
L9372 1 2 C9372 1 2
44 23 IN T29_R2D_C_N<0> 1.0NH+/-0.1NH 0201 1 44 T29_R2D_C_F_N<0> 10% 6 3V T29_R2D_P<0> OUT 43 44

0.22UF CERM X5R
44 23 IN T29_R2D_C_P<0> 44 T29_R2D_C_F_P<0> 402 T29_R2D_N<0> OUT 43 44
L9373 1 2 C9373 1 2
1.0NH+/-0.1NH 0201 1 10% 6 3V

0.22UF CERM X5R
(C9373.2) GND VOID=TRUE 402
T29 signals are

D P/N-swapped after AC
D
caps to improve layout. GND VOID=TRUE
(C9380/C9381)
C9380 1 2
44 23 OUT T29 D2R N<1> 10% 6 3V T29 D2R C P<1> IN 42 43 44

0.22UF CERM X5R
44 23 OUT T29_D2R_P<1> 402 T29_D2R_C_N<1> IN 42 43 44
C9381 1 2
OVERSIZE PAD=0 875 mm^2 10% 6 3V

0.22UF CERM X5R
(Both L’s) 402
(C9383.2) GND VOID=TRUE
T29: TX_1
L9382 1 2 C9382 1 2
44 23 IN T29_R2D_C_N<1> 1.0NH+/-0.1NH 0201 1 44 T29_R2D_C_F_N<1> 10% 6 3V T29_R2D_P<1> OUT 43 44

0.22UF CERM X5R
44 23 IN T29 R2D C P<1> 44 T29 R2D C F P<1> 402 T29 R2D N<1> OUT 43 44
L9383 1 2 C9383 1 2
1.0NH+/-0.1NH 0201 1 10% 6 3V

0.22UF CERM X5R
(C9383.2) GND VOID=TRUE 402
C C
43 42 PP3V3_SW_DPAPWR
1
R9399
100K
5%
1/16W
MF LF
2 402
T29 A RSVD N OUT 43 44
T29_A_RSVD_P BI 43 44
T29: Unused
1 1
Port A MCU R9392

51
5%
R9393
51
5%
1/16W 1/16W
B 43 42 PP3V3_SW_DPAPWR
Must be 3.3V DP A port power
MF LF
402
2 2
MF LF
402 B
T29 D2R C P<1> BI 42 43 44
T29_D2R_C_N<1> BI 42 43 44
T29: RX_1 Bias Sink

29
C9330 C9331
6
1 1
VDD
0.1UF
20%
0.1UF
20%
R9337 1 1
R9338
CRITICAL OMIT_TABLE 10V
2 2
10V 10K 10K 1
U9330 CERM
402
CERM
402
5%
1/16W
5%
1/16W
R9398
LPC1112FHN33/CP3281 MF LF MF LF 100K
402 402 5%
2 2
HVQFN 1/16W
SINGLE PORT DEVICES MF LF
7 OUT DP_A_PWRDWN 2 RESET*/PIO0_0 R/PIO1_0/AD1/CT32B1_CAP0 22 T29DPA_CONFIG1_RC IN 43 2
402
STILL USE T29_BIAS 3 23 R9334
34 BI MCU_CA_DET PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_1/AD2/CT32B1_MAT0 T29DPA_CONFIG2_RC IN 43
IN PORT LOW VOLTAGE POWER 10K
23 IN =T29_LSEO<0> 8 PIO0_2/SSEL0/CT16B0_CAP0 R/PIO1_2/AD3/CT32B1_MAT1 24 T29_A_HV_EN_R 1 2 T29_A_HV_EN OUT 37 43
7 OUT T29_A_BIAS 40
25 20 OUT PM_S0_EN 9 PIO0_3 SWDIO/PIO1_3/AD4/CT32B1_MAT2 25 42 T29_A_UC_ADDR 5%
35 34 1/16W
35 IN =I2C TBLTAMCU SCL 10 PIO0_4/SCL PIO1_4/AD5/CT32B1_MAT3/WAKEUP 26 DP A EXT HPD 32 MF LF
C9357 1
=I2C TBLTAMCU SDA 11 30 TBLT AC PRESENT
402
0.1UF 35 BI PIO0_5/SDA PIO1_5/RTS*/CT32B0_CAP0 IN 34
20%
43 T29DPA_HPD 15 31 (T29 A LSX P2R) P2R = Plug to Receptacle T29DPA_ML_N<1>
10V
2
IN PIO0_6/SCK0 PIO1_6/RXD/CT32B0_MAT0 BI 43 44
CERM 16 32 (T29 A LSX R2P) R2P = Receptacle to Plug T29DPA_ML_P<1>
402 PIO0_7/CTS* PIO1_7/TXD/CT32B0_MAT1 OUT 43 44
23 OUT =T29_LSOE<0> 17 PIO0_8/MISO0/CT16B0_MAT0 PIO1_8/CT16B1_CAP0 7 T29_LSEO<1> IN 23

1
23 OUT T29_LSOE<1> 18 PIO0_9/MOSI0/CT16B0_MAT1 PIO1_9/CT16B1_MAT0 12 I2C_MCU_SCL OUT 34 35 45 R9339
TBLT_WAKE_L 19 20 I2C_MCU_SDA 1M
34 7 IN SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_10/AD6/CT16B1_MAT1 BI 34 35 45
5%
OMIT 34 BI TBLT_PWR_REQ_L 21 R/PIO0_11/AD0/CT32B0_MAT3 PIO1_11/AD7 27 PM_DPO_EN OUT 7 34
1/16W
MF LF
R9330 1 SWCLK JTAG TBLT TDI OUT 11 34 2

402
0 40 35 34 20 OUT PM S3 EN 1 PIO2_0/DTR* PIO3_2 28 JTAG TBLT TCK OUT 11 34

5%
A 1/16W
MF LF
402
2
4 XTALIN PIO3_4 13
14
=JTAG_TBLTA_TMS OUT 11
SYNC_MASTER=T29_D SYNC_DATE=11/01/2010 A
SWDIO PIO3_5 JTAG_TBLT_TDO IN 11 34 PAGE TITLE
5 XTALOUT
NC
42 T29 A UC ADDR VSS T29 A PORT MICROCONTROLLER
R9330 provides pads for programming/debug of MCU, please make accessible.
33
DRAWING NUMBER SIZE

R9335 1
1
If project has space for 10-pin programming header it should be used. I2C Addr: R9336
0x26/0x27 (Wr/Rd) 1K 10K REVISION
5% 5%
R
1/16W
MF LF
1/16W
MF LF
C.0.0
402
2 2
402
93 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_SW_DPAPWR
3.3V/HV Power MUX Port A 3.3V Power Switch
42
MIN LINE WIDTH=0 38 MM CRITICAL
MIN NECK WIDTH=0 20 MM DP_PWR must be S4 to support
VOLTAGE=3 3V
CRITICAL wake from T29 devices.
U9480
Port A HV Power Switch SI8409DB:
Vds(max): -30V
D9425
POWERDI 123
2 1
3.3V Always
1
TPS2051B
SOT23
5
=PP3V3_S4_DPAPWRSW 6 7
OUT IN
Nominal Min Max Vgs(max): +/-12V
IFLT 2A 1.8A 2.2A Vgs(th): -1.4V 3 4 =DPAPWRSW_EN
DFLS1100 OC* EN IN 7 43
6 =PPHV_SW_DPAPWRSW ILIM 829mA 687mA 971mA (*) Rds(on): 65mOhm @ 2.5V Vgs GND
20V Max CRITICAL 2
TFLT 18.3ms 13.4ms 26.7ms Id(max): 3.7A @ 70C Q9425
D TSD 470ms 235ms 724ms
Blocking FET, off when
SI8409DB
BGA C9486 1 1
C9485 C9481 1 1
C9480
CRITICAL
1
CRITICAL
C9487
D
(*) U9410 tolerance @ 210K per TI Source >3.4V or HV_EN high. 10UF 0.1UF 0.1UF 22UF 100UF
3.3V/HV MUXed 20% 20% 20% 20%
3
1 CRITICAL 6 3V 10V 10V 6 3V
20%
2 2 2 2 2 6 3V
D
10 X5R CERM CERM X5R CERM 1
2
PPHV_SW_DPAPWR_D POLY TANT
603 402 402 603 CASE B2 SM
11 MIN NECK WIDTH=0 20 MM
3 VIN VOUT CRITICAL
R9416 1 C9410 1 12 VOLTAGE=15V 1 1
R9417
1
R9425
G
4 D9410
30K 0.1UF DSN2 10K 4.7K R9430 1
5%
1/16W
10%
50V
2
U9410 NSR20F20NXXXG 5%
1/16W
5%
1/16W
4.7K
5%
1
MF LF X7R
603 1
SN1010017 2 MF LF MF LF 1/16W
402 2 QFN 402 402 MF LF
2 2
402
DPAPWRSW_HVEN_L 16 EN* FLT* 15 TP_DPAPWRSW_FLT_L 2
CRITICAL 3
1
C9435
DPAPWRSW_P3V3_ON_L
IN 0.1UF
6 RTRY* ILIM 7 DPAPWRSW ILIM DPAPWRSW P3V3 ON 5
OUT 20%
10V
2 CERM
9 CT Q9426 U9435
DPAPWRSW_CT IFLT 8 DPAPWRSW_IFLT Q9427 ZXRE060A
402
NOSTUFF CRITICAL GND THRM T29HV:P15V SSM3K15FV D 3 3 DMB53D0UV SOT353

PAD 4
SOT 563 FB
R94151
3 1
D9415 R9412 R9410 1
1
R9411
SOD VESM HF
5
Bleeder Resistor PGND GND
5
13
14
17
24K SOT23 0
1
C9411
5% 5% 0.1UF 100K 210K 1 2
1/16W
MMBZ5227BLT1H 1/16W 10%
5% 1% 2.5V / 249 ohm = 10mA
MF LF MF LF 50V 1/16W 1/16W 4 6
2 MF LF MF LF P = ~27mW DPAPWR_BLDR_E_R
402 2 1 2 402 X7R
402 402 MIN LINE WIDTH=0 20 MM
603 1 2 2 MIN NECK WIDTH=0 20 MM
1 G S 2 Q9426 D
<CT> <RFLT> <RLIM> DMB53D0UV
Q9415
SSM3K15FV Q9418 STOP LEAK SOT 563
D 3
SSM3K15FV G 2 T29_A_HV_EN 37 42 43
SOD VESM HF 3 D
IFLT = 200k / RFLT = 2A 3
SOD VESM HF
R9435
1
DPAPWR_BLDR_B 5 R9419 2 100K

ILIM = 201k / RLIM = 829mA +/- 142mA 249 1%
Q9419 1%
S 1/16W
1 G S TFLT = CCT * 38900 6 DMB53D0UV 4

1/16W
MF LF
MF LF
402
2 2
SOT 563 402
1 2
S G 1 1
TSD = CCT * 100000 D Q9419 =DPAPWRSW_EN IN 7 43 DPAPWR_FB_DIV
C DMB53D0UV
SOT 563
DPAPWR_BLDR_E 1
C
43 42 37 T29_A_HV_EN 2 G MIN LINE WIDTH=0 20 MM
R9436
IN 21.5K
Note: Bleeder active when T29_A_HV_EN is LOW 1%
1/16W
and DPAPWRSW_P3V3_ON_L is HIGH (>0.8V). MF LF
For 12V systems: 402
2
S
ILIM = 201k / RLIM = 1033mA +/- 156mA
1 L9400
FERR-120-OHM-3A
DisplayPort/T29 A Connector
PP3V3RHV_SW_DPAPWR_UF 1 2 PP3V3RHV_SW_DPAPWR
114S0434 1 RES MTL FILM 1/16W 174K 1 0402 SMD LF R9411 T29HV:P12V MIN LINE WIDTH=0 38 MM
0603
MIN NECK WIDTH=0 20 MM MIN NECK WIDTH=0 20 MM
VOLTAGE=15V VOLTAGE=15V
Nominal Min Max C9400 1
0.01UF C9405
ILIM 1033mA 877mA 1190mA, tolerance @ 174K per TI 10%
GND VOID=TRUE 0.1UF
50V GND_DPACONN_1 1 2
X7R 2
MIN NECK WIDTH=0 20 MM 10%
VOLTAGE=0V 25V
X5R
T29 Dir DP Dir DP Dir T29 Dir 402
T29_R2D_P<0> IN 42 44
44 42 OUT T29_D2R_C_P<0> T29_R2D_N<0> IN 42 44

CRITICAL
T29_D2R_C_N<0>
44 42 OUT J9400
GND VOID=TRUE GND VOID=TRUE MDP-J59
F-ANG-TH T29: TX_0
R9494 1
1
R9495 GND VOID=TRUE GND VOID=TRUE
1K 1K 1 1
C9406 R9470 R9471
5%
1/16W
5%
1/16W
R9403 GND VOID=TRUE GND VOID=TRUE 0.1UF 470K 470K
12 2 1
MF LF MF LF
1 2 GND_DPACONN_8 HPD GND GND_DPACONN_7 1 2 5% 5%
402 402 1/20W 1/20W
2 2
MIN LINE WIDTH=0 38 MM 4 3 MIN LINE WIDTH=0 38 MM
SIGNAL MODEL=EMPTY SIGNAL MODEL=EMPTY 5% MIN NECK WIDTH=0 20 MM
CONFIG1 ML_LANE0P MF MF
MIN NECK WIDTH=0 20 MM 10% 201 201
1/16W VOLTAGE=0V 6 5 VOLTAGE=0V
2 2
MF LF
CONFIG2 ML_LANE0N 25V
8 7 X5R
402
GND GND 402
44 42 T29_A_RSVD_P 10 ML_LANE3P 9 T29DPA_ML_P<1> 42 44
BI ML_LANE1P IN
B 44 42 BI T29_A_RSVD_N
T29: Unused
12
14
ML_LANE3N
GND
ML_LANE1N
GND
11
13
T29DPA_ML_N<1> BI 42 44
B
R9404 16 15
T29: LSX_R2P/P2R (P/N)
12
GND VOID=TRUE AUX_CHP ML_LANE2P
1 2 GND_DPACONN_14 18 17
AUX_CHN ML_LANE2N
5%
MIN NECK WIDTH=0 20 MM 20 DP_PWR 19 GND VOID=TRUE
R9407
1/16W VOLTAGE=0V RETURN 12
MF LF GND DPACONN 13 1 2
SHIELD PINS MIN NECK WIDTH=0 20 MM 5%
VOLTAGE=0V 1/16W
MF LF
T29_R2D_P<1>
22
21
402 42 44
IN
44 42 OUT T29_D2R_C_P<1> T29_R2D_N<1> IN 42 44
44 42 OUT T29 D2R C N<1>
R9402 T29: TX_1

12
1 2 T29DPA_HPD_R L9408 1
R9472
1
R9473
5%
FERR-120-OHM-3A 470K 470K
1/16W 5% 5%
MF LF
R9401 GND_DPACONN_19 1 2
1/20W 1/20W
402 MIN LINE WIDTH=0 38 MM MF MF
12 MIN NECK WIDTH=0 20 MM 0603 201 201
DPACONN_20_RC 1 2 VOLTAGE=0V 2 2
5%
VOLTAGE=18V 1/16W R9408
MF LF 12
402 1 2 470k R’s for ESD protection
C9402 1 1
C9401
0.01UF 0.01UF
5% on AC-coupled signals.
1/16W
10% 10% MF LF
50V 50V 402
X7R 2 2 X7R
402 402
T29DPA HPD
A 42
42
OUT
T29DPA_CONFIG1_RC DP Source must pull

SYNC_MASTER=MASTER SYNC_DATE=N/A A
OUT 1 PAGE TITLE
down HPD input with R9441
42 OUT T29DPA_CONFIG2_RC
greater than or equal
100K
5%
DisplayPort/T29 A Connector
1/16W DRAWING NUMBER SIZE
to 100K (DPv1.1a). MF LF
R9452 1
1
R9451 C9494 1 1
C9495 2
402
1M 1M 330PF 330PF REVISION
5% 5% Sink HPD range: R
1/16W
MF LF
1/16W
MF LF
10%
50V
2 2
10%
50V
High: 2.0 - 5.0V
C.0.0
CERM CERM
402
2 2
402 402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Low: 0 - 0.8V
94 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI-Express Signal Constraints T29 Net Properties
NET TYPE
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? ELECTRICAL CONSTRAINT SET PHYSICAL SPACING
PCIE 85D * 85 OHM DIFF =85 OHM DIFF =85 OHM DIFF =85 OHM DIFF =85 OHM DIFF =85 OHM DIFF
PCIE CLK100M T29 CLK PCIE 90D CLK PCIE PCIE CLK100M T29 P 22 23
PCIEG2 85D * N =85 OHM DIFF =85 OHM DIFF =85 OHM DIFF =85 OHM DIFF =85 OHM DIFF PCIE CLK100M T29 CLK PCIE 90D CLK PCIE PCIE_CLK100M_T29_N 22 23
PCIEG2 85D TOP BOTTOM Y =85 OHM DIFF =85 OHM DIFF =85 OHM DIFF =85 OHM DIFF =85 OHM DIFF I2C 55SE I2C I2C_T29_SCL 23 35
I2C 55SE I2C I2C T29 SDA 23 35

CLK PCIE 90D * 90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF
T29 SPI CLK T29 SPI 55S T29 SPI T29 SPI CLK 23
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT T29 SPI MOSI T29 SPI 55S T29 SPI T29 SPI MOSI 23
T29_SPI_MISO
D PCIE * =3X DIELECTRIC ? PCIE TOP BOTTOM =4X DIELECTRIC ?
T29 SPI MISO
T29 SPI CS L
T29 SPI 55S
T29 SPI 55S

T29 SPI
T29 SPI T29_SPI_CS_L

23
23
D
PCIEG2 * =3X DIELECTRIC ? PCIEG2 TOP BOTTOM =4X DIELECTRIC ?
CLK PCIE * 20 MIL ?

T29DP 90D T29DP T29 R2D C P<3..0> 23 42
BEAD PROBE TRUE
T29DP 90D T29DP T29 R2D C N<3..0> 23 42
T29 I2C Signal Constraints T29DP 90D T29DP T29_D2R_P<3..0>

BEAD PROBE TRUE
23 42
T29 DP AND DOWNSTREAM PORTS

BEAD PROBE TRUE
ALLOW ROUTE T29DP 90D T29DP T29_D2R_N<3..0> 23 42
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP BEAD PROBE TRUE
I2C 55SE * =55 OHM SE =55 OHM SE =55 OHM SE =55 OHM SE 0 1MM =STANDARD T29 R2D0 T29DP 90D T29DP T29_R2D_P<0> 42 43
BEAD PROBE TRUE
T29 R2D0 T29DP 90D T29DP T29_R2D_N<0> 42 43
BEAD PROBE TRUE
T29 R2D1 T29DP 90D T29DP T29_R2D_P<1> 42 43
BEAD PROBE TRUE
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT T29 R2D1 T29DP 90D T29DP T29_R2D_N<1> 42 43
BEAD PROBE TRUE
I2C * =2x DIELECTRIC ?
T29DP 90D T29DP T29_R2D_C_F_P<1..0> 42
BEAD PROBE TRUE
T29DP 90D T29DP T29_R2D_C_F_N<1..0> 42
T29 SPI Signal Constraints BEAD PROBE TRUE
ON LAYER? T29 D2R0 T29DP 90D T29DP T29 D2R C P<0> 42 43
BEAD PROBE TRUE
T29 SPI 55S * =55 OHM SE =55 OHM SE =55 OHM SE =55 OHM SE =STANDARD =STANDARD T29 D2R0 T29DP 90D T29DP T29 D2R C N<0> 42 43
BEAD PROBE TRUE
T29 D2R1 T29DP 90D T29DP T29 D2R C P<1> 42 43
BEAD PROBE TRUE
T29 D2R1 T29DP 90D T29DP T29_D2R_C_N<1> 42 43
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT BEAD PROBE TRUE
DP 90D DISPLAYPORT T29DPA_ML_P<1> 42 43

T29 SPI * =2x DIELECTRIC ?
DP 90D DISPLAYPORT T29DPA_ML_N<1> 42 43
T29/DP Connector Signal Constraints T29_A_RSVD_P

C
C PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
USB2 90D
USB2 90D
USB2
USB2 T29_A_RSVD_N
42 43
42 43
ON LAYER?
T29DP 90D * N =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF
T29DP 90D TOP BOTTOM Y =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF
T29/DP TETHERED CABLE

T29DP 90D T29DP T29_R2C_P<1..0> 41
BEAD PROBE TRUE
T29DP 90D T29DP T29_R2C_N<1..0> 41
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT BEAD PROBE TRUE
T29 R2C0 T29DP 90D T29DP T29_R2C_C_P<0> 23 41
BEAD PROBE TRUE
T29DP * =5x DIELECTRIC ? T29 R2C0 T29DP 90D T29DP T29_R2C_C_N<0> 23 41
BEAD PROBE TRUE
T29 R2C1 T29DP 90D T29DP T29_R2C_C_P<1> 23 41
SOURCE: Bill Cornelius’s T29 Routing Notes BEAD PROBE TRUE
T29 R2C1 T29DP 90D T29DP T29_R2C_C_N<1> 23 41
BEAD PROBE TRUE
T29 C2R0 T29DP 90D T29DP T29_C2R_P<0> 23 41
BEAD PROBE TRUE
DP CONNECTOR SIGNAL CONSTRAINTS T29 C2R0 T29DP 90D T29DP T29_C2R_N<0>
T29_C2R_P<1>
BEAD PROBE TRUE
23 41
T29 C2R1 T29DP 90D T29DP 23 41

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP BEAD PROBE TRUE
ON LAYER? T29 C2R1 T29DP 90D T29DP T29_C2R_N<1> 23 41
BEAD PROBE TRUE
DP 90D * =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF T29DP 90D T29DP T29_C2R_C_P<1..0> 41
BEAD PROBE TRUE
T29DP 90D T29DP T29_C2R_C_N<1..0> 41
BEAD PROBE TRUE
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
DISPLAYPORT * =4 1 SPACING ? DISPLAYPORT TOP BOTTOM =4 1 SPACING ?
B B
INTERNAL PANEL PROPERTIES

NET TYPE
ELECTRICAL CONSTRAINT SET PHYSICAL SPACING
A SYNC_MASTER=TONY SYNC_DATE=11/17/2010 A
DP 90D DISPLAYPORT DP INT ML C P<3..0> 7
PAGE TITLE
I366
I367 DP 90D DISPLAYPORT DP_INT_ML_C_N<3..0> 7 CONSTRAINTS: T29

I368 DP INT ML DP 90D DISPLAYPORT DP_INT_ML_P<3..0> 7 21 48 DRAWING NUMBER SIZE
I369 DP INT ML DP 90D DISPLAYPORT DP_INT_ML_N<3..0> 7 21 48
I371 DP 90D DISPLAYPORT DP_INT_AUXCH_C_P 7 REVISION
R
I370 DP 90D DISPLAYPORT DP_INT_AUXCH_C_N 7 C.0.0
I372 DP INT AUXCH DP 90D DISPLAYPORT DP_INT_AUXCH_P 7 21 48 NOTICE OF PROPRIETARY PROPERTY: BRANCH
I373 DP INT AUXCH DP 90D DISPLAYPORT DP INT AUXCH N 7 21 48 THE INFORMATION CONTAINED HEREIN IS THE
100 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Temp Sensor Constraints Temp Sensor Net Properties

NET TYPE
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL CONSTRAINT SET PHYSICAL SPACING
ON LAYER?
I424 TMPSNS PAIR TMPSNS DX1_P 8
TMPSNS PAIR * 55 OHM SE =55 OHM SE =55 OHM SE 20MM 0 25MM 0 10MM
I425 TMPSNS PAIR TMPSNS DX1_N 8
Temp sensor routes
I426 TMPSNS PAIR TMPSNS TDX1_P 8 48
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
I427 TMPSNS PAIR TMPSNS TDX1_N 8 48
D TMPSNS * =2x DIELECTRIC ?
I428 TMPSNS PAIR TMPSNS DX2_P 8

D
I431 TMPSNS PAIR TMPSNS DX2_N 8
I430 TMPSNS PAIR TMPSNS TDX2_P 8 48
I429 TMPSNS PAIR TMPSNS TDX2_N 8 48
AUDIO CONSTRAINTS AUDIO NET PROPERTIES

ALLOW ROUTE NET TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
AUDIODIFF * Y 0 6 MM 0 2 MM 10 MM 0 2 MM 0 2 MM
I448 AUDIODIFF AUDIO AUD_LTWT_N 15
I449 AUDIODIFF AUDIO AUD_LTWT_P 15
I450 AUDIODIFF AUDIO AUD LWFR N 15
I451 AUDIODIFF AUDIO AUD_LWFR_P 15
I452 AUDIODIFF AUDIO AUD_RTWT_N 16
I453 AUDIODIFF AUDIO AUD_RTWT_P 16

I454 AUDIODIFF AUDIO AUD RWFR N 16
AUDIO * 0 2 MM ? AUDIODIFF AUDIO AUD_RWFR_P 16
I455
I456 AUDIODIFF AUDIO AUD_SUB_N 17
I457 AUDIODIFF AUDIO AUD_SUB_P 17
SPEAKER NET PROPERTIES

C ELECTRICAL CONSTRAINT SET PHYSICAL
NET TYPE
SPACING
C
I458 AUDIODIFF AUDIO SPKRAMP_LTWT_OUT_N 15 18 48
I459 AUDIODIFF AUDIO SPKRAMP_LTWT_OUT_P 15 18 48
I460 AUDIODIFF AUDIO SPKRAMP_LWFR_OUT_N 15 18 48
I461 AUDIODIFF AUDIO SPKRAMP_LWFR_OUT_P 15 18 48
I462 AUDIODIFF AUDIO SPKRAMP_RTWT_OUT_N 16 18 48
I463 AUDIODIFF AUDIO SPKRAMP RTWT OUT P 16 18 48
I464 AUDIODIFF AUDIO SPKRAMP_RWFR_OUT_N 16 18 48
I465 AUDIODIFF AUDIO SPKRAMP_RWFR_OUT_P 16 18 48
I466 AUDIODIFF AUDIO SPKRAMP_SUB_OUT_N 17 18 48
I467 AUDIODIFF AUDIO SPKRAMP_SUB_OUT_P 17 18 48
I2C Net Properties

NET TYPE
I2C 55SE I2C I2C_LPCREM_SDA 20 21
I2C 55SE I2C I2C_LPCREM_SCL 20 21
I2C 55SE I2C DDC_SDA_FC 21 48
I2C 55SE I2C DDC_SCL_FC 21 48 I2C pairs from LPC

I2C 55SE I2C SDA FC 21 48
I2C 55SE I2C SCL_FC 21 48
I2C 55SE I2C SDA_SWREM 21
I2C 55SE I2C SCL_SWREM 21
B I2C 55SE
I2C 55SE
I2C
I2C
I2C_DP628_SDA
I2C_DP628_SCL
35
35
B
I2C 55SE I2C I2C_LPCLOC_SDA 20 35
I2C 55SE I2C I2C LPCLOC SCL 20 35
I2C 55SE I2C I2C FALS SDA 10
I2C 55SE I2C I2C_FALS_SCL 10
I2C 55SE I2C I2C_LPC1_SDA 35
I2C 55SE I2C I2C_LPC1_SCL 35
I2C 55SE I2C I2C_ALS_SCL 35 48
I2C 55SE I2C I2C ALS SDA 35 48
I2C 55SE I2C I2C_USBHOST_SCL 35
I2C 55SE I2C I2C_USBHOST_SDA 35
I2C 55SE I2C ADAV4601 I2C SDA

I2C 55SE I2C ADAV4601 I2C SCL
14
14
MicroCtlr Net Properties
NET TYPE
I2C 55SE I2C I2C_SDA 12 14 18
I2C 55SE I2C I2C_SCL 12 14 18
Audio I2C pairs MICROCTLR 55SE MICROCTLR ADC STR0 V
I2C 55SE I2C AUD_161_I2C_SDA 12
9 20
AUD_161_I2C_SCL MICROCTLR 55SE MICROCTLR ADC_STR1_V 9 20

I2C 55SE I2C 12
MICROCTLR 55SE MICROCTLR ADC_STR2_V 9 20
MICROCTLR 55SE MICROCTLR DAC_OUT 9 20
I2C 55SE I2C I2C_MCU_SCL 34 35 42
A I2C 55SE I2C I2C_MCU_SDA 34 35 42 MICROCTLR 55SE MICROCTLR ADC_USB5V 20 33

MICROCTLR 55SE MICROCTLR P5VP3V3_VREF 9 39 PAGE TITLE
CONSTRAINTS: AUDIO & MISC

DRAWING NUMBER SIZE

REVISION
R
C.0.0
103 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Ethernet MDI Constraints Ethernet MDI Net Properties

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET TYPE
ON LAYER?
ENET MDI 100D * 100 OHM DIFF =100 OHM DIFF =100 OHM DIFF =100 OHM DIFF =100 OHM DIFF =100 OHM DIFF
I128 ENET MDI ENET MDI 100D ENET MDI ENETCONN_MDI_P<3..0> 26 27
I127 ENET MDI ENET MDI 100D ENET MDI ENETCONN_MDI_N<3..0> 26 27

I130 ENET MDI 100D ENET MDI ENETCONN_MDI_T_P<3..0> 27
ENET MDI * 25 MIL ? ENET MDI 100D ENET MDI ENETCONN_MDI_T_N<3..0> 27
I129
D
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
D
PCIe Net Properties
NET TYPE
I117 PCIE 85D PCIE PCIE ENET R2D P 26
I118 PCIE 85D PCIE PCIE_ENET_R2D_N 26
I119 PCIE ENET R2D PCIE 85D PCIE PCIE_ENET_R2D_C_P 7 26
I120 PCIE ENET R2D PCIE 85D PCIE PCIE_ENET_R2D_C_N 7 26
I121 PCIE ENET D2R PCIE 85D PCIE PCIE_ENET_D2R_P 7 26
I122 PCIE ENET D2R PCIE 85D PCIE PCIE_ENET_D2R_N 7 26
I123 PCIE 85D PCIE PCIE ENET D2R C P 26
I124 PCIE 85D PCIE PCIE ENET D2R C N 26
I125 PCIE CLK100M ENET CLK PCIE 90D CLK PCIE PCIE_CLK100M_ENET_P 22 26
I126 PCIE CLK100M ENET CLK PCIE 90D CLK PCIE PCIE_CLK100M_ENET_N 22 26
FireWire Interface Constraints FireWire Net Properties

ON LAYER?
FW 110D * 110 OHM DIFF =110 OHM DIFF =110 OHM DIFF =110 OHM DIFF =110 OHM DIFF =110 OHM DIFF
FW P0 TPA FW 110D FW TP FW PORT0 TPA P 29 30
FW P0 TPA FW 110D FW TP FW PORT0 TPA N 29 30

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT FW P0 TPB FW 110D FW TP FW_PORT0_TPB_P 29 30
FW TP * =3 1 SPACING ? FW P0 TPB FW 110D FW TP FW_PORT0_TPB_N 29 30
C FIREWIRE PCIE NET PROPERTIES C

NET TYPE
PCIE 85D PCIE PCIE FW R2D P 28
PCIE 85D PCIE PCIE_FW_R2D_N 28
PCIE FW R2D PCIE 85D PCIE PCIE_FW_R2D_C_P 7 28
PCIE FW R2D PCIE 85D PCIE PCIE_FW_R2D_C_N 7 28
PCIE FW D2R PCIE 85D PCIE PCIE_FW_D2R_P 7 28
PCIE FW D2R PCIE 85D PCIE PCIE_FW_D2R_N 7 28
PCIE 85D PCIE PCIE_FW_D2R_C_P 28
PCIE 85D PCIE PCIE_FW_D2R_C_N 28
PCIE CLK100M FW CLK PCIE 90D CLK PCIE PCIE_CLK100M_FW_P 22 28
PCIE CLK100M FW CLK PCIE 90D CLK PCIE PCIE_CLK100M_FW_N 22 28
USB 2.0 Interface Constraints USB Net Properties

ON LAYER?
USB2 90D * 90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF =90 OHM DIFF USB2
USB2 90D USB HUB UP DP 31
USB2 USB_HUB_UP_DM
USB2 90D 31
USB2 USB_DEV_DP
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB2 90D 31
USB2 USB_DEV_DM
USB2 90D 31
USB2 * =4 1 SPACING ? USB2
USB UPSTREAM USB2 90D USB_DEV_F_DP 31
USB2 USB_DEV_F_DM
USB2 90D 31
B USB PCIE NET PROPERTIES USB2 90D

USB2
USB2
USB_HOST_DP 31 32 B
NET TYPE USB2 90D USB HOST DM 31 32
PCIEG2 85D PCIEG2 PCIE_USB_D2R_C_P 32
PCIEG2 85D PCIEG2 PCIE USB D2R C N 32
PCIEG2 85D PCIEG2 PCIE USB R2D P 32
PCIEG2 85D PCIEG2 PCIE USB R2D N 32
PCIE USB R2D PCIEG2 85D PCIEG2 PCIE_USB_R2D_C_P 7 32
PCIE USB R2D PCIEG2 85D PCIEG2 PCIE_USB_R2D_C_N 7 32 USB2 USBDN1_H1_DP

USB2 90D 31 33
PCIE USB D2R PCIEG2 85D PCIEG2 PCIE_USB_D2R_P 7 32 USB2 USBDN1_H1_DM
USB2 90D 31 33
PCIE USB D2R PCIEG2 85D PCIEG2 PCIE_USB_D2R_N 7 32
USB2 90D USB2 USBDN2 H1 DP 31 33
USB2 90D USB2 USBDN2 H1 DM

PCIE CLK100M USB CLK PCIE 90D CLK PCIE PCIE_CLK100M_USB_P 7 32
31 33
USB2 USBDN3 H1 DP
PCIE_CLK100M_USB_N USB2 90D 31 33
PCIE CLK100M USB CLK PCIE 90D CLK PCIE 7 32
USB2 90D USB2 USBDN3_H1_DM
PCIE CLK100M USB CLK PCIE 90D CLK PCIE PCIE_CLK100M_USB_C_P 32
USB Hub ports
31 33
USB2 USB_UC_DP
PCIE_CLK100M_USB_C_N USB2 90D 20 31
PCIE CLK100M USB CLK PCIE 90D CLK PCIE 32
USB2 USB_UC_DM
USB2 90D 20 31
USB2 USB_AUDIO_DP
USB2 90D 11 31
USB2 90D USB2 USB_AUDIO_DM 11 31
USB2 90D USB2 USB CAMERA DP 10 31

USB2 USB CAMERA DM
USB2 90D 10 31
USB2 CAM DP
USB2 90D 10 48
USB2 CAM_DM
USB2 90D 10 48
USB2 AUD_161_USB_DP
USB2 90D 12
USB AUDIO USB2 90D
USB2 AUD_161_USB_DM 12
A USB2 90D
USB2 DM1 33
USB2
PAGE TITLE
USB2 90D DP1 33
USB2 90D USB2 DM2 33

CONSTRAINTS:ENET, FIREWIRE & USB
USB connector routes USB2 DRAWING NUMBER SIZE
USB2 90D DP2 33
USB2 90D
USB2 DM3 33
USB2 90D USB2 DP3 33
REVISION
R
C.0.0
105 OF 110
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T29 Dr.B-Specific Physical & Spacing Constraints Standard Spacing Rules
BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
(MIL or MM) VERSION
TOP ISL2 ISL3 ISL4 ISL5 ISL6 ISL7 BOTTOM NO TYPE MM 15 7 DEFAULT * 0 1 MM ?
STANDARD * =DEFAULT ?
ON LAYER?
DEFAULT * Y =55 OHM SE =55 OHM SE 6 35 MM 0 MM 0 MM SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
STANDARD * Y =DEFAULT =DEFAULT =DEFAULT =DEFAULT =DEFAULT 1 1 SPACING * 0 1 MM ?
2 1 SPACING * 0 2 MM ?
D PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
3 1 SPACING * 0 3 MM ? D
55 OHM SE * Y 0 076 MM 0 076 MM =STANDARD =STANDARD =STANDARD
55 OHM SE TOP BOTTOM Y 0 085 MM 0 085 MM
2X DIELECTRIC TOP BOTTOM 0 140 MM ?
2X DIELECTRIC * 0 152 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 3X DIELECTRIC * 0 228 MM ?
ON LAYER?
80 OHM DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 4X DIELECTRIC * 0 304 MM ?
80 OHM DIFF ISL3 ISL6 Y 0 120 MM 0 120 MM 0 150 MM 0 150 MM 5X DIELECTRIC * 0 380 MM ?
80 OHM DIFF TOP BOTTOM Y 0 135 MM 0 135 MM 0 160 MM 0 160 MM
ON LAYER?
85 OHM DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
85 OHM DIFF ISL3 ISL6 Y 0 115 MM 0 115 MM 0 200 MM 0 200 MM
C 85 OHM DIFF TOP BOTTOM Y 0 125 MM 0 125 MM 0 200 MM 0 200 MM

C
ON LAYER?
ON LAYER?
ON LAYER?
B PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
B
1 1 DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0 1 MM 0 1 MM
A SYNC_MASTER=TONY SYNC_DATE=11/17/2010 A
PAGE TITLE
T29 PCB Rule Definitions

DRAWING NUMBER SIZE

REVISION
R
C.0.0
109 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FUNCTIONAL TEST POINTS NC AND NO_TEST NETS

FLIP SIDE PCI BRIDGE AND USB CONTROLLER MOUNTING AND ROUTING MAKES TEST VIRTUALLY IMPOSSIBLE
J2726 PANEL POWER

J1013 ODD FAN
D 8 IN FAN0_PWR FUNC TEST TRUE 21 IN PP12V PANEL FC FUNC TEST TRUE
MIN ALLOWED TPS=4
TP_PCIBR_WAKE_L NC_PCIBR_WAKE_L
NO TEST=TRUE
PCI AD<31..0> D
MAKE BASE=TRUE
8 IN FAN_TACH0 FUNC TEST=TRUE NO TEST=TRUE PCI_C_BE_L<3 0>
4 GROUND TESTPOINTS NEAR J2726 NO TEST=TRUE
19 IN PP12V FAN FET FUNC TEST=TRUE PCI_PAR
MIN ALLOWED TPS=3 NO TEST=TRUE
3 GROUND TESTPOINTS NEAR J1013 PCI_FRAME_L
NO TEST=TRUE
TP_PEX8112_EECS_L NC_PEX8112_EECS_L PCI_IRDY_L
J1115 BLC CONNECTOR NO TEST=TRUE PCI_TRDY_L
J2725 INTERNAL DP PANEL NO TEST=TRUE
PCI_DEVSEL_L
9 STR0_+ FUNC TEST TRUE
TP PEX8112 EECLK NC PEX8112 EECLK NO TEST=TRUE
IN MAKE BASE=TRUE PCI_STOP_L
STR0_- FUNC TEST TRUE NO TEST=TRUE NO TEST=TRUE
9 IN 44 21 7 IN DP_INT_ML_P<3..0> FUNC TEST=TRUE PCI PERR L
9 IN STR0C FUNC TEST TRUE DP_INT_ML_N<3..0> FUNC TEST=TRUE
TP_PEX8112_EERDDATA NC_PEX8112_EERDDATA NO TEST=TRUE
44 21 7 IN MAKE BASE=TRUE PCI SERR L
NO TEST=TRUE NO TEST=TRUE
9 IN STR1 + FUNC TEST=TRUE 44 21 7 DP_INT_AUXCH_P FUNC TEST TRUE
PCI NECUSB REQ L
IN TP PEX8112 EEWRDATA NC PEX8112 EEWRDATA NO TEST=TRUE
9 IN STR1_- FUNC TEST TRUE 44 21 7 DP_INT_AUXCH_N FUNC TEST=TRUE MAKE BASE=TRUE
PCI_NECUSB_GNT_L
IN NO TEST=TRUE
9 STR1C FUNC TEST TRUE NO TEST=TRUE PCI_NECUSB_INT_L
IN DDC SCL FC
45 21 IN FUNC TEST=TRUE TP_PEX8112_GPIO0 NC_PEX8112_GPIO0 NO TEST=TRUE
MAKE BASE=TRUE
PCI_CLKRUN_L
9 IN STR2 + FUNC TEST=TRUE 45 21 IN DDC SDA FC FUNC TEST=TRUE NO TEST=TRUE NO TEST=TRUE
PCI_RESET_L
9 IN STR2_- FUNC TEST TRUE NO TEST=TRUE
45 21 IN SCL_FC FUNC TEST=TRUE TP_PEX8112_GPIO1 NC_PEX8112_GPIO1
9 IN STR2C FUNC TEST TRUE MAKE BASE=TRUE
45 21 IN SDA FC FUNC TEST=TRUE NO TEST=TRUE
2 GROUND TESTPOINTS NEAR J1013
21 IN AUDIO_ON_FC FUNC TEST TRUE TP_PEX8112_GPIO2 NC_PEX8112_GPIO2
MAKE BASE=TRUE
21 IN AUDIO_MUTE_FC_L FUNC TEST TRUE NO TEST=TRUE
TP_PEX8112_GPIO3 NC_PEX8112_GPIO3
MAKE BASE=TRUE
21 IN I2S_SCLK_FC FUNC TEST=TRUE NO TEST=TRUE
21 IN I2S_WS_FC FUNC TEST=TRUE TP PEX8112 PWR OK NC PEX8112 PWR OK
J1204 USB CAMERA 21 IN I2S SD0 FC FUNC TEST=TRUE MAKE BASE=TRUE
NO TEST=TRUE
21 IN DP_PWR_UP_FC FUNC TEST TRUE TP_PEX8112_BAR0ENB_L NC_PEX8112_BAR0ENB_L
10 IN PP5V_CAM_FILT FUNC TEST TRUE MAKE BASE=TRUE
MIN ALLOWED TPS=1 21 IN INT_FC_L FUNC TEST TRUE NO TEST=TRUE
C 46 10
46 10
IN
IN
CAM_DM
CAM_DP
FUNC TEST=TRUE
FUNC TEST=TRUE
21
21
IN DP_INT_HPD_FC
VIDEO ON FC
FUNC TEST=TRUE
FUNC TEST=TRUE
TP PEX8112 PCLKO62SEL L NC PEX8112 PCLKO62SEL L
MAKE BASE=TRUE
C
IN NO TEST=TRUE
21 IN VSYNC FC FUNC TEST=TRUE TP_PEX8112_PMEOUT_L NC_PEX8112_PMEOUT_L
45 35 IN I2C ALS SCL FUNC TEST=TRUE MAKE BASE=TRUE
NO TEST=TRUE
45 35 I2C_ALS_SDA FUNC TEST=TRUE 17 GROUND TESTPOINTS NEAR J2725
IN TP_PEX8112_GNT1_L NC_PEX8112_GNT1_L
MAKE BASE=TRUE
4 GROUND TESTPOINTS NEAR J1204 NO TEST=TRUE
TP_PEX8112_GNT2_L NC_PEX8112_GNT2_L
MAKE BASE=TRUE
NO TEST=TRUE
J2007 MICROPHONE TP_PEX8112_GNT3_L NC_PEX8112_GNT3_L
MAKE BASE=TRUE
NO TEST=TRUE
18 IN AUD_MIC_IN_N_CONN FUNC TEST TRUE
GND_AUD_MIC_CONN GND TP_PEX8112_PCLKO NC_PEX8112_PCLK0
18 IN FUNC TEST TRUE 36 TP’S FUNC TEST TRUE MAKE BASE=TRUE
MIN ALLOWED TPS=36 NO TEST=TRUE
18 IN AUD_MIC_IN_P_CONN FUNC TEST=TRUE
TP_NECUSB_SMI_L NC_NECUSB_SMI_L
J2003 AUDIO LEFT SPEAKER MAKE BASE=TRUE
NO TEST=TRUE
45 18 15 IN SPKRAMP_LWFR_OUT_P FUNC TEST TRUE
TP_NECUSB_PPON1 NC_NECUSB_PPON1
45 18 15 IN SPKRAMP_LWFR_OUT_N FUNC TEST TRUE MAKE BASE=TRUE
NO TEST=TRUE
45 18 15 IN SPKRAMP_LTWT_OUT_P FUNC TEST TRUE
45 18 15 IN SPKRAMP_LTWT_OUT_N FUNC TEST TRUE MAKE BASE=TRUE
NO TEST=TRUE
MAKE BASE=TRUE
NO TEST=TRUE
J2004 AUDIO RIGHT SPEAKER TP_NECUSB_SRCLK NC_NECUSB_SRCLK
B 45 18 16 IN SPKRAMP_RWFR_OUT_P FUNC TEST=TRUE
MAKE BASE=TRUE
NO TEST=TRUE B
45 18 16 IN SPKRAMP RWFR OUT N FUNC TEST=TRUE TP NECUSB SRDTA NC NECUSB SRDTA
MAKE BASE=TRUE
45 18 16 IN SPKRAMP RTWT OUT P FUNC TEST=TRUE NO TEST=TRUE
45 18 16 IN SPKRAMP_RTWT_OUT_N FUNC TEST TRUE TP_NECUSB_SRMOD NC_NECUSB_SRMOD
MAKE BASE=TRUE
NO TEST=TRUE
TP_NECUSB_TESTEN NC_NECUSB_TESTEN
J2005 AUDIO SUBWOOFER MAKE BASE=TRUE
NO TEST=TRUE
45 18 17 IN SPKRAMP_SUB_OUT_P FUNC TEST=TRUE TP_NECUSB_TEST3 NC_NECUSB_TEST3
MAKE BASE=TRUE
45 18 17 IN SPKRAMP_SUB_OUT_N FUNC TEST=TRUE NO TEST=TRUE
TP NECUSB TEST4 NC NECUSB TEST4
MAKE BASE=TRUE
18 17 16 15 13 GND_AUDIO_SPKRAMP FUNC TEST TRUE NO TEST=TRUE
IN
MIN ALLOWED TPS=6
J1011 BLOWER TEMP SENSOR

45 8 IN TDX1_N FUNC TEST=TRUE
45 8 IN TDX1 P FUNC TEST=TRUE
J1012 PSU TEMP SENSOR

45 8 IN TDX2_N FUNC TEST TRUE
45 8 IN TDX2_P FUNC TEST TRUE
A 2 GROUND TESTPOINTS NEAR J1012 SYNC MASTER=MASTER SYNC DATE=N/A A

PAGE TITLE
J59 ICT/FCT
DRAWING NUMBER SIZE

REVISION
R
C.0.0
110 OF 110
8 7 6 5 4 3 2 1

J59 820-2997 APPLE THUNDERBOLT 27_ Display_LS

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8 7 6 5 4 3 2 1

Page Contents Sync

Apple Inc. 051-8774 D

J59 BLOCK DIAGRAM

Apple Inc. 051-8774 D

mDP Tethered Q7560 24V FW FW FW FW FW FW N/A FW N/A N/A

BOM NUMBER BOM NAME BOM OPTIONS

D 338S0753 1 IC FW643 E 1394B PHY/OHCI LINK/PCI E 12 U4100 CRITICAL D

338S0977 1 PCI EXPRESS TO USB 2 0 HOST CONTROLLER(REV B) U4600 CRITICAL

BOM GROUP BOM OPTIONS

RAW: 335S0800 341T0331 1 ENET FLASH C IV NO SD J59 U3990 CRITICAL

RAW: 353S2320 341T0369 1 IC PRGRMD PNX0161 AUDIO/HID TFBGA88 U1400 CRITICAL

376S0977 376S0859 ALL DIODESINC ALT FET

376S0972 376S0612 ALL ROHM ALT FET

377S0107 377S0066 ALL ON SEMI ALT RCLAMP

155S0431 155S0289 L1204 ALTERNATE CM CHOKE

376S1029 376S0953 ALL ALTERNATE DC/DC FET

376S1030 376S0801 ALL ALTERNATE DC/DC FET

376S1017 376S0612 ALL ALTERNATE TOSH SS FET

377S0124 377S0057 ALL ALTERNATE VARISTOR

152S1483 152S1376 ALL ALTERNATE INDUCTOR

155S0691 155S0183 ALL ALT BEAD FOR BL FILT

128S0262 128S0220 ALL ADDS KEMET TO SANYO

138S0684 138S0660 ALL ADDS MURATA TO TAIYO

B 155S0571 155S0309 ALL ALTERNATE FERRITE B

Schematic / PCB / EEEE #’s

051-8774 1 SCH MLB J59 SCH1 CRITICAL

825-7122 1 MLB LABEL 48 0MM X 4 8MM [EEEE_DHMY] CRITICAL

BOM Configuration & Misc

Apple Inc. 051-8774 D

A SYNC MASTER=MASTER SYNC DATE=N/A A

Apple Inc. 051-8774 D

PP12V_S5 PP12V_S5_ACDC 5 PP24V_S0_BLC PP24V_BLC_FET 5

=PPVIN SW T29BST 6 37 PP12V S0 =PP12V S0 FET 40

PP5V S5 PP5V S5 REG 39

C MIN NECK WIDTH=0 2 mm

Apple Inc. 051-8774 D

23 OUT PCIE_T29_D2R_P<0> PCIE_USB_D2R_P IN 32 46

23 IN T29_PCIE_RESET_L<2> FW_RESET_L OUT 28

C 23 IN T29_PCIE_RESET_L<3> NC_T29_PCIE_RESET_L3 R909 R950 1

44 7 IN DP_INT_ML_C_P<0> DP_INT_ML_P<0> OUT 21 44 48 U5000 IS SLAVE MCU - U9330 IS MASTER

44 7 IN DP_INT_ML_C_N<0> DP_INT_ML_N<0> OUT 21 44 48

0.1UF 10% 16V X5R 402 35 32 6 =PP3V3_S3_USB

C902 CLOCKS Q952

44 7 IN DP_INT_ML_C_N<1> DP_INT_ML_N<1> OUT 21 44 48 22 IN PCIE_CLK100M_PCIBR_N PCIE_CLK100M_USB_N OUT 32 46

44 7 IN DP_INT_ML_C_P<2> DP_INT_ML_P<2> OUT 21 44 48

44 7 IN DP_INT_ML_C_N<2> DP_INT_ML_N<2> OUT 21 44 48

44 7 IN DP_INT_ML_C_P<3> DP_INT_ML_P<3> OUT 21 44 48

B 0.1UF 10% 16V X5R 402

44 7 IN DP_INT_ML_C_N<3> DP_INT_ML_N<3> OUT 21 44 48 22 IN PCIE_CLK100M_SLOT_N NC_PCIE_CLK100M_SRC1N

44 7 IN DP_INT_AUXCH_C_P DP_INT_AUXCH_P OUT 21 44 48

0.1UF 10% 16V X5R 402

PCIE_CLK100M_SATA_P NC_PCIE_CLK100M_SRC9P R9001 Q900

22 IN PCI CLK33M PCIBR NC PCI0 CLK33M

22 IN PCI CLK33M NECUSB NC PCI2 CLK33M

CURRENT LIMIT TO PROTECT UC

BLOWER TEMPERATURE 2 48 45 TDX1_N 1% 2 DX2 CRITICAL SDA 6 =I2C_TMP_SDA 35

1 48 45 TDX2 P R1073 1 1.5K 2 45 DX2 P

A SYNC MASTER=MASTER SYNC DATE=N/A A