UNIT - I INTRODUCTION TO OPERATIONAL AMPLIFIER AND ITS APPLICATIONS

PART – B

1. Draw the circuit of inverting and non – inverting amplifiers using Op – Amp and Derive an
expression for their gain.
Inverting Operational Amplifier
In the inverting operational amplifier circuit, the signal is applied at the inverting input
and the non-inverting input is connected to the ground. In this type of amplifier, the output is
180⁰ out of phase to the input, i.e. when positive signal is applied to circuit, the output of the
circuit will be negative. By assuming the Op-Amp is ideal, then the concept of virtual short can
be applied at the input terminals of the Op-Amp. So that voltage at the inverting terminal is
equal to the voltage at non-inverting terminal.

Applying KCL at inverting node of Op-Amp

0−Vin/R1+0−Vout/R2=0
Voltage Gain (Av) =Vout/Vin= −R2/R1
Non-Inverting Operational Amplifier
When the signal is applied at the non-inverting input, the resulting circuit is known as Non-
Inverting Op-Amp. In this amplifier the output is exactly in phase with the input i.e. when a positive
voltage is applied to the circuit, the output will also be positive. By assuming the Op-Amp is ideal,
then concept of virtual short can be applied i.e. the voltage at the inverting and non-inverting terminal

is equal.

2. Explain integrator and differentiator with a neat diagram.

Differentiator
A differentiator is an electronic circuit that produces an output equal to the first derivative of its input.
This section discusses about the op-amp based differentiator in detail. An op-amp based differentiator
produces an output, which is equal to the differential of input voltage that is applied to its inverting
terminal. The circuit diagram of an op-amp based differentiator is shown in the following figure −
In the above circuit, the non-inverting input terminal of the op-amp is connected to ground. That
means zero volts is applied to its non-inverting input terminal.

According to the virtual short concept, the voltage at the inverting input terminal of opamp will be
equal to the voltage present at its non-inverting input terminal. So, the voltage at the inverting input
terminal of op-amp will be zero volts.

The nodal equation at the inverting input terminal's node is −

Cd(0−Vi)/dt+0−V0/R=0
-𝐶d(0−𝑉𝑖)d𝑡+0−𝑉0𝑅=0
=>−CdVi/dt=V0/R
=>−𝐶d𝑉𝑖d𝑡=𝑉0𝑅
=>V0=−RCdVi/dt
=>𝑉0=−𝑅𝐶d𝑉𝑖/d𝑡

If RC=1sec𝑅𝐶=1sec, then the output voltage V0 will be −

V0=−dVi /dt
𝑉0=−d𝑉𝑖/d𝑡

Thus, the op-amp based differentiator circuit shown above will produce an output, which is the
differential of input voltage Vi𝑉𝑖, when the magnitudes of impedances of resistor and capacitor are
reciprocal to each other.

Note that the output voltage V0𝑉0 is having a negative sign, which indicates that there exists a
1800 phase difference between the input and the output.

Integrator

An integrator is an electronic circuit that produces an output that is the integration of the applied
input. This section discusses about the op-amp based integrator.

An op-amp based integrator produces an output, which is an integral of the input voltage applied to its
inverting terminal. The circuit diagram of an op-amp based integrator is shown in the following
figure −
In the circuit shown above, the non-inverting input terminal of the op-amp is connected to ground.
That means zero volts is applied to its non-inverting input terminal.

The nodal equation at the inverting input terminal is −

0−ViR+Cd(0−V0)dt=00−𝑉𝑖𝑅+𝐶d(0−𝑉0)d𝑡=0
=>−ViR=CdV0dt=>−𝑉𝑖𝑅=𝐶d𝑉0d𝑡
=>dV0dt=−ViRC=>d𝑉0d𝑡=−𝑉𝑖𝑅𝐶
=>dV0=(−ViRC)dt=>𝑑𝑉0=(−𝑉𝑖𝑅𝐶)d𝑡

Integrating both sides of the equation shown above, we get −

∫dV0=∫(−ViRC)dt∫𝑑𝑉0=∫(−𝑉𝑖𝑅𝐶)d𝑡
=>V0=−1RC∫Vtdt=>𝑉0=−1𝑅𝐶∫𝑉𝑡d𝑡

If RC=1sec𝑅𝐶=1sec, then the output voltage, V0𝑉0 will be −

V0=−∫Vidt𝑉0=−∫𝑉𝑖d𝑡
So, the op-amp based integrator circuit discussed above will produce an output, which is the integral
of input voltage Vi𝑉𝑖, when the magnitude of impedances of resistor and capacitor are reciprocal to
each other.
3. Explain Astable & Monostable multivibrator using Op - Amp with a neat diagram.
Op-amp Monostable Circuit
Firstly let’s consider the Inverting Amplifier circuit as shown.

In this inverting operational amplifier configuration, some of the output signal (called the feedback
fraction) is fed back to the inverting input of the operational amplifier via the resistive network.
In this basic inverting configuration the feedback fraction is therefore negative as it is fed back to the
inverting input. This negative feedback configuration between the output and the inverting input
terminal forces the differential input voltage towards zero.
The result of this negative feedback is that the op-amp produces an amplified output signal which is
180o out-of-phase with the input signal. So an increase in the inverting terminal voltage, -V fed back
from the output causes a decrease in the output voltage, VO producing a balanced and stable amplifier
operating within its linear region.
Consider now the same identical operational amplifier circuit in which the inverting and non-inverting
inputs of the op-amp have been interchanged. That is the feedback signal is fed back to the non-
inverting input and the feedback process is now positive producing a basic op-amp comparator circuit
with built-in hysteresis.
The op-amp monostable multivibrator circuit is constructed around an operational amplifier
configured as a closed-loop Schmitt Trigger circuit that uses positive feedback provided by
resistors R1 and R2 to generate the required hysteresis. The use of positive feedback means that the
feedback is regenerative and provides the required state dependence which in effect changes the op-
amp into a bistable memory device.
Basic Op-amp Monostable Circuit

At initial power on (that is t = 0), the output (VOUT) will saturate towards either the positive rail
(+Vcc), or to the negative rail (-Vcc), since these are the only two stable states allowed by the op-amp.
Lets assume for now that the output has swung towards the positive supply rail, +Vcc. Then the
voltage at the non-inverting input, VB will be equal to +Vcc*β where β is the feedback fraction.
The inverting input is held at 0.7 volts, the forward volt drop of diode, D1 and clamped to 0v (ground)
by the diode, preventing it from going any more positive. Thus the potential at VA is much less than
that at VB and the output remains stable at +Vcc. At the same time, the capacitor, (C) charges up to the
same 0.7 volts potential and is held there by the forward-biased voltage drop of the diode.
If we were to apply a negative pulse to the non-inverting input, the 0.7v voltage at VA now becomes
greater than the voltage at VB since VB is now negative. Thus the output of the Schmitt configured op-
amp switches state and saturates towards the negative supply rail, -Vcc. The result is that the potential
at VB is now equal to -Vcc*β.
This temporary meta-stable state causes the capacitor to charge up exponentially in the opposite
direction through the feedback resistor, R from +0.7 volts down to the saturated output which it has
just switched too, -Vcc. Diode, D1 becomes reverse-biased so has no effect. The capacitor, C will
discharge at a time constant τ = RC.
As soon as the capacitor voltage at VA reaches the same potential as VB, that is -Vcc*β, the op-amp
switches back to its original permanent stable state with the output saturated once again at +Vcc.
Note that once the timing period is complete and the op-amps output changes back to its stable state
and saturates towards the positive supply rail, the capacitor tries to charge up in reverse to +Vcc but
can only charge to a maximum value of 0.7v given by the diodes forward voltage drop. We can show
this effect graphically as:
Op-amp Monostable Waveforms

Then we can see that a negative-going trigger input, will switch the op-amp monostable circuit into its
temporary unstable state. After a time delay, T while the capacitor, C charges up through the feedback
resistor, R, the circuit switches back to its normal stable state once the capacitor voltage reaches the
required potential.
4. Briefly explain triangular wave generators with a neat circuit diagram.
Triangular Wave Generator
A triangular wave generator is an electronic circuit, which generates a triangular wave. The block
diagram of a triangular wave generator is shown in the following figure −

The block diagram of a triangular wave generator contains mainly two blocks: a square wave
generator and an integrator. These two blocks are cascaded. That means, the output of square wave
generator is applied as an input of integrator. Note that the integration of a square wave is nothing but
a triangular wave.
The circuit diagram of an op-amp based triangular wave generator is shown in the following figure −

We have already seen the circuit diagrams of a square wave generator and an integrator. Observe that
we got the above circuit diagram of an op-amp based triangular wave generator by replacing the
blocks with the respective circuit diagrams in the block diagram of a triangular wave generator.
 5. Explain in detail about V to I converter and I to V converter.
Voltage to Current Converter?
An electronic circuit that takes voltage as the input and produces a current as the output is known as
a voltage to current converter. The voltage to current converter is also known as V to I converter.
In other words, an electronic circuit that produces a current which is directly proportional to the
applied voltage is known as a voltage to current converter (V to I converter).
The voltage to current converters are used in instrumentation circuits. Where, the voltage to current
converter produces a current corresponding to the input voltage. Therefore, it can convert electrical
data from voltage to current form. The block diagram of a voltage to current converter is shown in
Figure-1.

Transfer Ratio of Voltage to Current Converter

The ratio of the output current to the input voltage of a voltage to current converter is known as
the transfer ratio of the converter.
TransferRatio,A=OutputCurrent(Iout)InputVoltage(Vin)TransferRatio,A=OutputCurrent(Iout)InputVo
ltage(Vin)
Circuit Diagram of Voltage to Current Converter
A voltage to current converter can be implemented using an operational amplifier. In practice, IC
LM741 operational amplifier is often used for this purpose. The operational amplifier can convert a
voltage signal into a corresponding current signal.
The circuit diagram of a typical voltage to current converter using Op-Amp is shown in Figure-2.

In the voltage to current converter using Op-Amp, an input voltage signal is applied at the non-
inverting terminal of the Op-Amp, while the output current is taken through the output terminal.
Types of Voltage to Current Converters
There are two types of voltage to current converters which are implemented using Op-Amp −
 Floating Load Voltage to Current Converter
 Ground Load Voltage to Current Converter
Let us discuss each of these two types of voltage to current converters one by one in detail.
Floating Load Voltage to Current Converter
As the name implies, the type of voltage to current converter in which the load resistor remains
floating in the converter circuit is known as a floating load voltage to current converter. Here, the
“floating load” means the load resistor is not connected to the ground. The circuit diagram of a
floating load voltage to current converter is shown in Figure-3.
In the floating load voltage to current converter, the input voltage (V in) is provided at the noninverting
terminal of the operational amplifier (Op-Amp), whereas the inverting terminal of the Op-Amp is
supplied with the feedback voltage (Vf). The feedback voltage is determined by the output current. In
this type of voltage to current converter, the feedback voltage (V f) is in series with the input difference
voltage (Vd). For this reason, the floating load voltage to current converter is also known as
the current series negative feedback amplifier.
The voltage equation of the floating load voltage to current converter is obtained by applying KVL in
the input loop as
Vin=Vd+VfVin=Vd+Vf
The transfer function or gain of the Op-Amp (A) is very large. Thus, Vd = 0.
∴Vin=Vf∴Vin=Vf
Since the input current IB to the Op-Amp is zero.
∴Vin=Io×R∴Vin=Io×R
Thus, the output current is
Io=VinRIo=VinR
Hence, from the above equation, it is clear that the output current depends upon the input voltage and
input resistance of the circuit. Since, the output current is controlled by the resistor R, hence,
Io∝VinIo∝Vin
i.e., the output current is directly proportional to the input voltage of the circuit.
Ground Load Voltage to Current Converter
In the ground load voltage to current converter, one end of the load resistor R L is always connected
to the ground. The ground load voltage to current converter is also known as Howland Current
Converter. The circuit diagram of this voltage to current converter is shown in Figure-4.

In order to analyze the circuit of the ground load voltage to current converter, we first determine the
relationship between the input voltage 𝑉𝑖𝑛 and the output current 𝐼𝑂. For that, we apply KVL at the
node 𝑉1, and get,
 I1+I2=IoI1+I2=Io
⇒Vin−V1R+Vo−V1R=Io⇒Vin−V1R+Vo−V1R=Io
Vin+Vo−2V1=IoRVin+Vo−2V1=IoR
But, for a non-inverting amplifier, the transfer gain A is
A=1+(RfR1)A=1+(RfR1)
In this circuit,
Rf=R1=RRf=R1=R
∴A=1+RR=2∴A=1+RR=2
Thus, the voltage at the output terminal is,
Vo=2V1Vo=2V1
Thus, the above voltage equation of the ground load voltage to current converter will become,
Vin+2V1−2V1=IoRVin+2V1−2V1=IoR
∴Vin=IoR∴Vin=IoR
Hence, the output load current is,
Io=VinRIo=VinR
Thus, it is clear that the output current is related to the input voltage Vin and the resistor R.

UNIT – II DIGITAL TO ANALOG AND ANALOG TO DIGITAL CONVERTERS AND PLL

PART – B

1. i) Draw and explain the working principle of op-amp based voltage controlled oscillator
circuit.
VCO using Op-amp

A square wave is generated at the output of the above circuit whose frequency is controlled by the
input voltage.
The Op-amp at the beginning of the circuit works as an integrator. As the control voltage is applied, at
the input terminal of the op-amp, due to the voltage divider arrangement only half of the control
voltage is applied at the positive terminal. The voltage at the negative terminal is at the same level so
as to maintain a voltage drop across R1.
The current from resistor R1 flows through MOSFET. The input voltage charges the capacitor. Thus,
providing steadily rising output voltage.
Now, when MOSFET is turned OFF, the current through R1 discharges the capacitor C1. Thus we will
have falling output voltage. So, we will have a triangular waveform at the output of op-amp 1.
Here, op-amp 2 works a Schmitt trigger. The output of op-amp 1 serves as the input of op-amp 2. At
the output of op-amp 2, a square wave is obtained.
Applications of VCO
1. These are used in function generators.
2. VCO is the elemental building block of phase locked loops.
3. In frequency shift keying techniques.
4. In frequency modulation.
5. These are used in tone generators.
2. Explain AM demodulation using PLL.
AM demodulation using PLL

The PLL is locked to the carrier frequency of the incoming AM signal. Once locked the output
frequency of VCO is same as the carrier frequency, but it is in unmodulated form. The modulated
signal with 90° phase shift and the unmodulated carrier from output of PLL are fed to the
multiplier. Since VCO output is always 90° out of phase with the incoming AM signal under the
locked condition, both the signals applied to the multiplier are in same phase.
Therefore, the output of the multiplier contains both the sum and the difference signals. The low
pass filter connected at the output of the multiplier rejects high frequency components gives
demodulated output. As PLL follows the input frequencies with high accuracy, a PLL AM
detector exhibits a high degree of selectivity and noise immunity which is not possible with
conventional peak detector type AM modulators.
3. Explain in detail about successive approximation DAC.
Successive Approximation type ADC
Successive Approximation type ADC is the most widely used and popular ADC method. The
conversion time is maintained constant in successive approximation type ADC, and is proportional to
the number of bits in the digitaloutput, unlike the counter and continuous type A/D converters. The
basic principle of this type of A/D converter is that the unknown analog input voltage is approximated
against an n-bit digital value by trying one bit at a time, beginning with the MSB. The principle of
successive approximation process for a 4-bit conversion is explained here. This type of ADC operates
by successively dividing the voltage range by half, as explained in the following steps.
(1) The MSB is initially set to 1 with the remaining three bits set as 000. The digital equivalent voltage
is compared with the unknown analog input voltage.
(2) If the analog input voltage is higher than the digital equivalent voltage, the MSB is retained as 1
and the second MSB is set to 1. Otherwise, the MSB is set to 0 and the second MSB is set to 1.
Comparison is made as given in step (1) to decide whether to retain or reset the second MSB.
The above steps are more accurately illustrated with the help of an example.
Let us assume that the 4-bit ADC is used and the analog input voltage is VA = 11 V. when the
conversion starts, the MSB bit is set to 1.
Now VA = 11V > VD = 8V = [1000]2
Since the unknown analog input voltage VA is higher than the equivalent digital voltage VD, as
discussed in step (2), the MSB is retained as 1 and the next MSB bit is set to 1 as follows
VD = 12V = [1100]2
Now VA = 11V < VD = 12V = [1100]2
Here now, the unknown analog input voltage VA is lower than the equivalent digital voltage VD. As
discussed in step (2), the second MSB is set to 0 and next MSB set to 1 as
VD = 10V = [1010]2
Now again VA = 11V > VD = 10V = [1010]2
Again as discussed in step (2) VA>VD, hence the third MSB is retained to 1 and the last bit is set to 1.
The new code word is
VD = 11V = [1011]2
Now finally VA = VD , and the conversion stops.
The functional block diagram of successive approximation type of ADC is shown below.

It consists of a successive approximation register (SAR), DAC and comparator. The output of SAR is
given to n-bit DAC. The equivalent analog output voltage of DAC, VD is applied to the non-inverting
input of the comparator. The second input to the comparator is the unknown analog input voltage VA.
The output of the comparator is used to activate the successive approximation logic of SAR.
When the start command is applied, the SAR sets the MSB to logic 1 and other bits are made logic 0,
so that the trial code becomes 1000.
Advantages:
1Conversion time is very small.
2 Conversion time is constant and independent of the amplitude of the analog input signal VA.

4. Explain the operation of D/A converter and give some of the Advantages and Disadvantages
Types of DAC
The DAC can be designed using one of the following types of circuits.
Weighted Resistor Method
The weighted resistor method utilizes the summing operational amplifier circuit. The summing
amplifier adds the input signals with different gains corresponding to their resistors.

Vout = – {(Rf /R0) V0 + (Rf /R1) V1 + (Rf /R2) V2 +… + (Rf/Rn-1) Vn-1}

It can be used as a DAC if we assign each resistor a with specific value to scale their gain in the form
of 2, 4, 8 ,16 & so on. As we know the Vref (the reference voltage or the maximum analog output
voltage) is the only input signal (beside the binary input) so;

Vout = – {(Rf /R0) Vref + (Rf /R1) Vref + (Rf /R2) Vref +… + (Rf/Rn-1) Vref}
Vout = – Vref {(Rf /R0) + (Rf /R1) + (Rf /R2) +… + (Rf/Rn-1) }
In this circuit, the binary input 1 or 0 is used for switching between the v ref & GND. The input B = 1
means the switch is connected with Vref & B = 0 means the switch is connected with GND. In such
case the equation for a binary number B0, B1, B2… Bn ; where B0 is LSB & Bn is MSB, become
Vout = – Vref { B0 (Rf /R0) + B1 (Rf /R1)+ B2 (Rf /R2) +… + Bn-1 (Rf/Rn-1) }
The resistor Rf = R. while the R0, R1, R2, & Rn-1 are scaled to provide the necessary gain corresponding
to the weight of each bit. The resistors are scaled with the values 2(N-1)-n, such that;
Rn = 2(N-1)-n R where N is number of bits & n is the bit position
So
Vout = – Vref { B0 (R/2(N-1) R) + B1 (R /2(N-2) R) + B2 (R /2(N-3) R) +… + BN-2 (R /21 R) +BN-1 (R /20 R) }
 Vout = – Vref { B0 (1/2(N-1)) + B1 (1 /2(N-2)) + B2 (1/2(N-3)) +… + BN-2 (1 /2(1)) +BN-1 (1 /20) }
The output voltage for a 4 bit binary number would be;
Vout = – Vref { B0 (1/23) + B1 (1 /2(2)) + B2 (1/2(1)) + B3 (1/20) }
Vout = – Vref { B0 (1/8) + B1 (1 /4) + B2 (1/2) + B3 }

As you can see, each resistor is scaled to add the bit-weight of each bit of a binary input.
Simplified formulae for such circuit would be
Vout = – Vref { B0 (1/2(N-1))) + B1 (1 /2(N-2)) + B2 (1/2(N-3))) + B3 (1/2(N-4)) + B4 (1/2(N-5) +…}
Where the denominator 2(N-1) represents the scaling factor of each corresponding resistor.
5. Write in detail about r- 2r ladder DAC
R-2R Ladder Circuit
This method is more precise, accurate & easy to design then the weighted resistor method. R- 2R
ladder circuit is made by adding combination R & 2R resistor in cascaded form as shown in the
following figure.

There are only two types of resistors used. Each stage contains R & 2R, is used for a single bit. There
is switch between the Vref & GND which is controlled by the binary input. Bit 0 means the GND is
connected & bit 1 means the Vref is connected.
Working;
Let’s assume a 3 bit DAC using R-2R ladder network.
B2B1B0 are the 3 bits of the binary input. When B 0 = 1, B1 & B2 = 0. Then the equivalent circuit would
be;

Replacing the 1st stage with its Vth & Rth;

Vth = Vref/2 & Rth = R

Now the 2nd stage Vth & Rth;

Vth = Vref/4 & Rth = R

Now the 3rd stage Vth & Rth

Vth = Vref/8 & Rth = R

So the output voltage in this case would become

 Vout = -Vth (Rf/R) = -(Vref/8) (R/R) = -(Vref/8)
When B1 = 1, B0 & B2 = 0. Then the equivalent circuit would be;

Applying the same process the output voltage will be

Vout = -(Vref/4)

When B2 = 1, B0 & B1 = 0. Then the equivalent circuit would be;

Applying the same process the output voltage will be

Vout = -(Vref/2)

As we know the output of the opamp is the sum of individual inputs where each bit is
Vout = -{ B0 (Vref/8) + B1 (Vref/4) + B2 (Vref/2)}
Vout = – Vref { B0(1/8) + B1 (1/4) + B2 (1/2)}
Vout = – Vref { B0(1/23) + B1 (1/22) + B2 (1/21)}
We can generalize this formula for an N bit binary number as;
Vout = – Vref {B0(1/2N) + B1(1/2N-1) + B2(1/2N-2) +…+ BN-2(1/22) + BN-1(1/21)}
Advantages of R-2R Ladder DAC;
 Uses only two types of resistors
 Easiliy scalable to any number of bits
 Output impedance is always R
 UNIT – III THE BASIC GATES ANDCOMBINATIONAL LOGIC CIRCUITS
PART – B

1. i) Reduce the following function using k-map technique

ii) What are the methods for converting Decimal to Binary conversion?
Give some examples.

2. i) Minimise the following expression in the POS form

(6 Marks)
ii) Explain De Morgan’s theorem and the duality principle with proof. (6 Marks)

3. i) Minimize the Boolean expression: (6 Marks)

ii) Convert the given expression in to standard SOP.
(6 Marks)

4. i) Convert the following (37)10 to equivalent hexadecimal (2 Marks)

ii) Convert the following (25B) 16, (5A9.B4)16 to octal and binary. (4 Marks)
iii) Perform (4)10 - (9)10 using the 2’s complement method. (3 Marks)
iv) Subtract (9)10 - (4)10 using 1’s complement method. (3 Marks)

5. Find the following i) (CB9.F5)16 + (AB8.CD)16. (3 Marks)

ii) (9E4A)16 – (5FD6)16 (3 Marks)
iii) (E75)16 * (2A)16 (3 Marks)
iv) (745)8 - (263)8 (3 Marks)

6. Subtract the following using 2’s complement.

(i) 11101010 & 11010101 (3 Marks)
(ii) 10101010 & 11010100 (3 Marks)
(iii) 01011101 & 11001010 (3 Marks)
(iv) 10010101 & 11100010 (3 Marks)
 7. i) Convert 10101011 into its equivalent Decimal, Octal, Hexadecimal. (6 Marks)
ii) What the two method for Simplification of Boolean Functions (6 Marks)

8. i) Obtain the octal equivalent of (3964)10 . (3 Marks)

ii) Convert octal number (1654)8 into decimal system. (3 Marks)
iii) Convert (634.640625)10 to the octal system. (3 Marks)
iv) Convert (17.35)10 to binary form. (3 Marks)

9. Minimize the expression using Quine McCluskey method.

Step 1

Step 2.
 Quine McCluskey Tabular Method
Step 3

Tabular Method
Step 4.

Quine McCluskey Minimized Form

Step 5

Minterm Minimization

10. i) Reduce the following function using Karnaugh map technique.

(6 Marks)
ii) Reduce the following function using Karnaugh map technique.
(6 Marks)
 UNIT – IV COMBINATIONAL LOGIC CIRCUITS
PART – B

1. i) Design of half adder and full adder using gates. (8 Marks)

ii) Design the logic circuit for odd parity checker. (4 Marks)

2. i) Design of half subtractor & full subtractor using gates. (8 Marks)

ii) List out the design procedure of a combinational circuit. (4 Marks)

3. i) Design a 3 to 8 Decoder using gates. (8 Marks)

ii) Draw the logic diagram of BCD to Excess 3 – code converter. (4 Marks)

4. i) Explain the various types of ROM. (4 Marks)

ii) Implement the following Boolean function using ROM.
and (8 Marks)

5. i) Explain in detail about parallel binary adder with neat block diagram. (6 Marks)
ii) Give the comparison between PROM, PLA and PAL. (6 Marks)

6. Explain details about the design procedure of circuit 4 - bit multiplier with example. (12 Marks)

7. i) Design a BCD to 7-Segment display decoder. (6 Marks)

ii) Design a priority encoder. (6 Marks)

8. How will you build a full adder using two half adders and an OR gate? Explain briefly. (12 Marks)

9. Draw and explain the block diagram of n - bit parallel and binary adder subtractor. (12 Marks)

10. i) Draw and explain the block diagram of PLA. (4 Marks)

ii) Implement the following Boolean function using PLA.
, & (8 Marks)
 UNIT – V SEQUENTIAL LOGIC CIRCUITS
PART B

1. i) Distinguish between combinational and sequential logic circuits. (6 Marks)

ii) What is race around condition? How it’s avoided? (6 Marks)

2. Explain in detail SR & D flip-flop with neat circuit diagram (12 Marks)

3. Explain synchronous decade counter using JK flip-flop with block diagram in detail. (12 Marks)

4. i) Distinguish between synchronous and asynchronous sequential circuits. (6 Marks)

ii) Comparison between synchronous and asynchronous counters. (6 Marks)

5. Explain in detail JK & T flip-flop with neat circuit diagram (12 Marks)

6. i) Briefly explain about Ring counter with neat block diagram. (8 Marks)
ii) Write a short notes on State tables and State diagram (4 Marks)

7. Explain right shift register using JK flip-flop with block diagram in detail. (12 Marks)

8. Explain synchronous decade counter using D flip-flop with block diagram in detail. (12 Marks)

9. Explain right shift register using D flip-flop with block diagram in detail. (12 Marks)

10. Explain synchronous decade counter using T flip-flop with block diagram in detail. (12 Marks)