Ka-Band Low-Loss and High-Isolation 0.

13 µm CMOS
SPST/SPDT Switches Using High Substrate Resistance
Byung-Wook Min∗ and Gabriel M. Rebeiz†
∗ EECS, University of Michigan, Ann Arbor, Michigan 48109
Email: bmin@umich.edu
† ECE, University of California, San Diego, California 92093

Email: rebeiz@ece.ucsd.edu

Abstract— This paper presents 35 GHz single-pole-single- low loss switches using high substrate contact resistances.
throw (SPST) and single-pole-double-throw (SPDT) CMOS Also, the isolation is greatly improved using tuned parallel
switches using a 0.13 µm BiCMOS process (IBM 8HP). The resonators.
CMOS transistors are designed to have a high substrate
resistance to minimize the insertion loss and improve power
handling capability. The SPST/SPDT switches have a inser- II. S WITCH D ESIGN
tion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB A. NMOS Transistor and Switch Model
compression point (P1dB) greater than 22 dBm. The isolation
is greater than 30 dB at 35−40 GHz and is achieved using Fig. 1(a) shows a simplified equivalent circuit of a
two parallel resonant networks. To our knowledge, this is the nMOS transistor. The nMOS transistor is a 4-port device
first demonstration of low-loss, high-isolation CMOS switches with a body node of the substrate contact. Cjs and Cjd are
at Ka-band frequencies.
Index Terms— microwave switch, CMOS switch, SPST,
junction capacitances of the source/drain junction diodes,
SPDT, T/R switch, substrate resistance, Ka-band, RFIC and Cgs and Cgd are the parasitic capacitance between the
gate and the source/drain. The substrate resistance consists
I. I NTRODUCTION of the vertical and horizontal resistances (Rbv and Rbh )
In recent years, CMOS integrated circuits have and the substrate contact resistance (Rbc ).
been developed for microwave and millimeter-wave An nMOS switch can be modeled as shown in Fig. 1(b).
transceiver components as a potential competitor to III- In order to prevent signal leaking and oxide breakdown, the
V semiconductor-based circuits. Recent publications show gate of the nMOS switch is biased using a large resistor,
that low loss and high power switches can be integrated RG . Cs is the series capacitance due to Cgs and Cgd ,
in a CMOS process at 0.9 MHz to 5.8 GHz for a trans- and Rch is the on-state channel resistance. Rsub is the
mit/receive (T/R) switch application [1]–[4]. However, series resistance of Rbv , Rbh and Rbc . Rsub is not usually
CMOS switch design above 10 GHz is still challenging modeled in a CMOS process because it highly depends on
due to a high insertion loss and low isolation, as well
as relatively low power handling capability [5]. The main Body Drain Gate Source
limitation of CMOS transistors used as a switch is their
junction diodes between the source/drain and the substrate. Substrate Rbc Cgd Cgs
Cox
The junction diodes increase the signal loss and also limit Contact
n+ n+
the signal voltage swing. p+ STI Cjd Cjs
In order to increase the power handling capability of
Rbv
CMOS switches, the substrate resistance between the
source/drain junction and the RF ground of the substrate Rbh NMOSFET p
is often increased. Ohnakado et. al. developed a depletion (a)
VC Cs Cs Gate length/width
layer extended transistor [2] and Talwalkar et. al. used
= 0.13/100 µm
tuned LC tank [3] to increase this resistance. Yeh et. RG
al. biased the body of the CMOS transistors with a Rch Rch 4.2 Ω
Cjd Cjs Cjd Cjs
large resistor [4]. These efforts achieved input P1dB of Cs 19 fF
IN OUT Cjd 77 fF
20−28 dB with a insertion loss of 0.9−1.5 dB, but the Rsub Rsub
Cjs 77 fF
design frequencies were lower than 10 GHz. At frequen- NMOS Switch ON OFF
cies higher than 10 GHz, the increased substrate resistance (b)
does in fact decrease the insertion loss, but also results in
Fig. 1. (a) Cross sectional view and equivalent circuit model of NMOS
very poor isolation due to input/output coupling through transistor and (b) schematic of a nMOS switch and its simplified circuit
the junction diodes. In this paper, we present Ka-band model of on and off states.

1-4244-0530-0/1-4244-0531-9/07/$20.00  2007 IEEE 569 2007 IEEE Radio Frequency Integrated Circuits Symposium
 VC VC 1 Port 1 VC 2
nMOSFET
L1 RG L2 RG length / width RG RG RG RG
380 PH 340 PH 20 KΩ L2 L1 LIN L1 L2
= 0.13 / 100 µm
Port 1 Port 2 Port 2 Port 3

Rb Rb Rb Rb Rb Rb Rb Rb
Rsub Rsub Rsub Rsub Rsub Rsub
>1KΩ
(a) (b)

Fig. 2. Schematic of the CMOS (a) SPST and (b) SPDT switches with high substrate contact resistances.

the size and distance of substrate contacts as well as the for a III-V switch at W-band [7].
transistor size [6].
To improve the insertion loss, Rch of the nMOS tran- B. High Substrate-Contact Resistance Switches
sistor is usually reduced by enlarging the gate width. Fig. 2 presents the designed SPST and SPDT switches
However, the increased junction capacitances (Cjs and at 35 GHz. The SPST switch consist of two series nMOS
Cjd ) also increase the capacitive coupling to the substrate, transistors with a gate length of 0.13 µm, and each
resulting in an increase of the signal loss, especially transistor has 21 fingers with a total gate width of 100 µm.
at a frequency higher than 10 GHz. One can resonate In order to increase Rsub , the substrate contact resistance
out Cjs and Cjd with inductors when Rsub ≈ 0 or (Rbc ) is increased to 1 KΩ by adopting a small substrate
eliminate the capacitive coupling when Rsub ≈ ∞. Rsub contact (0.28×5 µm2 ) close to the nMOS transistor. The
is roughly estimated to be 10−100 Ω with a very large switches are controlled by a gate bias, VC = 0 or 1.5 V.
substrate contact, so Cjs and Cjd can not be completely
resonated out with inductors. However, the capacitive
coupling can be minimized with a large Rsub as long as 115 µm
Rsub  1/(jω◦ Cjs ). In terms of power handling, it is
Ground
advantageous to have a large Rsub since this will minimize Plane L2 240 µm
the RF voltage across the diodes and prevent any forward
bias condition. Port1 Port2
When the substrate resistance, Rsub is high, the isolation L1
nMOS
becomes very poor at frequencies higher than 10 GHz. Reference
Planes
This is because the common node of Cjs and Cjd is
floating, and Cjs and Cjd couple the signal between the
VC
source and drain nodes. However the switch isolation can
be greatly improved by adding an inductor between the (a)
source and drain nodes, which resonates with the switch
capacitance ((Cjs × Cjd )/(Cjs + Cjd ) + Cs ) at the desired
frequency. A similar resonating technique was also used Port1

Reference
Planes
Substrate Contact
Rsub Rsub Resistance
L1 VC L2 240 µm L2 L2
LIN
Port 1 RG RG Port 2
Port2 Port3

p n-epi nMOS
2 µm L1 L1
SPST
6 µm 20 µm 50 µm
250 µm
Deep
p- Trench 10 µm V C1 VC2
13.5 Ω-cm Rb
(b)

Fig. 3. Cross sectional view of the SPST switch. Fig. 4. Micrograph of the CMOS (a) SPST and (b) SPDT switches.

570
 0.0 0 0.0 0
Meas.
Sim
-2.0 -2.0
Insertion Loss (dB)

Return Loss (dB)

Insertion Loss (dB)

Return Loss (dB)

-10 -10
I.L. = 1.8 dB
-4.0 R.L. = 20 dB -4.0
S11
@ 35 GHz
-20 S11 -20
-6.0 -6.0 I.L. = 2.2 dB
Meas. R.L. = 21 dB
Sim @ 35 GHz
S22
-8.0 -30 -8.0 -30
25 30 35 40 45 25 30 35 40 45
Frequency (GHz) Frequency (GHz)

Fig. 5. Simulated and measured insertion loss and return loss of the Fig. 7. Simulated and measured insertion loss and return loss of the
SPST switch. SPDT switch.

0 0
Meas.
Sim. Rb = 2 K Ω Isol. > 30 dB @ 34-39 GHz
Sim. Rb = 500 Ω
-10 -10
Meas.
Isolation (dB)

Isolation (dB)
Sim. (Rb = 2 KΩ)
-20 -20

-30 -30

Isol. > 25 dB @ 34-42 GHz

-40 -40
25 30 35 40 45 25 30 35 40 45
Frequency (GHz) Frequency (GHz)

Fig. 6. Simulated and measured isolation of the SPST switch. Fig. 8. Simulated and measured isolation of the SPDT switch.

The resonant inductors (L1 =380 pH, L2 =340 pH) are a meander line inductor, LIN . The total chip size of the
connected between the source and drain to increase the SPST and SPDT is 115×240 µm2 and 250×240 µm2 , re-
isolation. L1 and L2 have different sizes and resonate spectively, excluding pads. All inductors and interconnect-
with the series capacitances at two different frequencies ing lines were modeled using full-wave EM simulations
(34 GHz and 36 GHz) to increase the total isolation (Sonnet1 ). For the CMOS transistors, the CMOS BSIM4v2
bandwidth. Two switches are used in order to result in model provided by the IBM 8HP design kit was used.
high isolation, low insertion loss and reasonable values
for the resonating inductors. III. S IMULATION AND M EASUREMENTS
The nMOS transistors are separated 50 µm away for A. Small Signal Results
a isolation between the junctions (Fig. 3). Because the The CMOS switches were measured on-chip with Agi-
substrate contacts have a high resistance, the substrate lent E8364B network analyzer using SOLT calibration to
resistance, Rb between the junctions of the two nMOS the probe tips. The pad transitions are deembeded using
transistors has to be as high as possible. To increase Rb , measured back-to-back transition (0.4 dB loss at 35 GHz).
the nMOS transistors are surrounded by a isolation moat Fig. 5 presents the measured insertion loss of the SPST
and deep trenches. The isolation moat and deep trench switch. The measured insertion loss is 1.8 dB at 35 GHz
have a thickness of 2 µm and 6 µm, respectively, and also with a return loss of 20 dB, and each nMOS transistor
prevent the nMOS transistors from latch-up and coupling switch accounts for 0.95 dB loss.
with other circuits around the switch. Fig. 6 shows the measured and simulated isolation of
The SPDT switch are implemented using two SPST the SPST switch. Because there is no deterministic way
switches, and the chip photos are shown in Fig. 4. The
shunt capacitance of the reactive T-junction is matched by 1 Sonnet, ver. 10.53, Sonnet Software Inc., Syracuse, NY, 1986-2005.

571
 0.0
@ 36 GHz
-2.0
Insertion Loss (dB)
-4.0 SPST
SPDT
-6.0
-8.0
-15 -10 -5 0 5 10 15 20
Input Power (dBm)
Fig. 9. Measured power handling of the SPST and SPDT switches.
for calculating the substrate resistance, Rb , the switch is
simulated with Rb of 2 KΩ and 500 Ω. The measured
isolation is greater than 25 dB at 34−42 GHz and proves
that the signal does not couple much through the substrate
(Rb ). The measured insertion loss and return loss of the
SPDT switch are shown in Fig. 7. The insertion loss and
return loss are 2.2 dB and 21 dB, respectively, at 35 GHz.
The isolation is >30 dB at 34−39 GHz and >25 dB at
33−43 GHz (Fig. 8).
B. Power Handling
Fig. 9 shows the measured insertion loss and isolation
of the SPST and SPDT switches versus the input power
at 36 GHz. The insertion loss of the SPST switch does
not compress even with a input power of 22 dBm because
the junction diode cannot be forward biased due to the
high substrate contact resistance. Also, the input P1dB
of the SPDT is about 23 dBm. The insertion loss of the
SPDT switch compresses because the isolation decreases
decreases when the input power is increased. This is
because the voltage drop across the drain and source
node (vds ) increases with higher input power. When the
nMOS switch is off, it is self-biased by the gate-source
voltage (vgs ) because the gate voltage is bootstrapped by
source/drain voltages and vgs ≈ vds /2. The self-biasing
occurs at a higher input power for the SPDT design since
the SPDT switch has a lower drain node voltage than the
SPST switch due to its lower impedance. The SPDT switch
always has a 50 Ω input impedance, but the SPST switch
has a high input impedance when the switch is off. For
the SPDT switch, the isolation is better than 25 dB up to
Pin =16 dBm.
As a Tx switch, the P1dB of the SPDT switch is
23 dBm, which is the highest power handling of any Ka-
band CMOS switch to-date. However, such a switch is
not suitable as an Rx switch since the isolation suffers
at high input powers. Therefore, for a T/R switch, it will
0
TABLE I
P ERFORMANCE S UMMARY OF T HE S WITCHES .
35 GHz I.L. R.L. Isol. P1dB
-10
SPST 1.8 dB 20 dB >30 dB >22 dBm
Isolation (dB)
SPDT 2.2 dB 21 dB >30 dB 23 dBm
-20 SPDT [8] Typ. 2.0 dB 18 dB 28 dB 14 dBm
-30 be best to use the high substrate resistance switch for the
Tx path, and a conventional switch for the Rx path. The
-40
measured performance of the SPST and SPDT switches are
summarized and compared with a commercially available
PHEMT SPDT switches in Table I.
IV. C ONCLUSION
Ka-band SPST and SPDT CMOS switches are devel-
oped using a 0.13 µm BiCMOS process. A high substrate
contact resistance is used to minimize the insertion loss
and improve linearity. The SPST/SPDT switches have a
insertion loss of 1.8 dB/2.2 dB, respectively, and input
P1dB of greater than 22 dBm. Two parallel resonant
networks result in an SPDT switch with an isolation
greater than 30 dB over a 15% bandwidth (34−39 GHz).
ACKNOWLEDGMENT
The authors thank Alfred Hung and Ed Viveiros at the
US Army Research Laboratories for their supporting the
research, and Michael Chang at the University of Michigan
for his valuable comments.
R EFERENCES
[1] Z. Li, H. Yoon, F.-J. Huang, , and K. K. O, “5.8 GHz CMOS T/R
switches with high and low substrate resistances in a 0.18 µm CMOS
process,” IEEE Microwave and Wireless Components Letters, vol. 13,
pp. 1–3, Jan. 2003.
[2] T. Ohnakado, S. Yamakawa, T. Murakami, A. Furukawa,
E. Taniguchi, H. Ueda, N. Suematsu, and T. Oomori, “21.5-dBm
power-handling 5-GHz transmit/receive CMOS switch realized by
voltage division effect of stacked transistor configuration with
depletion-layer-extended transistors (DETs),” IEEE Journal of Solid-
State Circuits, vol. 39, pp. 577–584, Apr. 2004.
[3] N. A. Talwalkar, C. P. Yue, H. Gan, and S. S. Wong, “Integrated
CMOS transmit-receive switch using LC-tuned substrate bias for
2.4 GHz and 5.2 GHz applications,” IEEE Journal of Solid-State
Circuits, vol. 39, pp. 863–870, Jun. 2004.
[4] M.-C. Yeh, Z.-M. Tsai, R.-C. Liu, K.-Y. Lin, Y.-T. Chang, and
H. Wang, “Design and analysis for a miniature CMOS SPDT switch
using body-floating technique to improve power performance,” IEEE
Transactions on Microwave Theory and Techniques, vol. 54, pp. 31–
39, Jan. 2006.
[5] Z. Li and K. K. O, “A 15-GHz integrated CMOS switch with 21.5-
dBm IP1dB and 1.8-dB insertion loss,” in VLSI Circuit Symposium
Digest of Technical Papers, Honolulu, HI, Jun. 2004, pp. 366–367.
[6] J. Han and H. Shin, “A scalable model for the substrate resistance
in multi-finger RF MOSFETs,” in IEEE MTT-S International Mi-
crowave Symposium Digest, Philadelphia, PA, Jun. 2003, pp. 2105–
2108.
[7] H. Takasu, F. Sasaki, H. Kawasaki, H. Tokuda, and S. Kamihashi,
“W-band SPST transistor switches,” Microwave and Guided Wave
Letters, vol. 6, pp. 315–316, Sep. 1996.
[8] Agilent AMMC-2008 DC−50 GHz SPDT switch, Agilent Technolo-
gies, Data sheet.
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