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34. Lecture-34 October 05-2020_MA_2020-2021
34. Lecture-34 October 05-2020_MA_2020-2021
Example for
input voltage
of 6.8 V
Successive Approximation Method
Example for input voltage of 5.4 V with 4 bit ADC having range of
10 V. Calculate the digital bit value and decoded output value.
Successive Approximation Method
Example for input voltage of 5.4 V with 4 bit ADC having range of
10 V.
L L
R ADC n
Nq 1 2 1
1
Quantizati on Error R DAC
2
Analog-to-Digital Conversion
A continuous voltage signal is to be converted into its digital
counterpart using an analog-to-digital converter. The maximum
voltage range is 30 V. The ADC has a 12-bit capacity. Determine
(a) number of quantization levels, (4096)
(b) resolution, (0.014652 volts) and
(c) the quantization error for this ADC. (0.007326)
Analog-to-Digital Conversion for
Practice
A continuous voltage signal is to be converted into its digital
counterpart using an analog-to-digital converter. The maximum
voltage range is ±30 V. The ADC has a 15-bit capacity. Determine
(a) number of quantization levels,
(b) resolution,
(c) the spacing of each quantization level, and the quantization
error for this ADC.
Analog-to-Digital Conversion
A voltage signal with a range of 0 to 115 V is to be converted by
means of an ADC. Determine the minimum number of bits
required to obtain a quantization error of
(a) 5 V maximum,
(b) 1 V maximum,
(c) 0.1 V maximum.
L L
R ADC n
Nq 1 2 1
1
Quantizati on Error R DAC
2
Analog-to-Digital Conversion
A voltage signal with a range of 0 to 115 V is to be converted by
means of an ADC. Determine the minimum number of bits
required to obtain a quantization error of
(a) 5 V maximum, (3.64)
(b) 1 V maximum, (5.87)
(c) 0.1 V maximum. (9.17)
Analog-to-Digital Conversion
A voltage signal with a range of 0 to 115 V is to be converted by
means of an ADC. Determine the minimum number of bits
required to obtain a quantization error of
(a) 5 V maximum, (3.64) n = 4
(b) 1 V maximum, (5.87) n = 6
(c) 0.1 V maximum. (9.17) n = 10
Digital-to-Analog Conversion
Decoding:
Decoding is accomplished by transferring the
digital value from the computer to a binary
register that controls a reference voltage source.
Each successive bit in the register controls half
the voltage of the preceding bit, so that the level
of the output voltage is determined by the status
of the bits in the register.
The output voltage is given by:
E0 Eref 0.5B1 0.25B2 0.125B3 ..... (2n )1 Bn
Digital-to-Analog Conversion
Data Holding:
Objective is to approximate the envelope formed
by the data series.
Data holding devices are classified according to
the order of the extrapolation calculation used to
determine the voltage output during sampling
intervals.
Zero-order hold
First-order hold
Digital-to-Analog Conversion
Zero-order Holding:
It is the most common extrapolator.
The output voltage between the sampling
instants is a sequence of step signals
The voltage function during the sampling interval
is constant and can be expressed very simply as:
E(t) = E0
where,E(t) = voltage as a function of time t
during the sampling interval (V),
E0 = voltage output from the decoding
step
Digital-to-Analog Conversion
First-order Holding:
Less common than the zero-order, but usually
approximates the envelope of the sampled data
values more closely.
The voltage function E(t) during the sampling
interval changes with a constant slope
determined by the two preceding E0 values.
Digital-to-Analog Conversion
First-order Holding:
The voltage function during the sampling interval can
be expressed as:
E(t) = E0 + t
where, = rate of change of E(t),
E0 = voltage output from the decoding step at
the start of the sampling interval, V
t = time in sec.
Digital-to-Analog Conversion
First-order Holding:
The value of is computed each sampling interval
as: E E ( τ)
α 0 0
τ
where,E0 = voltage output from the decoding step at
the start of the sampling interval, V
= time interval between sampling instants
(sec.)
E0(-) = value of E0 from the preceding
sampling instant (removed backward in
time by , V)
Data Holding Step in DAC: (a) Zero-
Order Hold and (b) First-Order Hold
(a) (b)