COIMBATORE INSTITUTE OF TECHNOLOGY, COIMBATORE-641 014.

(Government Aided Autonomous Institution)

B.E. EEE Sec.2 Sem I - DIGITAL ELECTRONICS 23 EE 213
Questions & Problems with Answers - Unit 3 GATE-LEVEL MINIMIZATION

S.
No.
Questions / Problems with Answers (Short Version)
Why Gate level minimization is required in the design task of Digital Circuits ?
The complexity of the digital logic circuits that implement a Boolean function is directly related to
the complexity of the algebraic expression from which the function is implemented. Boolean expressions may
1 be simplified by algebraic means. The Karnough map method may be regarded as a Pictorial form of a truth
table and provides a simple, straightforward procedure for minimizing Boolean functions. In turn the Level
and complexity of Digital Logic Circuits is highly reduced.

How the minterms are arranged in the 3 variable Karnough map? Why?
The minterms are arranged, not in a binary sequence, but in a sequence similar to the Gray code . The
characteristic of this sequence is that only one bit changes in value from one adjacent column to the next.
2
Any two adjacent squares in the map differ by only one variable, which is primed in one square and un-primed
in the other. Hence it is easy to couple the adjacent squares, so as to minimize the logic equation.

Find the simplified Expression for the given logical sum of product
terms using the K Map F (x, y, z) = Σ (2, 3, 4, 5).

3 F = x'y + xy'

Find the simplified Expression for the given logical sum of product terms using the K Map F (x, y, z) = Σ
(3, 4, 6,7)

F = yz + xy'z' + xyzy'
4 = yz + xz' (y'+ y) = yz + xz'
The simplified function then becomes F = yz + xz'

In K-map what do the One square, Two adjacent squares, Four adjacent squares, and Eight adjacent
squares represent a term with how many literals?
One square represents one minterm, giving a term with three literals.
5 Two adjacent squares represent a term with two literals.
Four adjacent squares represent a term with one literal.
Eight adjacent squares encompass the entire map and produce a function that is always equal to 1.

Find the simplified Expression for the given logical sum of product terms using the K Map F (x, y, z) =
Σ (0, 2, 4, 5, 6).
F = y'z' + yz' + xy'
6 = z'(y' +y) + xy' = z' + xy'
The simplified function is F = z' + xy'

Simplify the Boolean function expressed in sum-of-minterms form as

F (A, B, C) = Σ (1, 2, 3, 5, 7).

The function has a total of five minterms, as indicated by the five 1’s
7 in the map.
Foue squares are coupled. In this big square the variable C alone is
not changing in row and column.
It can be simplified, as shown in the map, to an expression with only
two terms: F = C + A'B.
 Simplify the Boolean function F (w, x, y, z) = Σ (0, 1, 2, 4, 5, 6, 8, 9,
12, 13, 14).

F = y' + [w'y'z' + w'yz‘] + [xy'z' + xyz']

8
= y' + w'z'(y'+y) + xz'(y'+y)
= y' + w'z' + xz'
Thus the simplified function is
F = y' + w'z' + xz'

Simplify the Boolean function F = A'B'C' + B'CD' + A'BCD' + AB'C'

K map is drawn in a surface with top and bottom edges, as well as left
and right edges, touching one another.
9
The two left-hand 1’s in the top row are combined with the two 1’s in
the bottom row to give the term B'C'.
The remaining 1 may be combined in a two square area to give the
term A'CD'. The simplified function is
F = A'B'C' + B'CD' + A'BCD' + AB'C' = B'D' + B'C' + A'CD '
What are the steps to form a K- map for 5 variables ?
A 5 variable K-map contains 2^5 = 32 cells and it is used to simplify any 5 variable logic
expression (A,B, C,D, E).
In order to construct a 5 variable K- map, two number of 4 variable K-maps with 16 cells
10
each can be used adjacently.
The first K-map is kept for A=0 and the second one is kept for A=1. Every cell in one
map is adjacent to the corresponding cell in the other map. Because it differs by a single variable.

Simplify the Boolean Function F (A, B,C, D, E) = Σ m(0, 2, 4, 6, 9, 11, 13, 15, 16, 17, 18, 19, 25, 27, 29,
31)
Solution:-
A K- map for 5 variables (A,B,C,D,E) is
plotted. The value 1 is placed in the appropriate
squares as per the respective digits of minterms
of the given function.The group of 1s have been
formed as pairs, quads and octets… etc.
11
There are 4 quads in this K map for 5 variables
Hence the given Boolean Function
F (A, B,C, D, E) = Σ m(0, 2, 4, 6, 9, 11, 13, 15,
16, 17, 18, 19, 25, 27, 29, 31)
is simplified as
F (A, B,C, D, E) = A'B'E' + AB'C ' + A'BE + ABE = A'B'E' + AB'C ' + BE (A'+A)
= A'B'E' + AB'C ' + BE
Simplify the Boolean Function F (A, B,C, D, E) = Σ m(0, 1, 4, 5, 6, 11, 12, 14, 16, 20, 22, 28, 30, 31)
The Minterms are plotted in a 5 variable K-map. These Minterms are grouped as shown in the map.

12

The minimized SOP function is given by

F (A, B,C, D, E) = CE' + A'B'D' +
ABCD +B'D'E' + A'BC'DE
 Find all prime implicants for: G(v,w,x,y,z) =
Σm(0,1,2,4,5,6,7,8,10,16,17,18,20, 21,24,25,26,27,29)

13 Σm = w’y’+x’z’+v’w’x+vy’z+vwx’
ΣC = Σm +v’w’z’

Simplify the Boolean function F (A, B, C, D) = Σ (0, 1,

2, 5, 8, 9, 10) into
(a) Sum-of-Products form and (b) Product-of-Sums form:

The 1’s marked in the map of Fig. represent all the

minterms of the function. The squares marked with
0’s represent the minterms not included in F and
therefore denote the complement of F .
Combining the squares with 1’s gives the simplified
function in sum-of-products form:
14
F (A, B, C, D) = Σ (0,1, 2, 5, 8, 9,10)
= B'D' + B'C' + A'C'D
Applying DeMorgan’s theorem (by taking the
dual and complementing each Literal),
we obtain the simplified function in Product of Sums form:

F = (A' + B')(C' + D')(B' + D)

In sum-of-minterms form,
this function is expressed as F (x, y, z) = Σ (1, 3, 4, 6) In product-of-
Maxterms form, it is expressed as F (x, y, z) = Π (0, 2, 5, 7).
Simplify this equations by K map method.
The 1’s of the function represent the minterms and the 0’s represent
the maxterms. The map for this function is shown. Once the 1’s and
0’s are marked, the function can be simplified in either one of the
15 standard forms.
For the Sum of Products, we combine the 1’s to obtain F = x'z + xz'
which shows that the Exclusive-OR function.
For the Product of Sums, we combine the 0’s to obtain the
simplified complemented function F' = xz + x'z'
This is the complement of the ExOR function (Equivalence
function).

What is Don’t Care condition in minterms of K map ?

16 Functions that have unspecified outputs for some input combinations are called incompletely specified
functions. In most applications, we simply don’t care what value is assumed by the function for the
unspecified minterms.
For this reason, it is customary to call the unspecified minterms of a function don’t-care
conditions . These don’t-care conditions can be used on a map to provide further simplification of the
Boolean expression.

How to indicate the Don’t Care condition in K map? Shall it be taken into account for Function
simplification process ?
 An X inside a square in the map indicates that we don’t care whether the value is 0 or 1, assigned to F for the
17 particular minterm.
In choosing adjacent squares to simplify the function in a map, the don’t-care minterms may be assumed to
be either 0 or 1. When simplifying the function, we can choose to include each don’t-care minterm with
either the 1’s or the 0’s, depending on which combination gives the simplest expression.

Simplify the Boolean function F (w, x, y, z) = Σ (1, 3, 7, 11, 15), which has the don’t-care conditions d (w, x,
y, z) = Σ (0, 2, 5).
The minterms of F are marked by 1’s, those of d are marked by X’s, and
the remaining squares are filled with 0’s. The term yz covers the four
minterms in the third column. The remaining minterm, m1, can be
combined with minterm m3 to give the three-literal term w'x'z. However,
by including one or two adjacent X’s we can combine four adjacent
squares to give a two-literal term w'x'.

Don’t-care minterms 0 and 2 are included with the 1’s, resulting in the
18
simplified function.
F = yz + w'x'

In Fig. (b), the term yz covers the four minterms in the third column.
Don’t-care minterm 5 is included with the 1’s. A quad is being formed
which gives w'z. The simplified function is now
F = yz + w'z
The don’t-care minterms marked with X’s in the map are considered as
being either 0 or 1. The choice between 0 and 1 is made depending on the
way the incompletely specified function is simplified.
Once the choice is made, the simplified function will be obtained
by combining some of “unspecified sum of minterms (X)” can be chosen
to be included with the 1’s.
Simplify the Boolean function F (w, x, y, z) = Σ (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14).

19

Simplify the following Boolean function into (a) sum-of-products form and
(b) product-of-sums form: F (A, B, C, D) = Σ (0, 1, 2, 5, 8, 9, 10)

20
 Implement the following Boolean function with NAND gates:
F (x, y, z) = Σ (1, 2, 3, 4, 5, 7) Give the two-level NAND implementation for the simplified expression.
21
 Figure shows the K map for a four-variable problem. Simplify process to reduce the K map to an SOP
expression.

22
Step 1 (construct a K map from the problem truth table) has been completed.
The squares are numbered for convenience in identifying each loop.
Step 2 Square 4 is the only square containing a 1 that is not adjacent to any
other 1. It is looped and is referred to as loop 4.
Step 3 Square 15 is adjacent only to square 11. This pair is looped and referred
to as loop 11, 15.
Step 4 There are no octets.
Step 5 Squares 6, 7, 10, and 11 form a quad. This quad is looped (loop 6, 7,
10, 11). Note that square 11 is used again, even though it was part of
loop 11, 15.
Step 6 All 1s have already been looped.
Step 7 Each loop generates a term in the expression for X. Loop 4 is
simply
A BCD. Loop 11, 15 is ACD (the B variable is eliminated). Loop 6, 7,
10, 11 is BD (A and C are eliminated).

Simplify the K map given in Figure.

Step 1 (construct a K map from the problem truth table) has been completed.
The squares are numbered for convenience in identifying each loop.
Step 2 There are no isolated 1s.
Step 3 The 1 in square 3 is adjacent only to the 1 in square 7. Looping this
pair (loop 3, 7) produces the term ACD.
Step 4 There are no octets.
23 Step 5 There are two quads. Squares 5, 6, 7, and 8 form one quad. Looping
this quad produces the term AB. The second quad is made up of
squares 5, 6, 9, and 10. This quad is looped because it contains two
squares that have not been looped previously. Looping this quad produces
BC.
Step 6 All 1s have already been looped.
Step 7 The terms generated by the three loops are ORed together
to obtain
the expression for X.

exAmple 4-exAmple
Simplify the K map given in Figure.
Step 1 (construct a K map from the problem truth table) has been completed.
The squares are numbered for convenience in identifying each loop.
Step 2 There are no isolated 1s.
Step 3 The 1 in square 2 is adjacent only to the 1 in square 6. This pair
is looped to produce A CD. Similarly, square 9 is adjacent only to
square 10. Looping this pair produces ABC. Likewise, loop 7, 8 and
24 loop 11, 15 produce the terms ABC and ACD, respectively.
Step 4 There are no octets.
Step 5 There is one quad formed by squares 6, 7, 10, and 11. This quad, however,
is not looped because all the 1s in the quad have been included
in other loops.
Step 6 All 1s have already been looped.
Step 7 The expression for X is shown.
 Simplify the Boolean function f = ABCD' + A'B'C + AB'C' + B'CD' using a K-map.

25

Plot two different K-maps, as shown in for determining the SOP form and
map used for determining the POS form of the function/(A, B, C, D) =
Σ m(0,2,4,8,10,14).

26

Compare the minimized SOP forms of the function/(A, B, C, D) = Σ m (3, 6, 12, 14, 15)+d(l, 5, 7, 9, 13) by
grouping (a) Is and (b) Os.

27
 Simpify the following Boolean Equations using Karnaugh Maps.

28

Simplify the logic function F in the two following cases: a) F(A,B,C) = Σ m(1, 3, 4, 7);
b) F(A,B,C) = Σ m(1, 3, 4, 7) + x (2, 5), where the don’t care terms are represented by x.

The minimal expressions of the function F may

be obtained from the Karnaugh maps
represented in Figures 2.31 and 2.32.
29
It should be noted that a don’t care term is taken
into account only if it can contribute to the
simplification of the logic function.
 Propose a circuit that implements the following circuit:
F(A,B,C,D) = Σ m(0, 2, 3, 4, 6, 7, 10, 11)
G(A,B,C,D) = Σ m(0, 4, 8, 9, 10, 11, 12, 13)
Taking into account the common terms (see the Karnaugh maps shown
in Figures 2.33 and 2.34), we can obtain the circuit in Figure 2.35 that
consists of six logic gates with a total of 16 inputs.
By independently simplifying the two functions, we arrive at:
F(A,B,C,D) = A' · C + A' · D' + B' · C
G(A,B,C,D) = A · C' + C' · D' + A · B'
In this case, eight logic gates with a total of 18 inputs are needed for the
implementation of the functions F and G.
30

What are Universal Logic Operations ? Give reasons.

Accordingly, it is possible to design any arbitrary logic circuit using either only NAND or only NOR
logic gates. These two logic operations are also known as UNIVERSAL LOGIC OPERATIONS since one
may not need any other logic gates for implementing a function.
Besides, NAND and NOR gates both have a SMALLER PROPAGATION DELAY when compared to
31 other logic gates.
NAND and NOR operations are DUAL OF EACH OTHER. This simplification follows directly
from Boolean theorems. Typically, the DUAL OF A BOOLEAN EXPRESSION is obtained by replacing
each of the ANDs with ORs, ORs with ANDs, 0s with 1s, and 1s with 0s.
XOR and XNOR logic functions are also expressible in either a SOP or a POS form, all of the logic functions
may be generated using either only NAND or only NOR logic.
Mention 2 steps to realize the NAND – NAND implementation process.
1. The function is complemented first by complementing each of the AND terms and replacing each of the
32 OR operations with an AND operation.
2. The complement function is then complemented once again to recover the original function.
How the Level of Gates in the logic circuit is classified?
The gate level containing the logic gate that produces the function output is referred to as the FIRST
33 LEVEL of a logic circuit. The preceding gate level is referred to as the SECOND LEVEL, and the level
preceding the second level is referred to as the THIRD LEVEL, and so on.
In a given a multilevel NAND-NAND circuit, when a complemented and un-complemented output
appears in the final logical expression?
Input to NAND gate in odd-numbered levels, if it has not gone through a preceding level of NAND gate,
34
appears complemented in the final logical expression.
Inputs to NAND gate at even-numbered levels, on the other hand, appear uncomplemented in the final logical
expression.
Implement the function given by f (A, B,C) = Σm(l, 2,3,5,6), using only NAND logic gates,
Since,

Therefore,

35
The final circuit, therefore, is obtained as shown in Figure. The logic
Level 1
circuit requires Three 2-input NAND gates and one 3-input NAND gate
provided that all inputs are also available in complemented form. Level 2
f (A, B,C) = Σm(l, 2,3,5,6) =
 Mention the design steps required for the NOR-only implementation of SOP expressions.
1. Plot the given SOP function on a K-map.
36 2. Obtain the complemented function by grouping only the 0s.
3. Use DeMorgan's theorem to expand each of the resulting AND terms.
4. Complement the complemented function.
In a given a multilevel NOR-NOR circuit, when a complemented and un-complemented output appears in
the final logical expression?
37 Input to NOR gate in odd-numbered levels, if it has not gone through a preceding level of NOR gate,
appears complemented in the final Boolean expression. Input to NOR gate in even-numbered levels appear
simply as uncomplemented in the final logical expression.
Implement the following logical function using only NOR gates.
f(A,B,C,D) = Σm(l, 5-9,12-14) The 4-variable K-map of Figure
shows the plotted minterms. By grouping all the 0s, we obtain

38

The NOR-only circuit is, therefore,

obtained as shown in Figure. It
requires one 2-input NOR gate and
three 3-input NOR gates, provided f = [(B+C')'+ (A+C+D)' + (A'+C'+D')']'
the inputs are also available in their
complemented form.
Determine the Boolean expression for the output of the multilevel logic circuit shown in Figure
Inputs I, B and G are considered as complemented.

This is a 4-level circuit. Next, we identify each of the logic gates with
its corresponding gate level. The Boolean operations associated with
these seven logic gates are as follows:
(a) Gate 1 (in level 1) performs an AND operation where input I is
considered complemented.
(b) Gates 2 and 3 (in level 2) respectively perform OR and AND
39 operations.
(c) Gates 4 and 5 (in level 3) respectively perform OR and AND operations, and the inputs B and G are
considered complemented.
(d) Gates 6 and 7 (in level 4) perform OR and AND operations respectively
Therefore,

This particular form is conceptually acceptable since its implementation requires us to have one 4-input OR
gate and one 6-input AND gate. If we were to expand it instead to its SOP form, for example, its
implementation will require us to have four 6-input AND gates and one 4-input OR gate.
The expression for output of this logic circuit may be determined also by starting at level 4
and then by repeatedly applying DeMorgan's theorem, when needed, to determine respective outputs.
What parameters are to be taken into account for the design of Multi Level Digital Circuits?

40 The design of Multi-Level Circuits is based on the factorization and decomposition of logic functions which
are taken in their minimal form. In practice, the use of supplementary levels in a circuit helps to
reduce the maximum number of inputs for logic gates to the value permitted by the manufacturing technology.
Implement the five-variable function,: F(A,B,C,D,E) = (A · C) + (A ·
D) + (B · C) + (B · D) + E' as logic circuits using multi level gates

F(A,B,C,D,E), expressed in the sum-of-product form. This function

can be implemented using four 2-input AND gates or one 5-input
41 OR gate as shown in Figure
Level 1
Upon factorizing, we can also arrive at: F(A,B,C,D,E) =
(A + B)(C + D) + E'
Level 2
 As a result, the function F(A,B,C,D,E) can be implemented using
three 2-input OR gates and one 2-input AND gate, as illustrated in
Figure.
This approach, in addition to reducing the number
of logic gates, makes it possible to improve the fan-in of logic gates. Level 1

Level 2

Level 3

Mention the norms for transformation of logic gate circuits into circuit with only NAND gates.
(1) By replacing the AND gates with NAND gates,
42 adding inverters at the OR gate inputs and by inserting
inverters wherever necessary to correct for the effect of
non-compensated inversions, (2) By replacing all OR gates with input inverters to NAND gates

Implement the four variable function,: F(A,B,C,D) = (A + B') . ((C·D') + (C'· D)) as logic circuits and
transform the logic circuits into circuit with only NAND gates, using multi level gates
Consider the following logic function of four variables A, B, C and D:
F(A,B,C,D) = (A + B') . ((C·D') + (C'· D)) This function may be
implemented by using AND and OR gates, as illustrated in
Figure(a). By applying the transformations (1) and (2), we can Level 2
Level 1
obtain the circuit shown in Figure(b). Level 3
43
The NAND gate based circuit shown in Figure (c) respectively.

Level 2
Level 2
Level 3
Level 3 Level 1 Level 4 Level 1

Implement the four variable function,: G(A,B,C,D) = (A · B · C') + (A · D ') + (B '· D ') + (C ' · D ') as
logic circuits and transform the logic circuits into circuit with only NAND gates, using multi level gates
Let us consider another function G of four variables A, B,
C and D, defined by:
G = (A · B · C') + (A · D ') + (B '· D ') + (C ' · D ') Level 2
we first observe that: G = [A + (B · C')'] . ((B · C')) + D')
and subsequently derive the circuit built up of AND and OR Level 3 Level 1
gates, as illustrated in Figure.
44 Using transformations based on DeMorgan’s theorems, we can obtain the equivalent circuit in Figure.
The NAND gate based circuit represented in Figure.

Level 4
Level 2
Level 2 Level 3
Level Level Level 5 Level 1
3 1

Mention the norms for transformation of logic gate circuits into circuit with only NOR gates.
(1) By replacing the OR gates by NOR gates; by adding input
inverters to the AND gates and by inserting inverters wherever
45
necessary to correct for the effect of non-compensated inversions;
(2) By replacing all AND gates that have input inverters with NOR gates.(Figure).
 Implement the four variable function,: F(A,B,C,D) = (A + B') ((C · D') + (C'· D)) as logic circuits and
transform the logic circuits into circuit with only NAND gates, using
multi level gates
The implementation of this function using AND and OR gates is
illustrated in Figure(a). Level 2
For the NOR gate based implementation, the first step is Level 1
Level 3
transformation which results in the circuit shown in Figure (b).
Then it is converted to the NOR gate based circuit as shown
46
in Figure (c).

Level 2
Level 2
Level 3 Level 1
Level 3 Level 1

Use only two-input NOR gates to implement the following function of four variables: G = (A · B · C') +
(A · D') + (B' · D') + (C' · D').
We can have G = [(A + (B · C')'] [(B · C') + D'] Level 3
we can derive the circuit shown in Figure (a) or the
equivalent circuit shown in Figure (b). Level 2
The NOR-gate based circuit corresponding to the
function G is illustrated in Figure (c). Level 1
Each product-of-sums logic expression corresponds to a
circuit consisting of OR and AND gates or to a NOR gate
47 based circuit.
Level 3
Level 3

Level 2
Level 2
Level 4 Level 1
Level 1