Chapter 5

Flip-Flops, Registers, Counters, and

a Simple Processor

Fundamentals of Digital Logic Department of Electrical Engineering

 Sequential Circuits

• Difference b/w combinational & sequential circuits

Combinational outputs
inputs
Circuit

inputs outputs
Combinational
Circuit
Memory
Elements

Fundamentals of Digital Logic Department of Electrical Engineering

 Sequential Circuits

Motivation

Set
Sensor
Memory On Off
Alarm
element
Reset

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 6.1 Basic Latch
R S R Qa Qb
Qa
0 0 0/1 1/0 (no change)
0 1 0 1
1 0 1 0
Qb 1 1 0 0
S

(a) Circuit (b) Characteristic Table

Fundamentals of Digital Logic Department of Electrical Engineering

 6.2 Gated SR Latch

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 Basic SR Latch with NAND Gates

S S R Qa Qb
Q
1 1 0/1 1/0 (no change)
1 0 0 1
0 1 1 0
0 0 1 1

Q
R (b) Characteristic Table

Fundamentals of Digital Logic Department of Electrical Engineering

 6.2.1 Gated SR Latch with NAND Gates

S
Clk S R Q(t+1)
Q
0 x x Q(t) (no change)
1 0 0 Q(t) (no change)
Clk 1 0 1 0
1 1 0 1
1 1 1 x
Q
(b) Characteristic Table
R

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 6.3 Gated D Latch

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 6.3.1 Effects of Propagation Delays

t su
th

Clk

Figure 7.9. Setup and hold times.

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 6.4.1 Master Slave D Flip Flop
Master Slave
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q D Q

(a) Circuit
(c) Graphical symbol

Clock

Qm

Q = Qs

(b) Timing diagram

Fundamentals of Digital Logic Department of Electrical Engineering

 6.4.2 Edge Triggered D Flip-Flop

1 P3 Clk =0
P1=P2=High (no change state)
P3=D, P4=D’

P1
2 Clk =0>>>>1
5 Q
P1= D’, P2= D
Q = D and Q’ = D’
Clock

P2 6 Q
3

D Q

Clock Q
4 P4
D

(a) Circuit (b) Graphical symbol

Fundamentals of Digital Logic Department of Electrical Engineering

 6.4.2 Edge Triggered D Flip-Flop

Clk =0
P1=P2=High (no change state)
P3=D, P4=D’

Clk =0>>>>1
P1= D’, P2= D
Q = D and Q’ = D’

Fundamentals of Digital Logic Department of Electrical Engineering

 6.4.2 Edge Triggered D Flip-Flop

Clk =0
P1=P2=High (no change state)
P3=D, P4=D’

Clk =0>>>>1
P1= D’, P2= D
Q = D and Q’ = D’

Fundamentals of Digital Logic Department of Electrical Engineering

 6.4.2 Edge Triggered D Flip-Flop

Clk =0
P1=P2=High (no change state)
P3=D, P4=D’

Clk =0>>>>1
P1= D’, P2= D
Q = D and Q’ = D’

Fundamentals of Digital Logic Department of Electrical Engineering

 6.4.2 Edge Triggered D Flip-Flop

Clk =0
P1=P2=High (no change state)
P3=D, P4=D’

Clk =0>>>>1
P1= D’, P2= D
Q = D and Q’ = D’

Fundamentals of Digital Logic Department of Electrical Engineering

 Level Sensitive versus Edge Triggered Storage Element

D D Q Qa
Clock Clk Q Qa

D Q Qb

Q Qb

D Q Qc

Q Qc

(a) Circuit

Clock

D
Qa

Qb

Qc

(b) Timing diagram

Fundamentals of Digital Logic Department of Electrical Engineering
 6.4.3 D Flip-Flops with Clear & Preset

Fundamentals of Digital Logic Department of Electrical Engineering

 6.4.3 D Flip-Flops with Clear & Preset
Preset

D
Q
Clock

Clear

(a) Circuit

Preset

D Q

Clear

(b) Graphical symbol

Fundamentals of Digital Logic Department of Electrical Engineering

 6.5 T Flip-Flops

T Q(t + 1)
0 Q(t )

Q 1 Q(t )
D Q

T
Q Q (b) Truth table

Clock
T Q

(a) Circuit
Q

Clock (c) Graphical symbol

(d) Timing diagram

Fundamentals of Digital Logic Department of Electrical Engineering

 6.6 JK Flip-Flops

J
D Q Q
K Q Q

Clock

(a) Circuit

J K Q ( t + 1)
0 0 Q (t) J Q
0 1 0
1 0 1
K Q
1 1 Q (t )

(b) Truth table (c) Graphical symbol

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 6.8 Registers
Q1 Q2 Q3 Q4
In D Q D Q D Q D Q Out

Clock Q Q Q Q

(a) Circuit

In Q1 Q2 Q3 Q4 = Out
t0 1 0 0 0 0
t1 0 1 0 0 0
t2 1 0 1 0 0
t3 1 1 0 1 0
t4 1 1 1 0 1
t5 0 1 1 1 0
t6 0 0 1 1 1
t7 0 0 0 1 1
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 6.8 Registers
Parallel output

Q3 Q2 Q1 Q0

D Q D Q D Q D Q

Q Q Q Q

Serial Clock
input Shift/Load Parallel input
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 6.8 Registers

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 6.9 Counters

1 T Q T Q T Q

Clock Q Q Q

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 6 7 0

(b) Timing diagram

Fundamentals of Digital Logic Department of Electrical Engineering
 6.9 Counters

1 T Q T Q T Q

Clock Q Q Q

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 7 6 5 4 3 2 1 0

(b) Timing diagram

Fundamentals of Digital Logic Department of Electrical Engineering
 Designing Counters

A sequential circuit that goes through a prescribed sequence of

states upon the application of input pulses is called a counter.

Design Procedure

1. State Diagram (Showing Count Sequence)

2. Excitation Table for counter (Showing Present State, Next State & Flip-
-Flop Inputs)
3. In step 2, we need excitation tables for respective flip flops.

4. After finding the flip flop inputs, the logic expressions for flip flop inputs
are obtained.

5. The counter is implemented.

Fundamentals of Digital Logic Department of Electrical Engineering

 Designing Counters

Excitation Table for T Flip-Flops

Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0

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 6.9.2 Synchronous Counters

1 T Q T Q T Q T Q
Q0 Q1 Q2 Q3
Clock Q Q Q Q

(a) Circuit

Clock

Q0

Q1

Q2

Q3

Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

(b) Timing diagram

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 6.9.2 Synchronous Counters

Enable T Q T Q T Q T Q

Clock Q Q Q Q

Clear

Figure 7.23. Inclusion of Enable and Clear capability.

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 Synchronous Counters with D Flip-Flops
Excitation Table for D Flip-Flops Excitation Table for T Flip-Flops
Q(t) Q(t+1) D Q(t) Q(t+1) T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0

Excitation Table for SR Flip-Flops Excitation Table for JK Flip-Flops

Q(t) Q(t+1) S R Q(t) Q(t+1) J K
0 0 0 X 0 0 0 X
0 1 1 0 0 1 1 X
1 0 0 1 1 0 X 1
1 1 X 0 1 1 X 0

Fundamentals of Digital Logic Department of Electrical Engineering

 Synchronous Counters with D Flip-Flops

Enable D Q Q0
Q

D Q Q1
Q

D Q Q2
Q

D Q Q3
Q
Output
Clock carry

Fundamentals of Digital Logic Department of Electrical Engineering

 0
Enable D Q Q0
D0 1
Q

0
1 D Q Q1
D1
Q

0
1 D Q Q2
D2
Q

0
1 D Q Q3
D3
Q

Output
carry
Load
Clock
Figure 7.25. A counter with parallel-load capability.
 6.10 Counters with Synchronous/ Asynchronous reset

1 Enable
0 D0 Q0
0 D1 Q1
0 D2 Q2
Load
Clock
Clock

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1

(b) Timing diagram

Figure 7.27. A modulo-6 counter with synchronous reset.

Fundamentals of Digital Logic Department of Electrical Engineering
 6.10 Counters with Synchronous/ Asynchronous reset

1 T Q T Q T Q
Q0 Q1 Q2
Clock Q Q Q

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1 2

(b) Timing diagram

Figure 7.27. A modulo-6 counter with asynchronous reset.
Fundamentals of Digital Logic Department of Electrical Engineering
 6.11 Other Type of Counters (BCD Counter)

1 Enable
0 D0 Q0
0 D1 Q1
D2 Q2 BCD 0
0
0 D3 Q3

Load
Clock
Clock

Clear Enable
0 D0 Q0
0 D1 Q1
D2 Q2 BCD1
0
0 D3 Q3

Load
Clock

Fundamentals of Digital Logic Department of Electrical Engineering

 6.11 Other Type of Counters (Ring Counter)
Q0 Q1 Qn ” 1

Start

D Q D Q D Q

Q Q Q

Clock

(a) An n -bit ring counter

Q0 Q1 Q2 Q3

y0 y1 y2 y3

2-to-4 decoder
w1 w0 En

Q1 Q0
Clock Clock
Two-bit up-counter

Start Clear

(b) A four-bit ring counter

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 6.11 Other Type of Counters (Johnson Counter)

Q0 Q1 Qn – 1

D Q D Q D Q

Q Q Q

Reset
Clock

Fundamentals of Digital Logic Department of Electrical Engineering