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Chapter_1(DLD)
Chapter_1(DLD)
Chapter_1(DLD)
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Introduction (Chapter 1)
Variables & Functions, Inversion, Truth tables, Logic Gates & Networks, Boolean
Algebra, Synthesis using AND, OR & NOT gates, NAND & NOR logic networks,
Design Examples, Minimization of Karnaugh maps, Strategy of Minimization,
Minimization of POS, Multiple Output Circuits etc
Basic latch, Gated SR-Latch, Gated D-Latch, Master-Slave & Edge Triggered Flip-
Flops, T Flip-Flop, JK Flip-Flop, Registers, Counters, Reset Synchronization,
Other Type of Counters
Lab 25%
Theory 75%
Quizzes 10.00%
Home works 5.00%
Mid Term 22.5%
Final 37.5%
Group Size: 2
Individual Tasks
Simulation on Proteus
Hardware Implementation
Technology Evolution
Moore’s Law
Semiconductor Industry
Association (SIA)
Roadmap
Figure 1.1. A silicon wafer
(courtesy of Altera Corp.).
Utility
VDD
Drawbacks
Gnd
Advantages
Disadvantages
B=bn-1bn-2bn-3……..b2b1b0
V(B)=bn-1X2n-1+bn-2X2n-2…….. b1X21+b0X20
Dividing by 2 again
V/4=bn-1X2n-3+bn-2X2n-4…….. b2+b1/2
• Utility
• Conversion from binary
to Octal
• Conversion from Octal
to binary
• Conversion from binary
to Hexadecimal
• Conversion from
Hexadecimal to binary