Chapter_2(DLD)

Chapter 2
Introduction to Logic Circuits
Fundamentals of Digital Logic Department of Electrical Engineering

2.1 Variables & Functions
The simplicity of binary logic

is the motivation for their use x=0 x =1
in digital circuits (a) Two states of a switch
What is the simplest device S

with two states x
(b) Symbol for a switch
Switch
Figure 2.1. A binary switch.

2.1 Variables & Functions (Contd.)
The switch turns the light ON S
or OFF with the battery Battery x Light
providing the power source

(a) Simple connection to a battery
Output = L
Input = x
S
If x =1 then L = 1 Power
Light
supply x
If x =0 then L = 0
(b) Using a ground connection as the return path
L(x) = x
Logic
Expression Figure 2.2. A light controlled by a switch.

Series Connection
S S
L = 1 if x1 =1 and x2 = 1 Power
x1 x2 Light
supply
L = 0 otherwise
(a) The logical AND function (series connection)
L(x1,x2) = x1.x2
S
Parallel Connection x1
Power
L = 1 if x1 =1 or x2 = 1 or if supply S Light
x1 = x2 = 1 x2
(b) The logical OR function (parallel connection)

L = 0 if x1 = x2 = 0
Figure 2.3. Two basic functions.
L(x1,x2) = x1 + x2
Series Parallel Connection x1

S
L(x1,x2,x3) = (x1+x2).x3
Power
x3 Light
supply S
The light is ON if x3 = 1 and,
at the same time, at least one x2
of the x1 and x2 is equal to 1.
Figure 2.4. A series-parallel connection.

2.2 Inversion
L = 1 if x = 0
R
L = 0 if x = 1
-
L(x) = x Power
supply
x S Light
L(x) is the inverse (complement)
of the input variable x, and
x- =x’ =~x=!x Logical NOT
Operation
Figure 2.5. An inverting circuit.

The complement operation can be
extended to more complex operations as
well, e.g. ____
-
f(x1,x2) = (x1 + x2) then f(x1,x2) = (x1 + x2)
2.3 Truth Tables
The information about any

logic function against all the
possible combinations of
the inputs presented in
tabular format is termed as
“Truth Table”
Figure 2.6. A truth table for the AND and OR
operations.

2.3 Truth Tables (Contd.)
Figure 2.7. Three-input AND and OR operations.

2.4 Logic Gates & Networks
x1
x2
x1
The Three basic operations x2 x1 x2 x1 x2 
 xn
AND, OR & NOT can be used to xn

implement any complex function.
(a) AND gates
Each logic operation can be x1

x2
implemented electronically with x1
x1+x2 x1+x2+
+xn
x2
transistors, resulting in a circuit
xn
element called “Logic Gate”
(b) OR gates
A convenient way to present
logic gate is to use its graphical x x
symbol or schematic. (c) NOT gate
Figure 2.8. The basic gates.

2.4 Logic Gates & Networks (Contd.)
A larger circuit is implemented by the network of gates
x1 x
S 1
Power x
2
supply S
x3 Light f = (x + x )  x
x 1 2 3
3
x2
Figure 2.9. The function from Figure 2.4.
The complexity of a given network has direct impact on its

cost and it is always desirable to reduce the cost and
consequently find ways to implement logic circuits with
minimum number of gates
2.4.1 Analysis of Logic Network
x1
A
f
B
x2
(a) Network that implements f = x1 + x1  x2
x x f (x , x ) A B
1 2 1 2
0 0 1 1 0
0 1 1 1 0
1 0 0 0 0
1 1 1 0 1
(b) Truth table

x 1
1 0
x 1
2 0
1
A
0
1
B
0
1
f
0 Time
(c) Timing diagram

x1
g
x2
(d) Network that implements g = x1+ x2
Figure 2.10. An example of logic networks.
x x f (x , x )
1 2 1 2
0 0 1
0 1 1
1 0 0
1 1 1
Truth table

2.5 Boolean Algebra
Axioms of Boolean Algebra Single Variable Theorems
1a. 0.0 = 0 5a. x.0 = 0

1b. 1+1= 1 5b. x+1= 1
2a. 1.1 = 1 6a. x.1 = x
2b. 0+0= 0 6b. x+0= x
3a. 0.1=1.0=0 7a. x.x=x
3b. 1+0=0+1=1 7b. x+x=x
4a. If x = 0, then x’=1 8a. x.x’=0
4b. If x=1,then x’=0 8b. x+x’=1
9. (x’)’=x

2.5 Boolean Algebra (Contd.)
Two & Three Variable Properties

10a. x.y = y.x (Commutative) 14a. x.y +x.y’= x (Combining)
10b. x+y= y+x 14b. (x+y).(x+y’)= x
11a. x.(y.z) = (x.y).z (Associative) (DeMorgan’s Theorem)
11b. x+(y+z)=(x+y)+z 15a. (x.y)’ = x’+y’
12a. x.(y+z)=x.y+x.z (Distributive) 15b. (x+y)= x’.y’
12b. x+y.z=(x+y).(x+z) 16a. x+x’y=x+y
13a. x+xy=x (Absorption) 16b. x.(x’+y)=x.y
13b. x.(x+y)=x
The validity of the above properties can be proved by perfect induction or by

performing algebraic manipulation.
2.5 Boolean Algebra
Following table shows, how perfect induction can be used to prove the
validity of DeMorgan’s theorem.
Figure 2.11. Proof of DeMorgan’s theorem in 15a.

2.5.2 Notation & Terminology
Boolean algebra is based on AND & OR operations
AND ‘.’
OR ‘+’
1+1 = 2 (Ordinary Arithmetic Addition)
1+1 = 1 (Logical Sum in Boolean Algebra)

2.5.3 Precedence of Operations
Three basic operations are “AND”, “OR” and “NOT”
It is possible to construct an infinite number of logical expressions
Parenthesis are used to indicate the order in which the order

should be performed
To avoid excessive use of parenthesis, there is a convention

which defines the precedence of basic operations
Operations in a logic expression must be performed in the order:
NOT AND OR

2.6 Synthesis using AND, OR & NOT Gates
We have “AND”, “OR” and “NOT” gates in our arsenal
Suppose we wish to design a logic circuit with two inputs.

Assume the inputs represent the states of two switches. The
function of the circuit is to monitor the state of the switches and
produce an output logic value ‘1’ whenever the switches (x1, x2)
are in states (0,0), (0,1) or (1,1).

1- Obtaining a truth table
Figure 2.15. A function to be synthesized.
2- Obtaining a logical expression for logic circuit

3- Obtaining a logical diagram from logic function

x1
x2
(a) Canonical sum-of-products

4- Minimizing the cost by simplifying the logic function
x1
x2 f
(b) Minimal-cost realization

Figure 2.16. Two implementations of a function in Figure 2.15.
Summary
1- The straight forward implementation of a function can be
obtained by using a product term for each row of the truth table
for which the function value is ‘1’. Each product term contains all
input variables. The sum of these product terms realize the
desired function.
2- There are many different networks that can realize the

given function.

2.6.1 Sum of Products & Product of Sums
Sum of Products Form (SOP)

Any function ‘f’ can be represented by sum of minterms that
correspond to the truth table for which f =1.
The resulting implementation is functionally correct but its not
necessarily the lowest cost implementation of ‘f’

Minterms
For a function of ‘n’ variables, a product term in which each of
the ‘n’ variables appear once is called a minterm. The variables
may appear in complemented or complemented form.
Figure 2.17 Three-variable minterms and maxterms.

Minterms
What are canonical sum of products?
What are minimum cost sum of products?
x1 x2 x3 f (x1, x2, x3)

0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
(a) Truth table

f=Σ(m1,m4,m5,m6)
OR
f=Σm(1,4,5,6)
x2
f
x3
x1
(a) A minimal sum-of-products realization
Figure 2.18. A three-variable function.

Cost of a logic function?

Product of Sums Form (POS)

If a function ‘f’ is specified by a truth table , then its complement
!f can be represented by sum of minterms for which !f = 1 which
are the rows where f = 0. Then by complementing those sum of
products using DeMorgan’s theorem, the POS are obtained.
The resulting implementation is functionally correct but its not
necessarily the lowest cost implementation of ‘f’
What are canonical product of sums

Maxterms
For a function of ‘n’ variables, a sum term in which each of the ‘n’
variables appear once is called a maxterm. The variables may
appear in complemented or complemented form. The Maxterms
are the complements of minterms
Figure 2.17 Three-variable minterms and maxterms.

f=Π(M0.M2.M3.M7)
OR
f=ΠM(0,2,3,7)
x1
x3
f
x2
(b) A minimal product-of-sums realization

Figure 2.18. A three-variable function. Figure 2.19. Two realizations of a function in
Figure 2.18.
Example: 2.3
f= Σ m(2,3,4,6,7)
Obtain
a) Canonical SOP expression
b) Simplified SOP expression
Example: 2.4
f=ΠM(0,1,5)
Obtain
a) Canonical POS expression
b) Simplified POS expression
2.7 NAND & NOR Logic Networks
x1
x2
x1
x 1  x 2 x 1  x 2    x n
x2
xn
(a) NAND gates
x1
x2
x1
x1 + x2 x 1 + x 2 +  + x n
x2
xn
(b) NOR gates
Figure 2.20. NAND and NOR gates.

x1
x1 x1
x2 x2
x2
(a) x1 x2 = x1 + x2
x1
x1 x1
x2 x2
x2
(b) x1 + x2 = x1 x2
Figure 2.21. DeMorgan’s theorem in terms of logic gates.

x1
x2 F
F= (x1.x2)+(x3.x4.x5)
x3
x4
x5
x1 x1
x2 F x2 F
x3 x3
x4 x4
x5 x5
Figure 2.22. Using NAND gates to implement a sum-of-products.

x1
x2
F
F= (x1+x2).(x3+x4+x5)
x3
x4
x5
x1
x1
x2
F x2 F
x3
x3
x4
x4
x5
x5
Figure 2.23. Using NOR gates to implement a product-of sums.

x1
F= Σm(2, 3, 4, 6, 7) x2 f
x3
(a) POS implementation
x1
x2 f
x3
(b) NOR implementation

Figure 2.24. NOR-gate realization of the function in Example 2.4.

x1
f
F= Σm(2, 3, 4, 6, 7) x2
x3
(a) SOP implementation
x1
f
x2
x3
(b) NAND implementation

Figure 2.25. NAND-gate realization of the function in Example 2.3.

2.8 Design Examples
Assume that a large room has

three doors and that a switch
near each door controls a light in
the room. It has to be possible to
turn the light ON or OFF by
changing the state of any of
these switches.

2.8.1 Three-Way Light Control
Logical Expression in
terms of SOP
x1
x2
x3
(a) Sum-of-products realization
Figure 2.26. Truth table for a three-way light Figure 2.27. Implementation of the
control. function in Figure 2.26.
2.8.1 Three-Way Light Control
Logical Expression in
terms of POS
x3
x2
x1
(b) Product-of-sums realization
Figure 2.26. Truth table for a three-way light Figure 2.27. Implementation of the
control. function in Figure 2.26.
2.8.2 Multiplexer Circuit
x1 s
s x1 x2 f (s, x1, x2)

f x1 0
000 0 f
s x2 1
001 0
x2
010 1
(b) Circuit (c) Graphical symbol
011 1
100 0
101 1
110 0
Logical Expression f (s, x1, x2)
111 1 s
0 x1
(a) Truth table
1 x2
(d) More compact truth-table representation
Figure 2.28. Implementation of a multiplexer.

2.11 Karnaugh Map
• Canonical SOP expression
• Canonical POS expression
• Simplified SOP expression
• Simplified POS expression
• Grouping of minterms
• Grouping of Maxterms
• Kanaugh Map’s link with

Truth Table
Figure 4.1. The function f (x1, x2, x3) =
 m(0, 2, 4, 5, 6).

2.11.1 Two Variable Map
x1 x2 x1
x2
0 0 m0 0 1
0 1 m1 0 m0 m2
1 0 m2
1 m1 m3
Easy 1 1 m3
Recognition of
minterms that (a) Truth table (b) Karnaugh map
can be grouped Figure 4.2. Location of two-variable minterms.
x
x2 1
1
0 1
A minterm can
be grouped 0 1 0
f = x2 + x1
twice
1 1 1
Figure 4.3. The function of Figure 2.15.

2.11.2 Three Variable Map
x1 x2 x3
x1 x2
0 0 0 m0 x3
00 01 11 10
0 0 1 m1
0 m0 m2 m6 m4
0 1 0 m2
0 1 1 m3 1 m1 m3 m7 m5
1 0 0 m4
1 0 1 m5 (b) Karnaugh map
1 1 0 m6
Adjacent Cells
1 1 1 m7
(a) Truth table
Figure 4.4. Location of three-variable minterms.

2.11.2 Three Variable Map
x1 x2
x3
00 01 11 10
0 0 0 1 1
f = x1 x3 + x2 x3
1 1 0 0 1
(a) The function of Figure 2.18

x1 x2
x3
00 01 11 10
0 1 1 1 1
f = x3 + x x2
1 0 0 0 1 1
(b) The function of Figure 4.1
Figure 4.5. Examples of three-variable Karnaugh maps.

2.11.3 Four Variable Map
x1
x1 x2
x3 x4
00 01 11 10
00 m0 m4 m 12 m8
01 m1 m5 m 13 m9
x4
11 m3 m7 m 15 m 11
x3
10 m2 m6 m 14 m 10
x2
Figure 4.6. A four-variable Karnaugh map.

xx xx
x3x4 1 2 x3x4 1 2
00 01 11 10 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 0 0 1 1 01 0 0 1 1
11 1 0 0 1 11 1 1 1 1
10 1 0 0 1 10 1 1 1 1
f 1 = x2x3 + x1x3x4 f 2 = x3 + x1x4
xx xx
x3x4 1 2 x3x4 1 2
00 01 11 10 00 01 11 10
00 1 0 0 1 00 1 1 1 0
01 0 0 0 0 01 1 1 1 0
11 1 1 1 0 11 0 0 1 1
10 1 1 0 1 10 0 0 1 1
x1x2
f 3 = x2x4 + x1x3 + x2x3x4 f 4 = x1x3 + x1x3 + or
x2x3
Figure 4.7. Examples of four-variable Karnaugh maps.


2.11.4 Five Variable Map
x1 x2 x1 x2
x3 x4 x3 x4
00 01 11 10 00 01 11 10
00 00 1
01 1 1 01 1 1
11 1 1 11 1 1
10 1 1 10 1 1
x5 = 0 x5 = 1
f 1 = x1 x3 + x1 x3 x4 + x1 x2 x3 x5
Figure 4.8. A five-variable Karnaugh map.

2.12 Strategy for Minimization
Terminology
x1 x2
• Literal x3
00 01 11 10
• Implicant 0 1 1 0 0
• Prime Implicant 1 1 1 1 0
• Cover
x x2 x3
• Cost 1
• Essential Prime Implicants

2.12.1 Strategy for Minimization
Minimization Procedure
• Generate all Prime Implicants for the given function f
• Find the set of Essential Prime Implicants
• If the set of EPI covers all valuations for which f =1, then the set is
desired cover of f. Otherwise, determine the nonessential Prime
Implicants that should be added to form a complete minimum cover.

2.12.2 Minimization Procedure
x1 x2 • Sometimes there is a choice in

x3 x4
00 01 11 10 choosing the prime implicants.
00 x1 x2 x4
• Five prime implicants
01 1 1 x2 x3 x4
11 1 1 1 • What are essential prime

x x
implicants? And why?
10 1 1 1 1 3 4
• Do the essential prime

x1 x3 x2 x3 implicants cover all the minterms
for which f = 1?
Figure 4.10. Four-variable function
f ( x1,…, x4) =  m(2, 3, 5, 6, 7, 10, 11, 13, 14).
• What should be the final cover?

• The choice of non-essential x x2

x3 x4
1
prime implicant is not always 00 01 11 10

obvious. x3 x4
00 1 1 1 1
x1 x2 x3
• Six prime implicants 01 1
x1 x2 x4
11 1 1 x1 x3 x4
• What are essential prime
implicants? And why? 10 1 x 1 x2 x3
• Do the essential prime x1 x2 x4

implicants cover all the minterms
for which f = 1? Figure 4.11. The function
f ( x1,…, x4) =  m(0, 4, 8, 10, 11, 12, 13, 15).

x1x2 • Sometimes there may not be

x3x4 any essential prime implicants at
00 01 11 10
00 1 1 x1x3x4 all.
01 1 1 x2x3x4
• Eight prime implicants
11 1 1 x1x3x4
• What are essential prime
10 1 1
x2x3x4
implicants? And why?
x1x2x4 x1x2x4
x1x2x3 x1x2x3
Figure 4.12. The function

f ( x1,…, x4) =  m(0, 2, 4, 5, 10, 11, 13, 15).

2.13 Minimization of Product-of-Sums Forms
x1 x2
x3
00 01 11 10
0 1 1 0 0 (x 1 + x 3 )
1 1 1 1 0
(x 1 + x 2 )
Figure 4.13. POS minimization of f (x1, x2, x3) =  M(4, 5, 6).

2.13 Minimization of Product-of-Sums Forms
x1 x2
x3x4
00 01 11 10
00 0 0 0 0 (x3 + x4)
01 0 1 1 0
(x2 + x3)
11 1 1 0 1
10 1 1 1 1
(x1 + x2 + x3 + x4)
Figure 4.14. POS minimization of

f ( x1,…, x4) =  M(0, 1, 4, 8, 9, 12, 15).

2.14 Incompletely Specified Functions
x x x1x2
x3x4 1 2 x3x4
00 01 11 10 00 01 11 10
(x2 + x3)
00 0 1 d 0 00 0 1 d 0
x2x3
01 0 1 d 0 01 0 1 d 0
11 0 0 d 0 11 0 0 d 0 (x3 + x4)
10 1 1 d 1 x3x4
10 1 1 d 1
(a) SOP implementation (b) POS implementation
Figure 4.15. Two implementations of the function

f ( x1,…, x4) =  m(2, 4, 5, 6, 10) + D(12, 13, 14, 15).

Example 2.15

2.15 Multiple Output Circuits
x1 x2
x3 x4
00 01 11 10
00 1 1 x2
x3
01 1 1 1 x4
f1
11 1 1 x1
10 1 1 x3
(a) Function f 1 x1
x1 x2 x3
x3 x4 f2
00 01 11 10 x2
00 1 1 x3
x4
01 1 1
(c) Combined circuit for f 1 and f 2
11 1 1 1
10 1 1
Figure 4.16. An example of multiple-output synthesis.

(b) Function f 2

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Chapter 2

Introduction to Logic Circuits

Fundamentals of Digital Logic Department of Electrical Engineering

The simplicity of binary logic

What is the simplest device S

Fundamentals of Digital Logic Department of Electrical Engineering

The switch turns the light ON S

or OFF with the battery Battery x Light

providing the power source

Fundamentals of Digital Logic Department of Electrical Engineering

(b) The logical OR function (parallel connection)

Series Parallel Connection x1

Figure 2.4. A series-parallel connection.

Fundamentals of Digital Logic Department of Electrical Engineering

Figure 2.5. An inverting circuit.

The information about any

Fundamentals of Digital Logic Department of Electrical Engineering

Figure 2.7. Three-input AND and OR operations.

Fundamentals of Digital Logic Department of Electrical Engineering

AND, OR & NOT can be used to xn

Each logic operation can be x1

Figure 2.8. The basic gates.

A larger circuit is implemented by the network of gates

The complexity of a given network has direct impact on its

(a) Network that implements f = x1 + x1  x2

(b) Truth table

Fundamentals of Digital Logic Department of Electrical Engineering

Fundamentals of Digital Logic Department of Electrical Engineering

(d) Network that implements g = x1+ x2

Figure 2.10. An example of logic networks.

Fundamentals of Digital Logic Department of Electrical Engineering

Axioms of Boolean Algebra Single Variable Theorems

1a. 0.0 = 0 5a. x.0 = 0

Fundamentals of Digital Logic Department of Electrical Engineering

Two & Three Variable Properties

The validity of the above properties can be proved by perfect induction or by

Figure 2.11. Proof of DeMorgan’s theorem in 15a.

Fundamentals of Digital Logic Department of Electrical Engineering

Boolean algebra is based on AND & OR operations

1+1 = 1 (Logical Sum in Boolean Algebra)

Fundamentals of Digital Logic Department of Electrical Engineering

Three basic operations are “AND”, “OR” and “NOT”

It is possible to construct an infinite number of logical expressions

Parenthesis are used to indicate the order in which the order

To avoid excessive use of parenthesis, there is a convention

Operations in a logic expression must be performed in the order:

Fundamentals of Digital Logic Department of Electrical Engineering

We have “AND”, “OR” and “NOT” gates in our arsenal

Suppose we wish to design a logic circuit with two inputs.

Fundamentals of Digital Logic Department of Electrical Engineering

1- Obtaining a truth table

Figure 2.15. A function to be synthesized.

2- Obtaining a logical expression for logic circuit

Fundamentals of Digital Logic Department of Electrical Engineering

3- Obtaining a logical diagram from logic function

(a) Canonical sum-of-products

(b) Minimal-cost realization

2- There are many different networks that can realize the

Fundamentals of Digital Logic Department of Electrical Engineering

Sum of Products Form (SOP)

Fundamentals of Digital Logic Department of Electrical Engineering

Figure 2.17 Three-variable minterms and maxterms.

x1 x2 x3 f (x1, x2, x3)

(a) Truth table