Ec8661 Vlsi Design Record 2023

NEW PRINCE SHRI BHAVANI
COLLEGE OF ENGINEERING & TECHNOLOGY

Vengaivasal Main Road, Gowrivakkam, Chennai – 600073
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING
Name of the Student : ______________________________
Registration Number : ______________________________
Year / Semester : ______________________________
Lab Code / Name : ______________________________
2022 – 2023
NEW PRINCE SHRI BHAVANI
COLLEGE OF ENGINEERING & TECHNOLOGY
Vengaivasal Main Road, Gowrivakkam, Chennai – 600073
BONAFIDE CERTIFICATE
Certified to be the bonafide record of work done
by ...........................................................................................................
Reg. No. ................................ (III year / VI semester) in the

Department of Electronics and Communication Engineering during
the year 2021 – 2022.
STAFF IN CHARGE H.O.D.
Submitted for EC8661 – VLSI DESIGN LABORATORY
Practical Examination held in 4114 – NEW PRINCE SHRI BHAVANI
COLLEGE OF ENGINEERING AND TECHNOLOGY on ..................
Internal Examiner External Examiner

INDEX
EXP. PAGE
DATE TITLE INITIALS
NO. NO.
Page 3
Expt. No: 01 Date:
STUDY OF VERILOG HDL AND SPARTAN-3E FPGA BOARD
AIM:
To study Verilog HDL, Spartan-3E FPGA board and the related software.
SOFTWARE USED:
Xilinx 14.3
DEVICE USED:
Spartan-3E FPGA 250S
THEORY:
INTRODUCTION TO VERILOG HDL:
Verilog HDL is one of the Hardware Description Languages (HDL) used to

describe a digital system. VHDL is the other one. Verilog HDL allows a hardware
designer to describe designs at a high level of abstraction such as an the architectural or
behavioral level as a set of modules. Modules can either be specified behaviorally or
structurally (for a combination of two). A behavioral specification defines the behavior of
a digital system (module) using traditional programming language constructs. E.g. if
assignment statements. A structural specification expresses the behavior of a digital
system (module) as a hierarchical interconnection of sub modules. At the bottom of the
hierarchy the components must be primitives or specified behaviorally. Verilog provides
the following gate level primitives:
And/nand - logical AND/NAND

or/nor - logical OR/NOR
xor/xnor - logical XOR/XNOR
buf/not - buffer/inverter
bufif0/notif0 - tristate with low enable
bufif1/notif1 - tristate with high enable
The structure of a module is the following:
Module <module name> (<port list>);

<(declares)>
<module items>
End module.
The <module name> is an identifier that uniquely names the module. The <port list> is a
list of input, in-out and output ports which are used to connect to other modules. The
Page 4
<declares> section specifies data objects as registers, memories and wires as well as
procedural constructs such as functions and tasks. The <module items> may be initial
constructs, always constructs, continuous assignments or instances of modules.
OPERATORS:
Bitwise operators: ~(not), &(and), |(or) and ^(xor)

Arithmetic: +, -, *, /
Unary reduction: &, &&, |, ~|, ^, ~ ^
Logical: !, &&, ||
Equality: ==, != (0,1)
Identity: ===, !== (0,1,x,z)
Relational: <,>,<=,>=
Logical shift : <<, >>
Conditional: ?:
Concatenate: {}
Replicate: {{}}
DESIGN FLOW:
DESIGN ENTRY: The designed circuit is specified either by means of a schematic

diagram or by using a hardware description language, such as Verilog or VHDL.
SYNTHESIS: The entered design is synthesized into a circuit that consists of the logic
elements (LE’s) provided in the FPGA board.
FUNCTIONAL SIMULATION: The synthesized circuit is tested to verify it’s functional

correctness. This simulation does not take into account any timing issues. A test bench is
HDL code that allows you to provide a repeatable set of stimuli with clock and input dat
for
error checking, file input and output and conditional testing.
FITTING: The CAD filter told determines the placement of LE’s defined in the netlist into
the LE’s in the actual FPGA chip. It also chooses routing wires in the chip to make the
required connections between specific LE’s.
TIMING ANALYSIS: Propagation delays along the various paths in the fitted circuit are
analyzed to provide an indication of the expected performance of the circuit.
TIMING SIMULATION: The fitted circuit is tested to verify both its functional
correctness and timing.
Page 5
PROGRAMMING AND CONFIGURATION: The designed circuit is implemented in a
physical FPGA chip by programming the configuration switches that configure the LE’s
and established the required wiring connections.
Fig. Flow chart of VLSI design flow
PROCEDURE OF XILINX 14.3 SOFTWARE:
1. Start Xilinx ISE 13.1, click on “CREATE A NEW PROJECT” and then click on Next.
2. Select you’re working directory, give the name of the project, then click on
“NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed
grade (4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred
language (Verilog) from the available device list, and then click “NEXT” and click
FINISH.
4. Write the HDL code and be careful to give the entity name the same as project
name. After writing the code save the file and click on “Synthesis XST”.
5. If the HDL code is error free a green check mark will be shown on the synthesis
XST.
6. Select simulation then double click on “Simulate Behavioral Model” (here we can
change the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1’s
and 0’s and check whether the outputs are correct or not in the output waveform.
Page 6
8. In the design window change into implementation and click on “Synthesis XST”. If
the HDL code is error free a green check mark will be shown on the Synthesize –
XST.
9. Note down the Device Utilization Summary (Number of Slices , Number of LUTs
and Number of bonded IOBs)
10. Double Click the View RTL Schematic in the process window and RTL Schematic
view of your HDL code.
11. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
12. In User Constraints, double click I/O Pin Planning (PlanAhead) –Post synthesize.
PlanAhead window is opened.
13. Give the input ports and output port 9n the PlanAhead tool and save the
configuration and close the PlanAhead window.
14. Double Click the Implementation Design and green check mark will be shown on
the Implementation Icon.
15. In the Design window, change into Post – Route Simulation and by double clicking
the Post-Place & Route Check Syntax and if code is error free a green check mark
will be shown on the Post-Place & Route Check Syntax.
16. Double Click Simulate Post-Place & Route Model and analyze the output
waveform.
17. In the design window change into Implementation and process window under
implementation – Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
18. A BIT file will be generate by double clicking the Generate Programming File.
19. The BIT file is loaded in the FPGA processor through JTAG or USB cable and the
output can be verified using the hardware kit.
20. MCS file is created and loaded into the PROM for verification.
RESULT:
The verilog modelling methodology and Spartan 3E FPGA board were studied.
Page 7
Expt. No: : 02 Date:
DESIGN OF ADDER CIRCUITS
AIM:
To design and implement 8 bit adders circuits using Verilog HDL and simulate,
synthesize and implement in FPGA hardware.
APPARATUS REQUIRED:
 PC with Windows XP.

 XILINX 14.3.
 Spartan 3E FPGA Kit.
THEORY:
8-Bit Addition (Ripple Carry Adder)

The n-bit adder built from n number of one –bit full adders is known as ripple
carry adder because of the carry is computed. The addition is not complete until n-1th
adder has computed its Sn-1 output; that results depends upon ci input, n and so on down
the line, so the critical delay path goes from the 0-bit inputs up through ci’s to the n-1
bit.(We can find the critical path through the n-bit adder without knowing the exact logic
in the full adder because the delay through the n-bit adder without knowing the exact
logic in the full adder because the delay through the n-bit carry chain is so much longer
than the delay from a and b to s). The ripple-carry adder is area efficient and easy to
design but it is when n is large. It can also be called as cascaded full adder.
PROCEDURE:
“NEXT”.
FINISH.
XST.
Page 8
XST.
waveform.
8-Bit Addition (Ripple Carry Adder)

Logic Diagram:
Page 9
Programs:
Addition using Dataflow modeling
module addition8bit(a,b,oup);
input [7:0] a;
input [7:0] b;
output [8:0] oup;
assign oup = a + b;
endmodule
Ripple Carry Adder using Structural Modelling
module ripplecarry_adder(a,b,oup);
input [7:0] a,b;
output [8:0] oup;
wire [6:0]c;
parameter cin=1'b0;
// instantiating 1b-ti full adders

fulladder f1(c[0],oup[0], a[0],b[0],cin);
fulladder f2(c[1],oup[1], a[1],b[1],c[0]);
fulladder f8(oup[8],oup[7], a[7],b[7],c[6]);
endmodule
Full Adder using Dataflow Modelling

module fulladder(cout,sum, in1,in2,cin);
output cout;
output sum;
input in1,in2,cin;
assign {cout,sum}= in1 + in2 + cin;
endmodule
RESULT:
The 8-bit Adder was designed and implemented in hardware.
Page 10
Expt. No: 03 Date:
DESIGN OF MULTIPLIER CIRCUITS
AIM:
To design and implement 4 bit multiplier circuits using Verilog HDL and simulate,
APPARATUS REQUIRED:

 XILINX 14.3
THEORY:
4-Bit Multiplier
Binary multiplication can be accomplished by several approaches. The approach
presented here is realized entirely with combinational circuits. Such a circuit is called an
array multiplier. The term array is used to describe the multiplier because the multiplier is
organized as an array structure. Each row, called a partial product, is formed by a bit-by-
bit multiplication of each operand.
For example, a partial product is formed when each bit of operand ‘a’ is multiplied
by b0, resulting in a3b0, a2b0,a1b0, a0b0. The binary multiplication table is identical to the
AND truth table.
Each product bit {o(x)}, is formed by adding partial product columns. The product
equations, including the carry-in {c(x)}, from column c(x-1), are (the plus sign indicates
addition not OR). Each product term, p(x), is formed by AND gates and collection of
product terms needed for the multiplier. By adding appropriate p term outputs, the
multiplier output equations are realized, as shown in figure.
PROCEDURE:
“NEXT”.
FINISH.
XST.
Page 11
XST.
waveform.
4-Bit Multiplier
4 X 4 Array Multiplier:
a3 a2 a1 a0
b3 b2 b1 b0
a3b0 a2b0 a1b0 a0b0
a3b1 a2b1 a1b1 a0b1
a3b2 a2b2 a1b2 a0b2
a3b3 a2b3 a1b3 a0b3
o7 o6 o5 o4 o3 o2 o1
Page 12
a0b0 = p0 a1b2 = p8
a1b0 = p1 a0b3 = p9
a0b1 = p2 a3b1 = p10
a2b0 = p3 a2b2 = p11
a1b1 = p4 a1b3 = p12
a0b2 = p5 a3b2 = p13
a3b0 = p6 a2b3 = p14
a2b1 = p7 a3b3 = p15
Logic Diagram:
P14 P13 P11,P10 P7 P6 P4 P3 P2 P1 P0

P15
FA FA HA HA HA
P12 P8
FA FA FA
P9
FA FA FA HA
O7 O6 O5 O4 O3 O2 O1 O0
Programs:
Multiplier using Dataflow Modelling

module mult4bit(a,b,op);
input [3:0] a;
input [3:0] b;
output [7:0]op;
assign op= a * b;
endmodule
RESULT:
The 4-bit Multiplier was designed and implemented in hardware.
Page 13
Expt. No: 04 Date:
DESIGN ENTRY AND SIMULATION OF ALU
AIM:
To design and implement Arithmetic Logic Unit using Verilog HDL and simulate,
APPARATUS REQUIRED:

 XILINX 14.3.
THEORY:
Arithmetic Logic Unit (ALU) is the fundamental building block of the processor,
which is responsible for carrying out the arithmetic and logic functions. ALU comprises of
combinatorial logic that implements arithmetic operations such as Addition, Subtraction
and Multiplication, and logic operations such as AND, OR, NOT. The ALU gets operands
from the register file or memory. The ALU reads two input operands In A and In B. The
operation to perform on these input operands is selected using the control input Opcode.
The ALU performs the selected operation on the input operands In A and In B and
produces the output, Out. The ALU also updates different flag signals after performing
the selected function. Note that the ALU is purely combinatorial logic and contains no
registers or latches.
The arithmetic functions are much more complex to implement than the logic
functions. The performance of the ALU depends upon the architecture of each structural
components of the ALU. The ALU is divided into an arithmetic section and a logical
section.
The Arithmetic Unit compromises of three functions. They are:
 Addition
 Subtraction
 Multiplication
The Logical Unit compromises of five functions. They are:
 Bitwise AND
 Bitwise OR
 Bitwise NAND
 Bitwise NOR
 Bitwise XOR
PROCEDURE:
“NEXT”.
Page 14
FINISH.
XST.
XST.
waveform.
Page 15
Programs:
ALU using Behaviour modeling
`timescale 1ns / 1ps

module alu (op,a,b,opcode);
output reg [15:0] op; //output of alu

input [7:0] a,b; //inputs to alu
input [3:0] opcode; //control signal for different operation
always @(*)
begin
case (opcode)
4'b0000 : begin op = a + b; $display("Addition operation"); end
4'b0001 : begin op = a - b; $display("Subtraction operation"); end
4'b0010 : begin op = a * b; $display("Multiplication operation"); end
4'b0011 : begin op = a / b; $display("Division operation"); end
4'b0100 : begin op = a % b; $display("Modulo Division operation"); end
4'b0101 : begin op = a & b; $display("Bit-wise AND operation"); end
4'b0110 : begin op = a | b; $display("Bit-wise OR operation"); end
4'b0111 : begin op = a && b; $display("Logical AND operation"); end
4'b1000 : begin op = a || b; $display("Logical OR operation"); end
4'b1001 : begin op = a ^ b; $display("Bit-wise XOR operation"); end
4'b1010 : begin op = ~ a; $display("Bit-wise Invert operation"); end
4'b1011 : begin op = ! a; $display("Logical Invert operation"); end
4'b1100 : begin op = a >> 1; $display("Right Shift operation"); end
4'b1101 : begin op = a << 1 ; $display("Left Shift operation"); end
4'b1110 : begin op = a + 1; $display("Increment operation"); end
4'b1111 : begin op = a - 1; $display("Decrement operation"); end
default:op = 8'bXXXXXXXX;
endcase
end
endmodule
RESULT:
The Arithmetic Logic Unit was designed and implemented in hardware.
Page 16
Expt No: 05 Date:
DESIGN OF UNIVERSAL SHIFT REGISTER
AIM:
To design and implement the Universal Shift Register using Verilog HDL and
simulate, synthesize and implement in FPGA hardware.
APPARATUS REQUIRED:

 Xilinx 14.3
THEORY:
A Universal shift register is a register which has both the right shift and left shift
with parallel load capabilities. Universal shift registers are used as memory elements in
computers. A Unidirectional shift register is capable of shifting in only one direction. A
bidirectional shift register is capable of shifting in both the directions. The Universal shift
register is a combination design of bidirectional shift register and a unidirectional shift
register with parallel load provision.
n-bit universal shift register

A n-bit universal shift register consists of n flip-flops and n 4×1 multiplexers. All
the n multiplexers share the same select lines (S1 and S0)to select the mode in which the
shift register operates. The select inputs select the suitable input for the flip-flops.
Page 17
S1 S0 REGISTER OPERATION
0 0 No changes
0 1 Shift right
1 0 Shift left
1 1 Parallel load
PROCEDURE:
“NEXT”.
FINISH.
SRIRAM SUNDAR S / CARE GROUP OF INSTITUTIONS

Page 18
XST.
XST.
waveform.
Programs:
Universal Shift Register using Behaviour modeling
`timescale 1ns / 1ps

module universal_shift(a,s,clk,p);
input [3:0]a;
input [1:0]s;
input clk;
output reg [3:0]p;
Page 19
initial p<=4'b0110;
always@(posedge clk)
begin
case (s)
2'b00:
begin
p[3]<=p[3]; p[2]<=p[2];
p[1]<=p[1]; p[0]<=p[0];
end
2'b01:
begin
p[3]<=p[0]; p[2]<=p[3];
p[1]<=p[2]; p[0]<=p[1];
end
2'b10:
begin
p[0]<=p[3]; p[1]<=p[0];
p[2]<=p[1]; p[3]<=p[2];
end
2'b11:
begin
p[0]<=a[0]; p[1]<=a[1];
p[2]<=a[2]; p[3]<=a[3];
end
endcase
end
endmodule
RESULT:
The Universal Shift Register was designed and implemented in hardware.
Page 20
Expt No: 06 Date:
DESIGN OF FINITE STATE MACHINE
AIM:
To design and implement Finite State Machine model using Verilog HDL and
simulate, synthesize and implement in FPGA hardware.
APPARATUS REQUIRED:

 XILINX 14.3.
PROCEDURE:
“NEXT”.
FINISH.
XST.
XST.
Page 21
waveform.
State Diagram
Programs:
FSM Design using Behavioral Modelling

module m1011( clk, rst, inp, outp);
input clk, rst, inp;

output outp;
reg [1:0] state; reg outp;

always @( posedge clk, rst )
begin
if( rst )
state <= 2'b00;
else
begin
Page 22
case( {state,inp} )
3'b000: begin
state <= 2'b00;
outp <= 0;
end
3'b001: begin
state <= 2'b01;
outp <= 0;
end
3'b010: begin
state <= 2'b10;
outp <= 0;
end
3'b011: begin
state <= 2'b01;
outp <= 0;
end
3'b100: begin
state <= 2'b00;
outp <= 0;
end
3'b101: begin
state <= 2'b11;
outp <= 0;
end
3'b110: begin
state <= 2'b10;
outp <= 0;
end
3'b111: begin
state <= 2'b01;
outp <= 1;
end
endcase
end
end
endmodule
RESULT:
The Finite State machine was designed and implemented in hardware.
Page 23
Expt No: 07 Date:
DESIGN OF MEMORIES
AIM:
To design and implement Memory Circuit using Verilog HDL and simulate, synthesize
and implement in FPGA hardware.
APPARATUS REQUIRED:

 XILINX 14.3.
PROCEDURE:
“NEXT”.
FINISH.
XST.
XST.
Page 24
waveform.
Programs:
module raminfr (clk, we, a, di, do);
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
always @(posedge clk) begin

if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule
RESULT:
The Memory was designed and implemented in hardware.
Exp. No.: 8
LAYOUT EXTRACTION AND SIMULATION
OF C-MOS INVERTOR
AIM:
To draw the layout of an CMOS inverter
SOFTWARE USED:
 Microwind
 DSCH
DESCRIPTION:
CMOS INVERTER:
The NMOS transistor and the PMOS transistor form a typical complementary MOS (CMOS)
device. When a low voltage (0 V) is applied at the input, the top transistor (P-type) is
conducting (switch closed) while the bottom transistor behaves like an open circuit.
Therefore, the supply voltage (5 V) appears at the output. Conversely, when a high voltage
(5 V) is applied at the input, the bottom transistor (N-type) is conducting (switch closed)
while the top transistor behaves like an open circuit. Hence, the output voltage is low (0 V).
LAYOUT DIAGRAM
ALGORITHM:
 Open the DSCH2
 Drag the components like pmos,nmos,voltage source, ground, and LED from the
symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & run the simulation
 Make verilog file go to Microwind and compile the verilog file saved in DSCH2
 Compile it and obtain the layourt diagram & draw the waveform
CIRCUIT DIAGRAM:
MOS LAYOUT
We use MICROWIND2 to draw the MOS layout and simulate its behavior. Go to the
directory in which the software has been copied (By default MICROWIND2). Double-click
on the MicroWind2 icon. The MICROWIND2 display window includes four main windows:
the main menu, the layout display window,the icon menu and the layer palette. The layout
the
minimum available lithography of the technology. The default technology is a CMOS 6-
metal layers 0.25μm technology, consequently lambda is 0.125 μm.
Verilog code:
module cmosInv( in2,out2)

input in2;
output out2;
pmos #(17) pmos(out2,vdd,in2); // 1.0u 0.12u
nmos #(114) nmos(out2,vss,in2); // 0.48u 0.12u
endmodule
LAYOUT FOR C-MOS INVERTOR:

ANALOG SIMULATION:
Click on Simulate à Start Simulation. The timing diagrams will appears as follows
RESULT:
Thus the Layout design of a CMOS inverter has been drawn, verified and timing
analysis perform.
Exp. No.: 9
OF C-MOS NAND AND NOR GATE
AIM:
To design and simulate the cmos NAND and NOIR gate circuit.
SOFTWARE USED
 Microwind
 DSCH
THEORY:
NAND and NOR gates are known as universal gates as any function can be
implemented with them
NAND functionality can be implemented by parallel combination of PMOS and series

combination of NMOS transistor. When any one of the inputs is zero, then the output will be
one and when both the inputs are one the output will be low.
NOR functionality can be implemented by parallel combination of NMOS and series

combination of PMOS transistor. When any one of the inputs is one, then the output will be
one and when both the inputs are zero the output will be low.
ALGORITHM:
 Open the DSCH2
symbol library.
CIRCUIT DIAGRAM:
NAND gate:
Verilog code:
module cmosNand2( A,B,Nand2);

input A,B;
output Nand2;
nmos #(121) nmos(Nand2,w1,A); // 2.0u 0.25u
pmos #(121) pmos(Nand2,vdd,A); // 2.0u 0.25u
pmos #(121) pmos(Nand2,vdd,B); // 2.0u 0.25u
nmos #(107) nmos(w1,vss,B); // 2.0u 0.25u
endmodule
Layout:
Waveform:
NOR gate:
Verilog code:
module nor2Cmos( B,A,Nor2);

input B,A;
output Nor2;
nmos #(121) nmos(Nor2,vss,A); // 1.0u 0.12u
pmos #(121) pmos(Nor2,w4,B); // 2.0u 0.12u
pmos #(107) pmos(w4,vdd,A); // 2.0u 0.12u
nmos #(121) nmos(Nor2,vss,B); // 1.0u 0.12u
endmodule
Layout:
Waveform:
RESULT:
Thus the Layout design of a CMOS NAND and NOR gate has been drawn, verified
and timing analysis performed
Exp. No.: 10
OF C-MOS DIFFERENTIAL AMPLIFIER
AIM:
To design and simulate the emitter follower and differential amplifier circuit.
SOFTWARE USED
 Microwind
 DSCH
THEORY:
Differential amplifier:
Differential Amplifier amplifies the current with very little voltage gain. It consists of two
FETs connected so that the FET sources are connected together. The common source is
connected to a large voltage source through a large resistor Re, forming the "long tail" of the
name, the long tail providing an approximate constant current source. The higher the
resistance of the current source Re, the lower Ac is, and the better the CMRR. In more
sophisticated designs, a true (active) constant current source may be substituted for the long
tail. The output from a differential amplifier is itself often differential.
ALGORITHM:
 Open the DSCH2
symbol library.
CIRCUIT DIAGRAM:
DIFFERENTIAL AMPLIFIER:
Verilog code:
module diff amp( );
nmos #(17) nmos(w2,vss,w1); // 1.0u 1u
pmos #(10) P2LargeL(w5,w3,w4); // 2.0u 0.12u
pmos #(24) P1LargeL(w4,w6,w4); // 2.0u 0.12u
nmos #(10) N2LargeL(w5,w2,w7); // 1.0u 1u
nmos #(24) N1LargeL(w4,w2,w8); // 1.0u 1u
endmodule
LAYOUT:
WAVEFORM:
RESULT:
Thus the Layout design of a differential amplifier has been drawn, verified and timing
analysis performed
Exp. No.: 11
DESIGN OF CMOS INVERTER USING TANNER
AIM
To design a CMOS inverter using the Schematic entry tool, Tanner and
verify its functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
CMOS Inverter consists of nMOS and pMOS transistor in series connected between
VDD and GND. The gate of the two transistors are shorted and connected to the input. When
the input to the inverter A = 0, nMOS transistor is OFF and pMOS transistor is ON. The
output is pull-up to VDD. When the input A = 1, nMOS transistor is ON and pMOS transistor
is OFF. The Output is Pull-down to GND.
ALGORITHM
1. Draw the schematic of CMOS Inverter using S-edit.
2. Perform Transient Analysis of the CMOS Inverter.
3. Obtain the output waveform from W-edit.
4. Obtain the spice code using T-edit.

CMOS Inverter
]
WAVEFORM
Transient Analysis
Dc analysis
OUTPUT
\
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "C:\Tanner\S-Edit\Module011.sp"
Including "C:\Tanner\TSpice70\models\ml2_125.md"
Device and node counts:
MOSFETs - 2 BJTs - 0 MESFETs - 0 Capacitors - Inductors - 0

MOSFET geometries - 2
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors - 0
Voltage sources - 2
VCVS - 0
CCVS - 0
V-control switch - 0
Macro devices - 0
Subcircuits - 0
Independent nodes - 1
Total nodes - 4
Current sources - 0
VCCS - 0
CCCS - 0
I-control switch - 0
Functional model instances - 0
Subcircuit instances - 0
Boundary nodes - 3
Parsing 0.01 seconds
Setup 0.00 seconds
DC operating point 0.00 seconds
Transient Analysis 0.04 seconds
-----------------------------------------
Total 0.05 seconds
RESULT
Thus the design & simulation of a CMOS inverter has been carried out using S-Edit of
Tanner EDA Tools
Exp. No.: 12 DESIGN OF CMOS NAND GATE AND NOR GATE USING
TANNER
AIM
To design a CMOS NAND and NOR gates using the Schematic entry tool, Tanner
and verify its functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
NAND and NOR gates are known as universal gates as any function can be
implemented with them
NAND functionality can be implemented by parallel combination of PMOS and series

combination of NMOS transistor. When any one of the inputs is zero, then the output will be
one and when both the inputs are one the output will be low.
NOR functionality can be implemented by parallel combination of NMOS and series

combination of PMOS transistor. When any one of the inputs is one, then the output will be
one and when both the inputs are zero the output will be low.
ALGORITHM
CMOS NAND
1. Draw the schematic of CMOS NAND using S-edit.

2. Perform Transient Analysis of the CMOS NAND.
CMOS NOR
1. Draw the schematic of CMOS NOR using S-edit.

2. Perform Transient Analysis of the CMOS NOR.
CMOS NAND Ciruit:
WAVEFORM NAND
OUTPUT - NAND
Version 7.10
Parsing "F:\tanner\TSpice70\Module0.sp"
Including "F:\tanner\S-Edit\models\ml2_125.md"
Warning T-SPICE : DC sources have non-unique names. "vin".

MOSFETs - 4 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 3 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Functional model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Independent nodes - 2 Boundary nodes - 4
Total nodes - 6
*** 1 WARNING MESSAGES GENERATED

Setup 0.00 seconds
-----------------------------------------
Total 0.04 seconds
CMOS NOR Circuit
OUTPUT – NOR

Version 7.10
Parsing "F:\tanner\TSpice70\Module0.sp"
Including "F:\tanner\S-Edit\models\ml2_125.md"
Warning T-SPICE : DC sources have non-unique names. "vin".

MOSFETs - 4 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Voltage sources - 3 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Functional model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Independent nodes - 3 Boundary nodes - 4
Total nodes - 7
*** 1 WARNING MESSAGES GENERATED
Warning T-SPICE : The vrange voltage range limit (5.5) for diode tables has been exceeded.
Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has been
exceeded.
Warning T-SPICE : The vrange voltage range limit should be set to at least 7.11984 for best
accuracy and performance.

Setup 0.01 seconds
-----------------------------------------
Total 0.07 seconds
RESULT
Thus the design & simulation of a CMOS NAND and NOR gates have been carried
out using S-Edit of Tanner EDA Tools
Exp. No.: 13 DESIGN OF CMOS DIFFERENTIAL AMPLIFIER USING
TANNER
AIM
To design a CMOS Differential Amplifier using the Schematic entry tool, Tanner
and verify its functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
A differential amplifier is a type of electronic amplifier that multiplies the difference

between two inputs by some constant factor (the differential gain). Many electronic
devices use differential amplifiers internally. The output of an ideal differential
amplifier is given by:
Where Vin+ and Vin- are the input voltages and Ac is the differential gain. In
practice, however, the gain is not quite equal for the two inputs. This means that if
Vin+ and Vin-are equal, the output will not be zero, as it would be in the ideal case. A
more realistic expression for the output of a differential amplifier thus includes a
second term.
Ac is called the common-mode gain of the amplifier. As differential amplifiers are

often used when it is desired to null out noise or bias-voltages that appear at both
inputs, a low common-mode gain is usually considered good.
The common-mode rejection ratio, usually defined as the ratio between differential-
mode gain and common-mode gain, indicates the ability of the amplifier to accurately
cancel voltages that are common to both inputs. Common-mode rejection ratio
(CMRR):
ALGORITHM
 Draw the schematic of CMOS differential amplifier using S-edit.
 Perform Transient Analysis of the CMOS Inverter.
 Obtain the output waveform from W-edit.
 Obtain the spice code using T-edit.
DIFFERENTIAL AMPLIFIER CIRCUIT:

WAVEFORM:
OUTPUT

Version 7.10
Parsing "C:\Tanner\S-Edit\Module0.sp"
Including "C:\Tanner\TSpice70\models\ml2_125.md"
MOSFETs - 5 BJTs - 0 MESFETs - 0 Capacitors - 0 Inductors - 0

MOSFET geometries - 2
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors - 0
Voltage sources - 4
VCVS - 0
CCVS - 0
V-control switch - 0
Macro devices - 0
Subcircuits - 0
Independent nodes - 4
Total nodes - 9
Current sources - 0
VCCS - 0
CCCS - 0
I-control switch - 0
Functional model instances - 0
Subcircuit instances - 0
Boundary nodes - 5
Setup 0.01 seconds
-----------------------------------------
Total 0.09 seconds
RESULT
The design and simulation of Differential Amplifier has been performed using
Tanner EDA Tools.
CONTENT BEYOND SYLLABUS
Exp. No.: 1
DESIGN & FPGA IMPLEMENTATION OF
FLIPFLOPS (D & T FLIPFLOPS)
AIM:
To implement Flipflops using Verilog HDL.
APPARATUS REQUIRED:
 XILINX 9.2i
 FPGA-SPARTAN-3 KIT
 PARALLEL TO JTAG CABLE
ALGORITHM:
 New project and type the project name and check the top level source type as HDL
 Enter the device properties and click Next
 Click New Source And Select the Verilog Module and then give the file name
 Give the Input and Output port names and click finish.
 Type the Verilog program and save it
 Double click the synthesize XST and check syntax
 Simulate the waveform by behavioral simulation
 For implementation Select User constraints and give input and output port pin number
 Click Implement design for Translate, map and place & route
 Generate .bit file using programming file
 Implement in FPGA through parallel-JTAG cable
 Check the behavior of design in FPGA by giving inputs
D-FLIPFLOP:
PROGRAM:
Module DFF(Clock, Reset, d, q);

input Clock;
input Reset;
input d;
output q;
reg q;
always@(posedge Clock or negedge Reset)
if (~Reset)
q=1'b0;
else
q=d;
endmodule
Truth Table:
D FlipFlop
--------------------------------------------------------------------------
Clock Reset Input (d) Output q(~q)
---------------------------------------------------------------------------
0 0 0 0(1)
1 0 0 0(1)
0 0 1 0(1)
1 0 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 1 0 1(0)
1 1 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 0 0 0(1)
1 0 0 0(1)
0 0 0 0(1)
--------------------------------------------------------------------------
OUTPUT:
T-FLIPFLOP:
PROGRAM:
Module TFF(Clock, Reset, t, q);

input Clock;
input Reset;
input t;
output q;
reg q;
always@(posedge Clock , negedge Reset)
if(~Reset) q=0;
else if (t) q=~q;
else q=q;
endmodule
TRUTH TABLE:
---------------------------------------------------------------------------
Clock Reset Input (t) Output q(~q)
---------------------------------------------------------------------------
0 0 0 0(1)
1 0 0 0(1)
0 0 1 0(1)
1 0 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 1 0 1(0)
1 1 0 1(0)
0 1 1 1(0)
1 1 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 0 0 0(1)
--------------------------------------------------------------------------
OUTPUT WAVEFORM:
RESULT:
Thus the D & T flipflops are designed, simulated and implemented successfully.
Exp. No.: 2
DESIGN & ANALYSIS OF Half Adders
using Tanner
HALF ADDER
Aim:
a) To construct the Half Adder in Tanner EDA v13.1 and to do the Transient Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.
Tools used:
Tanner Tools v13.1
Schematic-Edit
Layout -Edit
Wave- Edit
Tanner Spice
Procedure:
Open S-Edit window.
Go to File  New  New design
Go to Cell New View
Add libraries file to the New Cell.
Instance the devices by using appropriate library files.
Save the design and setup the simulation.
Run design and observe waveforms.
Observe DC inputs and outputs by giving appropriate inputs.
Schematic Diagram:
Fig (a): Half Adder Schematic

Tanner Spice Code:
* SPICE export by: SEDIT 13.12
* Export time: Fri Apr 16 11:24:00 2010
* Design: adm705-1
* Cell: Cell2
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Documents and Settings\Administrator\Desktop\adm705-1
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools
v13.1\Libraries\Models\Generic_025.lib" TT
*************** Subcircuits *****************

.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 --------
* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 --------

MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
.ends
.subckt NAND2C A B Out1 Out2 Gnd Vdd

* Design: LogicGates / Cell: NAND2C / View: Main / Page:
* Info: 2 Input NAND with complementary output.
* Date: 6/14/2007 1:47:11 AM
* Revision: 2

MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt XNOR2 A B Out Gnd Vdd

* Design: LogicGates / Cell: XNOR2 / View: Main / Page:
* Info: 2 Input NOR
* Date: 7/18/2008 3:58:48 AM
* Revision: 4

MM3n 1 A 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM10n Out 1 5 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM9n 5 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM8n Out 1 4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM7n 4 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM4n 2 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM5p 3 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MM11p Out 1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM2p 1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MM1p 1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MM6p Out A 3 Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
.ends
.subckt XOR2 A B Out Gnd Vdd

* Design: LogicGates / Cell: XOR2 / View: Main / Page:
* Info: 2 Input NOR
* Date: 7/18/2008 1:30:51 AM
* Revision: 3
*-------- Devices: SPICE.ORDER == 0 --------

XXinv N_1 Out Gnd Vdd INV
XXxnor A B N_1 Gnd Vdd XNOR2
.ends
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER == 0 --------

XINV_1 N_1 carry Gnd Vdd INV
XNAND2C_1 In1 In2 N_1 N_2 Gnd Vdd NAND2C
XXOR2_1 In1 In2 sum Gnd Vdd XOR2
VVoltageSource_3 Vdd Gnd DC 5
VVoltageSource_1 In1 Gnd PULSE(0 5 0 5n 5n 50n 100n)
VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 25n 50n)
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(carry)
.PRINT TRAN V(sum)
********* Simulation Settings - Analysis section *********

.tran 350ns 500ns
.dc lin source VVoltageSource_1 0 5 0.5 sweep lin source VVoltageSource_2 0 5 0.5
.print dc v(XINV_1,GND)
.print dc v(XXOR2_1,GND)
********* Simulation Settings - Additional SPICE commands *********
.end
Output responses:
Result:
The Half Adder is constructed in Tanner EDA v13.1, the spice code is generated and wave forms
are verified.

Ec8661 Vlsi Design Record 2023

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Ec8661 Vlsi Design Record 2023

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NEW PRINCE SHRI BHAVANI

COLLEGE OF ENGINEERING & TECHNOLOGY

Name of the Student : ______________________________

Registration Number : ______________________________

Year / Semester : ______________________________

Lab Code / Name : ______________________________

Certified to be the bonafide record of work done

Reg. No. ................................ (III year / VI semester) in the

STAFF IN CHARGE H.O.D.

Submitted for EC8661 – VLSI DESIGN LABORATORY

Practical Examination held in 4114 – NEW PRINCE SHRI BHAVANI

COLLEGE OF ENGINEERING AND TECHNOLOGY on ..................

Internal Examiner External Examiner

STUDY OF VERILOG HDL AND SPARTAN-3E FPGA BOARD

INTRODUCTION TO VERILOG HDL:

Verilog HDL is one of the Hardware Description Languages (HDL) used to

And/nand - logical AND/NAND

The structure of a module is the following:

Module <module name> (<port list>);

Bitwise operators: ~(not), &(and), |(or) and ^(xor)

DESIGN ENTRY: The designed circuit is specified either by means of a schematic

FUNCTIONAL SIMULATION: The synthesized circuit is tested to verify it’s functional

Fig. Flow chart of VLSI design flow

PROCEDURE OF XILINX 14.3 SOFTWARE:

DESIGN OF ADDER CIRCUITS

 PC with Windows XP.

8-Bit Addition (Ripple Carry Adder)

8-Bit Addition (Ripple Carry Adder)

Ripple Carry Adder using Structural Modelling

// instantiating 1b-ti full adders

Full Adder using Dataflow Modelling

DESIGN OF MULTIPLIER CIRCUITS

 PC with Windows XP.

P14 P13 P11,P10 P7 P6 P4 P3 P2 P1 P0

Multiplier using Dataflow Modelling

DESIGN ENTRY AND SIMULATION OF ALU

 PC with Windows XP.

ALU using Behaviour modeling

`timescale 1ns / 1ps

output reg [15:0] op; //output of alu

DESIGN OF UNIVERSAL SHIFT REGISTER

 PC with Windows XP.

n-bit universal shift register

SRIRAM SUNDAR S / CARE GROUP OF INSTITUTIONS

Universal Shift Register using Behaviour modeling

`timescale 1ns / 1ps

DESIGN OF FINITE STATE MACHINE

 PC with Windows XP.

FSM Design using Behavioral Modelling

input clk, rst, inp;

reg [1:0] state; reg outp;

 PC with Windows XP.

module raminfr (clk, we, a, di, do);

always @(posedge clk) begin

To draw the layout of an CMOS inverter

 Open the DSCH2

 Connect the circuit as in the circuit diagram.

 Save the circuit & run the simulation

module cmosInv( in2,out2)

LAYOUT FOR C-MOS INVERTOR:

NAND functionality can be implemented by parallel combination of PMOS and series

NOR functionality can be implemented by parallel combination of NMOS and series

 Open the DSCH2

 Connect the circuit as in the circuit diagram.

* Simulation Settings - General section *

* Subcircuits ***

* Simulation Settings - Parameters and SPICE Options *

* Simulation Settings - Analysis section *

* Simulation Settings - Additional SPICE commands *