DE LAB manual

DE&MP LABORATORY II B.
Tech I Sem
EXP. NO : DATE:
LOGIC GATES
Aim: Verification of Truth Table for AND, OR, NOT, NAND, NOR and EX-OR gates.
Components Required:
Sl. No Name of the Component IC number Qty
1 AND gate 7408 2
2 OR gate 7432 2
3 Not gate 7404 2
4 EXOR gate 7486 2
5 NAND gate 7400 2
6 NOR gate 7402 2
7 EX-NOR gate 4077 1
8 Patch chords few
9 Trainer Kit
THEORY:
The basic logic gates are the building blocks of more complex logic circuits. These logic gates
perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR,
Exclusive-NOR. Fig. below shows the circuit symbol, Boolean function, and truth. It is seen from
the Fig that each gate has one or two binary inputs, A and B, and one binary output, C. The small
circle on the output of the circuit symbols designates the logic complement. The AND, OR, NAND,
and NOR gates can be extended to have more than two inputs. A gate can be extended to have
multiple inputs if the binary operation it represents is commutative and associative.
These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of
more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC gates
are classified not only by their logic operation, but also the specific logic-circuit family to which
they belong. Each logic family has its own basic electronic circuit upon which more complex
digital circuits and functions are developed. The following logic families are the most frequently
used.
TTL -Transistor-transistor logic

ECL -Emitter-coupled logic
MOS -Metal-oxide semiconductor
CMOS -Complementary metal-oxide semiconductor
TTL and ECL are based upon bipolar transistors. TTL has a well established popularity among
logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS, are
based on field effect transistors. They are widely used in large scale integrated circuits because of
their high component density and relatively low power consumption. CMOS logic consumes far
less power than MOS logic. There are various commercial integrated circuit chips available. TTL
ICs are usually distinguished by numerical designation as the 5400 and 7400 series.
PROCEDURE:
VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 1

DE&MP LABORATORY II B.Tech I Sem
1. Place the breadboard gently on the observation table.

2. Fix the IC which is under observation between the half shadow line of breadboard, so there is no
shortage of voltage.
3.Connect the wire to the main voltage source (Vcc) whose other end is connected to last pin of the IC
(14 place from the notch).
4. Connect the ground of IC (7th place from the notch) to the ground terminal provided on the digital lab
kit.
5. Give the input at any one of the gate of the ICs i.e. 1st, 2nd, 3rd, 4th gate by using connecting wires. (In
accordance to IC provided).
6. Connect output pins to the led on digital lab kit.
7. Switch on the power supply.
8. If LED glows red then output is true, if it glows green output is false, which is numerically denoted as 1
and 0 respectively. The Color can change based on the IC manufacturer it’s just verification of the Truth
Table not the color change.
NOT GATE
OR GATE
AND GATE
NAND GATE

NOR GATE
XOR GATE
EX-NOR GATE
RESULT:

VIVA QUESTIONS:
1. Why NAND & NOR gates are called universal gates?
2. Realize the EX – OR gates using minimum number of NAND gates?
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What is the principle of logic gates?
5. Which is the most commonly used logic family?
EXP. NO : DATE:
REALIZATION OF A LOGIC GATES USING NAND AND NOR

AIM: Realization of NOT, AND, OR, EX-OR gates with only NAND and only NOR gates.
1 AND gate 7408 2
2 OR gate 7432 2
3 NOT gate 7404 2
4 EX-ORgate 7486 2
5 NAND gate 7400 2
6 NOR gate 7402 2
7 EX-NOR gate 4077 1
8 Patch chords few
9 Trainer Kit
THEORY:
The basic logic gates are the building blocks of more complex logic circuits. These logic gates
perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR,
Exclusive-NOR. Fig. below shows the circuit symbol, Boolean function, and truth. It is seen from the Fig
that each gate has one or two binary inputs, A and B, and one binary output, C. The small circle on the
output of the circuit symbols designates the logic complement. The AND, OR, NAND, and NOR gates
can be extended to have more than two inputs. A gate can be extended to have multiple inputs if the
binary operation it represents is commutative and associative.
These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of
more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC gates are
classified not only by their logic operation, but also the specific logic-circuit family to which they
belong. Each logic family has its own basic electronic circuit upon which more complex digital circuits
and functions are developed. The following logic families are the most frequently used.
TTL -Transistor-transistor logic

ECL -Emitter-coupled logic
MOS -Metal-oxide semiconductor
CMOS -Complementary metal-oxide semiconductor
TTL and ECL are based upon bipolar transistors. TTL has a well established popularity among
logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS, are based
on field effect transistors. They are widely used in large scale integrated circuits because of their high
component density and relatively low power consumption. CMOS logic consumes far less power than
MOS logic. There are various commercial integrated circuit chips available. TTL ICs are usually
distinguished by numerical designation as the 5400 and 7400 series.
NAND gate as AND gate using IC7408

Logic Diagram Truth Table

NAND gate as OR gate using IC7432

NAND gate as NOT gate using IC7404

NAND gate as NOR gate using IC7402

NAND gate as Ex-OR gate using IC7486

NAND gate as Ex-NOR gate using IC4077

NOR gate as AND gate using IC7408

NOR gate as OR gate using IC7432


NOR gate as NOT gate using IC7404

NOR gate as NAND gate using IC7400

NOR gate as Ex-NOR gate using IC4077

NOR gate as Ex-OR gate using IC7486


PROCEDURE:
1.Connect the trainer kit to ac power supply.
2. Connect the NAND gates for any of the logic functions to be realized.
3. Connect the inputs of first stage to logic sources and output of the last gate to logic indicator.
4. Apply various input combinations and observe output for each one.
5. Verify the truth table for each input/ output combination.
6. Repeat the process for all logic functions.
7. Switch off the power supply.
RESULT:
VIVA QUESTIONS:
1) What are the different methods to obtain minimal expression?
2) What is a Min term and Max term
3) What is meant by canonical representation?
4) What is K-map? Why is it used?
5) What are universal gates?

EXP. NO : DATE:
DE-MORGAN’S THEOREM
AIM:
To verify De-Morgan’s theorem for two variables
COMPONENTS REQUIRED: IC Trainer kit, IC 7400, IC 7402
THEORY:
1. De Morgan theorem states that

a) AB’=A’+B’
b) (A+B)’=A’.B’
De-Morgan’s theorem is highly useful to simplify the Boolean expression
2. Gates NAND and NOR are known as universal gates, because any logic gates or Boolean
expression can be realized by either NAND or NOR gate alone. Each product term in the SOP
expression is called minterm and each sum term in the POS expression is called maxterm.
SOP expression can be economically realized using NAND gates and POS expression can be
economically realized using NOR gates.
DEMORGAN’S THEOREM:
a) AB’=A’+B’
TRUTH TABLE:
A B
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
CIRCUIT DIAGRAM:
b) (A+B)’=A’.B’
TRUTH TABLE:
A B
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
CIRCUIT DIAGRAM:
PROCEDURE:
1.Test all the IC packages using digital IC tester.

2.Set up the circuit one by one and verify their truth table.
3.Observe the output corresponding to input combinations and enter it in truth table.
RESULT:
VIVA QUESTIONS:
1.What is the use of De Morgan's theorem?

2.What are the importance of de Morgan's theorems in Boolean algebra?
3.What are DeMorgan's theorems prove algebraically the DeMorgan's theorems?
4.How do you remember DeMorgan's law?
EXP. NO : DATE:
HALF ADDER & HALF SUBTRACTOR

Aim: Realization of half adder and half Subtractor using logic gates.
1 AND gate 7408 1
2 OR gate 7432 1
3 Not gate 7404 1
4 EXOR gate 7486 3
5 NAND gate 7400 3
6 NOR gate 7402 3
7 Patch chords Few

8 Trainer Kit
THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits,
A and B, is called a half-adder. Addition will result in two output bits; one of which is
the sum bit, S, and the other is the carry bit, C. The Boolean functions describing the
half-adder are:
S =A  B C=AB
Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B )

produces a difference bit D and a borrow out bit B-out. This operation is called half
subtraction and the circuit to realize it is called a half subtractor. The Boolean functions
describing the half- Subtractor are:
S =A  B C = A’ B
Half Adder Using Basic Gates
Half Adder Using NAND Gates

Half Subtractor Using Basic Gates
Truth Table Circuit Diagram
Dec INPUTS OUTPUTS

Eq
A B Diff Barrow
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0
Using NAND gates
PROCEDURE:
1. Obtain the Boolean Expressions for half adder and half subtractor (sum & Carry) by
writing the truth table and simplifying with the help of K-map.
2. Make the connections as shown in the logic diagram.
3. Apply different combinations of inputs according to the truth table and verify the
outputs.
4. Repeat the above procedure for all the circuit diagrams.
RESULT:

VIVA QUESTIONS:
1)What is a half adder?
2)What are the applications of adders?
3)What is a half subtractor?
4) What are the applications of subtractors?
5) Realize a full adder using two half adders

EXP. NO : DATE:
FULL ADDER & FULL SUBTRACTOR
Aim: Realization of full adder and full Subtractor using logic gates.
1 AND gate 7408 1
2 OR gate 7432 1
3 Not gate 7404 1
4 EXOR gate 7486 3
5 NAND gate 7400 3
6 NOR gate 7402 3
7 Patch chords Few
8 Trainer Kit
THEORY:
Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean
functions describing the full-adder are:
S = (x  y)  Cin C = xy + Cin (x  y)
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The
Boolean functions describing the full-subtracter are:
D = (x  y)  Cin Br= A’B + A’(Cin) + B(Cin)
Truth Table
Inputs Outputs
Dec Equi
A B Bin Diff Borrow
0 0 0 0 0 0
1 0 0 1 1 1
2 0 1 0 1 1
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 0
6 1 1 0 0 0
7 1 1 1 1 1

Logic Diagram
Using NAND Gates
Full Adder:
Truth Table

Logic Diagram Using Basic Gates
Using NAND Gates:

Procedure:
1.Obtain the Boolean Expressions for full adder and full subtractor (sum & Carry) by writing
the truth table and simplifying with the help of K-map.
2.Make the connections as shown in the logic diagram.
3.Apply different combinations of inputs according to the truth table and verify the
outputs.
4.Repeat the above procedure for all the circuit diagrams.
RESULT:
VIVA QUESTIONS:
1)What is a full adder?
2)What is a full subtractor?
3)Obtain the minimal expression for above circuits.
4)Realize a full adder using two half adders
5) Realize a full subtractors using two half subtractors

EXP. NO : DATE:
FOUR BIT BINARY ADDER
AIM:
To design and implement 4-bit adder and subtractor using IC 7483.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40
THEORY:
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can
be constructed with full adders connected in cascade, with the output carry from each full adder connected
to the input carry of next full adder in chain. The augends bits of ‘A’ and the addend bits of ‘B’ are
designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through the full adder. The input carry to the adder is C 0 and it ripples
through the full adder to the output carry C4.
Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a
previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in
the sum being an input carry. The output of two decimal digits must be represented in BCD and should
appear in the form listed in the columns.ABCD adder that adds 2 BCD digits and produce a sum digit in
BCD. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce
the binary sum.
LOGIC DIAGRAM:
BCD ADDERS:
TRUTH TABLE:
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
K MAP
Y=S4(S3+S2)
TRUTH TABLE:
BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
PROCEDURE:
1.Connections were given as per circuit diagram.
2.Logical inputs were given as per truth table
3.Observe the logical output and verify with the truth tables.
RESULT:
VIVA QUESTIONS:
1.What does a 4-bit adder do?
2.What is an 8 bit adder?
3.What are the two types of basic adder circuits?
4.What is the function of parallel adder?

MICROPROCESSOR LAB

EXP. NO : DATE:
A.ADDITION OF TWO 8 BIT NUMBERS
AIM: To write an ALP for the addition of two 8 bit numbers using TASM software.
APPARATUS REQUIRED:
i) PC
ii) TASM software
ALGORITHM:
PROGRAM:
ASSUME CS:CODE
CODE SEGMENT
START:
ORG1000H
MOV AL,0031H
MOV BL,0021H
ADD AL,BL
MOV SI, 2000H
MOV[SI],AL
INT 03H
CODE ENDS
END START
RESULT:
INPUT: 1 OPR1 = 0031H OPR2 = 0067H
OUTPUT: RES = 0098 H
INPUT: 2 OPR1 =
OPR2 =
OUTPUT: RES =

B. SUBTRACTION OF TWO 8 BIT NUMBERS
AIM:To write an ALP for the subtraction of two 8 bit numbers using TASM software.
APPARATUS REQUIRED:
i) PC
ii) TASM software
ALGORITHM:
PROGRAM:

ASSUME CS:CODE
CODE SEGMENT
START:
ORG1000H
MOV AL,0031H
MOV BL,0021H
SUB AL,BL
MOV SI, 2000H
MOV[SI],AL
INT 03H
CODE ENDS
END START
RESULT:
INPUT: 1 OPR1 = 0085H

OPR2 = 0061H
OUTPUT: 2 RES = 0024H
INPUT: 2 OPR1 =
OPR2 =
OUTPUT: RES =

EXP. NO : DATE:
ADDITION OF TWO 16 BIT NUMBERS

AIM: To write an ALP for the addition of two 16 bit numbers using TASM software.
APPARATUS REQUIRED:
i) PC
ii) TASM software
ALGORITHM:

PROGRAM:
ASSUME CS:CODE
CODE SEGMENT
START:
ORG1000H
MOV AX,8888 H
MOV BX,3333H
ADD AX,BX
MOV SI, 2000H
MOV [SI],AX
MOV [SI+2],CX
INT 03H
CODE ENDS
END START
RESULT:
INPUT: 1 OPR1 = 8888 H

OPR2 = 3333 H
OUTPUT: RES = BBBBH
INPUT: 2 OPR1 =
OPR2 =
OUTPUT: RES =

EXP. NO : DATE:
MULTIPLICATION OF TWO 8 BIT NUMBERS

AIM: To write an ALP for the multiplication of two 8 bit numbers using TASM software.
APPARATUS REQUIRED:
i) PC
ii) TASM software
ALGORITHM:

PROGRAM:
16-bit mul
ASSUME CS:CODE
CODE SEGMENT
START:
ORG1000H
MOV AL,0025H
MOV BL,0003H
MUL BL
MOV SI, 2000H
MOV [SI],AL
INT 03H
CODE ENDS
END START
RESULT:
INPUT: 1 OPR1 = 0025H

OPR2 = 0003H
OUTPUT: RES = 004BH
INPUT: 2 OPR1 =
OPR2 =
OUTPUT: RES =

EXP. NO : DATE:
DIVISION OF TWO 8 BIT NUMBERS
AIM: To write an ALP for the division of two 8 bit numbers using TASM software.
APPARATUS REQUIRED:
i) PC
ii) TASM software
ALGORITHM:

PROGRAM:
ASSUME CS:CODE
CODE SEGMENT
START:
ORG1000H
MOV AL,0030H
MOV BL,0002H
DIV BL
MOV SI, 2000H
MOV[SI],AL
INT 03H
CODE ENDS
END START
RESULT:
INPUT: 1 OPR1 = 30 H
OPR2 = 02 H
OUTPUT: QUE = 15H

REM = 00 H
INPUT: 2 OPR1 =
OPR2 =
OUTPUT: QUE =
REM =

EXP. NO : DATE:
A.ASCENDING OREDR
AIM: To write an assembly language program to sorting of numbers in an ascending in a

given series by using MASM software.
APPARATUS REQUIRED: i) PC
ii) MASM software
ALGORITHM:

PROGRAM:
assume cs:code,ds:data
data segment
org 1000h
list db 05h,06h,03h,02h,09h
data ends
code segment
start: org 2000h
mov ax,data
mov ds,ax
mov cl,04h
mov dl,04h
l1: mov dl,cl
mov si,offset list
l2: mov al,[si]
cmp al,[si+1]
jc l
xchg al,[si+1]
mov [si],al
l: inc si
dec dl
jnz l2
dec cl
jnz l1
mov si,3000h
mov [si],al
int 03h
code ends
end start
RESULT:
INPUT: 1 LIST = 05h,06h,03h,02h,09h
OUTPUT: 1 SORTING LIST IS = 02H,03H,05H,06H,09H

INPUT: 2
OUTPUT: 2
EXP. NO : DATE:
B.DECENDING ORDER
AIM: To write an assembly language program to sorting of numbers in an descending in a

given series by using MASM software.
ii) MASM software
ALGORITHM:

PROGRAM:
data segment
org 1000h
data ends
code segment
start: org 2000h
mov ax,data
mov ds,ax
mov cl,04h
mov dl,04h
l1: mov dl,cl
mov si,offset list
l2: mov al,[si]
cmp al,[si+1]
jnc l
xchg al,[si+1]
mov [si],al
l: inc si
dec dl
jnz l2
dec cl
jnz l1
mov si,3000h
mov [si],al
int 03h
code ends
end start
RESULT:
OUTPUT: 1 SORTING LIST IS = 09h,06h,05h,03h,02h

INPUT: 2
OUTPUT: 2
EXP. NO : DATE:
A.SMALLEST NUMBER
AIM: To write an assembly language program to sorting of numbers in an smallest number
in a given series by using MASM software.
ii) MASM software
ALGORITHM:

PROGRAM:
data segment
org 1000h
data ends
code segment
start: org 2000h
mov ax,data
mov ds,ax
mov cl,04h
mov si,offset list
mov al,[si]
l1: cmp al,[si+1]
jc l
xchg al,[si+1]
l: inc si
dec cl
jnz l1
mov si,3000h
mov [si],al
int 03h
code ends
end start
RESULT:
OUTPUT: 1 AL=02h
INPUT: 2
OUTPUT: 2

EXP. NO : DATE:
B.LARGEST NUMBER
AIM: To write an assembly language program to sorting of numbers in an largest number
in a given series by using MASM software.
ii) MASM software
ALGORITHM:

PROGRAM:
data segment
org 1000h
data ends
code segment
start: org 2000h
mov ax,data
mov ds,ax
mov cl,04h
mov al,00h
mov si,offset list
mov al,[si]
l1: cmp al,[si+1]
jnc l
xchg al,[si+1]
l: inc si
dec cl
jnz l1
mov si,3000h
mov [si],al
int 03h
code ends
end start
RESULT:
OUTPUT: 1 AL=09h
INPUT: 2
OUTPUT: 2


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DE&MP LABORATORY II B.

TTL -Transistor-transistor logic

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 1

1. Place the breadboard gently on the observation table.

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 2

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 3

1. Why NAND & NOR gates are called universal gates?

2. Realize the EX – OR gates using minimum number of NAND gates?

4. What is the principle of logic gates?

5. Which is the most commonly used logic family?

REALIZATION OF A LOGIC GATES USING NAND AND NOR

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 4

TTL -Transistor-transistor logic

NAND gate as AND gate using IC7408

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 5

NAND gate as OR gate using IC7432

NAND gate as NOT gate using IC7404

NAND gate as NOR gate using IC7402

NAND gate as Ex-OR gate using IC7486

NAND gate as Ex-NOR gate using IC4077

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 6

Logic Diagram Truth Table

NOR gate as AND gate using IC7408

NOR gate as OR gate using IC7432

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 7

NOR gate as NOT gate using IC7404

NOR gate as NAND gate using IC7400

NOR gate as Ex-NOR gate using IC4077

NOR gate as Ex-OR gate using IC7486

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 8

2) What is a Min term and Max term

3) What is meant by canonical representation?

4) What is K-map? Why is it used?

5) What are universal gates?

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 9

COMPONENTS REQUIRED: IC Trainer kit, IC 7400, IC 7402

1. De Morgan theorem states that

De-Morgan’s theorem is highly useful to simplify the Boolean expression

1.Test all the IC packages using digital IC tester.

1.What is the use of De Morgan's theorem?

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 11

2.What are the importance of de Morgan's theorems in Boolean algebra?

3.What are DeMorgan's theorems prove algebraically the DeMorgan's theorems?

4.How do you remember DeMorgan's law?

HALF ADDER & HALF SUBTRACTOR

7 Patch chords Few

Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B )

Half Adder Using Basic Gates

Half Adder Using NAND Gates

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 13

Half Subtractor Using Basic Gates

Truth Table Circuit Diagram

Dec INPUTS OUTPUTS

Using NAND gates

2. Make the connections as shown in the logic diagram.

4. Repeat the above procedure for all the circuit diagrams.

VEMU INSTITUTE OF TECHNOLOGY, Dept of ECE. Page 14

2)What are the applications of adders?

3)What is a half subtractor?