UNIT 5: DIGITAL ELECTRONICS

Number system and codes. Logic gates AND. OR. NOT.NAND. NOR and their
truth table, Boolean logic theorems. De’Morgans Theorem. Karnaugh Map,
Half Adder, Full adder 1’s and 2’s complement Subtracter, Flip-flop (RS.JK.
D. T. MS).
With the help of half adder, we can design circuits that are capable of
performing simple addition with the help of logic gates.

Let us first take a look at the addition of single bits.

0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10
These are the least possible single-bit combinations. But the result for 1+1
is 10. Though this problem can be solved with the help of an EXOR Gate, if
you do care about the output, the sum result must be re-written as a 2-bit
output.

Thus the above equations can be written as

0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10

Here the output ‘1’of ‘10’ becomes

the carry-out. The result is shown in
a truth-table below. ‘SUM’ is the
normal output and ‘CARRY’ is the
carry-out.

INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0 Half Adder Circuit
0 1 1 0
1 0 1 0
1 1 0 1

From the equation it is clear that this 1-bit adder can be easily implemented
with the help of EXOR Gate for the output ‘SUM’ and an AND Gate for the
carry. Take a look at the implementation below.
For complex addition, there may be cases when you have to add two 8-bit
bytes together. This can be done only with the help of full-adder logic.

Full Adder
This type of adder is a little more difficult to implement than a half-adder.
The main difference between a half-adder and a full-adder is that the full-
adder has three inputs and two outputs. The first two inputs are A and B
and the third input is an input carry designated as CIN. When a full adder
logic is designed we will be able to string eight of them together to create a
byte-wide adder and cascade the carry bit from one adder to the next.
The output carry is designated as COUT and the normal output is designated
as S. Take a look at the truth-table.

INPUTS OUTPUTS
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
From the above truth-table, the full adder logic can be implemented. We
can see that the output S is an EXOR between the input A and the half-
adder SUM output with B and CIN inputs. We must also note that the COUT
will only be true if any of the two inputs out of the three are HIGH.
Thus, we can implement a full adder
circuit with the help of two half adder
circuits. The first half adder will be
used to add A and B to produce a
partial Sum. The second half adder
logic can be used to add CIN to the
Sum produced by the first half adder
to get the final S output. If any of the Full Adder Circuit
half adder logic produces a carry,
there will be an output carry. Thus, COUT will be an OR function of the half-
adder Carry outputs. Take a look at the implementation of the full adder
circuit shown below.
Though the implementation of larger logic diagrams is possible with the
above full adder logic a simpler symbol is mostly used to represent the
operation. Given below is a simpler schematic representation of a one-bit
full adder.
 Single-bit Full Adder
With this type of symbol, we can add two bits together taking a carry from
the next lower order of magnitude, and sending a carry to the next higher
order of magnitude.

HALF-SUBTRACTOR
Half-subtractor is used to subtract one binary
digit from another to give DIFFERENCE output
and a BORROW output. The truth table of a
Figure 1
half-subtractor is shown in figure.

Here, the DIFFERENCE i.e. the D output is

an EX-OR gate and the BORROW i.e. Bo
is AND gate with complemented input A.
Figure shows the logic implementation of a
half-subtractor. Comparing a half-subtractor
Figure 3
with a half-adder, it can
be seen that, the
expressions for SUM and
DIFFERENCE outputs are
same. The expression for
BORROW in the case of
the half-subtractor is
more or less same with Figure 2
CARRY of the half-adder. However, the case of BORROW output the
minuend is complemented and then ANDing is done.

FULL SUBTRACTOR
Full subtractor performs subtraction of two bits, one is minuend and other is
subtrahend. In full subtractor ‘1’ is borrowed by the previous adjacent
lower minuend bit. Hence there are three bits are considered at the input of
a full subtractor. There are two outputs, that are DIFFERENCE output D and
BORROW output Bo. The BORROW output indicates`that the minuend bit
requires borrow ‘1’ from the next minuend bit. Figure shows the truth table
of a full
subtractor. The K-maps for the two outputs are shown in figure. If we
compare DIFFERENCE output D and BORROW output Bo with full adder`it
can be seen that the DIFFERENCE output D is the same as that for the SUM
output. Further, the BORROW output Bo is similar to CARRY-OUT. In the
case of a half-subtractor, A input is complemented similar things are carried
out in full subtractor.

Figure below shows the implementation of full subtractor using logic gates.
Basic Flip Flops in Digital Electronics
Flip flops are actually an application of logic gates. With the help of Boolean
logic you can create memory with them. Flip flops can also be considered as
the most basic idea of a Random Access Memory [RAM]. When a certain
input value is given to them, they will be remembered and executed, if the
logic gates are designed correctly. A higher application of flip flops is helpful
in designing better electronic circuits.
The most commonly used application of flip flops is in the implementation of
a feedback circuit. As a memory relies on the feedback concept, flip flops
can be used to design it.
There are mainly four types of flip flops that are used in electronic circuits.
They are
1. The basic Flip Flop or S-R Flip Flop
2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop
4. T Flip Flop

1. S-R Flip Flop

The SET-RESET flip flop is designed with the help of two NOR gates and also
two NAND (Appendix-1) gates. These flip flops are also called S-R Latch.

S-R Flip Flop using NOR Gate

The design of such a flip flop includes two inputs, called the SET [S] and
RESET [R]. There are also two outputs, Q and Q’. The diagram and truth
table is shown below.

Basic flip-flop circuit with NOR gates

From the diagram it is evident that the flip flop has mainly four states. They
are
S=1, R=0—Q=1, Q’=0
This state is also called the SET state.
S=0, R=1—Q=0, Q’=1
This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of
each other and that the value of Q follows the value of S.
 S=0, R=0—Q & Q’ = Remember
If both the values of S and R are switched to 0, then the circuit remembers
the value of S and R in their previous state.
S=1, R=1—Q=0, Q’=0 [Invalid]
This is an invalid state because the values of both Q and Q’ are 0. They are
supposed to be compliments of each other. Normally, this state must be
avoided.
 Clocked S-R Flip Flop
It is also called a Gated S-R flip flop.
The problems with S-R flip flops using NOR and NAND gate is the invalid
state. This problem can be overcome by using a bistable SR flip-flop that
can change outputs when certain invalid states are met, regardless of the
condition of either the Set or the Reset inputs. For this, a clocked S-R flip
flop is designed by adding two AND gates to a basic NOR Gate flip flop. The
circuit diagram and truth table is shown below.

Clocked SR flip-flop
A clock pulse [CP] is given to the inputs of the AND Gate. When the value of
the clock pulse is ‘0’, the outputs of both the AND Gates remain ‘0’. As soon
as a pulse is given the value of CP turns ‘1’. This makes the values at S and
R to pass through the NOR Gate flip flop. But when the values of both S and
R values turn ‘1’, the HIGH value of CP causes both of them to turn to ‘0’ for
a short moment. As soon as the pulse is removed, the flip flop state
becomes intermediate. Thus either of the two states may be caused, and it
depends on whether the set or reset input of the flip-flop remains a ‘1’
longer than the transition to ‘0’ at the end of the pulse. Thus the invalid
states can be eliminated.
2. D Flip Flop
The circuit diagram and truth table is given below.

Clocked D flip-flop

D flip flop is actually a slight modification of the above explained clocked SR

flip-flop. From the figure you can see that the D input is connected to the S
input and the complement of the D input is connected to the R input. The D
input is passed on to the flip flop when the value of CP is ‘1’. When CP is
HIGH, the flip flop moves to the SET state. If it is ‘0’, the flip flop switches
to the CLEAR state.
To know more about the triggering of flip flop click on the link below.

3. J-K Flip Flop

The circuit diagram and truth-table of a J-K flip flop is shown below.

Clocked JK flip-flop
A J-K flip flop can also be defined as a modification of the S-R flip flop. The
only difference is that the intermediate state is more refined and
precise than that of a S-R flip flop.
The behavior of inputs J and K is same as the S and R inputs of the S-R flip
flop. The letter J stands for SET and the letter K stands for CLEAR.
When both the inputs J and K have a HIGH state, the flip-flop switch to the
complement state. So, for a value of Q = 1, it switches to Q=0 and for a
value of Q = 0, it switches to Q=1.
The circuit includes two 3-input AND gates. The output Q of the flip flop is
returned back as a feedback to the input of the AND along with other inputs
like K and clock pulse [CP]. So, if the value of CP is ‘1’, the flip flop gets a
CLEAR signal and with the condition that the value of Q was earlier 1.
Similarly output Q’ of the flip flop is given as a feedback to the input of the
AND along with other inputs like J and clock pulse [CP]. So the output
becomes SET when the value of CP is 1 only if the value of Q’ was earlier 1.
The output may be repeated in transitions once they have been
complimented for J=K=1 because of the feedback connection in the JK flip-
flop. This can be avoided by setting a time duration lesser than the
propagation delay through the flip-flop. The restriction on the pulse width
can be eliminated with a master-slave or edge-triggered construction.

4. T Flip Flop
This is a much simpler version of the J-K flip flop. Both the J and K inputs
are connected together and thus are also called a single input J-K flip flop.
When clock pulse is given to the flip flop, the output begins to toggle. Here
also the restriction on the pulse width can be eliminated with a master-slave
or edge-triggered construction. Take a look at the circuit and truth table
below.

Clocked T flip-flop
QB 37. Show

INVERTER/NOT
AND
A OR
AND
A AND INVERTER/NOT
AND INVERTER/NOT INVERTER/NOT
B AND B
OR
AND
C
D
INVERTER/NOT
C OR

INVERTER/NOT
D
 A B AB C D CD ABCD
0 0 0 0 0 0 0 1
0 1 0 0 1 0 0 1
1 0 0 1 0 0 0 1
1 1 1 1 1 1 1 0

A B C D

0 1 0 1 1 0 1 0 1 1 1
0 1 1 0 1 0 1 1 0 1 1
1 0 0 1 1 1 0 0 1 1 1
1 0 1 0 0 1 0 1 0 0 0

The truth tables are equal therefore the Boolean equation must be equal.

QB 38. Show

A OR INVERTER/NOT
A+B A AND
B INVERTER/NOT
B AND
OR INVERTER/NOT
INVERTER/NOT AND
C
C OR INVERTER/NOT
A+B+C+D
D
D C+D

A B A+B C D C+D A+B+C+D

0 0 0 0 0 0 0 1
0 1 1 0 1 1 1 0
1 0 1 1 0 1 1 0
1 1 1 1 1 1 1 0
 A B C D
0 1 0 1 1 0 1 0 1 1 1
0 1 1 0 0 0 1 1 0 0 0
1 0 0 1 0 1 0 0 1 0 0
1 0 1 0 0 1 0 1 0 0 0
The truth tables are equal therefore the Boolean equation must be equal.

QB 42 Write the Boolean Expression for the output Y in the following figure.

A B A+B C D A+B
0 0 0 0 1 0 1 0 0 0
0 1 0 0 1 1 1 0 0 0
1 0 0 1 0 0 0 0 1 1
1 1 0 1 0 1 1 0 0 0

QB 42 Write the Boolean Expression for the output Y in the following figure.
 A B A
0 1 0 0 0 1 0 0 1
0 1 1 1 0 0 0 1 0
1 0 0 0 1 1 1 1 0
1 0 1 0 1 0 0 1 0

QB 48 SIMPLIFY IT

HENCE PROVED
Introduction to Karnaugh Map
For n variable k-map 2n cells are required. Therefore for 2-variable k-map
22=4 cells will be required, for 3-variable k-map 23=8 cells will be required
and if 4-variable are used then k-map 24=16 cells will be required.
For 2-variable k-map representation is of any one from the following:

B B
B
A 0 1 A A 0 1
0 00 01 0 0 1
1 10 11 1 2 3

Fig. A Fig. C
Fig. B

The boxes in Fig. C are just the binary representation of boxes in Fig. A
For 3-variable k-map representation is of any one from the following:

BC
 A 00 01 11 10
0 0 1 3 2
1 4 5 7 6
For 4-variable k-map representation is of any one from the following:

CD
AB 00 01 11 10
00 0 1 3 2
01 4 5 7 6
11 12 13 15 14
10 8 9 11 10
Note: The variables format represented in the k-map is not to be changed.
The representation of CD topmost number is in the form of gray code with
difference of 1. the first is 00 the next is 01 i.e. 0 to 1 next is 11 i.e. 0 to 1
next is 10 i.e. 1 to 0, only one bit is changed.

QB 71. Solve the Boolean Equation using Karnaugh Map

By using Boolean Postulates we can reduce the equation:

OR
By using TRUTH TABLE we can reduce the equation:

A B B AB
0 1 0 1 0 0 1 1
0 1 1 0 1 0 0 1
1 0 0 1 0 0 0 0
1 0 1 0 0 1 0 1
B
B
A 0 1 A
0 1 1 1 1
1 0 1
0 1

Fig. A
Fig. B

For 3-variable k-map representation is of any one from the following:

A BC
00 01 11 10
0 1 0 1 1 1 3 0 2
1 1 4 0 5 1 7 0 6

OR

BC
A

1 0 1 1 1 3 0 2

1 4 0 5 1 7 0 6
For 4-variable k-map representation is of any one from the following:

CD

AB 00 01 11 10
00 1 0 1 1 1 3 X2
01 1 4 X5 1 7 X6
11 112 1 13 115 X14
10 18 X9 X11 X10

OR

For 4-variable k-map representation is of any one from the following:

CD

AB
1
RR0 I V A1
R 1I V A 1
R3 x2
1I 4 x5 17
R x6
I
1VR12I V A113 115 x14
I
1
A8 x9 x11 x10