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    vlsi physical design all inputs

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    vlsi physical design all inputs

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    Download as pdf
    3 views21 pages

    pd_inputs

    Uploaded by

    Teja Chode
    vlsi physical design all inputs

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    Download as pdf
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Er — fost Fast > Medium “ tb > Agpieet Aypicat slow —> Low fac) Sloe 3 fe calculated by ip -tranation % de load bac! on fookup tobles hp & basically a -Lirning model contains — and fod tire reqtatrernents cell delays, transitlen, hr ay I clo qroemte lb files. % ccs ond nicpm techniques are used ces — Composite cuen) Source mpm Neon Lfheat Delay Model. do colcellate teeta ~~) In © © hawng +the more variables olp lead: calcelate ty NEOM ise qe DeWgguibe lece variables Jo > €bransthon) — § ap Iwadl- > eco ee aecurale when compared She NEON > cee 10 Hee larger than NLDM file Shes unsties nemmmmepenearenyoret O02" ye destn needs to be testecl fer certain Pvt Comers Buk every PyT Comer , the Himing of the celle ore different torne x djence | thevcueaeaies ib file for every PVT pe ieee Me -fellowing unit altaibutes are pre sent / Tame Unit — Velkoge Unit — Garrent Unit ODnOogopgIopgagh oF * @ oo gssZy, - leakage Power Unit = Capacitive lood Unik — dew rate 2 Lower and Upper \mik values aie cleBined wf both we on fall Hine fn -+tenns OF percentage a =p threshold at cise ard fall Wme- a > ob -threchol fey rie ond fall me: a defined for different paramekyh se Liseup table templates are with different ome ite tike. delay , hold, Tecovent, removal, selup y= oe for each call (AND, NANO, ele) Following attributes am deFined > Area of cell: 9 beakage power ee (2 f= {> {2 [2 ooeod. VOVHLLLEULECCELUS EEE OG > Rie => and Fal) Gpactt Proper te 1 ance perties auch as clreclton of dhe pie defined for each ete Pin Cippur and output) eet wt i G Clock op data x + Ihe 4 si je okerms wo dimer n © dimensional model are faker shaneiti ‘ hien Hime gh the Constrained ~ Pl ae i pee aoe respectively «7 ri sew and —ing the lock tf oy clock -transitten (ck) ot t go fee for the THING | pn osune) Sc aeeean a es ee) | ener One le EF \ the related — Pin (elock. pin ck) dalc ransttten) (CO /Momntucmaaed edep dhe rising deta D pin vise —hansitien Shansjhon the» Deane “lable) - 5 calculate |] ues . assumed PE eee. q che assume call Bl | edge of athe ise. censhaint blive lood — ie havior slut phis — Net deloy Piralysing wlib filet \ebrory (( Sa0ed2e hve — C dviver- nmodel , Nbrary ¢ shing) opk, library , shing) 5 Wbrary, shriog) davis —thepre vizse 10 78 Y ) define ( def _ sinn- ( Simulator 5 ; Lechnelogy Comes) 3 5B yy yn & tee setup -thing Bee teckup "5 delay redel = “table a Wold sing ero eam ce For 9878 pio dete * aeeaes eleven erising - seloy 4 rel canst Semoval — isin Soon eee ott 2 “Y put leakage-Par uw Volta.ge- writ Current unt 2 “ypa" Cerpacirante__ oad — Unit + ( beven0e, \ 44 "he Iv TT ee default _ leakage power. density ¢ 0:0° Tip— threshold’ peba eho Ole u - rise igs ip u oral ae 2 ; 5 : : 20.9000°% Sle jower — Lieshold ==ae Z_ gy. coo ~ u Sole Z upper — i slew eavotenpes 1.000000 & tate stead Gia @a) t capacitance resistance ee canelen th slope nw t area “i \g- 268) fenour tengin ( Waa C 20" \ 3 26650) Peery tir yo eae eee fanout length CI o ---) erly wolre-load C teo00") Fea pacttance anor C! 90 ~--) —™ wirelead (35000 me Gam ji, (140080) vy (20000) Vil, SYoorO jy oe x BOL Ki, YO xi, goL Ally He. For &_ lv, beo0o e Wie ~ 004 _ Selection (Pred cops) Barge cpenplate (Paver Piao) Powe operading Meee lvl Opa RSC | icp av) Ju, table template (del! poe o/F ) (Loot) dsiver waveform ) PPPPPPPPERPPPRPPPPP HPP P YPoV ooo os geass Ccecdsdidésea if ce PeCCCCEC CEC ECCLEEEESEES Power _ lu temp cell CLSDNENe LSx(_Hvt) Papin (nw. vpn) volkage- name! 0g-*4PE nwetl} Chysicel Connection = device- layer ip volage range olp 5 6 ; level chiles type = av arene cell leakage power lwacl pio EN) | = Gren Giaume ia Signet, Fanout bac pin & | Pirly defo whelead ! “Fer an" lead celechisn + "pred caps Fer Cell CAwD gate) rise- eevee cee too ce (ANP 2x)-WT? cana — transite Internal Power ) Cell footprint ushen Eee = rise power ©) cell_leakage fe Seat driver. wowetarrn- V5 & spines driver — waveform - fall fol power O) , incor leakage — pou © ~ values osheny internal power ©) value : plo dy _ pin Cvoo) et pinty Monlog veltoge Nome velated ewer pin Meee ok 99 - t4P* alared grees! pi | -tming - sense pio) dlrection: tees | Aeneur — lead paiuer dour function i related — peer —plo output — voltage ee function values elated ~ qcund—plo Are ctlen fell. capeeltane fal capac! Fame - ¥ capoctian® ae capacitors ange marscapecttante. larite trasayy rar cition Max — transition Fndex ) Tnterna) . powert ) thoex Telated _ pin Value: : rise. pous c fall power intey nod — ce) DeLee ee tu econ —_ ™M, es PLL telee > te" ct 19i9 cutie layers- t Apour cmetel 14 ‘ fevel gn feehlef ’ Size ‘ ph . Pin avo ts jrevenetty| = , 5 Direction IN ,but at d Use signal ‘ vias: 7 > N wel) F in for Sqyae bi — Metat lager Ma Sy - VIO wy é vetkongalay YO > Mia via hart & bar’- dueferent “YP= large Or é > Spacing via g- Thee ow stand . — Cell q —> Pork 7 { 3 yes 12-6 oc The LEF fle {¢ the ahenecememerny ce cciay oth aly gna 3 ee cell. idea ebouk pin position ond metal layer infor ratio? } ‘ Jn ths 2 Sections awe defined: be < Technology o a. site 6 2. Macros p Ty the technology part layers, design mules, via definitions and mMetol capacitances cue dePined- é Cte = ste edension ts defined aod In the “macros the Toor e _emotion obour cell descripHon, dimension, layeuk of pins & and blockages gre capacitances are defined. & , « 3 For every technology the layer edhe Wel ctalameiia are ~ « aiffemnk ce qdtt a theg lnyer 04 VERs ithe _Aype of the loyer_ y @ dype,-wostersitce ox overlap) » ust /riicha, C er my be -routt ond antenna © J, dlveckion, vesistence, Capacitance, Fre) Goo fecter ae depined It Contains mame of the Pim pin location pin Byer, direction OF Hbe pin, ste wane Mog fry ape Ghia Q Ber a dadins tf - tbe Pin ard cell, e ee e ef ée Cell view ~ " Forn view . & “3 ~The resistance Of a wire can [eee *» RpERseU x wire length J wire whdth caper tan s MG x Resistance R FER sq value + : ; tre, in ohme per" S Specifies the cvesistaner fer 6 54-5 wre ~> mp rence era perance Value + oxo ns Specifies the eapegttans| iter eon) = ere auaas in preof S Per Sqyore amicron 2 “This ig used to -medel wlre —to- qreund Gapacitance- oJ Tech. lef cell. teF = ‘ sus I Version 65 version S42 s : WAME CASE SENSTTIVE on 3 Name cASE SENSITIVE ONS > pe? > BuspiTcHARS “C 3's Buspir ARS <7 2 DWIDER CHaR "7" 5 piper cae "J Gf - 2- Macro TN BOFFX2 — \UNT wp 2 veins ciAce Core 2 DATA BASE WMilerDNIs 10005 coute User o End Units ongio Mani farchurin d cool; size onze Be et ' > gq qd ocols 2 Symmetry > ¥ PAO | P sile vniks v. Layer NWELL 2. ein EN | , > Type Macler slice 5 pirection Toput 4 ¥ End ances Using Signet 3 i . : Layer © pork 5 ' > Type uk ayer MIS Spacing 0054 END ‘ PORT o > ESD nese) layer co > Layer MM (Mekal lay gS ele f a Ene > Type eee ee ANTENNA GATE AREA ? Oirection # Here END EN , prtrch PLN voP s Ye | Givectay Sound ee j Use pewER Spacing table paralle) we length rae | layer my aS Max width Mto wich layer wo a MINENCLOSEPD Area ee CAPMULT IPLIER Direction out Use GiROUNP _ Min.denctty | Max. dencrly Port 1 Densfly check window a pe joy CO Denstly check Step ie 2S End > eke Pio Min. Denci ly Es + Max. Denstt- ee S Layer vIn X These will be no. of Sra pe cob se In the -mocras there Of defined = Tead- Sete - & Usile _ede —output > Cony mame) # erie Wri ae - Output ere sde _picea— shat > Oper i [orf v sop. We oR” Desiqn Bical oueiey lab‘o Been. vicck/ Beck tele | cd Ritcoln- Design ~vi [ bitcoin- via] sde [bik Pe? ade a, ile Jel tole f cael A Sgreeet= data / Synepsys TeL- Sevipting) re —t- 2oIs -00/ Sextol-s [| exca— const _fune » tcl ce ae nue Pose TP OCC CE EE fo Censtraly tip [ole rest —pVirtunt \Gasaite — clock! OR een ee yee] as a reference “the. tater Pace PICS Piped pute of clk cde - OD Hue dodt gie op delay % ust Jake unt( the ctk ; default take a em es 4 cycle onda, Boul: & tate" on et. 4 wm aor lle cugcle - SE ue dent give fh delay values then the a cre Wake the clk fren ‘o! _ Onwor ——— al upr | cre Corrmon Power Formate (Cader Unified Power Formate je Low Power cells t= (Sqnopeys joo!) 1 level shifters Enable level shifter Cworl Rin ve : leve hiPker Cworlsg Bnction of eyeneey aman gn te law “den Law te high: 2. Teolation cells f eon . clomp | atch type Cpelestion | teelation) 3. Always PS cee EY (Gente ae 4. Power witches 5. Retention Cells Muttivoo - levelahifler we ose oSeg ‘ onitorr stale — ve on US ton x Levd ShiPhers t= Bike, § ae — High to lows 7 vpn 29 -” Rwer a eal ewitch - onl OFF = av ¥ oe — = & When fp given “1! a = = Gemblnation fedlation cels © Retention cells ore called os" Greble silt Regist“ Latch ype & 2 5 we FSCO EEEEEE EEC * Alurays ON) CFF t= TP Always on, then the Gell 1s ON Condition TF pilways ofr, then the eell (2 OFF condl/HO?- * Tedation cells clamp ‘o (AND) gete 2 clamp \! (6) gate 3 Late rer = | oxunng, ove) hough dhe cell & th ‘ocr’ Comitienmeomatne desk fer rg X To overcome this we use clamps Ff chomp ag ate these the design wept ger damaged % RetenHen Cells:- - | Aransfering the cok dala od Retention Gl When the -plipflop §© in OFF CondiHen, uohile & hen the device be cause is one eee wees previous of Retention ce Ne sranomittes, % Lateh-up “ype (Retention 4 Teolation) : & Power Switches: 3 % Lous Power = See ee ied: nents of pause as much Os pessible, hence decy Jota pour consumption « SucHtching and shesk ciscuih | power vist design to -wintmize the easing the ee up fhe pee pourr, Where ar leakage Cerrent thay Peta gcotbaamron Ee Wekeup the Static Power. Sie ivi Sant ace * 4 Thereasing hatte Promeas Ble ee ng lng pe —Ficant i ciiFferentlat - Graclal “lo the aypliccdione Consumrplion tm a Algnl eed by Weir end users an Static ¢ for eyperm'e * The power equation eantaine components Pe on X there on stedtic pour ih campricnl oF lated’ a a flows hough the transistor when there fs activity “" Faders (power Component % elated) Ss AcHvity “4 Pere : Fransition Time 2 Capacitive load my voltage +] Jeakage curtent 4 peck — caren * yw For example ~ igh vollage, the higher power toneurned by each component = esultiag 0 higher overall power i a Javer the pevall power. x lower the volFage, the e To achleve thesegel pev formance whith the fowest- Power Cone —-mption, trade offs Gor cosh) Sates different Sectors ae technique> and Lived ond -necled — VCCUSSSag jouw poet —me thelegie® PPP RP PMH Hs » Pp UpE (Unified Power Format) ! i‘ a contains power domain, creahenig operating conditions of +the x i 2 domaine level shifters, Suiteh Gis, Retention Flor, cells CIscktien, e low pout : Always on/or#). im to che upply se He le 5 te tise ee dlemtlias . lo powe » eas 49 te conneck a Gale ay Fel ableh NN pply nets serene REM a SS Aen Weis ft cae ela under) whieh power dome expected * i) Ea pecans pected to ba power OO Coot a : switehing stHehin choud be f asa" “Teclatton ore aie aid happen © ay i ‘ S aie vel Shean ce eet fies orer~ should > sitchen ant eal cells shoul be placed pe ta ' IS + Bo ee to ee Bie paver state ables: > Hew te cecal pocer Hae ee > Tr & used 4 os a create Pala alole jab] with & epectfie > erica Ses up ply. Tete mate abe fasted Deets to en me 2 le te ener clgnieg ee hes ope oo lest ; a defined powet ate be ene ape tet & > -cuprly nets or 4 | J “4 tet ports to fnchide 0 pe ee hie oF the cesip.| ; bob ead | falas ei. Reed | ntl Comm -U pF ved ———— et ETI SK ' “1 rettsty ha de—shet + jcco tool —> fe-shell design compiler : 5 ceratch [-41ain ] ditedong | eR —Desty | cos Se? pii2022 © / Fret] RA — Top bestan- Data) Orch Top +¥ inp This is design synthests olp Netlist SS ee a > nlet tit re) igre floor plan Fy, ae a an 9 floomplan.v na Sa ‘aah P(grun eb © | len powerd ae ieee aed ey check aut apicate” Mo Formal VE > Revised Netlist evict valence Routing wb lle tave “lo vefer \ ae Revised cater evise Ke vote ove Netlist Ae cotenna eflect un ates reverse Mace (on wo (netlist) (. cHHiexorch y 2 Module Info zener diode - § olp of design thet bules tnfrnattion & Ih He Pork 5 [Aire teas fun Cagrerys: 4200 feols| cad] Sqropsys pata/ Be\ccin Dest vi / pltcolnw ol L3/ Fert / seed 32 — (Pre Crna laps. PAM — | poly 9 rrekal lajers Comin 5) setap callcastation » dobles (Cadence dort) tech/ star => (as) se we four clabie chynam -fusfon Comptley yar Bi ata ProT PY OSH HPRHHKeese se’ PBPPP PP ppp pong rep(iech fsaed sbpemap dup rey t Tuy a Yead. paronilée tech yer? shed: Cr OTE ees ecu eee fessswealiiant one t oat roa TL Scmaane ess minsnaiqep rae ——— aod yn iad oun" a a | puto u inal capacttor chargee ; Sea 2 “me interna} capacitor more ON : i cat hanged a. witlat eae charge vey -fast Sey eat tte at do sup SZ crenge*canas! te hae colt Tk can do bow Volaiiens acitan po qr has ere OF FE > Cmax aro - ass Functiono) > 58 = conOaaa worst * jest ~ Fe = errata a = best case ! ty 4-5 ap cole ateo delay | > ap coleul croble “© coleulale Tt doar tave Hut file th icles net delays in the design SH ZTE + Inerconned Technology FI Pated on TH file they can Mean js poly cxtoct Hut, tPF ete files RPSQ — Resistance fer AUers ER 5 Elechicap Refeted conenr gomelbing volue DEF Design Exchong enlib 3 Tr & pon readable - f we led oh, ie omen dort have 40 ood at) tip files) Buty FNC oe ST as can change delup Wolations. Format (Tt & editable) rracros crsi. 7 We will sek Pe Read- def nile — def pep file obo contains physteal fforrnations bub of designs CHEF cents fifo of -# cath ond rota later , the best thing fous an cuan pee amet ) _ VOvVss ste’ euunouvuunvvvevevueouesevevserve So Re sic: ‘after ECO Atages & | P8R ee at read def Toosplan def ts the th Of the new sloge. orphan | place, crs, Routing or even REPS iy entains property defini lie” Rak aia aes oy 2 rau pubit chee yj 3. twacks, on % ust “5 4 vilax, 4 5° Component es 6 pis 4 4 special velr < 8 pete p q. San chain. - > Go to tec2 Ae & open_Nib > open —tib fano_ flooplon/ - Ub _ blocks. = open —block open 10? | Fleenplan 7 = man yeocl_deP a wile _ de floosp 00 def ’ > sh vin ‘Floorplan def & mg woos oe version > ae e ‘ a . cob > design de ode dicasee paced ferecl Gated: fe ai aiacela eer unpl 5 pies Toler fae ‘ end pins € net tfer “ end cee a end design Pa open—lip lab3_ place/ RA “Top: dliib/ « itet—fplecks . open—block one cop) intr cles 0 a of one stage a foo ee seucecoesscsga 2 vuws a SOC eet esis def place def dn thin exh a ra mows, jyaeka ova tls te Abert Gh) avi guint floorplan ideP place «del? DH quien place def digarea. th there OWA Tracks trfor f& thee 4, = 999 § miro. wi xo y ort viog —foter there culstze shape enclosure ou info in Mo End vias 2 Some He fired come Fhe cele enplaced, ee 1 ae ed components pins . ple an fee cee ig énd pln special nelr placement | end special net new ection elle end nex Scan chains end —scanchains end design sh guim elf flanplandet place -deF -fiom 4 do RVT come of the Gls are changed ‘ Some

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