LPC1768_manul

LPC1768DEVELOPMENT BOARD Technical Reference Manual
ARM [LPC1768] Development Board

USER MANUAL
SILICON MICRO SYSTEMS

#80, GANDHI BAZAARMAIN ROAD, BASAVANAGUDI,
BANGALORE – 560 004
Ph: 080 – 22425830/31
080 – 26609313/23
Website : www.simindia.net
Email: info@simsindia.net
Silicon Microsystems, Bangalore 1

INDEX
SI No. Contents Page No.
1 Board Features 3
2 SiMS LPC-1768 Board Layout 4

Power Supply Section 5
Introduction to ARM Cortex-M3 6
Reset Circuit 39
ISP and RS-232 Interface 40
Breakout I/O Connections Details 42
USB 2.0 Interface 42
3 Instruction for using the Development Board 43

4 List of Experiments 47

Board Features
1. An on-board NXP’s LPC1768 microcontroller with Cortex M3 architecture.
2. A power jack for an external power supply from 9 V to 12 V AC/DC. Alternatively the board can
also be powered through the on-board USB connector [USB1].
3. An on-board crystal of 12MHz to clock the microcontroller to up to 60MHz with

Internal PLL.
4. Two DB9 connectors to implement RS232 communication using the on-chip

UART 0 and UART 1.
5. An on-board crystal of 32.768 kHz and a battery backup for on-chip Real time
Clock.
6. Eight on-board user programmable LEDs [D9 TO D16] on selected GPIO pins with an option to
disable them using a jumper.
7. The microcontroller can be programmed using the on-chip serial bootloader

using the RS232 port [COM1].
8. Additional RS232 port [COM2] to read external serial data from external source.
9. On-board USB connector interfaced to on-chip USB peripheral of LPC1768 for

USB based communication.
10. On-board USB to Serial Convertor using FT232RL-FTDI
11. Dedicated FRC Connectors for ADC and PWM outputs [J7] and [J8].
12. Breakout FRC connectors for all I/O [J1], [J2], [J3], [J4], [J5],[J6],[J7],[J8],[J9] & [J10]
13. On Board push button Hardware Reset Circuitry.
14. On Board push button Hardware Interrupt.
15. On Board push button used in combination with Reset button to enter to ISP mode.

SiMS-LPC1768 BOARD LAYOUT
Fig: SiMS-LPC1768 BOARD LAYOUT

POWER SUPPLY SECTION

The ARM7 development board can be powered by either an external power supply or using the USB.
For external power supply adaptor, ensure that the output is in range of 8 to 16 Volts AC/DC with a
minimum current rating of 200 mA. An onboard LM317 voltage regulator is used to regulate the AC/DC
input to +5V output. Electrolytic capacitors are used to reduce the ripples in the voltage. The ceramic
capacitors are used to suppress the high frequency noise present at the output of the voltage regulator.
A 3.3V regulator is also provided for powering the microcontroller and other 3.3V operable devices on-
board. Test Points for 5V and 3.3V are provided to ensure that proper voltages are provided to the
MCU and Interfacing modules.
Fig: Power Supply Section

Introduction:
The LPC1768 is ARM Cortex-M3 based microcontrollers for embedded applications
featuring a high level of integration and low power consumption.
The ARM Cortex-M3 is a next generation core that offers system enhancements such as
enhanced debug features and a higher level of support block integration.
The LPC1768 operates at CPU frequencies of up to 100 MHz the LPC1769 operates at
CPU frequencies of up to 120 MHz the ARM Cortex-M3 CPU incorporates a 3-stage
pipeline and uses Harvard architecture with separate local instruction and data buses as
well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal
prefetch unit that supports speculative branching.
The peripheral complement of the LPC1768 includes
 512 kB of flash memory

 64 kB of data memory
 Ethernet MAC
 USB Device/Host/OTG interface
 8-channel general purpose DMA controller
 4 UARTs
 2 CAN channels
 2 SSP controllers
 SPI interface
 3 I2C-bus interfaces
 2-input plus 2-output I2S-bus interface,
 8-channel 12-bit ADC
 10-bit DAC
 motor control PWM
 Quadrature Encoder interface
 four general purpose timers
 6-output general purpose PWM
 ultra-low power Real-Time
 Clock (RTC) with separate battery supply
 70 general purpose I/O pins.
Application:
 E Metering
 Alarm systems
 Lighting
 White goods
 Industrial networking
 Motor control

ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller,
and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successors
being decoded, and a third instruction is being fetched from memory.
Features:
ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed
versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory Protection
Unit (MPU) supporting eight regions is included.
 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data
bus provides high code performance from flash.
 Up to 64 kB on-chip SRAM includes:
 Up to 32 kB of SRAM on the CPU with local code/data bus for high-
performance CPU access.
 Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
 These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as
for general purpose instruction and data storage.
 Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, the Analog-to-Digital and
 Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-
to-memory transfers.
 Multilayer AHB matrix interconnects provides a separate bus for each AHB master.
 AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and
the USB interface. This interconnect provides communication with no arbitration
delays unless two masters attempt to access the same slave at the same time.
 Split APB bus allows for higher throughput with fewer stalls between the CPU and
 DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
Serial interfaces:
 Ethernet MAC with RMII interface and dedicated DMA controller.
 USB 2.0 full-speed controller that can be configured for either device, Host, or
 OTG operation with an on-chip PHY for device and Host functions and a dedicated
 DMA controller.
 Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA
support. One UART has modem control I/O and RS-485/EIA-485 support.
 Two-channel CAN controller.
 Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.

 SPI controller with synchronous, serial, full duplex communication and programmable
data length. SPI is included as a legacy peripheral and can be used instead of SSP0.
 Three enhanced I2C-bus interfaces, one with an open-drain output supporting the full
I2C specification and Fast mode plus with data rates of 1Mbit/s, two with standard
port pins. Enhancements include multiple address recognition and monitor mode.
 I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I2S interface can be used with the GPDMA. The I2S interface supports
 3-wire data transmit and receive or 4-wire combined transmits and receive
connections, as well as master clock output.
Other peripherals:
 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with
configurable pull-up/down resistors, open drain mode, and repeater mode. All
 GPIOs are located on an AHB bus for fast access, and support Cortex-M3 bit-
banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin
of ports 0 and 2 can be used to generate an interrupt.
 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be
used with the GPDMA controller.
 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
 Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer events
can be selected to generate DMA requests.
 One motor control PWM with support for three-phase motor control.
 Quadrature encoder interface that can monitor one external quadrature encoder.
 One standard PWM/timer block with external count input.
 Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V Lithium button cell.
The RTC will continue working when the battery voltage drops to as low as 2.1 V. An
RTC interrupt can wake up the CPU from any reduced power mode.
 Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the
RTC oscillator, or the APB clock.
 Cortex-M3 system tick timer, including an external clock input option.
 Repetitive interrupt timer provides programmable and repeating timed interrupts.
 Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire
Trace Port options.
 Emulation trace module supports real-time trace.
 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-
down.
 Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.
 Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
 Non-maskable Interrupt (NMI) input.
 Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock or the USB clock.
 The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up
from any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep power-down modes.
 Processor wake-up from Power-down mode via any interrupt able to operate during
 Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).

 Each peripheral has its own clock divider for further power savings. Brownout detects
with separate threshold for interrupt and forced reset.
 On-chip Power-On Reset (POR).
 On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz
 4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a
system clock.
 An on-chip PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
 A second, dedicated PLL may be used for the USB interface in order to allow added
flexibility for the Main PLL settings.
 Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.
 Available as 100-pin LQFP (14 x 14 x 1.4 mm) and 80-pin LQFP (12 x 12 x 1.4 mm)
packages.

Introduction to Cortex M3
1. Introduction
System-on-chip solutions based on ARM embedded processors address many different
market segments including enterprise applications, automotive systems, home networking
and wireless technologies.
The ARM Cortex family includes processors based on the three distinct profiles of the
ARMv7 architecture
 The A profile for sophisticated, high-end applications running open and complex
operating systems
 The R profile for real-time systems
 The M profile optimized for cost-sensitive and microcontroller applications.
The Cortex-M3 processor is the first ARM processor based on the ARMv7-M architecture
and has been specifically designed to achieve high system performance in power- and
cost-sensitive embedded applications, such as microcontrollers, automotive body systems,
and industrial control systems and wireless networking.
1.1 Higher performance through better efficiency
In order to achieve higher performance, processors can either work hard or work smart.
 Pushing higher clock frequencies may increase performance but is also

accompanied by higher power consumption and design complexity. On the other
hand, higher compute efficiency at slower clock speeds results in simpler and lower
power designs that can perform the same tasks.
 At the heart of the Cortex-M3 processor is an advanced 3-stage pipeline core, based
on the Harvard architecture, that incorporates many new powerful features such as
branch speculation, single cycle multiply and hardware divide to deliver an
exceptional Dhrystone benchmark performance of 1.25 DMIPS/MHz
 The Cortex-M3 processor also implements the new Thumb®-2 instruction set
architecture, helping it to be 70% more efficient per MHz than an ARM7TDMI-S®
processor executing Thumb instructions, and 35% more efficient than the
ARM7TDMI-S processor executing ARM instructions, for the Dhrystone benchmark.

1.2 Ease of use for quick and efficient application development
Reducing time-to-market and lowering development costs are critical criteria in the choice
of microcontrollers, and the ability to quickly and easily develop software is key to these
requirements.
 The Cortex-M3 processor has been designed to be fast and easy to program, with
the users not required to write any assembler code or have deep knowledge of the
architecture to create simple applications.
 The processor has a simplified stack-based programmer’s model which still

maintains compatibility with the traditional ARM architecture but is analogous to the
systems employed by legacy 8-bit and 16-bit architectures, making the transition to
32-bit easier.
 Additionally a hardware based interrupt scheme means that writing interrupt service
routines (handlers) becomes trivial, and that start-up code is now significantly
simplified as no assembler code register manipulation is required.
 Key new features in the underlying Thumb-2 Instruction Set Architecture (ISA)
implement C code more naturally, with native bit field manipulation, hardware division
and If/Then instructions.
1.3 Reduced costs and lower power for sensitive markets
A constant barrier to the adoption of higher performance microcontrollers has always been
cost. Advanced manufacturing technologies are expensive and therefore smaller silicon
area requirements can reduce costs significantly.
 The Cortex-M3 processor reduces system area by implementing the smallest ARM
core to date, with just 33,000 gates in the central core (0.18um G) and by efficiently
incorporating tightly coupled system components in the processor.
 Memory requirements are minimized by implementing unaligned data storage, atomic

bit manipulation and the Thumb-2 instruction set that reduces instruction memory
requirements for the Dhrystone benchmark by more than 25% compared to ARM
instructions.
 The Cortex-M3 processor supports extensive clock gating and integrated sleep
modes. Enabled by these features, the processor delivers a power consumption of
just 4.5mW and a silicon footprint of 0.30mm2 when implemented at a target
frequency of 50MHz on the TSMC 0.13G process using ARM Metro™ standard cells.

1.4 Integrated debug and trace for faster time to market
Embedded systems typically have no graphical user interface making software debug a
special challenge for programmers.
 In-circuit Emulator (ICE) units have traditionally been used as plug-in devices to
provide a window into the system through a familiar PC interface. As systems get
smaller and more complex, physically attaching such debug units is no longer a
viable solution.
 The Cortex-M3 processor implements debug technology in the hardware itself with
several integrated components that facilitate quicker debug with trace & profiling,
breakpoints, watch points and code patching, significantly reducing time to market.
 Additionally, the processor provides a high level of visibility into the system through a
traditional JTAG port or the 2-pin Serial Wire Debug (SWD) port that is suitable for
devices in low pin-count packages.
Relative performance for ARM7TDMI-S (ARM) and Cortex-M3 (Thumb-2) Relative code size for ARM7TDMI-S (ARM)
and Cortex-M3 (Thumb-2)

1.5 Lower power consumption for wireless networks
Wireless networks are ubiquitous in today’s increasingly connected world. Various wireless
standards like Wi-Fi, WiMAX, Bluetooth and Zigbee drive the technology that enables
connectivity over the internet and with other similarly enabled devices. The common factor
between all of these technologies is the increasing need for lower power consumption. For
example, Zigbee based wireless devices are expected to last more than ten years when
powered by a pair of AA batteries.
 Clock gating and integrated sleep modes for lower power
Clock gating is a technique that shuts down the power to parts of the system,
effectively disabling them. The Cortex-M3 processor extensively uses gated clocks to
disable unused functionality, and disables inputs to unused functional blocks, so that
only actively used logic consumes any dynamic power.
Figure 8. Power control in Deep Sleep mode
In addition to the broad implementation of clock gating in the processor design the
Cortex-M3 processor also delivers a number of sleep modes to put the processor into
low power statues, effectively clock gating the entire processor with the exception of
sections of the interrupt controller. The sleep modes can be implemented through the
WFI (wait For Interrupt) and WFE (Wait for Event) instructions. Additionally the
Cortex-M3 processor enables wider system level power reduction through the use of
the SLEEPDEEP signal. This signal is asserted when in Sleep-now or Sleep-on-exit
modes when the SLEEPDEEP bit of the System Control Register is set. This signal is
routed to the clock manager and can be used to gate the processor and system
components including the Phase Locked Loop (PLL) to achieve greater power
savings. Figure 8 shows an example of how to reduce power consumption by
stopping the clock controller with SLEEPDEEP in the low-power state. When exiting
low-power state, the LOCK signal indicates that the PLL is stable, and it is safe to
enable the Cortex-M3 clock, ensuring that the processor is not re-started until the
clocks are stable. To detect interrupts, the processor must receive the free-running
FCLK in the low-power state.
 Working smarter to sleep longer
Typically, higher power consumption is due to the processor working at faster clock
speeds to meet challenging performance requirements. The processor can also
choose to lower power consumption by working smarter at lower clock frequencies.
The Cortex-M3 processor works at an outstanding efficiency of 1.25 DMIPS/MHz,
enabling the system to complete compute intensive tasks faster and hence allowing it
to spend more time in low power sleep modes.

Architecture
Architecture:
Architectural overview:
The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses which are faster and are used similarly to TCM interfaces: one bus
dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of
two core buses allows for simultaneous operations if concurrent operations target different
devices.
The LPC17xx uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other
bus masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals on different slaves ports of the matrix to be accessed simultaneously by
different bus masters. Details of the multilayer matrix connections are shown in Figure 2.
APB peripherals are connected to the CPU via two APB busses using separate slave ports
from the multilayer AHB matrix. This allows for better performance by reducing collisions
between the CPU and the DMA controller. The APB bus bridges are configured to buffer
writes so that the CPU or DMA controller can write to APB devices without always waiting
for APB write completion.
On-chip flash program memory:
The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash
accelerator maximizes performance for use with the two fast AHB-Lite buses.
On-chip SRAM:
The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main
32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two
additional 16 kB each SRAM blocks situated on a separate slave port on the AHB
multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate RAMs
that can be accessed simultaneously.

Block Diagram:

Cortex-M3 processor architecture and features

The Cortex-M3 processor, based on the ARMv7-M architecture, has a hierarchical
structure. It integrates the central processor core, called the CM3Core, with advanced
system peripherals to enable integrated capabilities like interrupt control, memory
protection and system debug and trace. These peripherals are highly configurable to allow
the Cortex-M3 processor to address a wide range of applications and be more closely
aligned with the system requirements. The Cortex-M3 core and the integrated components
(Figure 3) have been specifically designed to meet the requirements of minimal memory
implementation, reduced pin count and low power consumption.
The Cortex-M3 Core
The central Cortex-M3 core is based on the Harvard architecture characterized by

separate buses for instructions and data (Figure 3). The processor differs from the von
Neumann architecture based ARM7 family of processors which use the same signal buses
and memory for both instructions and data. By being able to read both an instruction and
data from memory at the same time, the Cortex-M3 processor can perform many
operations in parallel, speeding application execution.
 The core pipeline has 3 stages: Instruction Fetch, Instruction Decode and Instruction
Execute.
 When a branch instruction is encountered, the decode stage also includes a

speculative instruction fetch that could lead to faster execution. The processor

fetches the branch destination instruction during the decode stage itself. Later, during
the execute stage, the branch is resolved and it is known which instruction is to be
executed next. If the branch is not to be taken, the next sequential instruction is
already available. If the branch is to be taken, the branch instruction is made
available at the same time as the decision is made, restricting idle time to just one
cycle.
 The Cortex-M3 core contains a decoder for traditional Thumb and new Thumb-2
instructions, an advanced ALU with support for hardware multiply and divide, control
logic, and interfaces to the other components of the processor.
 The Cortex-M3 processor is a 32-bit processor, with a 32-bit wide data path, register
bank and memory interface. There are 13 general-purpose registers, two stack
pointers, a link register, a program counter and a number of special registers
including a program status register.
 The Cortex-M3 processor supports two operating modes, Thread and Handler and
two levels of access for the code, privileged and unprivileged, enabling the
implementation of complex and open systems without sacrificing the security of the
application.
 Unprivileged code execution limits or excludes access to some resources like certain
instructions and specific memory locations.
 The Thread mode is the typical operating mode and supports both privileged and
unprivileged code. The Handler mode is entered when an exception occurs and all
code is privileged during this mode. In addition, all operation is categorized under two
operating states, Thumb for normal execution and Debug for debug activities.
The Cortex-M3 processor is a memory mapped system with a simple, fixed memory map
for up to 4 gigabytes of addressable memory space with predefined, dedicated addresses
for code (code space), SRAM(memory space), external memories/devices and
internal/external peripherals. There is also a special region to provide for vendor specific
addressability.
The Cortex-M3 processor enables direct access to single bits of data in simple systems by
implementing a technique called bit-banding (Figure 5). The memory map includes two
1MB bit band regions in the SRAM and peripheral space that map on to 32MB of alias
regions. Load/store operations on an address in the alias region directly get translated to
an operation on the bit aliased by that address. Writing to an address in the alias region
with the least-significant bit set writes a 1 to the bit-band bit and writing with the least-
significant bit cleared writes a 0 to the bit. Reading the aliased address directly returns the
value in the appropriate bit-band bit. Additionally, this operation is atomic and cannot be
interrupted by other bus activities.

Thumb-2 Instruction Set Architecture
The ARMv7-M is the microcontroller profile of the ARMV7 architecture and is different from
earlier ARM architectures in that it supports Thumb-2 instructions alone. Thumb-2
technology is a blend of 16 and a 32-bit instruction that delivers the performance of 32-bit
ARM instructions, matches the code density of and is backwards compatible with, the
original 16-bit Thumb instruction set. Figure 6 shows indicative Dhrystone benchmark
results that illustrate that Thumb-2 technology indeed achieves this objective.
Relative Dhrystone performance and code size for ARM, Thumb and Thumb-2
In an ARM7 processor-based system, switching the processor core between the Thumb
state for code density and ARM state for high performance would be necessary for certain
applications. However, the Cortex-M3 processor does not need to interwork instructions
since both 16-bit and 32-bit instructions co-exist in the same mode, enabling higher code
density and performance with far less complexity. As theThumb-2 instructions are a
superset of 16-bit Thumb instructions, the Cortex-M3 processor can execute any
previously written Thumb code. By implementing Thumb-2 instructions, the Cortex-M3
processor also delivers compatibility with other members of the ARM Cortex processor
family.
The Thumb-2 instruction set includes instructions that make it easier to write compact code
for many different applications. The BFI and BFC instructions are bit-field instructions that
are useful in applications like network packet processing. The SBFX and UBFX
instructions improve the ability to insert or extract a number of bits to or from a register, a
capability particularly useful in automotive applications. The RBIT instruction reverses the
bits in a word and is useful in DSP algorithms such as DFT.Thumb-2 instructions also
introduce a new If-Then construct that predicates the conditional execution of up to four
subsequent instructions.

The Nested Vectored Interrupt Controller (NVIC)
The highly configurable NVIC is an integral part of the Cortex-M3 processor and provides
the processor’s outstanding interrupt handling abilities. In its standard implementation it
supplies a Non- Maskable Interrupt (NMI) and 32 general purpose physical interrupts with
8 levels of pre-emption priority. It can be configured to anywhere between 1 and 240
physical interrupts with up to 256 levels of priority though simple synthesis choices.
The Cortex-M3 processor uses a re-locatable vector table that contains the address of the
function to be executed for a particular interrupt handler. On accepting an interrupt, the
processor fetches the address from the vector table through the instruction bus interface.
The vector table is located at address zero at reset, but can be relocated by programming
a control register. To reduce gate count and enhance system flexibility the Cortex-M3 has
migrated from the banked shadow register exception model of the ARM7 processor to a
stack based exception model. When an exception takes place, the Program Counter,
Program Status Register, Link Register and the R0-R3,R12 general purpose registers are
pushed on to the stack. The data bus stacks the registers whilst the instruction bus
identifies the exception vector from the vector table and fetches the first instruction of the
exception code. Once the stacking and instruction fetch are completed, the interrupt
service routine or fault handler is executed, followed by the automatic restoration of the
registers to enable the interrupted program to resume normal execution. By handling the
stack operations in hardware, the Cortex-M3 processor removes the need to write
assembler wrappers that are required to perform stack manipulation for traditional C-based
interrupt service routines, making application development significantly easier.
The NVIC supports nesting (stacking) of interrupts, allowing an interrupt to be serviced
earlier by exerting higher priority. It also supports dynamic reprioritization of interrupts.
Priority levels can be changed by software during run time. Interrupts that are being
serviced are blocked from further activation until the interrupt service routine is completed,
so their priority can be changed without risk of accidental re-entry. In the case of back-to-
back interrupts, traditional systems would repeat the complete state save and restore cycle
twice, resulting in higher latency. The Cortex-M3 processor simplifies moving between
active and pending interrupts by implementing tail-chaining technology in the NVIC
hardware. Tail chaining achieves much lower latency by replacing serial stack pop and
push actions that normally take over 30 clock cycles with a simple 6 cycle instruction fetch.
The processor state is automatically saved on interrupt entry, and restored on interrupt
exit, in fewer cycles than a software implementation, significantly enhancing performance
in sub-100MHz systems.

The NVIC also implements the power-management scheme of the Cortex-M3 processor
that supports integrated sleep modes.
 The Sleep Now mode is invoked by either the Wait For Interrupt (WFI) or the Wait
For Event (WFE) instructions that immediately puts the core into low-power state
pending an exception.
 The Sleep on Exit mode puts the system into low-power mode as soon as it exits the
lowest priority interrupt-service routine. The core stays in sleep state until another
exception is encountered. Since only an interrupt can exit this mode, the system
state is not restored.
 The SLEEPDEEP bit of the system control register, if set; can be used to clock gate
the core and other system components for optimal power savings. The NVIC also
integrates a System Tick (SysTick) timer, which is a 24-bit count-down timer that can
be used to generate interrupts at regular time intervals, proving an ideal heartbeat to
drive a Real Time OS or other scheduled tasks.

The Memory Protection Unit (MPU)
The MPU is an optional component of the Cortex-M3 processor that can improve the
reliability of an embedded system by protecting critical data used by the operating system
from user applications, separating processing tasks by disallowing access to each other's
data, disabling access to memory regions, allowing memory regions to be defined as read-
only and detecting unexpected memory accesses that could potentially break the system.
The MPU enables the application to be broken down into a set of processes. Each process
owns specific memory (code, data, stack, and heap) and devices, as well as having
access to shared memory and devices. The MPU also enforces user and privilege access
rules. This includes executing code from the right privilege level as well as enforcing
ownership of memory and devices by privileged and user code.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to 8 regions each of which can be
divided into 8 sub regions. The region sizes supported start from 32 bytes and increase by
factors of 2 to all of the addressable memory of 4 gigabytes. Each region is associated
with a region number that is an index starting at 0, used to address the region. It is also
possible to define a default background memory map for privileged accesses. Accesses to
memory locations that are not defined in the MPU regions, or not permitted by the region
setting, will cause the Memory Management Fault exception to take place.
The protection for the regions is implemented with rules that are based on the type of
transaction (read, write or execute) and privilege of code performing the access. Each
region includes a set of bits which affect what kinds of accesses are permitted, as well as
bits that affect what kind of bus action is allowed. The MPU also supports overlapping
regions, which are regions that cover the same address. Since sizes are in multiples of 2,
overlap means that one may be fully enclosed within another. It is therefore possible to
have multiple regions enclosed by a single region and it is also possible to have nested
overlapping. In the case of address lookups to locations within overlapping regions, the
region with the highest region number is returned.

Architecture:
Architectural overview:
The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses which are faster and are used similarly to TCM interfaces: one bus
dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of
two core buses allows for simultaneous operations if concurrent operations target different
devices.
The LPC17xx uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other
bus masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals on different slaves ports of the matrix to be accessed simultaneously by
different bus masters. Details of the multilayer matrix connections are shown in Figure 2.
APB peripherals are connected to the CPU via two APB busses using separate slave ports
from the multilayer AHB matrix. This allows for better performance by reducing collisions
between the CPU and the DMA controller. The APB bus bridges are configured to buffer
writes so that the CPU or DMA controller can write to APB devices without always waiting
for APB write completion.
On-chip flash program memory:
The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash
accelerator maximizes performance for use with the two fast AHB-Lite buses.
On-chip SRAM:
The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main
32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two
additional 16 kB each SRAM blocks situated on a separate slave port on the AHB
multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate RAMs
that can be accessed simultaneously.

Block Diagram:

Cortex-M3 processor architecture and features

The Cortex-M3 processor, based on the ARMv7-M architecture, has a hierarchical
structure. It integrates the central processor core, called the CM3Core, with advanced
system peripherals to enable integrated capabilities like interrupt control, memory
protection and system debug and trace. These peripherals are highly configurable to allow
the Cortex-M3 processor to address a wide range of applications and be more closely
aligned with the system requirements. The Cortex-M3 core and the integrated components
(Figure 3) have been specifically designed to meet the requirements of minimal memory
implementation, reduced pin count and low power consumption.
The Cortex-M3 Core
The central Cortex-M3 core is based on the Harvard architecture characterized by

separate buses for instructions and data (Figure 3). The processor differs from the von
Neumann architecture based ARM7 family of processors which use the same signal buses
and memory for both instructions and data. By being able to read both an instruction and
data from memory at the same time, the Cortex-M3 processor can perform many
operations in parallel, speeding application execution.
 The core pipeline has 3 stages: Instruction Fetch, Instruction Decode and Instruction
Execute.
 When a branch instruction is encountered, the decode stage also includes a

speculative instruction fetch that could lead to faster execution. The processor

fetches the branch destination instruction during the decode stage itself. Later, during
the execute stage, the branch is resolved and it is known which instruction is to be
executed next. If the branch is not to be taken, the next sequential instruction is
already available. If the branch is to be taken, the branch instruction is made
available at the same time as the decision is made, restricting idle time to just one
cycle.
 The Cortex-M3 core contains a decoder for traditional Thumb and new Thumb-2
instructions, an advanced ALU with support for hardware multiply and divide, control
logic, and interfaces to the other components of the processor.
 The Cortex-M3 processor is a 32-bit processor, with a 32-bit wide data path, register
bank and memory interface. There are 13 general-purpose registers, two stack
pointers, a link register, a program counter and a number of special registers
including a program status register.
 The Cortex-M3 processor supports two operating modes, Thread and Handler and
two levels of access for the code, privileged and unprivileged, enabling the
implementation of complex and open systems without sacrificing the security of the
application.
 Unprivileged code execution limits or excludes access to some resources like certain
instructions and specific memory locations.
 The Thread mode is the typical operating mode and supports both privileged and
unprivileged code. The Handler mode is entered when an exception occurs and all
code is privileged during this mode. In addition, all operation is categorized under two
operating states, Thumb for normal execution and Debug for debug activities.
The Cortex-M3 processor is a memory mapped system with a simple, fixed memory map
for up to 4 gigabytes of addressable memory space with predefined, dedicated addresses
for code (code space), SRAM(memory space), external memories/devices and
internal/external peripherals. There is also a special region to provide for vendor specific
addressability.
The Cortex-M3 processor enables direct access to single bits of data in simple systems by
implementing a technique called bit-banding (Figure 5). The memory map includes two
1MB bit band regions in the SRAM and peripheral space that map on to 32MB of alias
regions. Load/store operations on an address in the alias region directly get translated to
an operation on the bit aliased by that address. Writing to an address in the alias region
with the least-significant bit set writes a 1 to the bit-band bit and writing with the least-
significant bit cleared writes a 0 to the bit. Reading the aliased address directly returns the
value in the appropriate bit-band bit. Additionally, this operation is atomic and cannot be
interrupted by other bus activities.

Thumb-2 Instruction Set Architecture
The ARMv7-M is the microcontroller profile of the ARMV7 architecture and is different from
earlier ARM architectures in that it supports Thumb-2 instructions alone. Thumb-2
technology is a blend of 16 and a 32-bit instruction that delivers the performance of 32-bit
ARM instructions, matches the code density of and is backwards compatible with, the
original 16-bit Thumb instruction set. Figure 6 shows indicative Dhrystone benchmark
results that illustrate that Thumb-2 technology indeed achieves this objective.
Relative Dhrystone performance and code size for ARM, Thumb and Thumb-2
In an ARM7 processor-based system, switching the processor core between the Thumb
state for code density and ARM state for high performance would be necessary for certain
applications. However, the Cortex-M3 processor does not need to interwork instructions
since both 16-bit and 32-bit instructions co-exist in the same mode, enabling higher code
density and performance with far less complexity. As theThumb-2 instructions are a
superset of 16-bit Thumb instructions, the Cortex-M3 processor can execute any
previously written Thumb code. By implementing Thumb-2 instructions, the Cortex-M3
processor also delivers compatibility with other members of the ARM Cortex processor
family.
The Thumb-2 instruction set includes instructions that make it easier to write compact code
for many different applications. The BFI and BFC instructions are bit-field instructions that
are useful in applications like network packet processing. The SBFX and UBFX
instructions improve the ability to insert or extract a number of bits to or from a register, a
capability particularly useful in automotive applications. The RBIT instruction reverses the
bits in a word and is useful in DSP algorithms such as DFT.Thumb-2 instructions also
introduce a new If-Then construct that predicates the conditional execution of up to four
subsequent instructions.

The Nested Vectored Interrupt Controller (NVIC)
The highly configurable NVIC is an integral part of the Cortex-M3 processor and provides
the processor’s outstanding interrupt handling abilities. In its standard implementation it
supplies a Non- Maskable Interrupt (NMI) and 32 general purpose physical interrupts with
8 levels of pre-emption priority. It can be configured to anywhere between 1 and 240
physical interrupts with up to 256 levels of priority though simple synthesis choices.
The Cortex-M3 processor uses a re-locatable vector table that contains the address of the
function to be executed for a particular interrupt handler. On accepting an interrupt, the
processor fetches the address from the vector table through the instruction bus interface.
The vector table is located at address zero at reset, but can be relocated by programming
a control register. To reduce gate count and enhance system flexibility the Cortex-M3 has
migrated from the banked shadow register exception model of the ARM7 processor to a
stack based exception model. When an exception takes place, the Program Counter,
Program Status Register, Link Register and the R0-R3,R12 general purpose registers are
pushed on to the stack. The data bus stacks the registers whilst the instruction bus
identifies the exception vector from the vector table and fetches the first instruction of the
exception code. Once the stacking and instruction fetch are completed, the interrupt
service routine or fault handler is executed, followed by the automatic restoration of the
registers to enable the interrupted program to resume normal execution. By handling the
stack operations in hardware, the Cortex-M3 processor removes the need to write
assembler wrappers that are required to perform stack manipulation for traditional C-based
interrupt service routines, making application development significantly easier.
The NVIC supports nesting (stacking) of interrupts, allowing an interrupt to be serviced
earlier by exerting higher priority. It also supports dynamic reprioritization of interrupts.
Priority levels can be changed by software during run time. Interrupts that are being
serviced are blocked from further activation until the interrupt service routine is completed,
so their priority can be changed without risk of accidental re-entry. In the case of back-to-
back interrupts, traditional systems would repeat the complete state save and restore cycle
twice, resulting in higher latency. The Cortex-M3 processor simplifies moving between
active and pending interrupts by implementing tail-chaining technology in the NVIC
hardware. Tail chaining achieves much lower latency by replacing serial stack pop and
push actions that normally take over 30 clock cycles with a simple 6 cycle instruction fetch.
The processor state is automatically saved on interrupt entry, and restored on interrupt
exit, in fewer cycles than a software implementation, significantly enhancing performance
in sub-100MHz systems.

The NVIC also implements the power-management scheme of the Cortex-M3 processor
that supports integrated sleep modes.
 The Sleep Now mode is invoked by either the Wait For Interrupt (WFI) or the Wait
For Event (WFE) instructions that immediately puts the core into low-power state
pending an exception.
 The Sleep on Exit mode puts the system into low-power mode as soon as it exits the
lowest priority interrupt-service routine. The core stays in sleep state until another
exception is encountered. Since only an interrupt can exit this mode, the system
state is not restored.
 The SLEEPDEEP bit of the system control register, if set; can be used to clock gate
the core and other system components for optimal power savings. The NVIC also
integrates a System Tick (SysTick) timer, which is a 24-bit count-down timer that can
be used to generate interrupts at regular time intervals, proving an ideal heartbeat to
drive a Real Time OS or other scheduled tasks.

The Memory Protection Unit (MPU)
The MPU is an optional component of the Cortex-M3 processor that can improve the
reliability of an embedded system by protecting critical data used by the operating system
from user applications, separating processing tasks by disallowing access to each other's
data, disabling access to memory regions, allowing memory regions to be defined as read-
only and detecting unexpected memory accesses that could potentially break the system.
The MPU enables the application to be broken down into a set of processes. Each process
owns specific memory (code, data, stack, and heap) and devices, as well as having
access to shared memory and devices. The MPU also enforces user and privilege access
rules. This includes executing code from the right privilege level as well as enforcing
ownership of memory and devices by privileged and user code.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to 8 regions each of which can be
divided into 8 sub regions. The region sizes supported start from 32 bytes and increase by
factors of 2 to all of the addressable memory of 4 gigabytes. Each region is associated
with a region number that is an index starting at 0, used to address the region. It is also
possible to define a default background memory map for privileged accesses. Accesses to
memory locations that are not defined in the MPU regions, or not permitted by the region
setting, will cause the Memory Management Fault exception to take place.
The protection for the regions is implemented with rules that are based on the type of
transaction (read, write or execute) and privilege of code performing the access. Each
region includes a set of bits which affect what kinds of accesses are permitted, as well as
bits that affect what kind of bus action is allowed. The MPU also supports overlapping
regions, which are regions that cover the same address. Since sizes are in multiples of 2,
overlap means that one may be fully enclosed within another. It is therefore possible to
have multiple regions enclosed by a single region and it is also possible to have nested
overlapping. In the case of address lookups to locations within overlapping regions, the
region with the highest region number is returned.

Introduction to LPC1768 Peripherals

Ethernet MAC
In 1985, the Institute of Electrical and Electronic Engineers (IEEE) in the United States of
America produced a series of standards for Local Area Networks (LANs) called the IEEE
802 standards. These have found widespread acceptability and now form the core of most
LANs. One of the IEEE 802 standards, IEEE 802.3, is a standard known as "Ethernet".
Frames of data are formed using a protocol called Medium Access Control (MAC), and
encoded using Manchester line encoding. Ethernet uses a simple Carrier-Sense Multiple
Access protocol with Collision Detection (CSMA/CD) to prevent two computers trying to
transmit at the same time (or more correctly to ensure both computers retransmit any frames
which are corrupted by simultaneous transmission).
Ethernet LANs may be implemented using a variety of media (not just the coaxial cable
described above). The types of media segments supported by Ethernet are:
 10B5 Low loss coaxial cable (also known as "thick" Ethernet)

 10B2 Low cost coaxial cable (also known as "thin" Ethernet)
 10BT Low cost twisted pair copper cable (also known as Unshielded Twisted Pair (UTP),
Category-5)
 10BF Fiber optic cable
Category-5)
 100BF Fiber Fast Ethernet
Category-5)
 1000BF Fiber Gigabit Ethernet
 10000BT Category 6 (Unshielded Twisted Pair (UTP), Category-6)
 10000BT Fiber 10 Gigabit Ethernet
The Medium Access Control (MAC) protocol is used to provide the data link layer of
the Ethernet LAN system. The MAC protocol encapsulates a SDU (payload data) by adding
a 14 byte header (Protocol Control Information (PCI)) before the data and appending
an integrity checksum, the checksum is a 4-byte (32-bit) Cyclic Redundancy Check
(CRC) after the data. The entire frame is preceded by a small idle period (the minimum inter-
frame gap, 9.6 microseconds (µS)) and an 8 byte preamble (including the start of frame
delimiter).
USB
Universal Serial Bus (USB) is an industry standard developed in the mid-1990s that defines
the cables, connectors and communications protocols used in a bus for connection,
communication and power supply between computers and electronic devices.
The design of USB is standardized by the USB Implementers Forum (USB-IF), an industry
standards body incorporating leading companies from the computer and electronics
industries. Connects peripherals with 4 wire connection.
Supports 3 data rates 480 Mbps (USB 2) (high-speed) 12 Mbps (full speed) and 1.5 Mbps
(low speed) used to connect human interface devices such as mouse, keyboard etc.
USB system consist of three units
1] USB host
2] USB Cable
3] USB Device
USB cable:
D+ = Signal Line
D- = Signal Line
VBUS = Power Supply5.25 to 4.2
VGND = Ground Signal Lines are twisted
Transfer types:
 Interrupt
 Bulk
 Isochronous
 Control Transfers
USB On-The-Go, often abbreviated USB OTG, is a specification that allows USB
devices such as digital audio players or mobile phones to act as a host, allowing other USB
devices like a USB flash drive, mouse, or keyboard to be attached to them. Unlike
conventional USB systems, USB OTG systems can drop the hosting role and act as normal
USB devices when attached to another host.
Standard USB uses master/slave architecture; a host acts as the master device for the entire
bus, and a USB device acts as the slave.
DMA controller
Direct memory access (DMA) is a feature of modern computers that allows certain hardware
subsystems within the computer to access system memory independently of the central
processing unit (CPU).
Without DMA, when the CPU is using programmed input/output, it is typically fully occupied
for the entire duration of the read or writes operation, and is thus unavailable to perform
other work. With DMA, the CPU initiates the transfer, does other operations while the
transfer is in progress, and receives an interrupt from the DMA controller when the operation
is done.
The DMA controller megafunction is designed for data transfer in different system
environments. Two module types—type 0 and type 1—are provided, and the user can
choose the number of each module type. Type 0 modules are designed to transfer data
residing on the same bus, and Type 1 modules are designed to transfer data between two
different buses. Each module can support up to 4 DMA channels; the megafunction supports
up to 16 total DMA channels.

Each DMA channel can be programmed for various features, such as transfer size,
synchronized and unsynchronized transfer control; transfer priority, interrupt generation,
memory and I/O address space, and address change direction. This megafunction is
designed to work with 32-bit and 64-bit bus systems, including the PCI bus, PowerPC bus,
and other CPU host buses. It can also be integrated with other megafunction to form a
complete functional block.
UART
A Universal Asynchronous Receiver/Transmitter, abbreviated UART, is a piece of computer

hardware that translates data between parallel and serial forms. UARTs are commonly used
in conjunction with communication standards such as EIA, RS-232, RS-422 or RS-485.
The universal designation indicates that the data format and transmission speeds are
configurable. The electric signalling levels and methods (such as differential signalling etc.)
are handled by a driver circuit external to the UART.
The Universal Asynchronous Receiver/Transmitter (UART) takes bytes of data and transmits
the individual bits in a sequential fashion. At the destination, a second UART re-assembles
the bits into complete bytes. Each UART contains a shift register, which is the fundamental
method of conversion between serial and parallel forms. Serial transmission of digital
information (bits) through a single wire or other medium is less costly than parallel
transmission through multiple wires.
The UART usually does not directly generate or receive the external signals used between
different items of equipment. Separate interface devices are used to convert the logic
level signals of the UART to and from the external signaling levels. External signals may be
of many different forms. Examples of standards for voltage signaling are RS-232, RS-
422 and RS-485 from the EIA.
SPI (Serial Peripheral Interface) Bus
SPI is a synchronous serial data link standard named by Motorola that operates in full duplex
mode. SPI is also referred to as SSI (Synchronous Serial interface). Devices communicate in
master/slave mode where the master device initiates the data frame. Multiple slave devices
are allowed with individual slave select (chip select) lines. Sometimes SPI is called a four
wire serial bus. The 4 logic signals are
 SCLK - serial clock (output from master)

 MOSI - master output slave input (output from master)
 MISO - master input slave output (output from slave)
 SS - slave select(active low, output from master)
The LPC17xx contain one SPI bus.
Features
 Maximum SPI data bit rate of 12.5 Mbit/s

 Compliant with SPI specification
 Synchronous, serial, full duplex communication
 Combined SPI master and slave
 Maximum data bit rate of one eighth of the input clock rate
 8 bits to 16 bits per transfer

SSP (Synchronous Serial Port) serial I/O controller
SSP is a controller that supports the Serial Peripheral Interface (SPI), 4 wire Synchronous
Serial Interface (SSI) and Microwave serial buses. A SSP uses a master-slave paradigm to
communicate across its connected bus.
The LPC17xx contain two SSP controllers.
Features
 Maximum SSP speed of 50 Mbps (master) or 8 Mbps (slave)

 Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
 Semiconductor Microwire buses
 Synchronous serial communication
 Master or slave operation
 8-frame FIFOs for both transmit and receive
 4-bit to 16-bit frame
 DMA transfers supported by GPDMA
I2S (Integrated Interchip Sound) bus serial I/O controllers
I2S is an electrical serial bus interface standard used for connecting digital audio devices
together. It is used to communicate PCM audio data between integrated circuits in an
electronic device. The I2S bus consists of at least 3 lines:
 Bit clock line

 Word clock line (also called Word Select line)
 And at least one multiplexed data line
Features
 The interface has separate input/output channels each of which can operate in master
 or slave mode
 Capable of handling 8-bit, 16-bit, and 32-bit word sizes
 Mono and stereo audio data supported
 The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48, 96) kHz
 Support for an audio master clock
 Configurable word select period in master mode (separately for I2Sbus input and output)
I2C (Inter Integrated Circuit) Bus
I2C is a 2 wire interface. It is multi-master serial single ended computer bus. It is used to
attach low speed peripherals to a motherboard, embedded system, cell phone or other
electronic devices.
It’s designed to be of moderate speed (up to 100 kbps for standard bus up to 400 kbps for
extended bus). It uses only 2 lines: the serial data line (SDL) for data and the serial clock line
(SCL) which indicates when valid data are on data line. Every node in the network is
connected to both SCL and SDL. Some nodes may act as bus masters and the bus may
have more than one master. Other nodes may act as slaves that only respond to requests
from masters.
The LPC17xx each contain three I2C-bus controllers.

CAN (Controller Area Network) Bus
CAN bus is a vehicle bus standard designed to allow microcontrollers and devices to
communicate with each other within a vehicle without a host computer. CAN bus is a
message based protocol designed specifically for automobile applications but now also used
in other areas such as industrial automation and medical equipment. CAN can run at rates of
1Mbps over twisted pair connection of 40 meters. CAN bus have its own electrical drivers
and receivers that connect the node to the bus in wired AND fashion. In CAN terminology,
logic 1 on the bus is called recessive and logic 0 is dominant. The driving circuits on bus
cause bus to be pulled down to 0 if any node on bus pulls the bus down. When all nodes are
transmitting 1s, bus is said to be in recessive mode
ADC (Analog to Digital converter):
LPC1768 contains a single 12 bit, Successive approximation Analog to Digital Converter

with 8 channels and DMA support.
ADC is a device that converts continuous physical input quantity to a digital number
representing the amplitude of that quantity. Conversion involves quantization of the input and
hence introduces small amount of error.
The ADC measures the range VREFN to VREFP with 12 bit conversion rate of 200 kHz.
There are 8 individual channels and any one of them can be selected for conversion. This
conversion can be optional conversion on transition of input pin or Timer match signal. It is
having individual registers for each ADC channel to reduce interrupt overhead.
Basic clocking for the A/D converters is provided by the APB clock. A programmable divider
is included in each converter to scale this clock to the clock (maximum 13 MHz) needed by
the successive approximation process. A fully accurate conversion requires 65of these
clocks.
DAC (Digital to Analog Converter):
LPC1768 includes a Digital to Analog Converter. This is a 10bit DAC. The DAC allows to
generate a variable analog output. The maximum output value can be VREFP.
Motor Control PWM:
The PWM is based on the standard Timer block and inherits all of its features, although only
the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of
the system derived clock and optionally switch pins, generate interrupts or perform other
actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features, and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be used
for more applications. For instance, multi-phase motor control typically requires three non-
overlapping PWM outputs with individual control of all three pulse widths and positions.

Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge controlled
PWM outputs require only one match register each, since the repetition rate is the same for
all PWM outputs. Multiple single edge controlled PWM outputs will all have arising edge at
the beginning of each PWM cycle, when a PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs require
only two matches registers each, since the repetition rate is the same for all PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising edge
occurs prior to the falling edge), and negative going PWM pulses (when the falling edge
occurs prior to the rising edge).
Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM
outputs, or a mix of both types. The match registers also allow:
 Continuous operation with optional interrupt generation on match.

 Stop timer on match with optional interrupt generation.
 Reset timer on match with optional interrupt generation.
Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler
If the PWM mode is not enabled
Motor Control PWM
The motor control PWM is a specialized PWM supporting 3-phase motors and other
combinations. Feedback inputs are provided to automatically sense rotor position and use
that information to ramp speed up or down. An abort input is also provided that causes the
PWM to immediately release all motor drive outputs. At the same time, the motor control
PWM is highly configurable for other generalized timing, counting, capture, and compare
applications.
Quadrature Encoder Interface (QEI)
A Quadrature encoder, also known as a 2-channel incremental encoder, converts angular

displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The Quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In addition,
the QEI can capture the velocity of the encoder wheel.
It uses 32 bit registers for position and velocity and also three position registers are used
with interrupt. It is connected to APB.

Reset Circuit
Fig: Reset Circuitry
A reset is generated by holding the RESET pin low. On reset all the pins of PORT0 and PORT1 are
configured as input with an exception when JTAG and TRACE functionality is enabled. Refer datasheet
of LPC1768 for more information.

ISP and RS-232 Interface
Fig: ISP Circuitry
The COM-1 port can be used to download program code into the internal Flash ROM of the LPC1768
microcontroller. To accomplish this ISP (In-System Programming) via a bootloader and an In-
Application Programming feature of the LPC1768 microcontroller is used. The standard way to start ISP
is to hold ISP low while issuing a processor reset. This can be manually done using the RESET and
ISP push button.
RS-232 0 Interface
The LPC1768 microcontroller features four UART. The UART0 interface is available to the user
using the RS232-0 port and UART1 is available using the RS232-1 port on the LPC1768 development
board.
Each RS232 circuit comes with a MAX3232, voltage level shifter to convert the TTL signals of
the microcontroller to RS232 level. The RS232-0 port can be used as a standard communication port
for serial communication between the microcontroller and the computer.
The RS232-0 port can also be used to download program code into the internal Flash ROM of
the LPC1768 microcontroller using ISP.
RS-232 1 Interface
The LPC1768 microcontroller features dual UART. The UART0 interface is available to the user using
the RS232-0 port and UART1 is available using the RS232-1 port on the ARM7 development board.
The RS232 circuit comes with a MAX232, voltage level shifter to convert the TTL signals of the
microcontroller to RS232 level. The RS232-1 port can be used as a standard communication port for
serial communication. RTS and CTS lines are also provided for this port to implement hardware flow
control.

Fig: RS-232 Interface

BREAKOUT I/O CONNECTIONS DETAILS OF LPC1768
Fig: I/O FRC CONNECTIONS
I/O FRC Connectors are provided as shown in the above Figure for I/O operations and for interfacing
with interfacing modules. All the GPIO’s are taken out and given out for further use.

USB 2.0 Interface

The LPC1768 features an on-chip USB 2.0 complaint peripheral. ARM7 development board
provides a USB connector to make the best of this feature. The USB bi-directional D+ and D- lines are
wired to the connector. A USB good link indicator LED is provided to show the status of the USB link.
An option to detect the presence of USB power is provided using the VBUS pin. The schematic of the
USB interface is shown below.
Instruction for using the Development Board
1. Place the development on a clean surface. Avoid using a static prone material right beneath
the development board.
2. Power up the board using an external adapter with an output rating of D.C 9V sourcing at least
500mA current.
3. The CD-ROM consists of demo test codes for all the peripherals on-board. To test the
peripherals like LCD 16x2, flash the LPC1768 microcontroller using the demo HEX codes.
4. Flash Magic is the software used to flash the HEX file to the microcontroller. Browse for the
Flash Magic software from the CD-ROM under the /SiMS_ARM7_ Dev Board/Software/
directory or download the latest version at www.flashmagictool.com
5. Install the Flash Magic software on your HDD.
6. Execute the installed Flash Magic software and load the settings by importing the settings file
from the Flash Magic Software directory of your CD-ROM as shown below.

7. Connect one end of the Serial cable provided to your computer serial port and the other end to
ISP/RS232-0 port on the ARM7 development board.(USB cable can also be used instead for
downloading)
8. Open Device Manager and find the COM port section from the Device tree to know your COM
port number as shown below. Select the respective COM port from the drop down list in your
Flash Magic tool. In this case it is COM1.

9. Browse for the .hex file from the HEX directory on the CD-ROM as shown below.
10. Click Start button to Program the device. Wait until the Programming Status Bar shows
Finished as shown below. ISP operation is executed for LPC17xx series of microcontrollers.


List of Experiments
1. Display “Hello World” message using Internal UART.
2. Interface and Control a DC motor.
3. Interface a Stepper motor and rotate it in clockwise and anti-clockwise direction.
4. Determine Digital output for a given Analog input using Internal ADC of ARM controller.
5. Interface a DAC and generate Square and Triangular waveforms..
6. Interface a 4x4 keyboard and display the key code on an LCD.
7. Using the Internal PWM module of ARM controller generate PWM and vary its duty cycle,
demonstrate the use of an external interrupt.
8. Demonstrate the use of an external interrupt to toggle an LED On/Off.
9. Display the Hex digits 0 to F on a 7-segment LED interface, with an appropriate delay in
between.
10. Interfacing a simple Switch and display its status through Relay, Buzzer and LED.

Program1: Display “Hello World” message using Internal UART.
 Code:
#include <lpc17xx.h>
#include "stdutils.h"
#define SBIT_WordLenght 0x00u

#define SBIT_DLAB 0x07u
#define SBIT_FIFO 0x00u
#define SBIT_RxFIFO 0x01u
#define SBIT_TxFIFO 0x02u
#define SBIT_RDR 0x00u

#define SBIT_THRE 0x05
/* Function to initialize the UART0 at specifief baud rate */

void uart_init(uint32_t baudrate)
{
uint32_t var_UartPclk_u32,var_Pclk_u32,var_RegValue_u32;
LPC_PINCON->PINSEL0 &= ~0x000000F0;
LPC_PINCON->PINSEL0 |= 0x00000050; // Enable TxD0 P0.2 and p0.3
LPC_UART0->FCR = (1<<SBIT_FIFO) | (1<<SBIT_RxFIFO) | (1<<SBIT_TxFIFO); // Enable
FIFO and reset Rx/Tx FIFO buffers
LPC_UART0->LCR = (0x03<<SBIT_WordLenght) | (1<<SBIT_DLAB) // 8bit data, 1Stop bit, No
parity
/** Baud Rate Calculation :

PCLKSELx registers contains the PCLK info for all the clock dependent peripherals.
Bit6,Bit7 contains the Uart Clock(ie.UART_PCLK) information.
The UART_PCLK and the actual Peripheral Clock(PCLK) is calculated as below.
(Refer data sheet for more info)
UART_PCLK PCLK
0x00 SystemFreq/4
0x01 SystemFreq

0x02 SystemFreq/2
0x03 SystemFreq/8
**/
var_UartPclk_u32 = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
switch( var_UartPclk_u32 )
{
case 0x00:
var_Pclk_u32 = SystemCoreClock/4;
break;
case 0x01:
var_Pclk_u32 = SystemCoreClock;
break;
case 0x02:
break;
case 0x03:
break;
}
var_RegValue_u32 = ( var_Pclk_u32 / (16 * baudrate ));
LPC_UART0->DLL = var_RegValue_u32 & 0xFF;
LPC_UART0->DLM = (var_RegValue_u32 >> 0x08) & 0xFF;
util_BitClear(LPC_UART0->LCR,(SBIT_DLAB)); // Clear DLAB after setting DLL,DLM
}
/* Function to transmit a char */
void uart_TxChar(char ch)
{
while(util_IsBitCleared(LPC_UART0->LSR,SBIT_THRE)); // Wait for Previous transmission
LPC_UART0->THR=ch; // Load the data to be transmitted
}
/* Function to Receive a char */
char uart_RxChar()
{
char ch;
while(util_IsBitCleared(LPC_UART0->LSR,SBIT_RDR)); // Wait till the data is received

ch = LPC_UART0->RBR; // Read received data
return ch;
}
int main()
{
char ch,a[]="Hello World";
int i;
SystemInit();
uart_init(9600); // Initialize the UART0 for 9600 baud rate
for(i=0;a[i];i++) //transmit a predefined string
uart_TxChar(a[i]);
while(1)
{
//Finally receive a char and transmit it infinitely
ch = uart_RxChar();
uart_TxChar(ch);
}
}

Program2: Interface and Control a DC motor.
 Code:
void delay_ms(unsigned int ms)
{
unsigned int i,j;
for(i=0;i<ms;i++)
for(j=0;j<20000;j++);
}
/* start the main program */
int main()
{
SystemInit(); //Clock and PLL configuration
LPC_PINCON->PINSEL4 = 0x000000; //Configure the PORT2 Pins as GPIO;
LPC_GPIO2->FIODIR = 0xffffffff; //Configure the PORT2 pins as OUTPUT;
while(1)
{
LPC_GPIO2->FIOSET = 0x50;
LPC_GPIO2->FIOCLR = 0x60;
delay_ms(5000);
LPC_GPIO2->FIOCLR = 0x50;
LPC_GPIO2->FIOSET = 0x60;
delay_ms(5000);
}
}

Program3: Interface a Stepper motor and rotate it in clockwise and anti-clockwise direction.
 Code: (clockwise direction)

{
unsigned int i,j;
for(i=0;i<ms;i++)
for(j=0;j<20000;j++);
}
void Forword()
{
LPC_GPIO2->FIOCLR = 0xfffffff9;
LPC_GPIO2->FIOSET = 0xfffffffA;
delay_ms(100);
LPC_GPIO2->FIOCLR = 0xfffffffA;
LPC_GPIO2->FIOSET = 0xfffffff6;
delay_ms(100);
delay_ms(100);
delay_ms(100)

int main()
while(1)
Forword();
 Code: (anti-clockwise direction)
unsigned int i,j;
for(i=0;i<ms;i++)
for(j=0;j<20000;j++);
void Reverse()
LPC_GPIO2->FIOCLR = 0xfffffffA;
delay_ms(100);

delay_ms(100);
delay_ms(100);
LPC_GPIO2->FIOSET = 0xfffffffA;
delay_ms(100);
int main()
while(1)
Reverse();

Program4: Determine Digital output for a given Analog input using Internal ADC of ARM
controller.
 Code:
#include<lpc17xx.h>
#include "lcd.h" //ExploreEmbedded LCD library which contains the lcd routines
#include "delay.h" //ExploreEmbedded delay library which contains the delay routines
/* Bit positions of ADCR and ADGR registers */

#define SBIT_BURST 16u
#define SBIT_START 24u
#define SBIT_PDN 21u
#define SBIT_EDGE 27u
#define SBIT_DONE 31u
#define SBIT_RESULT 4u
#define SBIT_CLCKDIV 8u
int main()
{
uint16_t adc_result;
/* Setup/Map the controller pins for LCD operation
RS RW EN D0 D1 D2 D3 D4 D5 D6 D7 */
LCD_SetUp(P0_1,P0_2,P0_3,P1_16,P1_17,P1_18,P1_19,P1_20,P1_21,P1_22,P1_23);
/* Specify the LCD type(2x16) for initialization*/
LCD_Init(2,16);
LPC_SC->PCONP |= (1 << 12); /* Enable CLOCK for internal ADC controller */
LPC_ADC->ADCR = ((1<<SBIT_PDN) | (10<<SBIT_CLCKDIV)); /*Set the clock and Power ON
ADC module */
LPC_PINCON->PINSEL1|= 0x01<<14; /* Select the P0_23 AD0[0] for ADC function *
while(1)
{
LPC_ADC->ADCR |= 0x01; /* Select Channel 0 by setting 0th bit of ADCR */
DELAY_us(10); /* allow the channel voltage to stabilize*/
util_BitSet(LPC_ADC->ADCR,SBIT_START); /*Start ADC conversion*/

while(util_GetBitStatus(LPC_ADC->ADGDR,SBIT_DONE)==0); /* wait till conversion

completes */
adc_result = (LPC_ADC->ADGDR >> SBIT_RESULT) & 0xfff; /*Read the 12bit adc result*/
LCD_GoToLine(0); /* Go to First line of 2x16 LCD */
LCD_Printf("Adc0: %4d",adc_result); /* Display 4-digit adc result */
}

Program5: Interface a DAC and generate Square and Triangular waveforms.
 Code: (Square Wave)
void initTimer0(void);
void delayMS(unsigned int milliseconds);
int count = 0;
int main(void)
SystemInit(); //gets called by Startup code before main(), sets CCLK = 100Mhz
initTimer0();
LPC_PINCON->PINSEL1 |= (1<<21); //Select AOUT function for P0.26 , bits[21:20] = [10]
unsigned int value=0; //Binary value used for Digital To Analog Conversion
while(1)
//For 10-bit DAC max-value is 2^10 - 1 = 1023
for(count = 0; count < 1023; count++)
LPC_DAC->DACR = (value<<6);
value = 1023;
for(count = 0; count < 1023; count++)

value = 0;
void initTimer0(void)
//Assuming that PLL0 has been setup with CCLK = 60Mhz
//using default PCLK = 25 which is configure by startup code
LPC_TIM0->CTCR = 0x0;
LPC_TIM0->PR = 25000-1; //25000 clock cycles @25Mhz PCLK = 1 ms
LPC_TIM0->TCR = 0x02; //Reset Timer
void delayMS(unsigned int milliseconds) //Using Timer0
LPC_TIM0->TCR = 0x01; //Enable timer
while(LPC_TIM0->TC < milliseconds); //wait until timer counter reaches the desired delay
LPC_TIM0->TCR = 0x00; //Disable timer

 Code: (Triangular Wave)
void initTimer0(void);
void delayMS(unsigned int milliseconds);
int main(void)
SystemInit(); //gets called by Startup code before main(), sets CCLK = 100Mhz
initTimer0();
LPC_PINCON->PINSEL1 |= (1<<21); //Select AOUT function for P0.26 , bits[21:20] = [10]
unsigned int value=0; //Binary value used for Digital To Analog Conversion
while(1)
//For 10-bit DAC max-value is 2^10 - 1 = 1023
for(value=0;value<1023;value++)
//delayMS(1);
for(value=1023;value>0;value--)
//delayMS(1);

void initTimer0(void)
//Assuming that PLL0 has been setup with CCLK = 60Mhz
//using default PCLK = 25 which is configure by startup code
LPC_TIM0->CTCR = 0x0;
LPC_TIM0->PR = 25000-1; //25000 clock cycles @25Mhz PCLK = 1 ms
void delayMS(unsigned int milliseconds) //Using Timer0
LPC_TIM0->TCR = 0x01; //Enable timer
while(LPC_TIM0->TC < milliseconds); //wait until timer counter reaches the desired delay
LPC_TIM0->TCR = 0x00; //Disable timer

Program6: Interface a 4x4 keyboard and display the key code on an LCD.
 Code:
#include <LPC17xx.h>
#include "keypad.h"
#include "lcd.h"
int main()
{
uint8_t key;
SystemInit();
/* RS RW EN D0 D1 D2 D3 D4 D5 D6 D7 P_NC(Not connected)*/
LCD_SetUp(P0_1,P0_2,P0_3,P1_16,P1_17,P1_18,P1_19,P1_20,P1_21,P1_22,P1_23);
LCD_Init(2,16);
KEYPAD_Init(P2_0,P2_1,P2_2,P2_3,P1_0,P1_1,P1_4,P1_8); // Keypad is connected to P2_0

- P2_3 and P1_0 - P1_3
LCD_Printf("Key Pressed:");
while (1)
{
key = KEYPAD_GetKey(); // Read the Ascii value of Key
LCD_GoToLine(1);
LCD_DisplayChar(key); // Display the Key pressed on LCD
}
}

Program7: Using the Internal PWM module of ARM controller generate PWM and vary its duty
cycle.
 Code:
{
unsigned int i,j;
for(i=0;i<ms;i++)
for(j=0;j<50000;j++);
}
#define SBIT_CNTEN 0
#define SBIT_PWMEN 2
#define SBIT_PWMMR0R 1
#define SBIT_LEN0 0
#define SBIT_LEN1 1
#define SBIT_LEN2 2
#define SBIT_LEN3 3
#define SBIT_LEN4 4
#define SBIT_PWMENA1 9
#define PWM_1 0 //P2_0 (0-1 Bits of PINSEL4)


int main(void)
{
int dutyCycle;
SystemInit();
/* Cofigure pins(P2_0 - P2_3) for PWM mode. */
LPC_PINCON->PINSEL4 = (1<<PWM_1) | (1<<PWM_2) | (1<<PWM_3) | (1<<PWM_4);
/* Enable Counters,PWM module */

LPC_PWM1->TCR = (1<<SBIT_CNTEN) | (1<<SBIT_PWMEN);
LPC_PWM1->PR = 0x0; /* No Prescalar */

LPC_PWM1->MCR = (1<<SBIT_PWMMR0R); /*Reset on PWMMR0, reset TC if it matches
MR0 */
LPC_PWM1->MR0 = 100; /* set PWM cycle(Ton+Toff)=100) */

LPC_PWM1->MR1 = 50; /* Set 50% Duty Cycle for all four channels */
LPC_PWM1->MR2 = 50;
LPC_PWM1->MR3 = 50;
LPC_PWM1->MR4 = 50;
/* Trigger the latch Enable Bits to load the new Match Values */
LPC_PWM1->LER = (1<<SBIT_LEN0) | (1<<SBIT_LEN1) | (1<<SBIT_LEN2) |
(1<<SBIT_LEN3) | (1<<SBIT_LEN4);
/* Enable the PWM output pins for PWM_1-PWM_4(P2_0 - P2_3) */

LPC_PWM1->PCR = (1<<SBIT_PWMENA1) | (1<<SBIT_PWMENA2) | (1<<SBIT_PWMENA3)
| (1<<SBIT_PWMENA4);
while(1)
{
for(dutyCycle=0; dutyCycle<100; dutyCycle++)
{
LPC_PWM1->MR1 = dutyCycle; /* Increase the dutyCycle from 0-100 */
LPC_PWM1->MR2 = dutyCycle;
delay_ms(5);
}
for(dutyCycle=100; dutyCycle>0; dutyCycle--)

{
LPC_PWM1->MR1 = dutyCycle; /* Decrease the dutyCycle from 100-0 */
delay_ms(5);
}
}
}

Program8: Demonstrate the use of an external interrupt to toggle an LED On/Off.
 Code:
#define PINSEL_EINT0 20
#define PINSEL_EINT1 22
#define LED1 0
#define LED2 1
#define SBIT_EINT0 0
#define SBIT_EINT1 1
#define SBIT_EXTMODE0 0
#define SBIT_EXTMODE1 1
#define SBIT_EXTPOLAR0 0
#define SBIT_EXTPOLAR1 1
void EINT0_IRQHandler(void)
{
LPC_SC->EXTINT = (1<<SBIT_EINT0); /* Clear Interrupt Flag */
LPC_GPIO2->FIOPIN ^= (1<< LED1); /* Toggle the LED1 everytime INTR0 is generated */
}
void EINT1_IRQHandler(void)
{
LPC_SC->EXTINT = (1<<SBIT_EINT1); /* Clear Interrupt Flag */
LPC_GPIO2->FIOPIN ^= (1<< LED2); /* Toggle the LED2 everytime INTR1 is generated */
}
int main()
{
SystemInit();
LPC_SC->EXTINT = (1<<SBIT_EINT0) | (1<<SBIT_EINT1); /* Clear Pending interrupts
*/
LPC_PINCON->PINSEL4 = (1<<PINSEL_EINT0) | (1<<PINSEL_EINT1); /* Configure
P2_10,P2_11 as EINT0/1 */

LPC_SC->EXTMODE = (1<<SBIT_EXTMODE0) | (1<<SBIT_EXTMODE1); /* Configure

EINTx as Edge Triggered*/
LPC_SC->EXTPOLAR = (1<<SBIT_EXTPOLAR0)| (1<<SBIT_EXTPOLAR0); /* Configure
EINTx as Falling Edge */
LPC_GPIO2->FIODIR = (1<<LED1) | (1<<LED2); /* Configure LED pins as OUTPUT */

LPC_GPIO2->FIOPIN = 0x00;
NVIC_EnableIRQ(EINT0_IRQn); /* Enable the EINT0,EINT1 interrupts */
NVIC_EnableIRQ(EINT1_IRQn);
while(1)
{
// Do nothing
}
}

Program9: Display the Hex digits 0 to F on a 7-segment LED interface, with an appropriate delay
in between.
 Code:
{
unsigned int i,j;
for(i=0;i<ms;i++)
for(j=0;j<20000;j++);
}
unsigned int digits[]={ 0xffff00BF, // '0'--->0x40
0xffff0086, // '1'--->0x79
0xffff00DB, // '2'--->0x24
0xffff00CF, // '3'--->0x30
0xffff00E6, // '4'--->0x19
0xffff00ED, // '5'--->0x12
0xffff00FD, // '6'--->0x02
0xffff0087, // '7'--->0x78
0xffff00FF, // '8'--->0x00
0xffff00E7, // '9'--->0x18
0xffff00F7, // 'A'--->0x08
0xffff00FF, // 'B'--->0x00
0xffff00B9, // 'C'--->0x46
0xffff00BF, // 'D'--->0x40
0xffff00F9, // 'E'--->0x06
0xfffff0F1 // 'F'--->0x0E
unsigned int digit_enable[] = {
0x01,
0x02,
0x04,
0x08,
0x10,
};


int main()
{
while(1)
{
unsigned int digit_value_index = 0;
unsigned int digit_index = 0;
unsigned int digit_select = 0;
while(digit_select < 0x06)
{
LPC_GPIO0->FIOSET0 = digit_enable[digit_index];
digit_value_index = 0;
while(digit_value_index < 0x10)
{
LPC_GPIO2->FIOCLR = 0xffff00FF;
LPC_GPIO2->FIOSET = digits[digit_value_index];
++digit_value_index;
delay_ms(2000);
}
++digit_select;
}
}
}

Program10: Interfacing a simple Switch and display its status through Relay, Buzzer and LED.
 Code:
#define SwitchPinNumber 5
#define LedPinNumber 0
#define buzzerPinNumber 1
#define relayPinNumber 2
int main()
{
uint32_t switchStatus;
SystemInit(); /* Clock and PLL configuration */
// LPC_PINCON->PINSEL2 = 0x000000; /* Configure the Pins for GPIO */
/* Configure the LED pin as output and SwitchPin as input */
// LPC_GPIO2->FIODIR = ((1<<LedPinNumber) | (0<<SwitchPinNumber));
LPC_GPIO2->FIODIR = 0x0F;
while(1)
{
/* Turn On all the leds and wait for one second */
switchStatus = (LPC_GPIO2->FIOPIN>>SwitchPinNumber) & 0x01 ; /* Read the switch status

*/
if(switchStatus == 1) /* Turn ON/OFF LEDs depending on switch status */
{
// LPC_GPIO2->FIOPIN = (1<<LedPinNumber);
//LPC_GPIO2->FIOPIN = (1<<buzzerPinNumber);
//LPC_GPIO2->FIOPIN = (1<<relayPinNumber);
LPC_GPIO2->FIOSET = 0x0F;
}

else
//LPC_GPIO2->FIOPIN = (0<<LedPinNumber);
//LPC_GPIO2->FIOPIN = (0<<buzzerPinNumber);
//LPC_GPIO2->FIOPIN = (0<<relayPinNumber);
LPC_GPIO2->FIOCLR = 0x0F;
}
}
}

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LPC1768DEVELOPMENT BOARD Technical Reference Manual

ARM [LPC1768] Development Board

SILICON MICRO SYSTEMS

Silicon Microsystems, Bangalore 1

2 SiMS LPC-1768 Board Layout 4

3 Instruction for using the Development Board 43

Silicon Microsystems, Bangalore 2

3. An on-board crystal of 12MHz to clock the microcontroller to up to 60MHz with

4. Two DB9 connectors to implement RS232 communication using the on-chip

7. The microcontroller can be programmed using the on-chip serial bootloader

9. On-board USB connector interfaced to on-chip USB peripheral of LPC1768 for

10. On-board USB to Serial Convertor using FT232RL-FTDI

13. On Board push button Hardware Reset Circuitry.

14. On Board push button Hardware Interrupt.

Silicon Microsystems, Bangalore 3

SiMS-LPC1768 BOARD LAYOUT

Fig: SiMS-LPC1768 BOARD LAYOUT

Silicon Microsystems, Bangalore 4

POWER SUPPLY SECTION

Fig: Power Supply Section

Silicon Microsystems, Bangalore 5

The peripheral complement of the LPC1768 includes

 512 kB of flash memory

Silicon Microsystems, Bangalore 6

ARM Cortex-M3 processor

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

Silicon Microsystems, Bangalore 7

Silicon Microsystems, Bangalore 8

Silicon Microsystems, Bangalore 9

1.1 Higher performance through better efficiency

 Pushing higher clock frequencies may increase performance but is also

Silicon Microsystems, Bangalore 10

1.2 Ease of use for quick and efficient application development

 The processor has a simplified stack-based programmer’s model which still

1.3 Reduced costs and lower power for sensitive markets

 Memory requirements are minimized by implementing unaligned data storage, atomic

Silicon Microsystems, Bangalore 11

1.4 Integrated debug and trace for faster time to market

Silicon Microsystems, Bangalore 12

1.5 Lower power consumption for wireless networks

 Clock gating and integrated sleep modes for lower power

Figure 8. Power control in Deep Sleep mode

 Working smarter to sleep longer

Silicon Microsystems, Bangalore 13

On-chip flash program memory:

Silicon Microsystems, Bangalore 14

Silicon Microsystems, Bangalore 15

Cortex-M3 processor architecture and features

The Cortex-M3 Core

The central Cortex-M3 core is based on the Harvard architecture characterized by

 When a branch instruction is encountered, the decode stage also includes a

Silicon Microsystems, Bangalore 16

Silicon Microsystems, Bangalore 18

Thumb-2 Instruction Set Architecture

Silicon Microsystems, Bangalore 19

The Nested Vectored Interrupt Controller (NVIC)

Silicon Microsystems, Bangalore 20

Silicon Microsystems, Bangalore 21

The Memory Protection Unit (MPU)