ELEN0040 - Electronique numérique

Patricia ROUSSEAUX

Année académique 2014-2015

 CHAPITRE 3

Combinational Logic Circuits

ELEN0040 3 - 96
1 Combinational Functional Blocks
1.1 Rudimentary Functions
1.2 Functions and Functional Blocks
1.3 Decoders
1.4 Encoders
1.5 Multiplexers
1.6 Implementing Combinational Functions with Multiplexers

2 Arithmetic Functions
2.1 Binary Adders
2.2 Binary Arithmetic
2.3 Binary Adders-Subtractors
2.4 Overflow
2.5 Other Arithmetic Functions

ELEN0040 3 - 97
Functions and Functional Blocks

◮ Introduction of fundamental components performing basic

combinational functions
◮ The basic functions considered are those found to be very useful in
design : decoding, encoding, selecting
◮ Corresponding to each of the functions is a combinational circuit
implementation called a functional block : decoder, encoder and
multiplexer
◮ In the past, functional blocks were packaged as
small-scale-integrated (SSI), medium-scale integrated (MSI), and
large-scale-integrated (LSI) circuits.
◮ Today, they are often simply implemented within a
very-large-scale-integrated (VLSI) circuit.

ELEN0040 3 - 98
Multiple-bit Rudimentary Functions

Multi-bit Examples:
A F3 A
3 2
1 F2 1 2 4 4 2:1 F(2:1)
F F
0 F1 0 1
0 (c)
A F0 A
(a) (b) 3
A wide line is used to represent 4 3,1:0 F(3), F(1:0)
F
a bus which is a vector signal
(d)
In (b) of the example, F = (F3, F2, F1, F0) is a bus.
The bus can be split into individual bits as shown in (b)
Sets of bits can be split from the bus : (c) bits 2 and 1 of F.
The sets of bits need not be continuous : (d) bits 3, 1, and 0 of F.

99
Enabling Function

Enabling permits an input signal to pass through

to an output
Disabling blocks an input signal from passing
through to an output, replacing it with a fixed
value !
The value on the output when it is disable can be
0 , or 1
X
• When disabled, 0 output F
EN
(a)
• When disabled, 1 output
X
F
EN

(b)
100
Decoding (n→m;n<m)

Decoding - the conversion of an n-bit input code to

an m-bit output code with
n ≤ m ≤ 2n
such that each valid input code word produces a
unique output code
Circuits that perform decoding are called decoders
Here, functional blocks for decoding are
• called : n-to-m line decoders, where m ≤ 2n, and
• generate 2n (or fewer) minterms for the n input
variables

101
 Decoder Examples
A D0 D1
1-to-2-Line Decoder D0 5 A
0 1 0
1 0 1 A D1 5 A

(a) (b)
2-to-4-Line Decoder
A0
A1 A0 D0 D1 D2 D3
A1
0 0 1 0 0 0
D0 5 A 1 A 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 5 A 1 A 0

(a)
D2 5 A 1 A 0
The 2-4-line decoder is made up of
2 1-to-2-line decoders and 4 AND
D3 5 A 1 A 0
gates.
(b)
102
Decoder Expansion

For a larger decoder with n inputs and 2n outputs, use

hierarchical design
Split the decoder into smaller dimensions ones
At each stage, divide by 2 the number of inputs
The output AND gates are driven by two decoders
with their numbers of inputs either equal or differing
by 1.
These decoders are then designed using the same
procedure until 2-to-1-line decoders are reached.
The procedure can be modified to apply to decoders
with the number of outputs ≠ 2n

103
Decoder Expansion - Example 1

3-to-8-line decoder
• Number of inputs n=3
• Number of output ANDs m=23=8
• First split : 3 = 1*2 + 1
One 2-to-4-line decoder
One 1-to-2-line decoder
• Second split : split the 2-to-4-line decoder, 2=2*1
Two 1-to-2-line decoders
• At each stage, each decoder with k (k>1) inputs
provides its 2k outputs through 2k 2-AND gates

104
Decoder Expansion - Example 1

Circuit 4 2-input ANDs 8 2-input ANDs

D0
A0

D1

A1
D2

2-to-4-Line D3
decoder
D4

A2 D5

1-to-2-Line decoders D6

D7

3-to-8 Line decoder

3 105
Decoder Expansion - Example 2
7-to-128-line decoder
• Number of output ANDs m=27= 128
• Number of inputs n= 7
• First split : 7=1*4+1*3
One 4-to-16-line decoder
One 3-to-8-line decoder
• Second split :
4-to-16-line decoder : 4=2*2 → Two 2-to-4-line decoders
3-to-8-line decoder : 3=1*2+1 → One 2-to-4-line decoder
+ one 1-to-2-line decoder
• Third split :
2-to-4-line decoders : 2=2*1 → Two 1-to-2-line decoders

106
 7-to-128-line decoder : hierarchical structure

128 2-ANDs
DEC 1-2 4 2-ANDs 16 2-ANDs

DEC 1-2 DEC 2-4

DEC 1-2 4 2-ANDs

7 inputs DEC 1-2 DEC 2-4

DEC 4-16

DEC 1-2 4 2-ANDs 8 2-ANDs

DEC 1-2 DEC 2-4

DEC 1-2
DEC 3-8

107
Decoder with Enable
In general, attach m-enabling circuits to the outputs
See truth table below for function
• Note the use of X’s to denote both 0 and 1 in the inputs
• Combination containing two X’s represent four binary combinations
Demultiplexer : distribute value of signal EN to 1 of 4
outputs EN

In this case, A 1

• input data =EN A0

D0
• Selection inputs = A1, A0
EN A 1 A 0 D0 D1 D2 D3 D1

0 X X 0 0 0 0
1 0 0 1 0 0 0 D2
1 0 1 0 1 0 0
1 1 0 0 0 1 0
D3
1 1 1 0 0 0 1

(a) (b) 108

 Combinational Logic Implementation
Decoder and OR Gates

A decoder provides 2n minterms

Any function can be represented by its SOM
expression
A decoder can be used to implement m functions
of n variables :
• Find the sum-of-minterms expressions
• Use one n-to-2n-line decoder
• Use m OR gates, one for each output
Not always the best solution !

109
Decoder and OR Gates Example
Implement the following set of odd parity functions of (A7, A6,
A5, A3)
P1 = A7 + A5 + A3 A7 DEC 4-16
0 P1
P2 = A7 + A6 + A3 A6 1
2
P4 = A7 + A6 + A5 A5 3
A3 4
Finding sum of
5 P2
minterms expressions 6
7
P1 = Σm(1,2,5,6,8,11,12,15) 8
P2 = Σm(1,3,4,6,8,10,13,15) 9

P4 = Σm(2,3,4,5,8,9,14,15)
10
11
P4
12
Find circuit 13
Best solution ? Better to resort 14
to XOR gates 15

110
Encoding

Encoding - the opposite of decoding - the conversion of

an m-bit input code to a n-bit output code with
n ≤ m ≤ 2n such that each valid code word produces a
unique output code
Circuits that perform encoding are called encoders
An encoder has 2n (or fewer) input lines and n output
lines which generate the binary code corresponding to
the input values
Typically, an encoder converts a code containing
exactly one bit that is 1 to a binary code corresponding
to the position in which the 1 appears.

111
Encoder Example

A decimal-to-BCD encoder
• Inputs: 10 bits corresponding to decimal digits 0
through 9, (D0, …, D9)
• Outputs: 4 bits with BCD codes
• Function: If input bit Di is a 1, then the output (A3,
A2, A1, A0) is the BCD code for i
The truth table could be formed, but alternatively,
the equations for each of the four outputs can be
obtained directly.

112
Encoder Example (continued)

113
Encoder Example (continued)

Input Di is a term in equation Aj if bit Aj is 1 in the

binary coded value of i.
Equations:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9

114
Priority Encoder
If more than one input value is 1, then the encoder
just designed does not work.
One encoder that can accept all possible
combinations of input values and produce a
meaningful result is a priority encoder.
It implements a priority function, one 1 value is given
the priority above others
For example, among the 1s that appear, it selects the
most significant input position (or the least significant
input position) containing a 1 and responds with the
corresponding binary code for that position.

115
Priority Encoder Example
Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to
most significant 1 present –
Code outputs A2, A1, A0 and V where V indicates at least one 1
present.
In the Table, X in input variable represent 0 or 1 so that row 6 of the
table represents 16 rows of the truth table
No. of Min- Inputs Outputs
terms/Row
D4 D3 D2 D1 D0 A2 A1 A0 V
1 0 0 0 0 0 X X X 0
1 0 0 0 0 1 0 0 0 1
2 0 0 0 1 X 0 0 1 1
4 0 0 1 X X 0 1 0 1
8 0 1 X X X 0 1 1 1
16 1 X X X X 1 0 0 1
116
Priority Encoder Example (continued)

Equations (after simplification) :

A2 = D4
A1 = D4 D3 + D4 D3 D2 = D4 F1, F1 = (D3 + D2)
A0 = D4 D3 + D4 D3 D2 D1 = D4 (D3 + D2 D1)
V = D4 + F1 + D1 + D0

117
Selecting

Selecting data or information is a critical function

in digital systems and computers

Circuits that perform selecting have:

• A set of information inputs from which the selection is made
• A single output
• A set of control lines for making the selection

Logic circuits that perform selecting are called

multiplexers

118
Multiplexers
A multiplexer selects information from an input
line and directs the information to the output line

A typical multiplexer has n control inputs

(Sn - 1, … S0) called selection inputs, 2n
information inputs (I2n - 1, … I0), and one output Y

A multiplexer can be designed to have m

information inputs with m < 2n as well as n
selection inputs

119
Multiplexers (2)

Inputs Output

Input Selection

120
2-to-1-Line Multiplexer

Two information inputs I0, I1, so n=1

A single selection input S:
• S = 0 selects input I0
• S = 1 selects input I1
Truth table :
The equation:
Y = S I0 + SI1

121
2-to-1-Line Multiplexer

The circuit:
Enabling
Decoder Circuits

I0
Y
S
I1

We recognize :
• 1-to-2-line Decoder
• 2 Enabling circuits
• 2-input OR gate

122
2n-to-1-Line Multiplexer

For n>1 selecting inputs

An 2n-to-1-line multiplexer can be built from :
• one n-to-2n-line decoder generating the mi
• one 2n × 2 AND-OR circuit combining the enabling
circuits and the OR gate
Example : n=2
Equation
+
+ +

123
Example: 4-to-1-line Multiplexer

one 2-to-22-line decoder

mi
one 22 × 2 AND-OR Inputs !
Decoder
S1

4 3 2 AND-OR
S0
Decoder
4×2 AND-OR
S1

S0
I0

Y
I1
Y

I2

I3

124
Multiplexer with m outputs
Select “vectors of bits” instead of “bits”
Use multiple copies of 2n × 2 AND-OR in parallel
Example: m=4 4×2 AND-OR I 0,0
4 3 2 AND-OR

4-to-1-line .
.
Y0

.
quad multi- I 3,0 4 3 2 AND-OR
4×2 AND-OR
D0
plexer A0
.
I 0,1

.
Y1
2-to-4-Line decoder .
. .
.
D3
A1 I 3,1 4 3 2 AND-OR
4×2 AND-OR
I 0,2
Y2
.
.
.
I 3,2 4 3 2 AND-OR
4×2 AND-OR
I 0,3
Y3
.
.
.
I 3,3

125
Combinational Logic Implementation
- Multiplexer Approach 1
Multiplexing is a universal function
Any combinational n-variable function can be
implemented with a
• A sum-of-minterms expression
• An 2n-to-1-line multiplexer
Design:
• Apply the function input variables to the multiplexer
selection inputs Sn - 1, … , S0
• Find the SOM expression from the truth table
• Put values to multiplexer inputs :
If minterm mj is present in SOM, put Ij=1
If minterm mj is not present in SOM, put Ij=0

126
 Example : F(X,Y) = Ʃm(0, 3)

Decoder
X S1

4 3 2 AND-OR
Y S0 4×2 AND-OR
Decoder
m0
S1

I1
S0
0
m1
Y
I01
m2 Y

I2
0
m3

I13

127
Example: Gray to Binary Code

Design a circuit to Gray Binary

convert a 3-bit Gray ABC xyz
code to a binary code 000 000
100 001
The formulation gives
110 010
the truth table on the 010 011
right 011 100
It is obvious from this 111 101
table that X = C and the 101 110
Y and Z are more complex 001 111

128
Gray to Binary (continued)
Gray Binary
Rearrange the table so ABC xyz
that the input combinations 000 000
are in counting order 001 111
010 011
011 100
Functions y and z can
100 001
be implemented using 101 110
a dual 8-to-1-line 110 010
multiplexer by: 111 101
• connecting A, B, and C to the multiplexer select inputs
• placing y and z on the two multiplexer outputs
• connecting their respective truth table values to the
inputs
129
 Gray to Binary (continued)

0 D00 0 D10
Gray Binary
1 D01 1 D11
ABC xyz
000 000
1 D02 1 D12
001 111
010 011 0 D03 0 D13
011 100
100 001 0 D04 1 D14
101 110 Out Y Out Z
110 010
1 D05 0 D15
111 101 1 D06 0 D16
0 D07 1 D17
A S2 A S2 8-to-1
8-to-1
B S1 B S1
C S0 MUX C S0 MUX

, , , , , ,

130
Combinational Logic Implementation
- Multiplexer Approach 2 (more economical !)
A simpler implementation is obtained by using :
• A 2n-1-to-1-line multiplexer
• A single inverter
Design:
• Apply the first n-1 function input variables to the
multiplexer selection inputs Sn - 2, … , S0
• Find the SOM expression from the truth table
• Define the multiplexer inputs to get the minterms of
the function :
let be the n-th function input variable
each multiplexer input is either : 1, 0, or

131
Gray to Binary (continued)

Gray Binary Rudimentary Rudimentary

ABC xyz Functions of Functions of
C for y C for z
000 000
F=C F=C
001 111
010 011
F=C F=C
011 100
100 001
F=C F=C
101 110
110 010
F=C F=C
111 101

132
 Gray to Binary (continued)

Assign the variables and functions to the multiplexer inputs:

C D00 C D10
C D01 C D11
C C
C D02 Out Y C D12 Out Z
C D03 C D13

A S1 8-to-1 A S1 8-to-1
B S0 MUX B S0 MUX

Y m 1,2,5,6 Z m 1,2,4,7

Note that this approach (Approach 2) reduces the cost by almost half
compared to Approach 1.

133
Summary

Decoder :

◮ n inputs
◮ m outputs, n ≤ m ≤ 2n
◮ generate minterms : output
Di = m i

Encoder :
◮ 2n inputs = 2n minterms, only
one equal to 1
◮ n outputs
◮ generate the binary
representation of the input
values : n-bit representation

ELEN0040 3 - 134
Summary (continued)

Multiplexer :

◮ n selecting inputs
◮ 2n information inputs
◮ one output
◮ select binary information from
one input

F = S¯1 S¯0 D0 + S¯1 S0 D1 + S1 S¯0 D2 + S1 S0 D3

ELEN0040 3 - 135
1 Combinational Functional Blocks
1.1 Rudimentary Functions
1.2 Functions and Functional Blocks
1.3 Decoders
1.4 Encoders
1.5 Multiplexers
1.6 Implementing Combinational Functions with Multiplexers

2 Arithmetic Functions
2.1 Binary Adders
2.2 Binary Arithmetic
2.3 Binary Adders-Subtractors
2.4 Overflow
2.5 Other Arithmetic Functions

ELEN0040 3 - 136
Arithmetic circuits
◮ An arithmetic circuit is a combinational circuit that performs
arithmetic operations :
◮ addition
◮ subtraction
◮ multiplication
◮ division
◮ The operations are performed with binary numbers or decimal
numbers in a binary code
◮ Apply the rules of arithmetic with binary numbers
◮ rules for numbers representation
◮ resort to 1 or 2’s complements
◮ An arithmetic circuit :
◮ operates on binary vectors
◮ uses the same subfunction for each bit position
◮ is made of the iterative interconnection of basic functional blocks,
one for each bit position = iterative array

ELEN0040 3 - 137
Adders

Functional blocks :
◮ Half-Adder : a 2-input, 2-output functional block that performs the
addition of the two input bits
◮ Full-Adder : a 3-input, 2-output functional block that performs the
addition of the three input bits, including a third carry input bit
obtained from a previous adder
Multiple bit adders :
◮ Ripple Carry Adder : an iterative array to perform binary addition

◮ Carry Look Ahead Adder : an improved structure with higher

performance

ELEN0040 3 - 138
Half-Adder

A Half-Adder performs the following computations:

X 0 0 1 1
+Y +0 +1 +0 +1
CS 00 01 01 10

It adds two bits to produce a two-bit sum

The sum is expressed as a Sum bit, S and
a Carry bit, C

139
Half-Adder : Truth table

From the truth table, we get the X Y C S

equations :
0 0 0 0
For S
0 1 0 1
S = X⋅Y+ X⋅Y = X⊕Y 1 0 0 1
S = ( X + Y) ⋅ ( X + Y) 1 1 1 0

And for C :
X
C = X⋅Y
C = ( ( X ⋅Y ) ) Y

140
Half-Adder : Five Implementations

We can derive the 5 following sets of equations for a

half-adder:
(a) S = X ⋅ Y + X ⋅ Y (d ) S = ( X + Y ) ⋅ C
C = X⋅Y C = ( X + Y)
( b) S = ( X + Y ) ⋅ ( X + Y ) (e ) S = X ⊕ Y
C = X⋅Y C = X⋅Y
( c ) S = ( C+ X⋅ Y)
C = X⋅Y
(a), (b), and (e) are SOP, POS, and XOR
implementations for S.
In (c), the C function is used as a term in the AND-
NOR implementation of S, and in (d), the C function
is used in a POS term for S.
141
Half-Adder : Implementations
The most common half
adder implementation is: X (e)
Y S

S = X⊕Y C
C = X⋅Y

A NAND only implementation is: (d)

C
S = (X + Y) ⋅ C X
C = ( ( X ⋅Y ) ) C
S
Y

XOR
142
Full-Adder

A full adder is similar to a half adder, but includes a

carry-in bit from previous stages.
Like the half-adder, it computes a sum bit, S and a
carry bit, C.
It performs the following computations
Z 0 0 0 0
For a carry-in Z=0
X 0 0 1 1
it is the same as +Y +0 +1 +0 +1
the half-adder C S 00 0 1 01 10
Z 1 1 1 1
For a carry- in Z=1 X 0 0 1 1
+Y +0 +1 +0 +1
CS 01 10 10 11
143
Full-Adder : Truth table
From the truth table, we get the X Y Z C S
equations : 0 0 0 0 0
0 0 1 0 1
S = XYZ+ XY Z+ XYZ+ XYZ 0 1 0
0 1 1
0
1
1
0
C = X YZ + X YZ + X YZ+ X YZ 1 0 0 0 1
1 0 1 1 0
After simplification : 1 1 0 1 0
1 1 1 1 1
S = X⊕Y⊕Z
Odd function
X
C = X Y + (X ⊕ Y) Z
Y
C= G + P Z Z

144
Full-Adder : Implementation

S = X⊕Y⊕Z C= G + P Z
P

The term G=X·Y is carry generate.

The term P= X⊕Y is carry propagate

145
Références

◮ Logic and Computer Design Fundamentals, 4/E, M. Morris Mano

Charles Kime , Course material
http ://writphotec.com/mano4/
◮ Cours d’électronique numérique, Aurélie Gensbittel, Bertrand
Granado, Université Pierre et Marie Curie
http ://bertrand.granado.free.fr/Licence/ue201/
coursbeameranime.pdf

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