1

Hardware Design Methodology

Timing metrics of a Sequential circuits
 Setup time and hold time
 Maximum operating frequency
Hold Time violation

HDM: Dr. Kavindra Kandpal, IIITA

2
Note to students
The slides are introductory and doesn’t include all the syllabus.
For understanding different logic style please follow following chapters:

 Chapter 7 & 10 : Digital Integrated Circuits, A Design perspective, 2nd edition,

Jan M. Rabaey et al.

Timing analysis and sequential logic

3
Setup time, hold time

A flip-flop has following critical parameters:

 tcq–clock to output: essentially a

propagation delay
 tsetup–setup time: the time the data
needs to arrive before the clock
 thold–hold time: the time the data has to
be stable after the clock

Timing analysis and sequential logic

Setup time, hold time and Clock-to-Q delay
4

Timing analysis and sequential logic

5
tcq

Timing analysis and sequential logic

6
Timing constraints

There are two main problems that can arise in synchronous logic:

 Max Delay: The data doesn’t have enough time to pass from one
register to the next before the next clock edge.
 Min Delay: The data path is so short that it passes through several
registers during the same clock cycle.

Timing analysis and sequential logic

7
Timing constraints
 Max delay violations are a result of a slow data path, including the
registers’ tsu, therefore it is often called the “Setup” path.
 Min delay violations are a result of a short data path, causing the data
to change before the thold has passed, therefore it is often called the
“Hold” path. Hold time violations

Timing analysis and sequential logic

8
Max (setup) constraints
 After the clock rises, it takes tcq for the data to propagate to point A.
 Then the data goes through the delay of the logic to get to point B.
 The data has to arrive at point B, tsu before the next clock.
So there is a race in timing path :
Between the Data Arrival, starting with the launching clock edge and the data
Capture, one clock period later.
Launch path

Capture path

Timing analysis and sequential logic

9
Min (hold) constraints
 The clock rises and the data at A changes after tcq.
 The data at B changes tpd(logic) later.
 Since the data at B had to stay stable for thold after the clock (for the second
register), the change at B has to be at least thold after the clock edge.
Hold time violation occur due to the logic changing before thold has passed.
•This is not a function of cycle time –it is relative to a single clock edge!

Timing analysis and sequential logic

10
Multiplexer-based Latches

Timing analysis and sequential logic

 Transistor level implementation of positive latch
11

vt = 0.7 v

5-1
= 4V

Due to body bias

effect in PTL, Vt
becomes 1 V

Reduced clock Load(clock is driving 2 transistors only)

Static Power Dissipation problem occurs at first inverter
High clock load (clock is driving 4 transistors)
because when we get high logic at output of PTL then nmos of inv1
No static Power dissipation.
should be on and pmos should be off but here Pmos also becomes On
output is at full swing ie if D= 5 then Q= 5
so there will be power dissipation.
Although output Qm is appropriate ie. if D= 5 V, then Qm =5 V.
Timing analysis and sequential logic
Due to static power dissipation problem in PTL, TG model is proposed for making Latch.
 Master Slave D FF
12

Make a positive edge triggered D-FF using Mux

Timing analysis and sequential logic

 Master Slave D FF
13

Timing analysis and sequential logic

 Master Slave D FF: Setup time, hold time
14

Before the positive clock edge comes, D needs to be stable for 3 inverter delays and one T.G. delay so that Qm should be sampled reliably i,e. Tsetup= 3.Pinv +T(t.g.).

QM should be sampled reliably., I1, T1, I3 and I2: 3x Pinv + Ttx

Hold time = 0
Propagation delay: QM takes to propagate to output Q : T3 and I6 .
After the first clock edge comes, Qm is already having the value of old D ie the D which was available to us when clock=0 & when lock comes ,then master latch
becomes opaque, so D has a full freedom to change its value. Hold time for D =0.

Timing analysis and sequential logic

 Reduced clock load D-FF
15

w/l(T1) > w/l(I1 &I2)

to overwrite any value at input of I1

 The penalty for the reduced clock load is increased design complexity. The transmission gate
(T1) and its source driver must overpower the feedback inverter (I2) to switch the state of the
cross-coupled inverter
 Another problem with this scheme is the reverse conduction

Timing analysis and sequential logic

 Why hold time will definitely violate in case of Positive skew?
Here, clock edge of 2nd Register will come after delta delay w.r.t. the arrival of clock edge of 1st register.So, jese hi first vale ki clock aayi ,it start
working and tclk-q hua, then tlogic aaya aur Q ki jo value h vo ready hokar aa gyi D ki state change krne k liye, ab D ko to uski clock aane k baad bhi
hold rehna h kuch time k liye aur launching flip flop ne rapidly apna sara delay de vekar bhj diya Q ko D ke input pr. That's why reg. 2 requires delta
Timing analysis
time apne delay ko compensate krne k liye chahiye and thold time chahiye hold krne k liye so

16

Timing analysis and sequential logic

 Timing analysis: Positive skew
17

So , tmin. decreases and frequency of clock increases but here hold time violation will be possible.

T >= tc-q + t logic + tsu- delta Timing analysis and sequential logic
 Timing analysis: Negative Skew (δ < 0)
18

Negative skew mein to humne delay introduce krdi hai pehle valew register ke kaam krne mein hi ,toh @nd vale ki to clock aa jaegi pehle aur
2nd vala clock aane k baad data hold krna start kr dega , aur jb tak 1st vala clock ki wait kr rha hoga and then clk-q ka transition kraega then
tlogic ka transition hoga ,uske baad D ke input pr reach krega uski state change krne ke liye tab tak to D sufficient time k liye data ko hold kra
chuka hoga
A negative skew implies that the system never fails
Timing analysis and sequential logic