VIVEKANANDHA COLLEGE OF ENGINEERING FOR WOMEN

(Autonomous Institution, Affiliated to Anna University ,Chennai)

Elayampalayam, Tiruchengode – 637 205

Programme B.E. Programme Code 103 Regulation 2019

ELECTRONICS AND COMMUNICATION Semester
Department
ENGINEERING
Periods Per Week Credit Maximum Marks
Course Code Course Name
L T P C CA ESE Total
U19ECV16 Foundations of VLSI 3 0 0 3 40 60 100
CAD
The main objective of the course is
 To provide an introduction to the fundamentals of Computer-Aided Design tools
for the modeling, design, analysis, test, and verification of digital Very Large Scale
Integration (VLSI) systems.
Course
 To understand the advanced techniques for solving computer-aided design
Objective
problems for a wide range of design styles.
 To Analysis different types of floor planning, placement and routing algorithms.
 To learn the two level logic synthesis and binary decision diagrams.
 To learn different Scheduling Algorithms
At the end of the course, the student should be able to Knowledge Level
CO1:Establish comprehensive understanding of the various
phases of CAD for digital electronic systems, from digital logic K3
simulation to physical design, including test and verification
Course CO2: Analyze the physical design process of VLSI design flow K4
Outcome CO3:Demonstrate knowledge of computational and optimization
K5
algorithms and tools applicable to solving CAD related problems.
CO4: Establish capability for CAD tool development and K3
enhancement.
CO5: Explore the hardware modeling and high level
K2
transformation
Pre-requisites
CO / PO Mapping CO/PSO
(3/2/1 indicates strength of correlation) 3-Strong, 2 – Medium, 1– Weak Mapping
Cos Programme Outcomes (Pos) PSOs
PO 1 PO 2 PO 3 PO 4 PO 5 PO 6 PO 7 PO 8 PO 9 PO PO PO PSO PSO PSO
10 11 12 1 2 3
CO 1 3 3 2 3 2
CO 2 3 3 2 3 2 2 2
CO 3 3 3 2 3 2 2 3 2
CO 4 3 3 2 2 2 3 2
CO 5 3 2 2 2 2 3

Course Assessment Methods

Direct
1. Continuous Assessment Test I, II & III
2. Assignment and Seminar
3. End-Semester examinations
Indirect
1. Course – end survey
Content of the syllabus
Unit – I VLSI DESIGN METHODOLOGIES Periods 9
168

Signature of BOS Chairman ECE

 Introduction to VLSI Design methodologies – Review of Data structures and algorithms –Review of VLSI
Design automation tools – Algorithmic Graph Theory and Computational Complexity – Tractable and
Intractable problems – general purpose methods for combinatorial optimization.
Unit – II DESIGN RULES Periods 9
Layout Compaction – Design rules – problem formulation – algorithms for constraint graph compaction –
placement and partitioning – Circuit representation – Placement algorithms – partitioning.
Unit – III FLOOR PLANNING Periods 9
Floor planning concepts – shape functions and Floor plan sizing – Types of local Routing problems – Area
routing – channel routing – global routing – algorithms for global routing.
Unit – IV SIMULATION Periods 9
Simulation – Gate-level Modeling and simulation – Switch-level Modeling and simulation- Combinational
Logic Synthesis – Binary Decision Diagrams – Two Level Logic Synthesis.
Unit – V MODELLING AND SYNTHESIS Periods 9
High level Synthesis – Hardware models – Internal representation – Allocation –assignment and scheduling –
Simple scheduling algorithm – Assignment problem – High level transformations.
Total Periods 45
TEXT BOOK
1. S.H. Gerez, ―Algorithms for VLSI Design Automation‖, John Wiley & Sons,2019
References
1. N.A. Sherwani, ―Algorithms for VLSI Physical Design Automation‖, Kluwer Academic
Publishers, 2002.
E-Resources
E1 https://nptel.ac.in/courses/108102042/CO-ORDINATED BY : IIT DELHI
E2 https://nptel.ac.in/courses/106102062/ CO-ORDINATED BY : IIT DELHI
https://drive.google.com/file/d/0BzoKWH8M1BoTVnBham5ENGZCUE0/view?usp=sharing&res
E3
ourcekey=0-fap9ekmWbZ0tZKnlXamzUg

169

Signature of BOS Chairman ECE