DESIGN AND IMPLEMENTATION OF 32-BIT ALU USING VERILOG A.Athihrii -12UEC001 M Stephen -12UEC016 Sanjay Kumar -12UEC020 @DESIGN AND IMPLEMENTATION OF 32-BIT ALU US! VERILOG Report submitted to National Institute of Technology Manipur for the award of the degree of Bachelor of Technology in Electronics and communication Engineering by A.Athihrii (12UECO01) M. Stephen (12UEC016) Sanjay kumar(12UEC020) Under the guidance of Shri MANOJ KUMAR Assistant Professor, NIT Manipur: is) DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING NATIONAL INSTITUTE OF TECHNOLOGY MANIPUR MAY 2016 © 2016, Athihrii, Stephen, Sanjay. All rights reserved (ii)DECLARATION We certify that a, the work contained in this report is original and has been done by me under the guidance of my supervisor's). b. the work has not been submitted to any other Institute for any degree or diploma, ¢. Thaye followed the guidelines provided by the Institute in preparing the report. 4, [haye conformed to the norms and guidelines given in the Ethical Code of Conduct of the Institute. €. whenever I have used materials (data, theoretical analysis, figures, and text) from other sources, I have given due credit to them by citing them in the text of the report and giving their details in the references. Further, I have taken permission from the copyright owners of the sources, whenever necessary. Signature of the Student Signature of the Student (vy)ACKNOWLEDGEME! es us immense pleasure to express our heartfelt gratitude and sincere thanks to our project mentor Shri, Manoj Kumar (Assistant Professor, Electronics And Communication Engineering) for his timeless and valuable contribution, suggestion and encouragement for the completion of this project. His continuous guidance had led us to execute our project titled “DESIGN AND IMPL We are deeply indebted to you Sir TATION OF 32-BIT ALU USING VERILOG”. A. ATHIHRII(12UECO01) M. STEPHEN (12UECO16) SANJAY KUMAR(12UECO020) (vi)ABSTRACT In this fast growing booming technology, the need for high-tech and superfast technology is on high demand. Hence through the use of FPGA (Field Programmable Gate Array) we can design superfast technology especially in the field of embedded system. Verilog standardized as IEEE 1364 is a hardware description language(HDL), @ textual format for describing electronics design and circuits. Applied to electronic design, verilog is intended to used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis. An Arithmetic Logie Unit (ALU) is a digital electronic circuits that performs arithmetic and bitwise logical operations on integer binary numbers. This is in contrast to FPU(Floating point unit jwhich operates on floating point numbers. ALU is a fundamental building block of many type of computing circuits incluling the central processing unit (CPU), FPU and GPU (Graphics Processing Unit)A single CP, FPU and GPU may contain multiple ALUs (vii)TITLE Title page Certificate Certificate Declaration Acknowledgement Abstract Contents List of Figures List of table CONTENTS Page NO. i vi vii viii xi xii CHAPTER-1 INTRODUCTION AND LITERATURE REVIEW 1-5 1.1 HDL (Hardware Description language) 1 1.2 Typical Design Flow 1.3 Literature review CHAPTER-2 INTRODUCTION TO VERILOG AND XILINX 6-10 2.1 Verilog 6 2.2 Xilinx 8 2.2.1 Procedure to Operate Xilinx (ISE 14.7) 9 2.3 Tools and Enviroment Used 10 2.3.1 Minimum Hardware Requirement 10 2.3.2 Minimum Software Requirement 10 (viii)3.1 Arithmetic Unit 3.2 Logic Unit 33 Shift unit 3.3.1 Left Shift 3.3.2 Right Shift 3.4 Arithmetic Logic Unit CHAPTER-4 VERILOG CODING AND WAVEFORM 4.1 Selection MUX 4 to 1 (1 bit YO) 4.2 Selection MUX 4 to 1 (32-bit /O) 4.3 Selection MUX 2 to I 32-bit VO) 4.4 Full adder 4.5 4-bit Adder 4.6 32-bit Adder 4.7 32-bit AND 4.832-bit OR 493 XOR 4.10 32-bit NOT. 4.11 Right shift 4.12 Left shift (ix) 11-19 MW 144.14 Arithmetic unit 4.15 Logic unit 4.16 32-bit ALU 4.17 Test Bench for 32-bit ALU CHAPTER-5 ADVANTAGE AND CONCLUSION 5.1 Importance of HDL. 5.2 Advantage of Verilog HDL §.3 Conclusion 5.4 Future scope of Verilog 5.4.1 Design process 5.4.2 System Level 5.4.3 Digital S44 Analog 5.4.5 Debugging REFERENCES © 40 48 - 52 48 48 49 50 51 51 SL 52 53LIST OF FIGURES 1.1 TYPICAL DESIGN FLOW 2.2 Xilinx ISE Interface 3.1 32-bit Arithmetic unit 3.2 32-bit Logic unit 3.31 (a) 32-bit before Left Shift (b) 32. it after Left Shift 3.3.2 (a) 32-bit before Right Shift (b) 32-bit after Right 3.3.3 32-bit Shift unit 3.4 Arithmetic Logic Unit A.A RTL of 32-bit ALU 4.2.40 1 32-bit Waveform 4.3 32-bit Arithmetic Unit Waveform 4.5 32-bit Shift unit Waveform 4.63 Waveform Arithmetic Logic w 5.4.1 Design process (xi) 16 7 19 47 50LIST OF TABLE ‘Table 1. Table of 32-bit Arithmetic unit Table 2, Table of 32-bit Logic uni Table 3. Table of 32-bit Shift unit Table 4, Table of 32-bit Arithmetic Logic unit (xii) 15 17DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING NATIONAL INSTITUTE OF TECHNOLOGY, MANIPUR Certificate This is to certify that the dissertation entitled “Design and Implementation of 32-bit ALU using Verilog” A.ATHIERIT (2UEC001) M.STEPHEN (22UEC016) SANJAY KUMAR (12UEC020) to the National Institute of Technology Manipur, India, is a record of bonafied project work carried out under my supervision and guidance and is worthy of consideration for the award of the degree of Bachelor of Technology in Electronics and Communication Engineering of the Institute. Signature of Guide (Shri.Manoj Kumar) (ii)Department of Electronics and Communication Engineering NATIONAL INSTITUTE OF TECHNOLOGY MANIPUR Takyelpar, Imphal- 79001, Ph.:0385-2445812, email: hodece@nitmanipur.ec.in Ref no.: NITMN/ECE:4/B. TECH ..... Dated... Certificate This is to certify that the Dissertation Report entitled, “Design and Implementation of 32-bit ALU using Verilog” submitted by Mr.“A.Athihrii, M. Stephen, Sanjay Kumar” to National Institute of Technology Manpur, India, is a record of bonafide Project work carried out by them under the supervision and guidance of Shri. Manoj Kumar (Assistant Professor, NIT Manipur) and is worthy of consideration for the award of the degree of Bachelor of Technology in Electronics and Communication Engineering of the Institute, HOD, ECE Department NIT MANIPUR (iy)Chapter 1 INTRODUCTION AND LITERATURE REVIEW Digital circuit design has evolved rapidly, the earliest digital circuits were designed with vacuum tubes and transistors. With the advent of VLSI (Very Large Scale Integration) technology, designers could design single chip with more than 100,000 transistors. Because of the complexity of these circuits, it was not possible to verify these circuits on a breadboard, Computer aided techniques hecame critical for verification and design of VLSI digital circuits. Computer programs to do automatic placement and routing of circuit layout also became popular. The designers were now building gate level digital circuits manually on graphic terminals. They would build small building blocks and then derive higher level blocks from them. This process would continue until they had built the top-level block. Logic simulator came into existence to verify the functionality of these circuits before they were fabricated on chip. 1.1 HDL (Hardware Description Language) Hardware Description Language (1] came into existence to replace programming language such as FORTAN, Pascal and C as a standard language to describe digital circuit. HDL is a specialized computer language used to describe the structure and behaviour of electronic circuit, and most commonly digital logic circuit ‘There are two types of HDL: 1. Verilog HDL 2. VHDL (VHSIC Hardware Description Language) ———— Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 1The advent of logic synthesis in the late 1980s changed the design methodology radically. Digital circuit could be described at RTL (Register Transfer Level) by use of an HDL. Thus, the designer had to specify how the data flow between register and how the design processes the data. The detail of gates and their interconnections to implement the circuits were automatically extracted by Logie synthesis tools from RTL descriptions HDL also began to use for system-level design. HDLs were used for simulation of system boards; interconnect buses, FPGA (Field Programmable Gate Array) and PALs (Programmable Array Logic). A common approach is to design each IC chip, using an HDL, and then verify system funetionality via simulation, Verilog HDL originates in 1983 at Gateway Design Automation, Later, VHDL was developed under contract from DARPA. Both Verilog and VHDL simulators to simulate large digital circuit quickly gain acceptance from designers. Verilog is a Hardware Description Language, a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis. ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page2Ta ea 1.2 TYPICAL DESIGN FLOW A typical design flow for designing VLSI IC circuits is shown in figure 1.1.Unshaded blocks show the level of design representation (1] :shaded blocks show processes in the design flow; U Physical Layout U Fig. 1.1 Typical Design Flow ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page31.3 LITERATURE REVIEW ‘The general idea of this particular project is to compile 32-bits logic gates, shift gates and arithmetic operation into one single MUX to carry out the desire operation successfully. L In ‘Verilog HDL, A guide to digital Design and Synthesis’ [1]. the book imparts the working knowledge of a broad variety of Verilog-based topics, thus giving the reader a global understanding of Verilog HDL-based design. The book leaves the in-depth coverage of each topic to the Verilog HDL language reference manual and the reference manuals of the individual Verilog-based products. it focus on tutorial In “The Verilog Hardware Description language’ [ approach to presenting the language. It continues with a more complete discussion of the language constructs. Numerous example are also provided to allow the reader to make it more easy to leam through examples. The rest of the book could be used in upper level logic design and architecture courses In ‘A Verilog HDL Primer’ (3](4], It is a practical and useful guide to Verilog HDL register-transfer level synthesis. A large number of synthesizable Verilog HDL examples are provided. Verilog HDL constructs that are supported for synthesis are described in detail. Common causes of functional mismatches between the design model and the synthesized netlist are described in detail and recommendations are make on how to avoid this. In ‘Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog’ [5] and “IEEE Std 1364-2001 : IEEE Standard Hardware Description Language based on the Verilog Hardware Description Language Published by the IEEE, Inc., hitp:/Avww.icee.org 345 Bast 47th Street, New York, NY 10017, USA” [6], mostly introduce a verifiable subset of Verilog and a simple RTL coding style. It enabled us to effectively incorporate these new verification technologies into our design flow. To provide a framework for discussion, it place emphasis on describing verification processes throughout the —S— Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page4text-as opposed to an in-depth discussion of the Verilog language. This book tells, how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. 5. In the project ‘Design and Implementation of 32-Bit ALU on XILINX FPGA using VHDL’ [7] they are designing an 32-bit ALU using VHDL and implementing on Xilinx FPGA. 6. In the project “Implementation of 32-bit Arithmetic Logic Unit on Xilinx using VHDL [8] the are implemeting the 32-bit ALU code on Xilinx. ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 PageSChapter 2 INTRODUCTION TO VERILOG AND XILINX 2.1 Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction, Verilog HDL has become an industry standard as a result of extensive used in the design of IC chips and digital systems, Verilog came into being as a proprietary language supported by a simulation environment that was the first to support by a simulation environment that was the first to support mixed-level design representations comprising switches, gates, RTL and higher levels of abstractions of digital circuits. The simulation environment provided a powerful and uniform method to express digital designs as well as tests that were meant to verify such designs. ‘There were three key factors that drove the acceptance and dominance of Verilog in the marketplace, First, introduction of Progrunming Language Interface (PLI) permitted users of Verilog to literally extend and customized the simulation environment. Since then users have exploited the introduction of Verilog-based synthesis technology by ‘Synopsys. The combination of the simulation and synthesis technologies serve to make Verilog the language of choice for PLI and their success at adapting Verilog to their environments has been a real winner for Verilog. The Second key factor which drove Verilog’s dominance came from Gateways paying close attention to the needs of the ASIC foundries and enhancing Verilog in close partnership with Motorola, National and UTMC.The realisation that the vast majority of logic simulation was being done by ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 6designers of ASIC chips drove this effort. The third key factor behind the success was the the hardware designers. Verilog also provide the concept of a module. A module is the basic building block in verilog. A module can be an element or a collection of lower-level design block. A module provides the necessary functionality to the higher level block through its port interface (inputs and outputs), but hides the internal implementation. This allows the designer to modify module internals without affecting the rest of the design Verilog is both a behavioural and structural language{1]. Internals of each module can be defined at four level of abstraction, The levels are defined below. i, Behavioural or algorithmic level This is the highest level of abstraction provided by verilog HDL. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. ii, Data flow At this level the module is designed by specifying the data flow. ‘The designer is aware of how data flows between hardware registers and how the data is processed in the design. iii, Gate level ‘The module is implemented in terms of logic gates and interconnection between these gates. Design at this level is similar to describing a design in terms of a gate level logic diagram. ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page7iv, Switeh level This is the lowest level of abstraction provided by verilog. A module can be implemneted in terms of switches, storage nodes and the interconnection between them. Verilog allows a designer to mix and match all four levels of abstraction in a design, In the digital design community, the term Register Transfer Level (RTL) is frequently used for a verilog description that uses a combination of behavioural and data flow constructs and is acceptable to logic synthesis tools. 2.2 Xilinx Xilinx is an American technology company, primarily a supplier of programmable logic devices and the first semi-conductor company with a fabulous manufacturing model. Founded in Silicon valley in 1984 and head quartered in San Jose, Califomia, USA, the company has cooperate offices throughout North America and Europe Xilinx ISE (Integrated Software environment) is a software tool produced by xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize their designs, perform timing analysis, examine RTL diagrams, simulate a design’s reaction to different stimuli and configure the target device with a programmer ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Pages2.2.1 Procedure to operate Xilinx. (ISE 14.7) 1. Open the Xilinx project Navigator 2. Following are the main areas of the Project Navigator, which are shown in the following figure. + Toolbar - provides convenient access to frequently used menu commands. + Design panel - provides access to the following areas: co Design View - allows you to select a design phase from the “Sources for” area, which controls the sources files displayed in the Hierarchy pane. © Hierarchy pane - allows you to view and manage design source files. © Processes pane allows you (o run processes, which move the design from design creation through programming the device. In addition, you can run processes that allow you to analyze and improve your design. + Workspace - allows you to view and edit your design using various tools, and provides access to reports in the Design Summary. + Transcript window - allows you to view output log, messages, errors, and ‘warming information as it is generated, ML lwebe thay Fig2.2 Xilinx ISE Interface ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page9Et elie evar) e VOT Ey) 2.3 Tools and Environment Used 2.3.1 Minimum Hardware Requirement: 1, Computer IBM or Compatible 2. Hard disk : 20 GB or higher 3. Processor : PENTIUM- IV 2 GHz orabove 4. Ram 2512 Mb and above 3. VDU : VGA 2.3.2 Minimum Software Requirement: 1. Operating System : Windows XP 2. Development Software : Xilinx ISE 8.21 ———— Department of Elect @Athihrii, Stephen, Sanjay 2016 Page 10Chapter 3 DESIGN OF ALU Designing of the ALU will follow the principle "Divide and Conquer” in order to use a modular design that consists of smaller, more manageable blocks, some of which can be re-used, An ALU consists of 3 units: 1. Arithmetic unit: Consists of addition, subtraction, addition with camry subtraction with borrow, increment, decrement and tansfer. 2. Logic Unit: Consists of AND gate, OR gate, NOT gate and XOR gate. 3, Shift Unit: Consists of left shifi, right shift. 3.1 Arithmetic unit An Arithmetic unit does the following tas \ddition, Addition with carry, Subtraction, Subtraction with borrow, Decrement, Increment and Transfer function. As the input is given in 32-bit, we get 32-bit output. The arithmetic will show only one output at a time , so a selector is necessary to select one of the operator. In this case, we use 8:1 multiplexer where s2, s1,s0 are selector lines, A and B is the input (o be given and Y is the output. Function Table for Arithmetic is shown in table 1. When s2s1s0= 000: then Y = A+B ie. Addition, ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 11When s2s1s0= 001: then RESULT= A-B ie. Subtraction. When s2s1s0= 010: then RESULT= A+B+l i.e. Addition with cary When 52s s0= O11: then RESULT= A+(~B) i.e. Subtraction with borrow. When s2s1s0= 100: then RESULT= A+1 i.e. Increment. When s2s1s0= 101: then RESULT= A-1 i.e. decrement. When s2s1s0= 110: then RESULT= A i.e. Transfer. 8 SL So Cin RESULT OPERATION a o 0 1 0 ACB Subtraction L,Y Eos 0 1 1 1 ACB ‘Subtraction with borrow a 1 0 1 0 Ad Decrement a a 1 1 1 0 xX ‘No function Table 1. Table of 32-bit Arithmetic Unit Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 12Subtraction Addition with carry Subtraction with borrow Increment Decrement ‘Transfer Fig 3.1. 32-bit Arithmetic unit ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 133.2 Logic Unit A Logic unit does the following task: Logical AND, Logical OR, Logical XOR and Logical NOT operation. We will design a logic unit that can perform the four basic logic Micro operations: OR, AND, XOR and Complement, because from these four micro- operations, all other logic micro-operations can be derived. A one-stage logic unit for these four basic ~—micro-operations. is shown in’ the Fig.3.2 Fig. 3.2 32-bit Logic Unit ‘The logic unit consists of four gates and a 4:1 multiplexer. The outputs of the gates are applied to the data inputs of the multiplexer. Using to selection Lines $0 and 1 one of the data inputs of the multiplexer is selected as the ontput. For a logic unit of 32bit, the output will be of 33-bit with 33th bit to be High-impedance. ‘The common selection lines are applied to all the stages When $1 S0= 00: RESULT=A-B i.e, AND. When $1 S0=01: RESULT= A+B ie. OR. Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 14When $1 SO= 10: RESULT= A@B i.e. XOR. ‘When $1 SO= 10; RESULT= A ie. NOT SI ‘sO ‘RESULT OPERATION 0 o AB AND 0 AB OR 1 o a NOT 1 1 AGB XOR Table 2 .Table of 32-bit Logic Unit 3.3 Shift Unit A Shift register is a storage device that used for storage or the transfer of da of binary numbers. Considering two types of register: i, Left shift ii, Right shift 3.3.1 Left Shift Data is shified in the left hand direction one bit at a time with each transition of the clock signal. The data enters the shift register serially from the right hand side and after 32 clock transition the 32-bit register has 32-bit of data . The data is shifted out serially one bit at a time from the left hand side of the register if clock signal are continuously applied. The operation of left shit is shown on the figure 3.3.1 (a) and (b).. p31 | p30 pi | 00 Cin (a) Department of Electronics and Communication Engineering ©Athihrii, Stephen, Sanjay 2016 Page 153 (b) Fig. 3.3.1 (a)32-bit before left shift. (b)32-bit after left shift. 3.3.2 Right Shift ‘The data is shifted in the right hand direction one bit at a time with each transition of the clock signal. The data enter the shift register serially from the left hand side and after 32 clock transition the 32- bit register has 32-bit of data. The data is shifted out serially one bit at a time from the right hand side of the register if clock signal are commonly applied The operation of right shift is shown on the figure 3.3.2 (a) and (b). p31 | 030 D1 | pa (a) Cin | 031 D1 Do (b) Fig 3.3.2 (a) 32-bit before right shift .(b) 32- bit after right shift ‘The contents of a register that has to be shifted first placed onto common bus. The ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 16circuit uses no clock pulse. When the shifting unit is activated, the register is shifted left orright according to the selection unit, It used only one selector line ies For a shift unit of 32-bit, the output will be of 33-bit with 33th bit to he the outgoing bit ‘The circuit of shift unit is shown in figure 3.3 RIGHT SHIFT UNIT i mp RESUET system LEFT SHIFT UNIT e 2 Fig 3.3. 32-bit Shift Unit 81 RESULT OPERATION 0 a> Right Shift 1 acel Left Shift Table 3. Table of 32-bit Shift Unit 3.4 Arithmetic Logic Unit ‘The technique used in these is to split ALU into three modules, Arithmetic, Logic and shift module, Here the arithmetic, logic and shift that define earlier are combined into ALU with common selection line. The shift micro-operation are often perform in seperate unit, but sometime the shifter unit made part of overall ALU. For 32-bit ALU a 33 bit 4:1 MUX is needed. A particular arithmetic or logic or shift operation is selected according to the selection inputs $4 ,85,S6 and $7. The final output ———— Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 17ERR susie Pee MURA oul pon of the ALU is determined by the set of multiplexers with selection lines $2 and $3 for logic and $1 for shift.. The function table for the ALU is shown in the Table. 4. The table lists 13 micro-operations: 7 for arithmetic, 4 for logic and 2 for shifter unit. For shifter unit, the selection line $1 is used to select either left or right shift micro-operation. “7 3S 4 8 2 1 0 CN RESULT OPERATION: oo10000 01 ATB1 Addition with carry o 10000011 ATL Subtraction ooo 01110 X A@B XOR oo01xX00XX ISR A Right shift Table 4. Table of 32-bit Arithmetic Logic Unit Department of Electronics and Communi @Athihrii, Stephen, Sanjay 2016 Page 18Fig.3.4 Arithmetic Logic Unit Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 19Et elie evar) e VOT Ey) Chapter 4 VERILOG CODING AND WAVEFORM 4.1 Selection MUX 4 tol (1-bit /O) module mux4(i0,i1,i2i3.90,s1,clk.y); input i0,i1 i2.i3,s0,s1,clk; output reg y; always @ (posedge clk) case (i0,i \s1}) 2b00:y=i0; 2bO1:y=il; 2b10:y=i2; 2bIL:y=i3; default y=1'bz: endease endmodule ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 20Et elie evar) e VOT Ey) 4.2. Selection MUX 4 tol (32-bit /O) module muxdl (out, 10,11. i2, 13, s1, $0); input{31:0] iO, 11,12, 13; input s1, $0; outpui[3 1:0] out; reg[31:0] out; always @(s1 or SO or i oril or i2 or i3) case ((s1, $0}) 200 : out = i0; 201 : out =il; 210 : out = 12; 2bI: ont =i3: default: Sdisplay("Invalid control signals"); endease endmodule 4.3 Selection MUX 2 to1(32-bit /O) module mux21 (out, 10, i1, $0); input{31:0] 10, i1; input $0; ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 21output(31:0] out; reg[31:0] out; always @( $0 or i ori ) case ({ $0}) V’b0 : out = i; Vb1 : out =il; default: $display( "Invalid control signals") endease endmodule 44 Full Adder module faddl (a,b.s.c,carry); input a,b,c; oulput scarry; assign s=atb’e; assign camy=a&btb&ct eda; endmodule 4.5 4-Bit Adder module add(a.b,y); input (3:0]a,b; ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 22Et elie evar) e VOT Ey) output{ 3:0] y; assign y=atb; endmodule 4.6 32-Bit Adder module ader32bit(a,b,y); input{31:0]a.b; output [31:0ly; assign y=ab; endmodule 4.7 32-Bit AND module and32(a.b.y): input (31:0]a; input [31:0)b: output [31:0]y; assign y=u&b; endmodule 48 32-Bit OR module orl(aby, input[31:0}a.b; ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 23Et elie evar) e VOT Ey) output(3 L:0ly; assign y=alb; endmodule 4.9 32-Bit XOR module xor32(a,b.y); input (31:0]a, input [31:0]b: output (31:0ly: assign y=a"b; endmodule 4.10 32-Bit NOT module not32(a,y); input (31:0), output (31:0ly; assign y= endmodule 4.11 Right Shift module rshilt(a,b); input{31:0]a; ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 24output(31:0]b; assign b=a>>1; endmodule 4.12 Left Shift module shift32a(a,b); input{31:0}4; output{31:0]b; assign b=a<>1; endmodule module Ishift(a.b); input (31:0]a;, output [31:0] b; assign b=a<<1; endmodule 4.14 Arithmetic Unit module arith (a,b,cin,s0,s1,s2, result); input[31:0] ab; input cin; ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 26input s0,s1,82; output{ 31:0] result; reg{31:0] result; wire[3 1-0] w0,w1,w2,w3,w4,w5,w6; add rl(a,b,w0); sub P(a.bw)s addwe r3(a,b,cin,w2); subwb r(a.b.cin,w3); inc rS(a,w4); dec r6(a,w5); tra 17 (a,w6); always@ (a,b,cin,s0,s1,52,.0,v 1, w2,W3,w4,W5,W6) case ({82,s1,s0}) 3000: result<=" Haddition// SPOOL: result<=w1; //subtraction// 31010: result<=w?; addition with carry// 3011: result<=w3; //subtraction with borrowi/! 316100: result<=w4; // increment// SIO: result<=" ; Idecrement/! ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 273'b1 10: result<=w6; //transfer!/ SILL: resulte=I'bx; //no need /! endease endmodule Wadd! module add(a.b.y); input (31:0]a,b; output(31:0] y; assign y=a+b; endmodule sub) module sub(a,b,y); input [31-0}ab; output(31:0] y; assign y=a-b; endmodule Wadditiion with carryl! module addweta,h,cin,y); input (31:0]ab: ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 28input cin; output [31:0]y: assign y=atbtcin; endmodule Jisub with borrow// module subwb(a,bciny); input (31:0]a,b; input cin; output [31:0]y; Houtput br; assign y=a+(~b)+cin; endmodule Hincrement/ module incta,y): input{31:0) & output{31:0] y; assign y=a4: endmodule Wderedmenti/ ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 29module dec(a.y): input [31:0]a; output [31:0]y; assign y=a-1; endmodule Mvanstert! module tra(ay); input{31:0]a; output(31:0]y; assign y=a; endmodule 4,15 Logic Unit module logicunit32bit(a,b,s1,s0,result ); input{31:0] a,b; input s1,s0; output reg (31:0)}result; wire [31:0]wl w2,w3,w4; andl al (a,b,wl); orl a2 (a,b,w2); ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 30not! a3(a,w3); exorl af(ab,w4); always @ (a,b,s1,s0,w1,w2,w3,w4) begin case({s1,s0}) 2b00:resultc= wi: 2bOL-result<=w2; 2bI0-result<=w3; 2bI L:resulte=w4; defaultresult<=1 0: endcase end endmodule module andl (ed); input{31:0] ed; output [31-0]: assign jec&d: endmodule module orl(cd,j): ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 31input{31:0] cd; output{31:0] j; assign j=cld; endmodule module not (c,d); input[31:01 output [31:0}4; assign d= ~c; endmodule module exor! (c,d); input (31:0]e4; output [31:0]; assign j=cMd; endmodule 4.16 32-bit ALU module alu2{a,b.s 83,81,80,s4,85,56,87.cin,result ); input(31:0] ab; input s2,s3,s1,s0,s4,s5,s6,s7,cin; output reg[31:0] result; ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 32wire [31:0]wI,w2; wire[31-0] w3; wire [31:0] 4 w5,w6,w7,w8,w9,W10; shifi al (s1acinyw1); logicunit32hit a2 (a,b,s2,83,w3); addearry 23(a,b,cin.w4,s4,55.8687); add ad (a,b,cin,w5,94.$5,56,87); sub a5 (a,b.cin,w6,54.85,96,87 ): subcarry a6 (a,b,cin,w7,s4,85,86,87 }; incremen22 a7 (a,cin,w8,s4,s5,56,87); decremen22 a8 (a,cin,w9.s4,s5,$6.87); td 09 (w10,a,cin,s4,85,36,87); always @ (a,b,w3,s1,s0,cin,s4,w 1, w4,w5,w6,W1,W8,W9,W10,85,2,$6,87,83) begin case( (84,55.96,87}) 4h0000-resulte= w3; 40001 sresule<=wl; 4'b0010:result<=w4; 4001 L:result<=w5; ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 334'b0100:result<=w6; 40101 sesultc=w7; 401 10:result<=w8; AOL Lsresultc=w9 4b1000:result<=wl0; 41001 sresulte=1'bx; 4b1010:result<= 'bx; 4101 Lsresult<=1'bx; 4'b1 100:resulte=I'bx; 41101 result<=l'bx; 4'b1 L10:resulte=I'bx; AIL Loresult<=l'bx; default:result<=I 'b0; endease end endmodule module shift(st.acin,res); input{31:0] a input s1,cin; ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 34output reg (31:0}res ; wire [31:0}w1w2, phiftrl@awl); Ishift s2(aw2); always @(a,s1,w1,w2) case((s1}) I'bO:res<=w 1; Vbl:tesc=w2; endease endmodule module rshift(a,b); input{31:0] output{31:0] b; assign b=a>>1; endmodule module Ishift(a.b); input{31:0] output [31:0] b; assign b=a<<1; ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 35endmodule module logicunit32bit(al I,b1,s11.s00zes ); input{31:0} al 1 b11; input s11,s00; output reg[3 1:0] res; wire(31-0] w31,w41.w51,w6l; andl al (al bl1w31); orl a2 (al ,b11,w41); not! a3(all,w51); exorl a4(al L.b11,w61); always @(alL bLL,s1 ,s00,w31,w4l,w51,w61) begin case( [s11,900}) 2hO0:res<= w31; 2bOL:res By describing designs in HDLs, functional verification of the design can be done early in the design cycle. Since designers work at RTL level, they can optimize and modify the RTL description until it mect the desired functionality, Most design bugs are eliminated at this point, > Designing with HDLs is analogous to computer programming. A textual description with comments is an easier way to develop and debug circuits. This also provides @ concise representation of the design, compare to gate level schematics, Gate level schematics are almost incomprehensible for very complex designs. 5.2 Advantages of Verilog HDL Y Verilog HDL is a general-purpose hardware description language that is easy to eam and easy to use. It is similar in syntax to the C programing language. Designers with C programing experience will find it easy to learn Verilog HDL. ¥ Verilog HDL allow different level of abstraction to mixed in the same model Thus , a designer can define a hardware model in terms of switches, gates, RTL, ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 48or behavioural codes. Also, a designer needs to leam only one language for stimulus and hierarchical design. ¥ Most popular logic synthesis tools support Verilog HDL. This makes it the language of choice for designers ¥ All fabrication vendors provide Verilog HDL libraties for post logic synthesis simulation. Thus, designing a chip in Verilog HDL allows the widest choice of vendors. ¥- The programming language interface (PLI) is a powerful feature that allow s the user to write custom C code to interact with the internal data structures of Verilog. Designers can customized a Verilog HDL simulator to their needs with the PLL 5.3 Conclusion In our project “Design and Implementation of a 32-hit ALU using Verilog” we have designed and implemented a 32 bit ALU. Arithmetic Logic Unit is the part of a computer that performs all arithmetic computations such as addition, subtraction, addition with carry, subtraction with borrow, increment and decrement shifting such as right shift and left shift and all basic logical operations like AND, OR,NOT and XOR. ALU represents the fundamental building block of the central processing unit (CPU) of a computer We have compare the number of MUX with [7],[8] which result in less number of MUX that we used, ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 495.4 Future scope of Verilog Verilog can be used at different levels of abstraction as we have already seen [9]. But how useful are these different levels of abstraction when it comes to using Verilog? 5.4.1 Design process ‘The diagram below shows a very simplified view of the electronic system design process incorporating Verilog. The central portion of the diagram shows the parts of the design process which will be impacted by Verilog System analysis and partitioning Physical spe——HIW spec Analog spec shi funetion spec Verilog SIW Sign off simulation xed sone Layout Fig.5.4.1 Design Process ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 505.4.2 System Level Verilog is not ideally suited for abstract system-level simulation, prior to the hardware- software split. This is to some extent add ressed by SystemVerilog. Unlike VHDL, which hhas support for user-defined types and overloaded operators which allow the designer to abstract his work into the domain of the problem, Verilog restricts the designer to working with pre-defined system functions and tasks for stochastic simulation and can be used for modelling performance, throughput and queueing but only in so far as those built-in language features allow. Designers occasionally use the stochastic level of abstraction for this phase of the design process. 5.4.3 Digital Verilog is suitable for use today in the digital hardware design process, from functional simulation, manual design and logic synthesis down to gate-level simulation. Verilog tools provide an integrated design environment in this area Verilog is also suited for specialized implementation-level design verification tools such as fault simulation, switch level simulation and worst case timing simulation, Verilog can be used to simulate gate level fanout loading effects and routing delays through the import of SDF files. The RTL level of abstraction is used for functional simulation prior to synthesis. The gate level of abstraction exists post-synthesis but this level of abstraction is not often created by the designer, it is a level of abstraction adopted by the EDA tools (synthesis and timing analysis. for example). 5.4.4 Analog Because of Verilog's flexibility as a programming language, it has been stretched to handle analog simulation in limited cases. There is a drait standard — Verilog-AMS ~ that addresses analog and mixed signal simulation, Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 515.4.5 Debugging Accuracy and time is essential—especially when it comes to your development simulation and debugging. Our Verilog simulator and compiler will change the way you can simulate, debug, and manage your development process. VeriLogger Extreme is a high-performance compiled-code Verilog 2001 simulator with automatic test bench generation that significantly reduces simulation debug_ time VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel/MicroSemi, Altera, Atmel, LSI Logic, Quick Logic, and Xilinx. ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 52References (1). [2 (3). (4) (5). Samir Paluitkar, Verilog HDL, A Guide to digital design and Synuhesis, Published by Prentice Hall PTR, 1996 ISBN 10: 0134516753 / ISBN. 13: 9780134516752. Donald E, Thomas and Philip R. Moorby, The Verilog Hardware Description language . Published by Springer; 5th ed, 2002 edition (27 October 2008). ISBN-10: 0387849300,ISBN-13: 978-0387849300 J Bhasker, A Verilog HDL Primer . Published by Bs Publications/bsp Books(2008). ISBN-10: $17800142X, ISBN-13: 978-8178001425 Lionel Benning and Harry Foster, Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog. Published by Springer; 2nd ed. 2001 edition (31 May 2001). ISBN-10: 0792373685, ISBN-13: 978-0792373681 IEEE Std 1364-2001 : IEEE Standard Hardware Description Language based on the Verilog Hardware Description Language Published by the IEEE, Inc., hup:/www.ieee.org 345 East 47th Steet, New York, NY 10017, USA. [6]. Douglas J Smith, FPGAs using VHDL or Verilog . Published by Doone Publications. 7. Anushka Pakrashi, Arindam Bose, Kausik Bhattacharya, Monigingir Pal, Tanaya Bose. Design and Implementation of 32-Bit ALU on XILINX FPGA using VHDLinstiute, FUTURE INSTITUTE OF ENGINEERING AND MANAGEMENT (2008-2012). ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 53{8]. Anadi Anant Jain, Ankush Bhushan, Bhavyai Gupta, Faizan Ayubi. Implementation of 32-Bit arithmetic Logic Unit on Xilinx using VHDL. Institute : DELHI TECHNOLOGICAL UNIVERSITY. [9]. https:/www doulos.com/knowhow/verilog_designers_guide/scope_of_verilog/ ee Department of Electronics and Communication Engineering @Athihrii, Stephen, Sanjay 2016 Page 54