5 4 3 2 1

ZYV BLOCK DIAGRAM

BEEMA VRAM
D
GPU Channel A
D

PEG PEG0~3(PCI-E x4)

TX/RX Opal XT(18/25W)
DDRIII-SODIMM1 BGA 769 Jet XT(18/25W) Channel B (Jet)
P9 29mm X 29mm
P11,12,13,14,15,16,17,18 VRAM DDR3-128Mb*4 = 1GB
Single Channel DDR III X'TAL VRAM DDR3-128Mb*8 = 2GB
DDRIII-SODIMM2 1066/1333/1600 MHZ IMC
27.0MHz
P19,20
P10
USB2-1 (CCD)

CLK USB2-3 (Touch)

eDP/CCD Con.

eDP
INT_eDP DP0
P21
SATA - HDD SATA 0 SATA0
P26
VGA DAC
INT_CRT CRT Con.
C EV@ -----> GPU C
P21 EV_O@ -----> OPAL GPU
EV_SP@ -----> GPU special part
FT3B TPM@ -----> TPM
SATA - ODD SATA 1 SATA1
HDMI
INT_HDMI DP1 HDMI Con. TPM_I@ -----> TPM SLB9655TT1.2
P26 APU TPM_N@ -----> TPM NPCT650AA0WX
P22 KBL@ -----> KB backlight
SP@ -----> Special part
USB3 - 0 & 1 RD@ -----> SATA redriver
USB3.0 USB3 Con. x2 HDT@ -----> HDT connector
USB2 - 8 & 9 P27
USB2 Con.
DB USB/IO Board USB2- 0 & 5 PCI-E x1
PCIE-1
Connector USB2.0
MINI CARD
P27 USB2-7 WLAN+BT
USB2 Con.
DB P24
X'TAL
32.768KHz

Card Reader IO PCIE-2

CR Con.
Board Conn USB2- 6 P3,4,5,6,7,7,8
RJ45 Con.
GL834L (SD) RTL8111GS-CG P23
DB P27 X'TAL 48MHz 10/100/1G
X'TAL
B 25MHz B
P23
SPI ROM
SPI
8M P6

Azalia IHDA RTC

BQ24737 ISL62771
LPC
BATTERY P6 Batery Charger P31 CPU CORE / VDDNB P35

TPM TPS51225 TPS54318

P24 3V/5V P32 1.8V P36
EC
ALC283-CG
TPS51216 TPS51728
AUDIO CODEC P25
IT8587 P30 +1.5V_SUS P33 VGPU CORE P37

PS/2
TPS51211 TPS54318 P38
A A
0.95V P34 GPU_POWER / VDDC_GFX

Phone Speaker DMIC K/B Con. HALL SENSOR FAN Con. I2C MCU USB2-2
Jack P25 (PWM)
P25 P25 P28 P21 P28 P28

Quanta Computer Inc.

Touch Pad PROJECT : ZYV
Con. Size Document Number Rev
P29 C3A
Block Diagram
Date: Monday, April 28, 2014 Sheet 1 of 40
5 4 3 2 1
 1 2 3 4 5 6 7 8

Power Sequence

ACIN
KABINI FT3 SMBUS
3V/5VPCU
SMBUS Pin NO. SMBUS Function Define
NBSWON#
A CLK_SCLK AU25 A
DDR / Touch Pad/ WLAN
DNBSWON# CLK_SDATA AV25
(+3V)
S5_ON/S5
SCL1 AY11 MBCLK
Battery / Charger/ EC
SDA1 BA11 MBDATA
RSMRST#
(+3V_S5) (+3VPCU)

SVC D27
PCIE_WAKE# +VDDNB_CORE
SVD E29
(+3V_S5)
SUSC
APU_SIC B22
APU / EC
SUSB APU_SID B21
(+3V)
SUSON

MAINON

VR_ON
B B

CPU_CORE
KBC(EC) SMBUS
VRM_PWRGD
NPCE985 SMBUS Pin NO. SMBUS Function Define
HWPG
Power States MBCLK 70
Battery / Charger/ EC
CONTROL ECPWROK MBDATA 69
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN
(+3VPCU)
SB_PWRGD_IN
VIN +10V~+19V MAIN POWER ALWAYS ALWAYS APU_SIC_EC 67
APU / EC
APU_SID_EC 68
+1.5V_RTC +1.5V RTC POWER ALWAYS ALWAYS CPU RESET
(+3VPCU)
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
CPU POWER OK
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

+3V_S5 +3.3V LAN/ TPM POWER S5_ON S0-S5

Thermal Follow Chart
C +5V_S5 +5V USB POWER S5_ON S0-S5 C

+1.8V_S5 +1.8V APU/PCH/Braidwood POWER S5_ON S0-S5

+1.5V_S5 +1.5V MINI CARD/NEW CARD POWER S5_ON S0-S5 APU CORE_PWM_PROCHOT#
+0.95V_S5 +0.95V APU CORE POWER S5_ON S0-S5 CORE PWR H/W Throttling APU
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0

+3V +3.3V APU/Peripheral component /WLAN POWER MAINON S0

THERM_ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0

PROCHOT_EC
+1.8V +1.8V APU/PCH/Braidwood POWER MAINON S0
SM-Bus
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

+0.95V +0.95V APU CORE POWER MAINON S0

EC
+VDDNB_CORE variation APU CORE POWER VRON S0 CPUFAN#

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0 NTC 3V/5 V

D SYS_SHDN# D
S5_ON Thermal SYS PWR
Protection

Quanta Computer Inc.

PROJECT : ZYV
Size Document Number Rev
C3A
PWR Status & GPU PWR CRL & THRM
Date: Monday, April 28, 2014 Sheet 2 of 40
1 2 3 4 5 6 7 8
 5 4 3 2 1

M_A_DQ[0..63] [9,10]
U24B
[9,10] M_A_A[15:0] M_A_A0 AG38 B30 M_A_DQ0
M_A_A1 W 35 M_ADD0 M_DATA0 A32 M_A_DQ1
M_A_A2 W 38 M_ADD1 KABINI M_DATA1 B35 M_A_DQ2
M_A_A3 W 34 M_ADD2 PART 2 OF 9 M_DATA2 A36 M_A_DQ3
D M_A_A4 U38 M_ADD3 M_DATA3 B29 M_A_DQ4 D
M_A_A5 U37 M_ADD4 M_DATA4 A30 M_A_DQ5
M_A_A6 U34 M_ADD5 M_DATA5 A34 M_A_DQ6
M_A_A7 R35 M_ADD6 M_DATA6 B34 M_A_DQ7
M_A_A8 R38 M_ADD7 M_DATA7
M_A_A9 N38 M_ADD8 B37 M_A_DQ8
M_A_A10 AG34 M_ADD9 M_DATA8 A38 M_A_DQ9
M_A_A11 R34 M_ADD10 M_DATA9 D40 M_A_DQ10
M_A_A12 N37 M_ADD11 M_DATA10 D41 M_A_DQ11
M_A_A13 AN34 M_ADD12 M_DATA11 B36 M_A_DQ12
M_A_A14 L38 M_ADD13 M_DATA12 A37 M_A_DQ13
M_A_A15 L35 M_ADD14 M_DATA13 B41 M_A_DQ14
[9,10] M_A_BS#[2..0] M_ADD15 M_DATA14 C40 M_A_DQ15 U24A
M_A_BS#0 AJ38 M_DATA15 R10 L2
M_A_BS#1 AG35 M_BANK0 F40 M_A_DQ16 R8 P_GPP_RXP0 P_GPP_TXP0 L1
M_A_BS#2 N34 M_BANK1 M_DATA16 F41 M_A_DQ17 P_GPP_RXN0 KABINI P_GPP_TXN0
[9,10] M_DM[7..0] M_BANK2 M_DATA17 K40 M_A_DQ18 PCIE_RXP1 R5 PART 1 OF 9 K2 PCIE_TXP1_C C597 0.1U/10V/X7R_4 PCIE_TXP1 [24]
M_DM0 B32 M_DATA18 K41 M_A_DQ19 [24] PCIE_RXP1 PCIE_RXN1 R4 P_GPP_RXP1 P_GPP_TXP1 K1 PCIE_TXN1_C C599 0.1U/10V/X7R_4 PCIE_TXN1 [24]
M_DM1 B38 M_DM0 M_DATA19 E40 M_A_DQ20 [24] PCIE_RXN1 P_GPP_RXN1 P_GPP_TXN1
M_DM2 G40 M_DM1 M_DATA20 E41 M_A_DQ21 PCIE_RXP2_LAN N5 J2 PCIE_TXP2_LAN_C C601 0.1U/10V/X7R_4
M_DM3 M_DM2 M_DATA21 M_A_DQ22 [23] PCIE_RXP2_LAN PCIE_RXN2_LAN P_GPP_RXP2 P_GPP_TXP2 PCIE_TXP2_LAN [23]
N41 J40 N4 J1 PCIE_TXN2_LAN_C C603 0.1U/10V/X7R_4
M_DM4 M_DM3 M_DATA22 M_A_DQ23 [23] PCIE_RXN2_LAN P_GPP_RXN2 P_GPP_TXN2 PCIE_TXN2_LAN [23]
AG40 J41

PCIE I/F
M_DM5 AN41 M_DM4 M_DATA23 N10 H2
M_DM6 AY40 M_DM5 M41 M_A_DQ24 N8 P_GPP_RXP3 P_GPP_TXP3 H1
M_DM7 AY34 M_DM6 M_DATA24 N40 M_A_DQ25 P_GPP_RXN3 P_GPP_TXN3
Y40 M_DM7 M_DATA25 T41 M_A_DQ26 R138 1.69K P_TX_ZVDD_095 W8 W 7 P_RX_ZVDD_095 1K R135
M_DM8 M_DATA26 M_A_DQ27 +0.95V P_TX_ZVDD_095 P_RX_ZVDD_095 +0.95V
U40
B33 M_DATA27 L40 M_A_DQ28
[9,10] M_A_DQS0 M_DQS_H0 M_DATA28 M_A_DQ29
A33 M40
[9,10] M_A_DQS#0 B40 M_DQS_L0 M_DATA29 R40 M_A_DQ30 L5 G2 PEG_TXP0_C C608 EV@0.1u/10V_4
C [9,10] M_A_DQS1 A40 M_DQS_H1 M_DATA30 T40 M_A_DQ31 [11] PEG_RXP0 L4 P_GFX_RXP0 P_GFX_TXP0 G1 PEG_TXN0_C PEG_TXP0 [11] C
C605 EV@0.1u/10V_4
[9,10] M_A_DQS#1 M_DQS_L1 M_DATA31 [11] PEG_RXN0 P_GFX_RXN0 P_GFX_TXN0 PEG_TXN0 [11]
H41
[9,10] M_A_DQS2 H40 M_DQS_H2 AF40 M_A_DQ32 J5 F2 PEG_TXP1_C C609 EV@0.1u/10V_4
[9,10] M_A_DQS#2 M_DQS_L2 M_DATA32 M_A_DQ33 [11] PEG_RXP1 P_GFX_RXP1 P_GFX_TXP1 PEG_TXN1_C PEG_TXP1 [11]
P41 AF41 J4 F1 C606 EV@0.1u/10V_4
[9,10] M_A_DQS3 M_DQS_H3 M_DATA33 M_A_DQ34 [11] PEG_RXN1 P_GFX_RXN1 P_GFX_TXN1 PEG_TXN1 [11]
P40 AK40

GFX
[9,10] M_A_DQS#3 AH41 M_DQS_L3 M_DATA34 AK41 M_A_DQ35 G5 E2 PEG_TXP2_C C612 EV@0.1u/10V_4
[9,10] M_A_DQS4 AH40 M_DQS_H4 M_DATA35 AE40 M_A_DQ36 [11] PEG_RXP2 G4 P_GFX_RXP2 P_GFX_TXP2 E1 PEG_TXN2_C PEG_TXP2 [11]
C610 EV@0.1u/10V_4
[9,10] M_A_DQS#4 AP41 M_DQS_L4 M_DATA36 AE41 M_A_DQ37 [11] PEG_RXN2 P_GFX_RXN2 P_GFX_TXN2 PEG_TXN2 [11]
[9,10] M_A_DQS5 AP40 M_DQS_H5 M_DATA37 AJ40 M_A_DQ38 D7 D2 PEG_TXP3_C C613 EV@0.1u/10V_4
[9,10] M_A_DQS#5 BA40 M_DQS_L5 M_DATA38 AJ41 M_A_DQ39 [11] PEG_RXP3 E7 P_GFX_RXP3 P_GFX_TXP3 D1 PEG_TXN3_C PEG_TXP3 [11]
C611 EV@0.1u/10V_4
MEMORY I/F

[9,10] M_A_DQS6 AY41 M_DQS_H6 M_DATA39 [11] PEG_RXN3 P_GFX_RXN3 P_GFX_TXN3 PEG_TXN3 [11]
[9,10] M_A_DQS#6 M_DQS_L6
AY33 AM41 M_A_DQ40 FT3B_BEEMA
[9,10] M_A_DQS7 BA34 M_DQS_H7 M_DATA40 AN40 M_A_DQ41
[9,10] M_A_DQS#7 AA40 M_DQS_L7 M_DATA41 AT41 M_A_DQ42
Y41 M_DQS_H8 M_DATA42 AU40 M_A_DQ43
M_DQS_L8 M_DATA43 AL40 M_A_DQ44
AC35 M_DATA44 AM40 M_A_DQ45
[9] M_A_CLK0 AC34 M_CLK_H0 M_DATA45 AR40 M_A_DQ46
[9] M_A_CLK0# M_CLK_L0 M_DATA46
[9] M_A_CLK1
AA34
M_CLK_H1 DIM0 M_DATA47
AT40 M_A_DQ47
AA32
[9] M_A_CLK1# AE38 M_CLK_L1 AV41 M_A_DQ48
[10] M_B_CLK0 M_CLK_H2 M_DATA48
AE37 AW 40M_A_DQ49
[10] M_B_CLK0# M_CLK_L2 M_DATA49 BA38 M_A_DQ50
[10] M_B_CLK1
AA37
M_CLK_H3 DIM1 M_DATA50
AA38 AY37 M_A_DQ51
[10] M_B_CLK1# M_CLK_L3 M_DATA51
R67 1K_4 AU41 M_A_DQ52
+1.5V_SUS M_DATA52
G38 AV40 M_A_DQ53
[9,10] DDR3_DRAMRST# AE34 M_RESET_L M_DATA53 AY39 M_A_DQ54
[9,10] M_A_EVENT# M_EVENT_L M_DATA54 AY38 M_A_DQ55
L34 M_DATA55
[9] M_A_CKE0 M0_CKE0 M_A_DQ56
[9] M_A_CKE1
J38
M0_CKE1 DIM0 M_DATA56
BA36
M_A_DQ57
B J37 AY35 B
[10] M_B_CKE0 M1_CKE0 M_DATA57
[10] M_B_CKE1
J34
M1_CKE1 DIM1 M_DATA58
BA32 M_A_DQ58
M_A_DQ59
AY31
AN38 M_DATA59 BA37 M_A_DQ60
[9] M_A_ODT0 M0_ODT0 M_DATA60 M_A_DQ61
[9] M_A_ODT1
AU38
M0_ODT1 DIM0 M_DATA61
AY36
M_A_DQ62
AN37 BA33
[10] M_B_ODT0 M1_ODT0 M_DATA62
[10] M_B_ODT1
AR37
M1_ODT1 DIM1 M_DATA63
AY32 M_A_DQ63

AJ34 V41
[9] M_A_CS#0 M0_CS_L0 M_CHECK0 +1.5V_SUS
[9] M_A_CS#1
AR38
AL38 M0_CS_L1 DIM0 M_CHECK1
W 40
AB40
[10] M_B_CS#0 M1_CS_L0 M_CHECK2
[10] M_B_CS#1
AN35
M1_CS_L1 DIM1 M_CHECK3
AC40
U41
AJ37 M_CHECK4 V40 R126
[9,10] M_A_RAS# AL34 M_RAS_L M_CHECK5 AA41 +1.5V_SUS
[9,10] M_A_CAS# AL35 M_CAS_L M_CHECK6 AB41 1K_4
[9,10] M_A_WE# M_W E_L M_CHECK7
AD41 +M_ZVDDIO R128 39.2/J_4
M_ZVDDIO_MEM_S AD40 M_VREF
M_VREF AC38
M_VREFDQ

2
FT3B_BEEMA R127 C309 C310 C303
C304
1K_4 1000P/50V_4 0.1U/10V/X7R_4 0.47U/10V_4 1U/10V_4

1
A A

Quanta Computer Inc.

PROJECT : ZYV
Size Document Number Rev
C3A
MEM/PCIE (1/6)
Date: Monday, April 28, 2014 Sheet 3 of 40
5 4 3 2 1
 5 4 3 2 1

U24D
+3V ANALOG/DISPLAY/MISC
INT_HDMITX2P A9 B16 DP_150_ZVSS R450 150/F_4
[22] INT_HDMITX2P INT_HDMITX2N B9 TDP1_TXP0 DP_150_ZVSS A21 DP_2K_ZVSS R452 2k/F_4
CORE_PWM_PROCHOT# [22] INT_HDMITX2N TDP1_TXN0 DP_2K_ZVSS B17 APU_BLEN
R542 1K_4

DP MISC
APU_SIC INT_HDMITX1P A10 3V_S0 DP_BLON A17 APU_DISP_ON APU_BLEN [21,30]
R536 1K_4
APU_SID [22] INT_HDMITX1P INT_HDMITX1N B10 TDP1_TXP1 DP_DIGON A18 APU_DPST_PWM APU_DISP_ON [21]
R537 1K_4
APU_ALERT# [22] INT_HDMITX1N TDP1_TXN1 DP_VARY_BL APU_DPST_PWM [21]
R544 1K_4

DISPLAYPORT 1
INT_HDMITX0P A11
HDMI [22] INT_HDMITX0P INT_HDMITX0N TDP1_TXP2 HDMI_DDCCLK_SW
R472 4.7K_4 DDCCLK B11 D17 HDMI_DDCCLK_SW [22]
[22] INT_HDMITX0N TDP1_TXN2 TDP1_AUXP E17 HDMI_DDCDATA_SW
R471 4.7K_4 DDCDATA HDMI_DDCDATA_SW [22]
INT_HDMICLK+ A12 3V_S0 TDP1_AUXN
[22] INT_HDMICLK+ INT_HDMICLK- B12 TDP1_TXP3 H19 HDMI_HPD
[22] INT_HDMICLK- TDP1_TXN3 TDP1_HPD HDMI_HPD [22]
EDP_TX0 A4 D15 EDP_AUX
D [21] EDP_TX0 LTDP0_TXP0 LTDP0_AUXP EDP_AUX [21] D
APU_VDD_18 EDP_TX0# B4 E15 EDP_AUX#
[21] EDP_TX0# LTDP0_TXN0 LTDP0_AUXN EDP_AUX# [21]
eDP
R520 300_4 APU_RST# [21] EDP_TX1
EDP_TX1 A5 3V_S0 H17 EDP_HPD
EDP_TX1# B5 LTDP0_TXP1 LTDP0_HPD EDP_HPD [21]
[21] EDP_TX1# R468 *SHORT_4 CRT_R [21]
R509 300_4 APU_PWRGD LTDP0_TXN1

DISPLAYPORT 0
LA_DATAP0 A6 B14 CRTR R447 150_4
TP93 LA_DATAN0 B6 LTDP0_TXP2 DAC_RED A14 CRTG R448 150_4
TP92 LTDP0_TXN2 DAC_GREEN B15 CRTB R449 150_4
LA_CLK A7 DAC_BLUE R469 *SHORT_4
TP90 LTDP0_TXP3 CRT_G [21]
LA_CLK# B7 R470 *SHORT_4
TP88 LTDP0_TXN3 CRT_B [21]
G19 CRT_HSYNC R487 *SHORT_4 HSYNC [21]
3V_S0 DAC_HSYNC E19 CRT_VSYNC R488 *SHORT_4
DAC_VSYNC VSYNC [21]
K15 1.8V_S0

VGA DAC
H15 DISP_CLKIN_H
DISP_CLKIN_L

CLK
D19 DDCCLK
3V_S0 DAC_SCL D21 DDCCLK [21]
DDCDATA
DAC_SDA DDCDATA [21]
SVT G31 +1.8V
SVC D27 SVT 1.8V_S0 A16 DAC_ZVSS R451 499_4
SVD E29 SVC DAC_ZVSS
SVD APU_THERMDA_R

SER
H27
APU_SIC B22 THERMDA H29 APU_THERMDC_R TP63
APU_SID B21 SIC 3V_S0 THERMDC D25 TP64
DIECRACKMON
SID DIECRACKMON A27 BP0 TP62
Can remove on MP +3V APU_RST# B20 BP0 B27 BP1
R505 *1K_4

LDT_RST# A20 APU_RST_L S5 BP1 A26 TP91

R521 *0_4 BP2 R503 *1K_4
LDT_RST_L BP2 B26 BP3 R504 *1K_4
APU_PWRGD B19 BP3 B28 PLLTEST1 R507 1K_4
C655 R500 *0_4 LDT_PWRGD A19 APU_PWROK S5 PLLTEST1 A28 PLLTEST0 R506 1K_4
*HDT@0.1U/10V/X7R_4 LDT_PWROK PLLTEST0 B24 BYPASSCLK_H R508 510_4

CTRL
CORE_PWM_PROCHOT# A22 BYPASSCLK_H A24 BYPASSCLK_L R519 510_4
[5,30,31,35] CORE_PWM_PROCHOT# PROCHOT_L BYPASSCLK_L PLLCHRZ_H
3V_S0 AV35

TEST
APU_ALERT# B18 PLLCHRZ_H AU35 PLLCHRZ_L TP20
U28 ALERT_L 3V_S0 PLLCHRZ_L E33 M_TEST TP18
APU_RST# 1 6 APU_LDT_RST_HTPA# APU_TDI D29 M_TEST TP59
1A 1Y C653 C647 APU_TDO D31 TDI
2 5 *150P/50V_4 *150P/50V_4 APU_TCK D35 TDO A29 FREE_2 R501 *1K_4
GND VCC APU_TMS D33 TCK 1.8V_S0 FREE_2 H21 GIO_TSTDTMO_SERIALCLK TP89 R524 *1K_4
APU_PWRGD 3 4 APU_PWRGD_BUF APU_TRST# G27 TMS GIO_TSTDTM0_SERIALCLK H25 GIO_TSTDTM0_CLKINIT R525 *1K_4
C
2A 2Y APU_DBRDY B25 TRST_L GIO_TSTDTM0_CLKINIT R502 *1K_4 +3V C

JTAG
APU_DBREQ# A25 DBRDY
*HDT@SN74LVC2G07DCKR DBREQ_L AJ10 USB_ATEST0
D23 USB_ATEST0 AJ8 USB_ATEST1 TP36 CRT_HSYNC R486 1K_4
VDDCR_NB_SENSE USB_ATEST1 M_ANALOGIN TP33
G23
VDDCR_CPU_SENSE M_ANALOGIN
R32
TP61
R485 *1K_4 CRT_HSYNC :
E25 N32 M_ANALOGOUT PU FOR INTERNAL
VDDIO_MEM_S_SENSE M_ANALOGOUT TP60
E23 AP29 TMON_CAL
TP15 PD FOR CUSTOMER(AMD suggest)
VSS_SENSE TMON_CAL 20131202 ZQN CRT can't work,
VDD_095_FB_H AV33 R522 *1K_4 need change to PU
[34] VDD_095_FB_H VDD_095_FB_L AU33 VDD_095_FB_H E21 DP_STEREOSYNC R499 *1K_4
[34] VDD_095_FB_L VDD_095_FB_LKABINI HDMI_EN/DP_STEREOSYNC
PART 4 OF 9 3V_S0
FT3B_BEEMA

VSS_SENSE R478 *SHORT_4 APU_VDD_RUN_FB_L

VDDCR_APU_SENSE APU_VDD_RUN_FB_H APU_VDD_RUN_FB_L [35]
R477 *SHORT_4
APU_VDD_RUN_FB_H [35] DIFFERENTIAL ROUTING

VDDIO_MEM_S_SENSE_R R460 *SHORT_4 VDDIO_MEM_S_SENSE

VDDIO_MEM_S_SENSE [33]

VDDCR_NB_SENSE R459 *SHORT_4 APU_VDDNB_RUN_FB_H

APU_VDDNB_RUN_FB_H [35]

HDT(Hardware Debug Tool ) Connector SMBUS (Internal Thermal sensor)

+3V

B B
+1.8V +1.8V HDT+ HEADER / PLACE ON TOP +1.8V

2
CN1
R206 1 2 APU_TCK R187 HDT@1K/F_4
CPU_VDDIO CPU_TCK
HDT@1K/F_4 3 4 APU_TMS R191 HDT@1K/F_4 3 1 APU_SIC
GND CPU_TMS
APU_TDI [12,30] 2ND_MBCLK
5 6 R192 HDT@1K/F_4
GND CPU_TDI
7 8 APU_TDO
GND CPU_TDO
APU_TRST# R207 HDT@0_4 HDT_TRST# 9 10 APU_PWRGD_BUF R188 *HDT@1K/F_4 2N7002K
CPU_TRST_L CPU_PWROK_BUF
R208 HDT@10K_4 11 12 APU_LDT_RST_HTPA#
R189 *HDT@1K/F_4 Q35
CPU_DBRDY3 CPU_RST_L_BUF
R209 HDT@10K_4 13 14 APU_DBRDY
CPU_DBRDY2 CPU_DBRDY0
R210 HDT@10K_4 15 16 APU_DBREQ# R193 HDT@1K/F_4
CPU_DBRDY1 CPU_DBREQ_L

2
17 18 J108_PLLTST0 R194 HDT@0_4 PLLTEST0
GND CPU_PLLTEST0
19 20 J108_PLLTST1 R190 HDT@0_4 PLLTEST1
CPU_VDDIO CPU_PLLTEST1
3 1 APU_SID
[12,30] 2ND_MBDATA
*HDT@HDT

2N7002K
Q36

R534 *0_4
+1.8V R535 *0_4
Serial VID +3V

R518 R516 R514 R523 R528 R527 R497

*1K_4 *1K_4 *1K_4 *300_4 *300_4 *300_4 *2.2K_4

R545
10K/F_4
SVT R513 33_4
APU_SVT [35]
2

SVC R517 33_4 Q39

APU_SVC [35]
PMST3904
SVD R515 33_4 THERM_ALERT# 3 1 APU_ALERT#
APU_SVD [35] [28] THERM_ALERT#
A A
APU_PWRGD R496 *SHORT_4
APU_PWRGD_SVID_REG [35]

R498 R529 R530 +3V

*220_4 *0_4 *0_4 VFIX MODE VID Override table (VDD)

SVC SVD Boot Voltage R543
*10K/F_4
0 0 1.1V Quanta Computer Inc.
0 1 1.0V
2

Q38
*PMST3904
PROJECT : ZYV
1 0 0.9V THERM_ALERT# 3 1 CORE_PWM_PROCHOT# Size Document Number Rev
C3A
1 1 0.8V DIS/MI (2/6)
Date: Monday, April 28, 2014 Sheet 4 of 40
5 4 3 2 1
 5 4 3 2 1

+3V_S5 +3V_S5

C559 150P/50V_4 U24C

U22 R335 [24,30] PLTRST# PLTRST# R375 33_4 LPC_RST#_R AY4

*MC74VHC1G08DFT2G PCIE_RST# AY9 LPC_RST_L 3V_S5 3V_S5 W4 R130 *33_4
*4.7K/F_4 PCIE_RST_L USBCLK/14M_25M_48M_OSC

3
PCIE AG4 USB_ZVSS 11.8K R422 TP41
1 PCH_RSMRST#_R AY5 USB_ZVSS
PCIERST# 4 RSMRST_L 1.8V_S5
[11,23,24,27] PCIERST# PCIERST_R# PCIE_RST#
2 R358 33_4 AL4
USB_HSD0P USBP0+ [27]
[30] DNBSWON#
DNBSWON#
SYS_PWRGD
BA8
PWR_BTN_L
3V_S5
USB_HSD0N
AL5
USBP0- [27] Daughter board side USB2.0
AM19 1.8V_S5
[8,28] SYS_PWRGD PWR_GOOD

5
C545 150P/50V_4 SYS_RST# AY7 AJ4
[8] SYS_RST# SYS_RESET_L/GEVENT19_L USB_HSD1P USBP1+ [21]
R342 *SHORT_4 PCIE_WAKE# AW11 3V_S5 AJ5 Camera USB

MISC
[23,24] PCIE_LAN_WAKE# USBP1- [21]

USB
C547 *100P/50V_4 WAKE_L/GEVENT8_L 3V_S5 USB_HSD1N

USB
D D

1.1
AG7
USB_HSD2P USBP2+ [29]
R333 *SHORT_4
[8,30] SUSB#
SUSB# AY3
SLP_S3_L USB_HSD2N
AG8
USBP2- [29] I2C translator
SUSC# BA5 3V_S5
[30] SUSC# SLP_S5_L AG1
USB_HSD3P USBP3+ [21]

ACPI / WAKE UP
APU_TEST0 AU13 AG2 Touch Panel
TP83 APU_TEST1 AY10 TEST0 3V_S5 USB_HSD3N USBP3- [21]
Test mode setting (Follow AMD's suggestion) TP77 APU_TEST2 AY6 TEST1/TMS AF1
TP74 TEST2 USB_HSD4P AF2

EVENTS
+3V_S5 KBRST# AR23 3V_S5 USB_HSD4N
NC,no install by default [30] KBRST# SIO_A20GATE AR31 KBRST_L 3V_S0 AE1
APU_TEST0 [30] SIO_A20GATE SIO_EXT_SCI# GA20IN/GEVENT0_L USB_HSD5P USBP5+ [27]
R366 *1K_4 R376 15K_4
[30] SIO_EXT_SCI# SIO_EXT_SMI#
AN5
LPC_PME_L/GEVENT3_L
3V_S0
USB_HSD5N
AE2
USBP5- [27] Daughter board side USB2.0
AL7 3V_S5
APU_TEST1 [30] SIO_EXT_SMI# LPC_SMI_L/GEVENT23_L
R339 *1K_4 R359 15K_4 LPCPD# AV2 3V_S5 AD1
[24,28] LPCPD# LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L3V_S5 USB_HSD6P USBP6+ [27]
APU_TEST2 USB_HSD6N
AD2
USBP6- [27] Card reader
R345 *1K_4 R362 15K_4 AP15
AV13 AC_PRES/IR_RX0/GEVENT16_L AC1
IR_TX0/GEVENT21_L USB_HSD7P USBP7+ [24]
BA9 AC2 WLAN Min-Card

USB
IR_TX1/GEVENT6_L USB_HSD7N USBP7- [24]

2.0
BA10 3V_S5
AV15 IR_RX1/GEVENT20_L AB1
TEST2 TEST1 TEST0 Description IR_LED_L/LLB_L/GPIO184 USB_HSD8P USBP8+ [27]
USB_HSD8N
AB2
USBP8- [27] USB Combo 3.0/2.0
0 0 0 FCH TAP accessible from APU when TAPEN is asserted AU29 AA1
USBP9+ [27]
PCIE_CLKREQ_WLAN# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 USB_HSD9P
FCH JTAG pins are overloaded for multiple [24] PCIE_CLKREQ_WLAN# PCIE_REQ_LAN#
AW29
CLK_REQ1_L/GPIO61 USB_HSD9N
AA2
USBP9- [27] USB Combo 3.0/2.0
functions, in this configuration the FCH JTAG are AR27 3V_S0
[23] PCIE_REQ_LAN# PCIE_REQ_3G# CLK_REQ2_L/GPIO62
used as non-JTAG pins AV27
TP16 R373 *0_4 PCIE_REQ_GPU#_R AY29 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63
[12] PCIE_REQ_GPU# CLK_REQG_L/GPIO65/OSCIN AE10 USB_SS_ZVSS 1K R122
USB_SS_ZVSS AE8 USB_ZVDD
0 0 1 Reserved USB_SS_ZVDD_095_USB3_DUAL
1K R392 +0.95V_DUAL
CLK_SCLK AU25
[9,10,24] CLK_SCLK CLK_SDATA AV25 SCL0/GPIO43 3V_S0
0 1 X Reserved [9,10,24] CLK_SDATA SDA0/GPIO47
SCL1 AY11 3V_S0 T2
SCL1/GPIO227 USB_SS_TX0P USB30_TX0+ [27]
FCH JTAG multi-function pins are configured as SDA1 BA11 3V_S5 T1
USB30_TX0- [27]
SDA1/GPIO228 3V_S5 USB_SS_TX0N
1 TMS 0 JTAG pins, in this configuration the FCH TAP
can be accessed from FCH JTAG pins V2
C USB_SS_RX0P V1 USB30_RX0+ [27] C
USB_SS_RX0N USB30_RX0- [27]
Use on ATE only 0.95
1 TMS 1 Yuba JTAG enabled BOARD_ID0 AP27

USB
GPIO
BOARD_ID1 AY28 GPIO49 R1

3.0
BOARD_ID2 GPIO50 USB_SS_TX1P USB30_TX1+ [27]
BA28 R2
AV23 GPIO51 USB_SS_TX1N USB30_TX1- [27]
BOARD_ID3 AP21 GPIO55 W1
GPIO57 USB_SS_RX1P USB30_RX1+ [27]
BA26 W2
+3V [21] BOARD_ID4 AV19 GPIO58 USB_SS_RX1N USB30_RX1- [27]
[11] DGPU_RST_L GPIO59 3V_S0
AY27
R354 2.2K_4 CLK_SCLK SPKR BA27 GPIO64
[25] SPKR DGPU_PWREN_A SPKR/GPIO66 SMBALERT#_R
to DDR3 SMBUS AU21
GPIO68 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L
AY8
R355 2.2K_4 CLK_SDATA AY26 AW1 USB_OC1#
GPIO69 USB_OC1_L/TDI/GEVENT13_L USB_OC2# USB_OC1# [27]
AV21 3V_S5 AV1
PROCHOT#_CTRL GPIO70 USB_OC2_L/TCK/GEVENT14_L USB_OC3# USB_OC2# [27]
+3V_S5 R344 *10K/F_4 R377 *0_4 AM21 AY1 0114_B_del R348, Q24, R322

USB
[4,30,31,35] CORE_PWM_PROCHOT# RAMID_0 GPIO71 USB_OC3_L/TDO/GEVENT15_L TP85
BA3

OC
R591 10K/F_4
J1 1 2 SYS_RST# GPIO174 3V_S5
SYS_RST# internal
*SOLDERJUMPER-2 AV17 AN2 ACZ_BCLK_R
10K pull up [8] GEVENT2# GEVENT2_L AZ_BITCLK ACZ_SDOUT_R
R589 10K/F_4 BA4 S0 AN1
R590 10K/F_4 AR15 GEVENT4_L AZ_SDOUT AK2 PCH_AZ_CODEC_SDIN0
AP17 GEVENT7_L AZ_SDIN0/GPIO167 AK1 RAMID_3
+3V_S5 AP11 GEVENT10_L S5 S5 AZ_SDIN1/GPIO168 AM1 RAMID_1 ACZ_BCLK_R R410 *10K/F_4
AN8 GEVENT11_L AZ_SDIN2/GPIO169 AL2 RAMID_2
R357 *10K/F_4 SMBALERT#_R R588 *10K/F_4 AU17 GEVENT17_L AZ_SDIN3/GPIO170 AM2 ACZ_SYNC_R PCH_AZ_CODEC_SDIN0 R423 *10K/F_4
+3V_S5 BLINK/GEVENT18_L AZ_SYNC
BA6 AL1 ACZ_RST#_R
R351 100K_4 PCIE_WAKE# 0303_C_follow AMD suggest GEVENT22_L AZ_RST_L

AUDIO
R306 10K/F_4 SCL1 SCL1, SDA1 BA29
AP23 GENINT1_L/GPIO32S0

HD
R307 10K/F_4 SDA1 TP I2C : R=10K [38] PE_PWRGD GENINT2_L/GPIO33
TP SMBUS : R=2.2K
AV31 KABINI

0114_B_del R177, R174 AU31 FANOUT0/GPIO52 3V_S0 PART 3 OF 9

FANIN0/GPIO56
B B
R356 10K/F_4 DNBSWON#
FT3B_BEEMA
R406 10K/F_4 USB_OC1#

R408 10K/F_4 USB_OC2#

To Azalia +3V +1.8V_S5

ACZ_SDOUT_R R413 33_4
PCH_AZ_CODEC_SDOUT [25]
ACZ_SYNC_R R416 33_4 Power side PU 10K to +3V
PCH_AZ_CODEC_SYNC [25]
ACZ_BCLK_R R409 33_4 R338 R374
PCH_AZ_CODEC_BITCLK [25]
*EV@100K/F_6 47K/F_4
ACZ_RST#_R R420 33_4
PCH_AZ_CODEC_RST# [25] DGPU_PWREN_A PCH_RSMRST#_R
D12 RB500V-40
PCH_AZ_CODEC_SDIN0 [38] DGPU_PWREN [30] PCH_RSMRST#
PCH_AZ_CODEC_SDIN0 [25] D22
EV@RB500V-40 R104
C543 C554 *10K_4
0.22u/10V_4 +3V_S5 S3 resume time measure point (RAMID_3)
BOARD ID BOARD_ID4 Depend on cable => always PU, PD DNI
EV@0.1U/10V/X7R_4
BIOS say keep PD
Touch cable PIN2 => NC
non-Touch cable PIN2 => GND R364 *10K/F_4 RAMID_0 R365 10K/F_4
+3V >1mS delay is required between all MXM power rail stable R414 *10K/F_4 RAMID_1 R412 10K/F_4
and MXM_PWREN(enables the module internal power) CRB 0.1uF, but check list need 10ms delay(47*0.22=10.34ms) R418 *10K/F_4 RAMID_2 R415 10K/F_4
R353 SP@10K_4 BOARD_ID0 R372 SP@10K_4 R421 *10K/F_4 RAMID_3 R419 10K/F_4
R370 SP@10K_4 BOARD_ID1 R381 SP@10K_4
R371 10K_4 BOARD_ID2 R382 *10K_4 DGPU_PWREN_A >1mS
R367 *10K_4 BOARD_ID3 R378 10K_4
BOARD_ID4 RAM RAMID_0 RAMID_1 RAMID_2 RAMID_3
R369 10K_4 R380 *10K_4 DGPU_PWREN
A A

Reserve Reserve Reserve Reserve Reserve

GPIO High Low

BOARD_ID0 dTPM iTPM

BOARD_ID1 dGPU UMA
BOARD_ID2 17'' 14'' Quanta Computer Inc.
BOARD_ID3 Reserve Reserve PROJECT : ZYV
BOARD_ID4 Touch non-Touch Size Document Number Rev
C3A
GPIO/USB/AZ (3/6)
Date: Monday, April 28, 2014 Sheet 5 of 40
5 4 3 2 1
 5 4 3 2 1

Vender Size Quanta P/N Vender P/N

APU SPI ROM
1st WND 8M AKE3EFP0N07 W25Q64FVSSIQ
? AMIC 8M ? ?
? MAX 8M ? MX25L6436E

U24E
? GGD 8M AKE3EGN0Q01 GD25B64BSIGR
KABINI
? EON 8M AKE3EZN0Q01 EN25QH64-104HIP
PART 5 OF 9
D SATA_TXP0 BA14 BA23 +3V_S5 D
[26] SATA_TXP0 SATA_TXN0 AY14 SATA_TX0P SD__PW R_CTRL +3V_S5 +3V_S5
AY22
[26] SATA_TXN0 SATA_TX0N SD_CLK/GPIO73
SATA HDD SATA_RXN0 BA16 AY23
[26] SATA_RXN0 SATA_RXP0 AY16 SATA_RX0N SD_CMD/GPIO74 [30] SPI_CS
AY20 R313
[26] SATA_RXP0 SATA_RX0P SD_CD/GPIO75 BA20 [30] SPI_SCK
C550
3V_S0 SD_W P/GPIO76 [30] SPI_SDI
10K/F_4
SATA_TXP1 AY19 0.95 BA22 [30] SPI_SDO
0.1U/10V_4
[26] SATA_TXP1 SATA_TXN1 BA19 SATA_TX1P SD_DATA0/GPIO77 AY21 U20
[26] SATA_TXN1 SATA_TX1N SD_DATA1/GPIO78 AY24 SPI_CS1# SPI_CS 1 8
R305 33_4 R363
SATA ODD SD_DATA2/GPIO79 CE# VDD

SERIAL
SATA_RXN1 AY17 BA24 SPI_CLK R360 33_4 SPI_SCK 6 10K/F_4
[26] SATA_RXN1 SATA_RXP1 BA17 SATA_RX1N SD_DATA3/GPIO80 SCK
5

ATA
[26] SATA_RXP1 SATA_RX1P AY25 2 SI 7 SPI_HOLD
C555 22P/50V_4
SD_LED/GPIO45 SO HOLD#
1K R396 SATA_ZVSS AR19 SPI_SI R361 33_4 SPI_SDI 3 4
1K R395 SATA_ZVDD AP19 SATA_ZVSS SPI_SO R321 33_4 SPI_SDO W P# VSS
+0.95V SATA_ZVDD_095

CARD
+3V_S5 R331 10K/F_4 W25Q64FVSSIQ

SD
SATA_ACT# BA30 SPI_WP R334 *SHORT_4 SPI_WP_R
TP84 SATA_ACT_L/GPIO67 3V_S0

AY12
SATA_X1
AU7 SPI_CLK TP78
1.8V_S0 SPI_CLK/GPIO162 AW 9 SPI_CS1# TP71
SPI_CS1_L/GPIO165 AR4 SPI_CS2# TP19
BA12 3V_S5 SPI_CS2_L/GPIO166 AR11 SPI_SI TP76
SATA_X2 SPI_DO/GPIO163 AR7 SPI_SO TP72
C
SPI_DI/GPIO164 AU11 SPI_HOLD TP75 C
SPI_HOLD_L/GEVENT9_L AU9 SPI_WP TP73
SPI_W P_L/GPIO161

ROM
LPC_CLK0_R R90 22_4

SPI
LPC_CLK0 [8]
R88 *22_4
CLK_PCIE_VGAP_C CLK_LPC_DEBUG [24]
R295 *short_4 U4 R384 22_4
[11] CLK_PCIE_VGAP CLK_PCIE_VGAN_C GFX_CLKP PCLK_TPM [24]
R294 *short_4 U5 AY2 R386 *22_4 C562 *15P/50V_4
[11] CLK_PCIE_VGAN GFX_CLKN LPCCLK0 AW 2 R385 22_4 C561 *15P/50V_4
Kabini LPCCLK1
AC8 LPC_CLK1_R CLK_PCI_775 [30]
R89 22_4 LPC_CLK1 [8]
AC10 GPP_CLK0P AT2 LPC_LAD0
GPP_CLK0N LAD0 LPC_LAD1 LPC_LAD0 [24,30]
3V_S5 AT1
LAD1 LPC_LAD2 LPC_LAD1 [24,30]
AR2
LAD2 LPC_LAD3 LPC_LAD2 [24,30]
AE4 AR1
[24] CLK_PCIE_WLAN GPP_CLK1P LAD3 LPC_LFRAME# LPC_LAD3 [24,30]
AE5 AP2
[24] CLK_PCIE_WLAN# GPP_CLK1N LFRAME_L LPC_LFRAME# [8,24,30]
0.95 AP1 LDRQ#0
LDRQ0_L TP17
AV29 SERIRQ
SERIRQ/GPIO48 LPC_CLKRUN#_R SERIRQ [24,30]
AC4 3V_S0 AP25 R379 *SHORT_4
GPP_CLK2P LPC_CLKRUN_L LPC_CLKRUN# [24,28,30]
AC5 3V_S0 C579 18p/50V_4
GPP_CLK2N

1
R428 *short_4 CLK_PCIE_LANP_R AA5 AJ2 32K_X1
[23] CLK_PCIE_LANP CLK_PCIE_LANN_R GPP_CLK3P 32K_X1
R429 *short_4 AA4
[23] CLK_PCIE_LANN GPP_CLK3N RTC R425 Y3 USE GROUND GUARD FOR 32K_X1 AND 32K_X2
AJ1 32K_X2 20M_4 32.768KHZ 0116_B_C579 change from 15p to 18p
32K_X2 C580 change from 15p to 22p
AP13
X14M_25M_48M_OSC 3V_S5

2
C580 22P/50V_4

AV11 RTCCLK R350 *SHORT_4

RTCCLK RTC_CLK [8]
C593 6p/50V_4 48M_X1 N2 3V_S5 D20
B X48M_X1 +3VPCU_R R323 *SHORT_4
B
Q10 +3VPCU
1

1.8V_S5
Y4 R441 48M_X2 N1 AN4 +1.5V_RTC_R R91 10K_4 AP2138N-1.5TRG1 +3VRTC +VCCRTC_2
X48M_X2 VDDBT_RTC_G
48MHz
1M/F_4 20MIL 20MIL BAT54CW
3

C242

1
C591 6p/50V_4 G1 0.22u/10V_4 +1.5V_RTC 1 3
*SHORT_ PAD1 C243
0.1U/10V/X7R_4
20MIL

2
C238

2
R304
0116_B_change from 10p to 6p 1u/10V_4
20MIL
C530 1K/F_4

1u/10V_4

+BAT
+5V_S5

*4.7K/J_4 R324 VCCRTC_3 *4.7K/J_4 R330 VCCRTC_2 3 1 +BAT 20MIL

1
Q25
RTC CR2032 Coin Battery

2
R315 CN5
*68.1K/F_4 *MMBT3904-7-F_200MA
DBV: AHL03003057
A VDE: AHL03003003 RTC_2032 A

2
R314
*150K/F_4
Quanta Computer Inc.
RTC changer circuit
PROJECT : ZYV
Size Document Number Rev
C3A
SATA/CLK (4/6)
Date: Monday, April 28, 2014 Sheet 6 of 40
5 4 3 2 1
 5 4 3 2 1

+1.5V_SUS +VDD_CORE U24G U24H

U24F
A8 J3 W 29 AL39
J35 L21 A13 VSS_1 KABINI VSS_63 J7 W 39 VSS_125 KABINI VSS_187 AL41
L32 VDDIO_MEM_S_1 VDDCR_CPU_1 L23 A23 VSS_2 PART 8 OF 9 VSS_64 J8 W 41 VSS_126 PART 9 OF 9 VSS_188 AM11
L37 VDDIO_MEM_S_2 VDDCR_CPU_2 L25 C325 A31 VSS_3 VSS_65 J39 Y1 VSS_127 VSS_189 AM27
C344 C222 C292 C386 C284 C387 C283 N35 VDDIO_MEM_S_3 VDDCR_CPU_3 L27 C410 C363 C416 C290 C409 C291 A35 VSS_4 VSS_66 K11 Y2 VSS_128 VSS_190 AM31
R31 VDDIO_MEM_S_4 VDDCR_CPU_4 L29 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 180P/50V_4 A39 VSS_5 VSS_67 K13 AA3 VSS_129 VSS_191 AN3
180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 R37 VDDIO_MEM_S_5 VDDCR_CPU_5 N21 B8 VSS_6 VSS_68 K17 AA7 VSS_130 VSS_192 AN7
U32 VDDIO_MEM_S_6 VDDCR_CPU_6 N23 B13 VSS_7 VSS_69 K19 AA8 VSS_131 VSS_193 AN39
U35 VDDIO_MEM_S_7 VDDCR_CPU_7 N27 B23 VSS_8 VSS_70 K21 AA11 VSS_132 VSS_194 AP31
D W 31 VDDIO_MEM_S_8 VDDCR_CPU_8 R21 B31 VSS_9 VSS_71 K23 AA15 VSS_133 VSS_195 AR3 D
W 32 VDDIO_MEM_S_9 VDDCR_CPU_9 R23 B39 VSS_10 VSS_72 K25 AA19 VSS_1134 VSS_196 AR13
W 37 VDDIO_MEM_S_10 VDDCR_CPU_10 R27 C1 VSS_11 VSS_73 K27 AA25 VSS_135 VSS_197 AR17
C375 C265 C376 C336 C264 C257 AA31 VDDIO_MEM_S_11 VDDCR_CPU_11 U21 C346 C314 C322 C360 C328 C2 VSS_12 VSS_74 K29 AA29 VSS_136 VSS_198 AR21
1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 AA35 VDDIO_MEM_S_12 VDDCR_CPU_12 U23 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 C5 VSS_13 VSS_75 K31 AA39 VSS_137 VSS_199 AR25
AC32 VDDIO_MEM_S_13 VDDCR_CPU_13 U27 C7 VSS_14 VSS_76 L3 AC3 VSS_138 VSS_200 AR29
AC37 VDDIO_MEM_S_14 VDDCR_CPU_14 W 21 C9 VSS_15 VSS_77 L7 AC7 VSS_139 VSS_201 AR39
AE31 VDDIO_MEM_S_15 VDDCR_CPU_15 W 23 C11 VSS_16 VSS_78 L8 AC11 VSS_140 VSS_202 AR41
AE35 VDDIO_MEM_S_16 VDDCR_CPU_16 W 27 C13 VSS_17 VSS_79 L10 AC15 VSS_141 VSS_203 AU1
AG32 VDDIO_MEM_S_17 VDDCR_CPU_17 AA21 C15 VSS_18 VSS_80 L11 AC19 VSS_142 VSS_204 AU2
C280 C326 C262 C274 C312 C286 AG37 VDDIO_MEM_S_18 VDDCR_CPU_18 AA23 C338 C354 C337 C356 C296 C355 C17 VSS_19 VSS_81 L15 AC25 VSS_143 VSS_205 AU3
1U/10V_4 1U/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 AJ35 VDDIO_MEM_S_19 VDDCR_CPU_19 AA27 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 C19 VSS_20 VSS_82 L19 AC29 VSS_144 VSS_206 AU15
AL32 VDDIO_MEM_S_20 VDDCR_CPU_20 AC21 C21 VSS_21 VSS_83 L31 AC31 VSS_145 VSS_207 AU19
AL37 VDDIO_MEM_S_21 VDDCR_CPU_21 AC23 C23 VSS_22 VSS_84 L39 AC39 VSS_146 VSS_208 AU23
AR35 VDDIO_MEM_S_22 VDDCR_CPU_22 AC27 C25 VSS_23 VSS_85 L41 AC41 VSS_147 VSS_209 AU27
VDDIO_MEM_S_23 VDDCR_CPU_23 AE21 C27 VSS_24 VSS_86 M1 AE3 VSS_148 VSS_210 AU39
VDDCR_CPU_24 AE23 C29 VSS_25 VSS_87 M2 AE7 VSS_149 VSS_211 AV9

GROUND

GROUND
VDDCR_CPU_25 AE27 +VDDNB_CORE C31 VSS_26 VSS_88 N3 AE25 VSS_150 VSS_212 AW 3
VDDCR_CPU_26 C33 VSS_27 VSS_89 N7 AE29 VSS_151 VSS_213 AW 7
+1.5V APU_VDDIO_AZ C35 VSS_28 VSS_90 N15 AE32 VSS_152 VSS_214 AW 13
L13 C37 VSS_29 VSS_91 N19 AE39 VSS_153 VSS_215 AW 15
VDDCR_NB_1 VSS_30 VSS_92 VSS_154 VSS_216

POWER
PLACE ON BOT LAYER L17 C39 N25 AG3 AW 17
R56 *SHORT_8 VDDCR_NB_2 N11 C41 VSS_31 VSS_93 N29 AG5 VSS_155 VSS_217 AW 19
VDDCR_NB_3 N13 C349 C285 C369 C357 C315 D9 VSS_32 VSS_94 N31 AG10 VSS_156 VSS_218 AW 21
C548 C544 C549 VDDCR_NB_4 N17 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 180P/50V_4 D11 VSS_33 VSS_95 N39 AG11 VSS_157 VSS_219 AW 23
VDDCR_NB_5 R11 D13 VSS_34 VSS_96 P1 AG13 VSS_158 VSS_220 AW 25
4.7U/6.3V_6 1U/10V_4 180P/50V_4 VDDCR_NB_6 R13 E3 VSS_35 VSS_97 P2 AG15 VSS_159 VSS_221 AW 27
VDDCR_NB_7 R17 E4 VSS_36 VSS_98 R3 AG19 VSS_160 VSS_222 AW 31
VDDCR_NB_8 U13 E9 VSS_37 VSS_99 R7 AG25 VSS_161 VSS_223 AW 33
VDDCR_NB_9 U17 C324 C330 C323 C339 C308 E11 VSS_38 VSS_100 R15 AG29 VSS_162 VSS_224 AW 35
C VDDCR_NB_10 W 13 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 E13 VSS_39 VSS_101 R19 AG31 VSS_163 VSS_225 AW 37 C
FT3B_BEEMA VDDCR_NB_11 W 17 E27 VSS_40 VSS_102 R25 AG39 VSS_164 VSS_226 AW 39
VDDCR_NB_12 AA13 E31 VSS_41 VSS_103 R29 AG41 VSS_165 VSS_227 AW 41
APU_VDDIO_AZ VDDCR_NB_13 AA17 E35 VSS_42 VSS_104 R39 AH1 VSS_166 VSS_228 AY13
PLACE ON TOP LAYER APU_VDDIO_AZ VDDCR_NB_14 AC13 E38 VSS_43 VSS_105 R41 AH2 VSS_167 VSS_229 AY15
VDDCR_NB_15 AC17 C345 C316 C329 C347 E39 VSS_44 VSS_106 U1 AJ3 VSS_168 VSS_230 AY18
VDDCR_NB_16 AE15 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 G3 VSS_45 VSS_107 U2 AJ7 VSS_169 VSS_231 AY30
C261 C275 VDDCR_NB_17 AE17 G7 VSS_46 VSS_108 U3 AJ15 VSS_170 VSS_232 BA2
VDDCR_NB_18 AE19 G11 VSS_47 VSS_109 U7 AJ17 VSS_171 VSS_233 BA7
1U/10V_4 1U/10V_4 AL10 VDDCR_NB_19 AG17 G13 VSS_48 VSS_110 U8 AJ19 VSS_172 VSS_234 BA13
AL11 VDDIO_AZ_ALW _1 VDDCR_NB_20 AG21 G15 VSS_49 VSS_111 U11 AJ23 VSS_173 VSS_235 BA15
APU_VDD18_ALW VDDIO_AZ_ALW _2 VDDCR_NB_21 G17 VSS_50 VSS_112 U15 AJ25 VSS_174 VSS_236 BA18
G21 VSS_51 VSS_113 U19 AJ29 VSS_175 VSS_237 BA21
B1 APU_VDD_18 G25 VSS_52 VSS_114 U25 AJ31 VSS_176 VSS_238 BA25
B2 VDD_18_ALW _1 A2 G29 VSS_53 VSS_115 U29 AJ32 VSS_177 VSS_239 BA31
VDD_18_ALW _2 VDD_18_1 A3 G35 VSS_54 VSS_116 U31 AJ39 VSS_178 VSS_240 BA35
VDD_18_2 B3 G37 VSS_55 VSS_117 U39 AL3 VSS_179 VSS_241 BA39
VDD_18_3 C3 G39 VSS_56 VSS_118 W3 AL8 VSS_180 VSS_242
APU_VDD33_ALW KABINI VDD_18_4 G41 VSS_57 VSS_119 W5 AL15 VSS_181
PART 7 OF 9 APU_VDD_33 H11 VSS_58 VSS_120 W 11 AL17 VSS_182
AL13 AM15 H13 VSS_59 VSS_121 W 15 AL19 VSS_183 A15
AM13 VDD_33_ALW _1 VDD_33_1 AM17 H23 VSS_60 VSS_122 W 19 AL25 VSS_184 VSSBG_DAC AL31
+0.95V_DUAL VDD_33_ALW _2 VDD_33_2 H31 VSS_61 VSS_123 W 25 AL29 VSS_185 VBURN AM29
APU_VDD_0.95 VSS_62 VSS_124 VSS_186 PSEN
AR5 AG23
AU4 VDD_095_USB3_DUAL1 VDD_095_1 AG27 Kabini Kabini
AV7 VDD_095_USB3_DUAL2 VDD_095_2 AJ21
VDD_0.95V_ALW AW 5 VDD_095_USB3_DUAL3 VDD_095_3 AJ27
VDD_095_USB3_DUAL4 VDD_095_4 AL21
AE11 VDD_095_5 AL23 APU_VDD_0.95 +0.95V
B AE13 VDD_095_ALW _1 VDD_095_6 AL27 B
+3V_S5 APU_VDD33_ALW AJ11 VDD_095_ALW _2 VDD_095_7 AM23 R59 *SHORT_8
AJ13 VDD_095_ALW _3 VDD_095_8 AM25
VDD_095_ALW _4 VDD_095_9
If P_GFX[3:0] are not used, leave VDD_095_GFX unconnected.
R57 *SHORT_8 42R
U10 VDD_095_GFX L20
C206 C259 C272 VDD_095_GFX_1 W 10 EV@PBY160808T-600Y-N(60,3A)
VDD_095_GFX_2 AA10
4.7U/6.3V_6 1U/10V_4 1U/10V_4 VDD_095_GFX_3 C307 C270 C263 C288 C271 C269 C276 C197 C198 C282 C277 C260

EV@1U/10V_4 EV@10u/6.3V_6 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 10u/6.3V_6 1U/10V_4 1U/10V_4 180P/50V_4

0114_B_change
S5 DOMAIN
+0.95V +0.95V_S5 +0.95V_DUAL

+3V APU_VDD_33 +0.95V

R71 *SHORT_8 Power trace tracking
R58 *SHORT_8 R63 *0_8
+3V_S5
[5,6,8,23,24,28,29,30,32,37] +3V_S5
C266 C267 C268 C278 C233 C207 C237 C570 C244 C247 C246 C566 C239 C199 C192 C190 C195 C191 C194 C189
C196 +3V
[4,5,9,10,21,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38] +3V
+1.8V
[4,36] +1.8V +1.8V_S5
4.7U/6.3V_6 1U/10V_4 1U/10V_4 180P/50V_4 10u/6.3V_6 10u/6.3V_6 1U/10V_4 1U/10V_4 1U/10V_4 0.1U/10V/X7R_4 0.1U/10V/X7R_4 0.1U/10V/X7R_4 180P/50V_4 10u/6.3V_6 10u/6.3V_6 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 180P/50V_4
[5,8,36,38] +1.8V_S5
S0 DOMAIN +0.95V
[3,6,34,36] +0.95V +0.95V_S5
[34] +0.95V_S5 APU_VDD_18
[4,35] APU_VDD_18

A A
+1.8V APU_VDD_18 +0.95V_S5 VDD_0.95V_ALW
+1.8V_S5 APU_VDD18_ALW

R492 *SHORT_8 R526 *SHORT_8 R96 *SHORT_8

C631 C646 C633 C627 C629 C640

C645 C624 C643 C626 C648 C644 C641 C650 C634 C630 C287 C281 C295 C289
180P/50V_4 C649 C258 C255 C254 C248 Quanta Computer Inc.
4.7U/6.3V_6 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10u/6.3V_6 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 180P/50V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4
PROJECT : ZYV
Size Document Number Rev
C3A
POWER/GND(5/6)
Date: Monday, April 28, 2014 Sheet 7 of 40
5 4 3 2 1
 5 4 3 2 1

STRAPS PINS OVERLAP COMMON PADS WHERE

DEBUG STRAPS
POSSIBLE FOR DUAL-OP RESISTORS.

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

D D

R80 R79 R411 R343 R341

*10K/F_4 10K/F_4 10K/F_4 *10K/F_4 *10K_4

LPC_CLK0
[6] LPC_CLK0
LPC_CLK1
[6] LPC_CLK1
LPC_LFRAME#
[6,24,30] LPC_LFRAME#

[5] GEVENT2# GEVENT2#

RTC_CLK
[6] RTC_CLK

R81 R82 R407 R352 R340

2K_4 *2K_4 *2K_4 2K_4 *2K_4

C C

REQUIRED STRAPS

RTC_CLK LPC_CLK0 LPC_CLK1 LFRAME# GEVENT2#

PULL Normal power up BOOT FAIL TIMER CLKGEN SPI ROM 1.8V SPI ROM
HIGH ENABLED ENABLED

DEFAULT
DEFAULT DEFAULT Power trace tracking
+3V
[4,5,7,9,10,21,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38] +3V
PULL Fast power on BOOT FAIL TIMER CLKGEN LPC ROM 3.3V SPI ROM
DISABLED +3V_S5
LOW DISABLED [5,6,7,23,24,28,29,30,32,37] +3V_S5
DEFAULT
DEFAULT

B B
+3V_S5
SYS PWRGD +1.8V_S5

R336
10K/F_4 C535
D25 *1N4148WS U19 *0.1U/10V/X7R_4
[5] SYS_RST#
5

2
D24 1N4148WS 4 SYS_PWRGD
[5,30] SUSB# 1 SYS_PWRGD [5,28]

D23 1N4148WS C541

[30] PWROK_EC
3

1U/10V_4 *TC7SH08FU

+3V_S5

SYS_PWRGD_R R325 *SHORT_4

R387
3

100K_4
Q29
2

2N7002K
3

A A
1

Q28
2
[30] HWPG

2N7002K
Quanta Computer Inc.
1

PROJECT : ZYV
Size Document Number Rev
C3A
STRAP (6/6)
Date: Monday, April 28, 2014 Sheet 8 of 40
5 4 3 2 1
 5 4 3 2 1

+1.5V_SUS
[3,10] M_A_A[15:0] JDIM1A M_A_DQ[63:0] [3,10] JDIM1B
M_A_A0 98 5 M_A_DQ5 75 44
M_A_A1 97 A0 DQ0 7 M_A_DQ0 76 VDD1 VSS16 48
M_A_A2 96 A1 DQ1 15 M_A_DQ2 81 VDD2 VSS17 49
M_A_A3 95 A2 DQ2 17 M_A_DQ3 82 VDD3 VSS18 54
M_A_A4 92 A3 DQ3 4 M_A_DQ1 87 VDD4 VSS19 55
M_A_A5 91 A4 DQ4 6 M_A_DQ4 88 VDD5 VSS20 60
M_A_A6 90 A5 DQ5 16 M_A_DQ6 93 VDD6 VSS21 61
M_A_A7 86 A6 DQ6 18 M_A_DQ7 94 VDD7 VSS22 65
M_A_A8 89 A7 DQ7 21 M_A_DQ8 99 VDD8 VSS23 66
D A8 DQ8 VDD9 VSS24 D
M_A_A9 85 23 M_A_DQ9 100 71
M_A_A10 107 A9 DQ9 33 M_A_DQ14 105 VDD10 VSS25 72
M_A_A11 84 A10/AP DQ10 35 M_A_DQ11 106 VDD11 VSS26 127

PC2100 DDR3 SDRAM SO-DIMM

M_A_A12 83 A11 DQ11 22 M_A_DQ12 111 VDD12 VSS27 128
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ13 112 VDD13 VSS28 133
M_A_A14 80 A13 DQ13 34 M_A_DQ15 2.48A 117 VDD14 VSS29 134
M_A_A15 78 A14 DQ14 36 M_A_DQ10 118 VDD15 VSS30 138
A15 DQ15 39 M_A_DQ16 123 VDD16 VSS31 139

PC2100 DDR3 SDRAM SO-DIMM

109 DQ16 41 M_A_DQ17 124 VDD17 VSS32 144
[3,10] M_A_BS#0 BA0 DQ17 M_A_DQ22 VDD18 VSS33
108 51 145
[3,10] M_A_BS#1 BA1 DQ18 M_A_DQ23 VSS34
79 53 199 150
[3,10] M_A_BS#2 BA2 DQ19 M_A_DQ20 +3V VDDSPD VSS35
114 40 151
[3] M_A_CS#0 S0# DQ20 M_A_DQ21 M_A_EVENT# VSS36
121 42 77 155
[3] M_A_CS#1 S1# DQ21 M_A_DQ18 [3,10] M_A_EVENT# NC1 VSS37
101 50 122 156
[3] M_A_CLK0 CK0 DQ22 M_A_DQ19 [3,10] DDR3_DRAMRST# NC2 VSS38
103 52 125 161
[3] M_A_CLK0# CK0# DQ23 M_A_DQ24 NCTEST VSS39
102 57 162
[3] M_A_CLK1 CK1 DQ24 M_A_DQ29 VSS40
104 59 C435 1000p/50V_4 198 167
[3] M_A_CLK1# CK1# DQ25 M_A_DQ27 EVENT# VSS41
73 67 30 168
[3] M_A_CKE0 CKE0 DQ26 M_A_DQ26 RESET# VSS42
74 69 C436 0.1u/10V_4 172
[3] M_A_CKE1 CKE1 DQ27 M_A_DQ28 VSS43
115 56 173
[3,10] M_A_CAS# CAS# DQ28 M_A_DQ25 +DDR_VREF2 VSS44
110 58 1 178
[3,10] M_A_RAS# RAS# DQ29 M_A_DQ31 +DDR_VREF VREF_DQ VSS45
113 68 126 179
[3,10] M_A_WE# DIMM2_SA0 WE# DQ30 M_A_DQ30 VREF_CA VSS46
R77 10K_4 197 70 184
R73 10K_4 DIMM2_SA1 201 SA0 DQ31 129 M_A_DQ36 VSS47 185
202 SA1 DQ32 131 M_A_DQ33 C301 0.1u/10V_4 2 VSS48 189
[5,10,24] CLK_SCLK 200 SCL DQ33 141 M_A_DQ39 3 VSS1 VSS49 190
[5,10,24] CLK_SDATA SDA DQ34 143 M_A_DQ38 C297 1000p/50V_4 8 VSS2 VSS50 195
C C

(204P)
116 DQ35 130 M_A_DQ37 9 VSS3 VSS51 196
[3] M_A_ODT0 ODT0 DQ36 M_A_DQ32 VSS4 VSS52
120 132 13
[3] M_A_ODT1 ODT1 DQ37 M_A_DQ34 VSS5
140 14
[3,10] M_DM[7..0] M_DM0 DQ38 M_A_DQ35 VSS6
11 142 19
M_DM1 28 DM0 DQ39 147 M_A_DQ41 20 VSS7 +SMDDR_VTT
M_DM2 46 DM1 DQ40 149 M_A_DQ40 25 VSS8
M_DM3 63 DM2
DM3
(204P) DQ41
DQ42
157 M_A_DQ46 26 VSS9
VSS10 VTT1
203 0.25A
M_DM4 136 159 M_A_DQ47 31 204
M_DM5 153 DM4 DQ43 146 M_A_DQ45 32 VSS11 VTT2
M_DM6 170 DM5 DQ44 148 M_A_DQ44 37 VSS12 205
M_DM7 187 DM6 DQ45 158 M_A_DQ42 38 VSS13 GND 206
DM7 DQ46 160 M_A_DQ43 43 VSS14 GND
[3,10] M_A_DQS[7:0] M_A_DQS0 DQ47 M_A_DQ48 VSS15
12 163
M_A_DQS1 29 DQS0 DQ48 165 M_A_DQ49
M_A_DQS2 47 DQS1 DQ49 175 M_A_DQ54
DQS2 DQ50 DDR3-DIMM0_H=5.2_REV
M_A_DQS3 64 177 M_A_DQ51
M_A_DQS4 137 DQS3 DQ51 164 M_A_DQ52
M_A_DQS5 154 DQS4 DQ52 166 M_A_DQ53
M_A_DQS6 171 DQS5 DQ53 174 M_A_DQ55 +1.5V_SUS
M_A_DQS7 188 DQS6 DQ54 176 M_A_DQ50
[3,10] M_A_DQS#[7:0] M_A_DQS#0 DQS7 DQ55 M_A_DQ60
10 181
M_A_DQS#1 27 DQS#0 DQ56 183 M_A_DQ61
M_A_DQS#2 45 DQS#1 DQ57 191 M_A_DQ63
M_A_DQS#3 62 DQS#2 DQ58 193 M_A_DQ62 R131
M_A_DQS#4 135 DQS#3 DQ59 180 M_A_DQ56
DQS#4 DQ60 1K/F_4
M_A_DQS#5 152 182 M_A_DQ57 +SMDDR_VREF
M_A_DQS#6 169 DQS#5 DQ61 192 M_A_DQ58
B DQS#6 DQ62 B
M_A_DQS#7 186 194 M_A_DQ59 R132 *0_6 +DDR_VREF
DQS#7 DQ63

DDR3-DIMM0_H=5.2_REV
3mA R124
1K/F_4

+1.5V_SUS Place these Caps near So-Dimm1. +1.5V_SUS +DDR_VREF

+1.5V_SUS
C365 C351 C382 C352 C368 C342 C212 C214 C213 C215 C216 C302 C298
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.1u/10V_4 0.1u/10V_4

R196
1K/F_4
+SMDDR_VTT +SMDDR_VREF
+1.5V_SUS +SMDDR_VTT +DDR_VREF2
R195 *0_6 +DDR_VREF2

3mA

2
R199
C395 C390 C378 C332 C333 C341 C227 C226 C209 C228 C208 C443 C437 C434 1K/F_4
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.1u/10V_4 0.1u/10V_4 0.47U/10V_4

1
A A

+1.5V_SUS

C385 C381 C361 C370 C358 C388 C373 C394

Quanta Computer Inc.
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4
PROJECT : ZYV
Size Document Number Rev
C3A
DDRIII SO-DIMM-0
Date: Monday, April 28, 2014 Sheet 9 of 40
5 4 3 2 1
 1 2 3 4 5 6 7 8

+1.5V_SUS
[3,9] M_A_A[15:0] JDIM2A M_A_DQ[63:0] [3,9] JDIM2B
M_A_A0 98 5 M_A_DQ5 75 44
M_A_A1 97 A0 DQ0 7 M_A_DQ0 76 VDD1 VSS16 48
M_A_A2 96 A1 DQ1 15 M_A_DQ2 81 VDD2 VSS17 49
M_A_A3 95 A2 DQ2 17 M_A_DQ3 82 VDD3 VSS18 54
M_A_A4 92 A3 DQ3 4 M_A_DQ1 87 VDD4 VSS19 55
M_A_A5 91 A4 DQ4 6 M_A_DQ4 88 VDD5 VSS20 60
M_A_A6 90 A5 DQ5 16 M_A_DQ6 93 VDD6 VSS21 61
M_A_A7 86 A6 DQ6 18 M_A_DQ7 94 VDD7 VSS22 65
M_A_A8 89 A7 DQ7 21 M_A_DQ8 99 VDD8 VSS23 66
A A8 DQ8 VDD9 VSS24 A
M_A_A9 85 23 M_A_DQ9 100 71
M_A_A10 107 A9 DQ9 33 M_A_DQ14 105 VDD10 VSS25 72
M_A_A11 84 A10/AP DQ10 35 M_A_DQ11 106 VDD11 VSS26 127

PC2100 DDR3 SDRAM SO-DIMM

M_A_A12 83 A11 DQ11 22 M_A_DQ12 111 VDD12 VSS27 128
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ13 112 VDD13 VSS28 133
M_A_A14 80 A13 DQ13 34 M_A_DQ15 2.48A 117 VDD14 VSS29 134
M_A_A15 78 A14 DQ14 36 M_A_DQ10 118 VDD15 VSS30 138
A15 DQ15 39 M_A_DQ16 123 VDD16 VSS31 139

PC2100 DDR3 SDRAM SO-DIMM

109 DQ16 41 M_A_DQ17 124 VDD17 VSS32 144
[3,9] M_A_BS#0 BA0 DQ17 M_A_DQ22 VDD18 VSS33
108 51 145
[3,9] M_A_BS#1 BA1 DQ18 M_A_DQ23 VSS34
79 53 199 150
[3,9] M_A_BS#2 BA2 DQ19 M_A_DQ20 +3V VDDSPD VSS35
114 40 151
[3] M_B_CS#0 S0# DQ20 M_A_DQ21 M_A_EVENT# VSS36
121 42 77 155
[3] M_B_CS#1 S1# DQ21 M_A_DQ18 [3,9] M_A_EVENT# NC1 VSS37
101 50 122 156
[3] M_B_CLK0 CK0 DQ22 M_A_DQ19 [3,9] DDR3_DRAMRST# NC2 VSS38
103 52 125 161
[3] M_B_CLK0# CK0# DQ23 M_A_DQ24 NCTEST VSS39
102 57 162
[3] M_B_CLK1 CK1 DQ24 M_A_DQ29 VSS40
104 59 C440 1000p/50V_4 198 167
[3] M_B_CLK1# CK1# DQ25 M_A_DQ27 EVENT# VSS41
73 67 30 168
[3] M_B_CKE0 CKE0 DQ26 M_A_DQ26 RESET# VSS42
74 69 C439 0.1u/10V_4 172
[3] M_B_CKE1 CKE1 DQ27 M_A_DQ28 VSS43
115 56 173
[3,9] M_A_CAS# CAS# DQ28 M_A_DQ25 +DDR_VREF2 VSS44
110 58 1 178
[3,9] M_A_RAS# RAS# DQ29 M_A_DQ31 +DDR_VREF VREF_DQ VSS45
113 68 126 179
[3,9] M_A_WE# DIMM1_SA0 WE# DQ30 M_A_DQ30 VREF_CA VSS46
R76 10K_4 197 70 184
+3V DIMM1_SA1 SA0 DQ31 M_A_DQ36 VSS47
R72 10K_4 201 129 185
202 SA1 DQ32 131 M_A_DQ33 C300 0.1u/10V_4 2 VSS48 189
[5,9,24] CLK_SCLK 200 SCL DQ33 141 M_A_DQ39 3 VSS1 VSS49 190
[5,9,24] CLK_SDATA SDA DQ34 143 M_A_DQ38 C293 1000p/50V_4 8 VSS2 VSS50 195
B B

(204P)
116 DQ35 130 M_A_DQ37 9 VSS3 VSS51 196
[3] M_B_ODT0 ODT0 DQ36 M_A_DQ32 VSS4 VSS52
120 132 13
[3] M_B_ODT1 ODT1 DQ37 M_A_DQ34 VSS5
140 14
[3,9] M_DM[7..0] M_DM0 DQ38 M_A_DQ35 VSS6
11 142 19
M_DM1 28 DM0 DQ39 147 M_A_DQ41 20 VSS7
M_DM2 46 DM1 (204P) DQ40 149 M_A_DQ40 25 VSS8
M_DM3 63 DM2 DQ41 157 M_A_DQ46 26 VSS9 203
DM3 DQ42 VSS10 VTT1 +SMDDR_VTT
M_DM4 136 159 M_A_DQ47 31 204
M_DM5 153 DM4 DQ43 146 M_A_DQ45 32 VSS11 VTT2
M_DM6 170 DM5 DQ44 148 M_A_DQ44 37 VSS12 205
0.25A
M_DM7 187 DM6 DQ45 158 M_A_DQ42 38 VSS13 GND 206
DM7 DQ46 160 M_A_DQ43 43 VSS14 GND
[3,9] M_A_DQS[7:0] M_A_DQS0 DQ47 M_A_DQ48 VSS15
12 163
M_A_DQS1 29 DQS0 DQ48 165 M_A_DQ49
M_A_DQS2 47 DQS1 DQ49 175 M_A_DQ54
DQS2 DQ50 DDR3-DIMM1_H=5.2_STD
M_A_DQS3 64 177 M_A_DQ51
M_A_DQS4 137 DQS3 DQ51 164 M_A_DQ52
M_A_DQS5 154 DQS4 DQ52 166 M_A_DQ53
M_A_DQS6 171 DQS5 DQ53 174 M_A_DQ55
M_A_DQS7 188 DQS6 DQ54 176 M_A_DQ50
[3,9] M_A_DQS#[7:0] M_A_DQS#0 DQS7 DQ55 M_A_DQ60
10 181
M_A_DQS#1 27 DQS#0 DQ56 183 M_A_DQ61
M_A_DQS#2 45 DQS#1 DQ57 191 M_A_DQ63
M_A_DQS#3 62 DQS#2 DQ58 193 M_A_DQ62
M_A_DQS#4 135 DQS#3 DQ59 180 M_A_DQ56
M_A_DQS#5 152 DQS#4 DQ60 182 M_A_DQ57
M_A_DQS#6 169 DQS#5 DQ61 192 M_A_DQ58
C DQS#6 DQ62 C
M_A_DQS#7 186 194 M_A_DQ59
DQS#7 DQ63

DDR3-DIMM1_H=5.2_STD

+1.5V_SUS +1.5V_SUS +DDR_VREF

Place these Caps near So-Dimm1.

C380 C353 C389 C391 C340 C366 C220 C217 C221 C218 C219 C299 C294
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.1u/10V_4 0.1u/10V_4

+SMDDR_VTT
+1.5V_SUS +SMDDR_VTT +DDR_VREF2

C383 C359 C393 C384 C362 C371 C205 C204 C225 C224 C223 C442 C438
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.1u/10V_4 0.1u/10V_4

D D

+1.5V_SUS

C392 C334 C350 C379 C367 C343 C331 C372

Quanta Computer Inc.
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4
PROJECT : ZYV
Size Document Number Rev
C3A
DDRIII SO-DIMM-1
Date: Monday, April 28, 2014 Sheet 10 of 40
1 2 3 4 5 6 7 8
 U16A

PART 1 0F 9

AA38 PCIE_RX0P PCIE_TX0P Y33 PEG_RXP0_C C523 EV@0.1u/10V_4

[3] PEG_TXP0 PEG_RXN0_C PEG_RXP0 [3]
Y37 PCIE_RX0N PCIE_TX0N Y32 C524 EV@0.1u/10V_4
[3] PEG_TXN0 PEG_RXN0 [3]

Y35 PCIE_RX1P PCIE_TX1P W33 PEG_RXP1_C C521 EV@0.1u/10V_4

[3] PEG_TXP1 PEG_RXP1 [3]
W36 PCIE_RX1N PCIE_TX1N W32 PEG_RXN1_C C522 EV@0.1u/10V_4
[3] PEG_TXN1 PEG_RXN1 [3]

W38 PCIE_RX2P PCIE_TX2P U33 PEG_RXP2_C C519 EV@0.1u/10V_4

[3] PEG_TXP2 PEG_RXP2 [3]
V37 PCIE_RX2N PCIE_TX2N U32 PEG_RXN2_C C520 EV@0.1u/10V_4
[3] PEG_TXN2 PEG_RXN2 [3]

V35 PCIE_RX3P PCIE_TX3P U30 PEG_RXP3_C C518 EV@0.1u/10V_4

[3] PEG_TXP3 PEG_RXP3 [3]
U36 PCIE_RX3N PCIE_TX3N U29 PEG_RXN3_C C517 EV@0.1u/10V_4
[3] PEG_TXN3 PEG_RXN3 [3]

U38 PCIE_RX4P PCIE_TX4P T33

T37 PCIE_RX4N PCIE_TX4N T32

T35 PCIE_RX5P PCIE_TX5P T30

R36 PCIE_RX5N PCIE_TX5N T29

R38 PCIE_RX6P PCIE_TX6P P33

P37 PCIE_RX6N PCIE_TX6N P32

P35 PCIE_RX7P PCIE_TX7P P30

N36 PCIE_RX7N PCIE_TX7N P29

N38 PCIE_RX8P PCIE_TX8P N33

M37 PCIE_RX8N PCIE_TX8N N32
PCI EXPRESS INTERFACE

M35 PCIE_RX9P PCIE_TX9P N30

L36 PCIE_RX9N PCIE_TX9N N29

L38 PCIE_RX10P PCIE_TX10P L33

K37 PCIE_RX10N PCIE_TX10N L32

+3V_GFX
K35 PCIE_RX11P PCIE_TX11P L30
J36 PCIE_RX11N PCIE_TX11N L29
C193 EV@0.1u/10V_4

J38 PCIE_RX12P PCIE_TX12P K33

5
H37 PCIE_RX12N PCIE_TX12N K32 U6
[5] DGPU_RST_L 2
4 PERST#_BUF
H35 PCIE_RX13P PCIE_TX13P J33 [5,23,24,27] PCIERST# 1
G36 PCIE_RX13N PCIE_TX13N J32
EV@TC7SH08FU R49

3
G38 PCIE_RX14P PCIE_TX14P K30 *EV@100K_4
F37 PCIE_RX14N PCIE_TX14N K29

F35 PCIE_RX15P PCIE_TX15P H33

E37 PCIE_RX15N PCIE_TX15N H32

CLOCK
AB35 PCIE_REFCLKP
[6] CLK_PCIE_VGAP
AA36 PCIE_REFCLKN
[6] CLK_PCIE_VGAN

CALIBRATION

PCIE_CALR_TX Y30 PCIE_CALR_TX R298 EV@1.69K/F_4

R256 EV@1K_4 TEST_PG AH16 TEST_PG PCIE_CALR_RX Y29 PCIE_CALR_RX R289 EV@1K/F_4 +PCIE_VDDC_GFX

PERST#_BUF AA30 PERSTB

Quanta Computer Inc.
EV_SP@GPU_M2
PROJECT : ZYV
Size Document Number Rev
C3A
Opal(Jet)_M2/PEG*4
Date: Monday, April 28, 2014 Sheet 11 of 40
 U16B

PART 2 0F 9

MUTI GFX
AD29 GENLK_CLK TXCAP_DPA3P AU24 +3V_GFX
AC29 GENLK_VSYNC TXCAM_DPA3N AV23

AT25 Q6
TX0P_DPA2P
AJ21 SWAPLOCKA TX0M_DPA2N AR24 5
DPA
AK21 SWAPLOCKB
TX1P_DPA1P AU26 3 4 GPUT_CLK
[4,30] 2ND_MBCLK
TX1M_DPA1N AV25

AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27 2

AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26
AP8 DVPCNTL_0 6 1 GPUT_DATA
[4,30] 2ND_MBDATA
AW8 DVPCNTL_1 TXCBP_DPB3P AR30
AR3 DVPCNTL_2 TXCBM_DPB3N AT29
AR1 DVPCLK
AU1 AV31 EV@2N7002DW
DVPDATA_0 TX3P_DPB2P
AU3 DVPDATA_1 TX3M_DPB2N AU30 R53 *EV@0/J_4
DPB
AW3 DVPDATA_2
AP6 DVPDATA_3 TX4P_DPB1P AR32 R50 *EV@0/J_4
AW5 DVPDATA_4 TX4M_DPB1N AT31
AU5 DVPDATA_5
AR6 DVPDATA_6 TX5P_DPB0P AT33
1.8V GPIO AW6 DVPDATA_7 TX5M_DPB0N AU32
AU6 DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 DVPDATA_10 TXCCM_DPC3N AV13
AN7 DVPDATA_11
AV9 DVPDATA_12 TX0P_DPC2P AT15
AT9 DVPDATA_13 TX0M_DPC2N AR14
AR10
AW10
AU10
DVPDATA_14
DVPDATA_15
DPC
TX1P_DPC1P AU16
AV15
EXTERNAL THERMAL SENSOR
DVPDATA_16 TX1M_DPC1N +3V_GFX
AP10 DVPDATA_17
AV11 DVPDATA_18 TX2P_DPC0P AT17 +3V_GFX
AT11 DVPDATA_19 TX2M_DPC0N AR16
AR12 DVPDATA_20
AW12 DVPDATA_21 TXCDP_DPD3P AU20
AU12 DVPDATA_22 TXCDM_DPD3N AT19 R337 R332 R329
+3V_GFX AP12 DVPDATA_23 EV@10K_4 EV@10K_4 EV@10K_4
+3V_GFX TX3P_DPD2P AT21 C542
TX3M_DPD2N AR20 EV@0.1u/10V_4
R253 *EV@10K_4 PCIE_REQ_GPU# U21
GPU_SMBCLK DPD
R269 EV@4.7K_4 AJ23 SMBCLK TX4P_DPD1P AU22
GPU_SMBDAT SMBus GPUT_CLK GPU_D+
R252 *EV@100_4 R272 EV@4.7K_4 AH23 SMBDATA TX4M_DPD1N AV21 8 1
SCLK VCC
TX5P_DPD0P AT23 GPUT_DATA 7 2
AR22 SDA DXP C537
TX5M_DPD0N
R276 *EV@4.7K_4 GPU_SCL AK26 SCL ALT#_GPIO17 6 3
+3V_GFX +3V_GFX GPU_SDA I2C ALERT# DXN
R279 *EV@4.7K_4 AJ26 SDA EV@2200p/50V_4
4 5
R258 *EV@0_4 AD39 OVERT# GND GPU_D-
R
[37] GPU_DPRSLPVR AD37
GENERAL PURPOSE I/O AVSSN#1
GPU_GPIO0 AH20 GPIO_0 EV@G781P8
TP69 GPU_GPIO1 AH18 AE36
R45 GPIO_1 G
TP11 GPU_GPIO2
EV@4.7K_4 AN16 GPIO_2 AVSSN#2 AD35
TP68
2

B AF37
3 1 GPU_AC_DC# AH17 GPIO_5_AC_BATT AVSSN#3 AE38
[30] DGPU_AC_DC# AJ17 GPIO_6
[37] PWRCNTRL2 DAC1
R257 *EV_O@10K_4 AK17 GPIO_7_BLON HSYNC AC36 R303 *EV_O@10K_4
EV@2N7002K GPU_GPIO8 AJ13 GPIO_8_ROMSO VSYNC AC38 R300 *EV_O@10K_4
TP2 GPU_GPIO9 AH15
Q5 TP5 GPIO_9_ROMSI
GPU_GPIO10 AJ16 GPIO_10_ROMSCK +1.8V_GFX
TP6 GPU_GPIO11 AK16 AB34
GPIO_11 RSET R290 EV@499/F_4 +1.8V_AVDD
TP9 GPU_GPIO12 AL16 GPIO_12 DAC1 Analog Power : 1.8V@18mA
TP4 GPU_GPIO12 AM16 GPIO_13 AVDD AD34 L16
TP8 GPU_GPIO13 AM14 AE34
GPIO_14_HPD2 AVSSQ EV_O@BLM15BD121SN1D_300MA
0,32,36,37] SYS_SHDN# TP7
AM13 GPIO_15_PWRCNTL_0
[37] PWRCNTRL0
3

AK14 GPIO_16 VDD1DI AC33 C164 C169 C180

[37] PWRCNTRL3 ALT#_GPIO17 AG30 GPIO_17_THERMAL_INT VSS1DI AC34 EV_O@0.1u/10V_4 EV_O@1u/6.3V_4 EV_O@10u/6.3V_6
Q3 AN14 GPIO_18_HPD3
2 GPIO_19_CTF AM17 GPIO_19_CTF VDDC_CT
AL13 GPIO_20_PWRCNTL_1 NC#1 V13
[37] PWRCNTRL1 GPU_GPIO21 AJ14 U13
GPIO_21 NC#2
TP3 GPU_GPIO22
*EV@ME2N7002K R23 AK13 GPIO_22_ROMCSB NC#3 AC31
TP1 PCIE_REQ_GPU#
*EV@10K_4 AN13 CLKREQB NC#4 AD30 +1.8V_VDD1DI R_pu R317
[5] PCIE_REQ_GPU#
1

NC#5 AC32 DAC1 Digital Power : 1.8V@117mA EV_SP@0_4

NC#6 AD32 L15
AG32 GPIO_29 NC#7 AF32 EV_O@BLM15BD121SN1D_300MA PS_3
[37] PWRCNTRL4
AG33 GPIO_30 NC#8 AA29
[37] PWRCNTRL5
NC#9 AG21 C163 C168 C178 R_pd
AJ19 GENERICA EV_O@0.1u/10V_4 EV_O@1u/6.3V_4 EV_O@10u/6.3V_6 Ca C531 R309
AK19 GENERICB EV@680n/6.3V_4 EV_SP@0_4
GPU_GENERICC AJ20 GENERICC
TP70
AK20 GENERICD
AJ24 GENERICE_HPD4 NC_TSVSSQ AF33
AH26 GENERICF_HPD5
AH24 GENERICG_HPD6

PS_0 AM34 PS_0 VDDC_CT VDDC_CT VDDC_CT

+1.8V_GFX
AC30 CEC_1
TP13
AK24 AD31 PS_1
TP12 HPD1
MLPS
PS_1 R_pu R320 R_pu R318 R_pu R319
R251 EV@8.45K/F_4 *EV@0_4 *EV@0_4
EV_O@499/F_4
PS_0 PS_1 PS_2
GPU_VREFG AH13 VREFG PS_2 AG31 PS_2
R_pd R_pd R_pd
Ca C534 R312 Ca C532 R310 Ca C533 R311
R248 C499 BACO *EV@82n/16V_4 EV@2K/F_4 *EV@0.1u/10V_4 EV@4.75K/F_4 *EV@680n/6.3V_4 EV@4.75K/F_4
EV_O@249/F_4 EV_O@0.1u/10V_4 R259 *EV@4.7K_4 AL21 PX_EN PS_3 AD33 PS_3

Place close to Chip

DEBUG DDC/AUX
DDC1CLK AM26
MLPS
DDC1DATA AN26
R291 EV@1K_4 TESTEN AD28 TESTEN R_pu R_pd Bits [3:1] Ra P/N MLPS Bit Bits [5:1] Ca Bits [5:4] P/N
AUX1P AM27
R301 *EV@5.11K/F_4 AUX1N AL27
+3V_GFX
NC 4.75K 000 2K CS22002FB19 PS_0 11001 680nF 00 CH4681K9B00
R262 *EV@10K_4 AM23 JTAG_TRSTB DDC2CLK AM19
R263 *EV@10K_4 AN23 JTAG_TDI DDC2DATA AL19
R265 *EV@10K_4 AK23 JTAG_TCK 8.45K 2K 001 3.24K CS23242FB09 PS_1 11000 82nF 01 CH3823K1B00
R266 *EV@10K_4 AL24 JTAG_TMS AUX2P AN20
R273 *EV@10K_4 AM24 JTAG_TDO AUX2N AM20
4.53K 2K 010 3.4K CS23402FB08 PS_2 11000 10nF 10 CH31003KB11
DDCCLK_AUX3P AL30
DDCDATA_AUX3N AM30
THERMAL 6.98K 4.99K 011 4.53K CS24532FB08 PS_3 00XXX NC 11
DDCCLK_AUX4P AL29
GPU_D+ AF29 DPLUS DDCDATA_AUX4N AM29
GPU_D- AG29 DMINUS 4.53K 4.99K 100 4.75K CS24752FB12
DDCCLK_AUX5P AN21
Opal/Jet:NC DDCDATA_AUX5N AM21
GPU_GPIO28 AK32
PU:Disable MLPS R296 EV@10K_4 GPIO_28_FDO 3.24K 5.62K 101 4.99K CS24992FB26
AK30
PD:Enable MLPS AL31
DDCCLK_AUX6P
AK29
TS_A DDCDATA_AUX6N
3.4K 10K 110 5.62K CS25622FB18
on-die thermal sensor power : 1.8V@13mA DDCVGACLK AJ30
L17 +1.8V_TSVDD AJ32 TSVDD DDCVGADATA AJ31
+1.8V_GFX
EV@BLM15BD121SN1D_300MA AJ33 4.75K NC 111 6.98K CS26982FB01
C160 C154
TSVSS
Quanta Computer Inc.
C173
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 EV_SP@GPU_M2 8.45K CS28452FB12 PROJECT : ZYV
Size Document Number Rev
10K CS31002JB28 Opal(Jet)_M2/GPIO_DP_CRT_I2C C3A

Date: Monday, April 28, 2014 Sheet 12 of 40

 237mA
L14 EV@PBY160808T-501Y-N_1.2A DPLL_PVDD
+1.8V_GFX
U16G
C155 C161
C177
U16I PART 7 0F 9
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4

VARY_BL AK27 R275 *EV_O@10K_4

PART 9 0F 9 AJ27 R278 *EV_O@10K_4
LVDS CONTROL DIGON

AM32 DPLL_PVDD XTALIN AV33 GPU_XTALIN C510 EV@10p/50V_4 TXCLK_UP_DPF3P AK35

280mA TXCLK_UN_DPF3N AL36

3
4
L13 EV@PBY160808T-501Y-N_1.2A DPLL_VDDC AN31 DPLL_VDDC
+PCIE_VDDC_GFX
R283 Y1 TXOUT_U0P_DPF2P AJ38
C145 C146 EV@1M/F_4 TXOUT_U0N_DPF2N AK37
C176 AN32 DPLL_PVSS EV@27MHz_XTAL
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 TXOUT_U1P_DPF1P AH35

1
2
XTALOUT AU34 GPU_XTALOUT C512 EV@10p/50V_4 TXOUT_U1N_DPF1N AJ36

0116_B_change from 8.2p to 10p TXOUT_U2P_DPF0P AG38

TXOUT_U2N_DPF0N AH37
H7 MPLL_PVDD
H8 MPLL_PVDD TXOUT_U3P AF35
90mA TXOUT_U3N AG36

LVTMDP
L1 EV@FCM1005KF-221T03_300MA MPLL_PVDD XO_IN AW34 R286 EV@10K_4
+1.8V_GFX
C50 C57 AM10 SPLL_PVDD

PLLS/XTAL
C52
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 TXCLK_LP_DPE3P AP34
TXCLK_LN_DPE3N AR34
AN9 SPLL_VDDC XO_IN2 AW35 R285 EV@10K_4
TXOUT_L0P_DPE2P AW37
TXOUT_L0N_DPE2N AU35

AN10 SPLL_PVSS TXOUT_L1P_DPE1P AR37

TXOUT_L1N_DPE1N AU39
75mA
L3 EV@BLM15BD121SN1D_300MA SPLL_PVDD TXOUT_L2P_DPE0P AP35
+1.8V_GFX
CLKTESTA AK10 CLKTESTA TXOUT_L2N_DPE0N AR35
C76 C75 AF30 NC_XTAL_PVDD CLKTESTB AL10 CLKTESTB
C77 AF31 NC_XTAL_PVSS route 50ohms TXOUT_L3P AN36
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 single-ended/100ohms diff TXOUT_L3N AP37
and keep short
C496 C494
*EV@0.1u/10V_4 *EV@0.1u/10V_4

EV_SP@GPU_M2
EV_SP@GPU_M2
100mA R246 R245
L2 EV@BLM15BD121SN1D_300MA SPLL_VDDC *EV@51.1/F_4 *EV@51.1/F_4
+PCIE_VDDC_GFX
C64 C65
C66
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4

Debug only, for clock observation

Quanta Computer Inc.

PROJECT : ZYV
Size Document Number Rev
C3A
Opal(Jet)_M2/ XTAL_LVDS
Date: Monday, April 28, 2014 Sheet 13 of 40
 PS_3 [3:1]
Opal Jet CONFIGURATION STRAPS -- SEE EACH DATABOOK FOR STRAP DETAILS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

Default Setting
Vendor Vendor P/N STN B/S P/N Size MLPS MLPS STRAPS MLPS GPIO PIN DESCRIPTION OF DEFAULT SETTINGS

MLPS_DISABLE NA GPIO_28_FDO Enable MLPS, NA for Thames/Whistler/Seymour X

0: Enable MLPS, disable GPIO PINSTRAP
AKD5MZDTW05 *4 1G 000 1: Disable MLPS, enable GPIO PINSTRAP

H5TC2G63FFR-11C
(128Mb*16) 2Gb TX_PWRS_ENB PS_1[4] GPIO0 Transmitter Power Savings Enable
0: 50% Tx output swing X
AKD5MZDTW05 *8
2G 001 1: Full Tx output swing

Hynix TX_DEEMPH_EN PS_1[5] GPIO1 PCIE Transmitter De-emphasis Enable X

0: Tx de-emphasis disabled
1: Tx de-emphasis enabled
AKD5PGWTW13 *4
2G BIF_GEN3_EN_A PS_1[1] GPIO2 PCIE Gen3 Enable (NOTE: RESERVED for Thames/Whistler/Seymour) 1
H5TC4G63AFR-11C 0: GEN3 not supported at power-on
(256Mb*16) 4Gb 1: GEN3 supported at power-on

AKD5PGWTW13 *8
4G BIF_VGA DIS PS_2[4] GPIO9 VGA Control
0: VGA controller capacity enabled
0

1: VGA controller capacity disabled (for multi-GPU)

AKD5MGST513 *4
1G 010 ROMIDCFG[2:0] PS_0[3..1] GPIO[13:11] Serial ROM type or Memory Aperture Size Select

K4W2G1646Q-BC1A If GPIO22 = 0, defines memory aperture size XXX

(128Mb*16) 2Gb If GPIO22 = 1, defines ROM type
100 - 512Kbit M25P05A (ST)
AKD5MGST513 *8
2G 011 101 - 1Mbit M25P10A
101 - 2Mbit M25P20
101 - 4Mbit M25P40
(ST)
(ST)
(ST)
Samsung 101 - 8Mbit M25P80 (ST)
100 - 512Kbit Pm25LV512 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)
AKD5PGWT504 *4
2G BIOS_ROM_EN PS_2[3] GPIO22 Enable external BIOS ROM device X
K4W4G1646D-BC1A 0: Disabled
(256Mb*16) 4Gb 1: Enabled

AKD5PGWT504 *8
4G AUD[1]
AUD[0]
NA
NA
HSYNC
VSYNC
00 - No audio function
01 - Audio for DP only
XX
10 - Audio for DP and HDMI if dongle is detected
11 - Audio for both DP and HDMI
HDMI must only be enabled on systems that are legally entitled. It is the
responsibility of the system designer to ensure that the system is entitled to
AKD5MGSTL25 *4 1G 100 support this feature.

MT41J128M16JT-093G:K CEC_DIS PS_0[4] GENLK_VSYNC Enable CEC function. Reserved for Thames/Whistler/Seymour X
(128Mb*16) 2Gb 0: Disabled
1: Enabled
AKD5MGSTL25 *8 2G 101
Micron
NOTE: ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR
AKD5PZSTL02 *4 2G IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET
MT41J256M16HA-093G:E RESERVED PS_1[3] GENLK_CLK Reserved 0
(256Mb*16) 4Gb RESERVED PS_1[2] GPIO8 Reserved 0
RESERVED NA GPIO21 Reserved 0
AKD5PZSTL02 *8 4G RESERVED NA GENERICC Reserved (for Thames/Whistler/Seymour only) 0

AUD_PORT_CONN_PINSTRAP[2]
AUD_PORT_CONN_PINSTRAP[1]
AUD_PORT_CONN_PINSTRAP[0]
PS_3[5] NA STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS XXX
PS_3[4] NA 111 = 0 usable endpoints
NA 110 = 1 usable endpoints
PS_0[5] 101 = 2 usable endpoints
100 = 3 usable endpoints
011 = 4 usable endpoints
010 = 5 usable endpoints
001 = 6 usable endpoints
000 = all endpoints are usable

System Memory Aperture size

GPIO9 GPIO11 GPIO12 GPIO13
BIOSROM ROMIDCFG0 ROMIDCFG1 ROMIDCFG2

0 128MB 0 0 0

0 256MB 1 0 0
( and above )

0 64MB 0 1 0
0 Reservd 1 1 0

Quanta Computer Inc.

PROJECT : ZYV
Size Document Number Rev
C3A
Opal(Jet)_M2/ STRAPS_Thermal
Date: Monday, April 28, 2014 Sheet 14 of 40
 U16E

PART 5 0F 9 +1.8V_GFX
+1.5V_GFX
(2.2A) MEM I/O (100mA)
AC7 VDDR1 NC_PCIE_VDDR AA31 PCIE_VDDR L19 EV@HCB1608KF-121T30_3A
AD11 VDDR1 NC_PCIE_VDDR AA32
C709 AF7 VDDR1 NC_PCIE_VDDR AA33
+ C710 C74 C97 C72 C49 C127 AG10 VDDR1 NC_PCIE_VDDR AA34 C170 C149 C162 C184
*100U/6.3V_1206 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 AJ7 VDDR1 NC_PCIE_VDDR W30 EV@0.01u/25V_4 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@10u/6.3V_6
*330u/2V_7343 AK8 VDDR1 NC_PCIE_VDDR Y31
AL9 VDDR1 NC_BIF_VDDC V28
G11 VDDR1 NC_BIF_VDDC W29
G14 VDDR1 PCIE_PVDD AB37 +PCIE_VDDC_GFX
G17

PCIE
VDDR1
G20 VDDR1 PCIE_VDDC G30
G23 VDDR1 PCIE_VDDC G31
C63 C56 C109 C55 C62 G26 VDDR1 PCIE_VDDC H29
EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 G29 VDDR1 PCIE_VDDC H30 C137 C147 C143 C144 C132 C142 C129 C152 C157 C159 C172
H10 VDDR1 PCIE_VDDC J29 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6
J7 VDDR1 PCIE_VDDC J30 2.5A
J9 VDDR1 PCIE_VDDC L28
K11 VDDR1 PCIE_VDDC M28
K13 VDDR1 PCIE_VDDC N28
K8 VDDR1 PCIE_VDDC R28
C69 C134 C51 C59 L12 VDDR1 PCIE_VDDC T28
EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 L16 VDDR1 PCIE_VDDC U28
L21 VDDR1
L23 VDDR1
L26 VDDR1 BIF_VDDC N27
L7 BACO T27
VDDR1 BIF_VDDC 1.4A
M11 VDDR1
+ N11 VDDR1
C60 C120 C99 C83 C482 P7 VDDR1 VDDC AA15
R11 CORE AA17
EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@100u/6.3V_3528 VDDR1 VDDC
U11 VDDR1 VDDC AA20
U7 VDDR1 VDDC AA22
Y11 VDDR1 VDDC AA24
Y7 VDDR1 VDDC AA27
VDDC AB16 +VGPU_CORE
VDDC AB18 (30A)
VDDC AB21
Level translation between core and I/O, VDDC AB23
excluding memory receivers. VDDC_CT LEVEL VDDC AB26
(13mA) TRANSLATION VDDC AB28 C113 C103 C125 C111 C100 C140 C102
L11 VDDC_CT AF26 VDD_CT VDDC AC17 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4
+1.8V_GFX
EV@BLM15BD121SN1D_300MA AF27 VDD_CT VDDC AC20
AG26 VDD_CT VDDC AC22
C166 C135 C133 C128 AG27 VDD_CT VDDC AC24
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@0.1u/10V_4 VDDC AC27
VDDC AD18
I/O VDDC AD21
I/O power for 3.3-V pins, such as GPIOs. (25mA) AF23 VDDR3 VDDC AD23
+3V_GFX L10 VDDR3 AF24 VDDR3 VDDC AD26
EV@BLM15BD121SN1D_300MA AG23 VDDR3 VDDC AF17 C101 C98 C138 C114 C124 C118 C112 C131 C110
AG24 VDDR3 VDDC AF20 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4 EV@2.2u/6.3V_4
C151 C121 C123 C122 VDDC AF22
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 DVP VDDC AG16
AD12 VDDR4 VDDC AG18
AF11 VDDR4
AF12 VDDR4 VDDC AH22
Power for all DVP pins; DVPDATA_[23:0]—DVO or GPIO. AF13 VDDR4 VDDC AH27
(300mA) VDDC AH28
L4 VDDR4 VDDC M26
+1.8V_GFX
EV_O@BLM15BD121SN1D_300MA AF15 VDDR4 VDDC N24 C108 C119 C115 C141 C116 C104
AG11 VDDR4 VDDC R18 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6
C79 C87 C86 C81 AG13 VDDR4 VDDC R21
EV_O@4.7u/6.3V_6 EV_O@1u/6.3V_4 EV_O@0.1u/10V_4 AG15 VDDR4 VDDC R23
EV_O@4.7u/6.3V_6 VDDC R26
VDDC T17
VDDC T20
VDDC T22
VDDC T24
VDDC U16
VDDC U18
VDDC U21
VDDC U23
VDDC U26
VDDC V17
VDDC V20
VDDC V22
VDDC V24
VDDC V27
VDDC Y16
VDDC Y18
VDDC Y21
VDDC Y23
VDDC Y26
VDDC Y28
(8.8A) L5 EV@HCB1608KF-121T30_3A +VGPU_CORE
VDDCI AA13 VDDCI L9 EV@HCB1608KF-121T30_3A
VDDCI AB13
VDDCI AC12
VDDCI AC15 C94 C84 C96 C95 C117
VDDCI AD13 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
VDDCI AD16
VDDCI M15
VDDCI M16
GPUVDDC/GPUVSS route a differtial pair. VDDCI M18
VOLTAGE M23
VDDCI
SENESE N13
CORE I/O

VDDCI
ISOLATED

R267 *SHORT_4GPUVDDC_SENSE_R AF28 FB_VDDC VDDCI N15

[37] GPUVDDC_SENSE N17
VDDCI C85 C88
VDDCI N20 EV@10u/6.3V_6 EV@10u/6.3V_6
AG28 FB_VDDCI VDDCI N22
TP14 R12
VDDCI
VDDCI R13
R268 *SHORT_4GPUVSS_SENSE_R AH29 R16
[37] GPUVSS_SENSE FB_GND VDDCI
VDDCI T12
T15
Quanta Computer Inc.
VDDCI
V15
VDDCI
VDDCI Y13 PROJECT : ZYV
Size Document Number Rev
C3A
EV_SP@GPU_M2
Opal(Jet)_M2/ MainPower
Date: Monday, April 28, 2014 Sheet 15 of 40
 U16H

PART 8 0F 9

DP_VDDR DP_VDDC
(330mA)
DP_VDDC AP31 DPAB_VDD10 L12 +PCIE_VDDC_GFX
Jet : DP_VDDC AP32 EV_O@PBY160808T-501Y-N_1.2A
NC PIN DP_VDDC AN33 C148 C153
DP_VDDC AP33 C158
AN24 DP_VDDR EV_O@10u/6.3V_6 EV_O@1u/6.3V_4 EV_O@0.1u/10V_4
AP24 DP_VDDR DP_VDDC AP13
AP25 DP_VDDR Opal/Jet : DP_VDDC AT13
AP26 DP_VDDR
NC PIN DP_VDDC AP14
AU28 DP_VDDR DP_VDDC AP15
AV29 DP_VDDR
DP_VDDC AL33
Jet : DP_VDDC AM33
AP20 DP_VDDR
NC PIN DP_VDDC AK33
AP21 DP_VDDR DP_VDDC AK34
AP22 DP_VDDR
AP23 DP_VDDR
AU18 DP_VDDR
+1.8V_GFX AV19 DP_VDDR
DP GND

DP_VSSR AN27
AH34 DP_VDDR DP_VSSR AP27
AJ34 DP_VDDR DP_VSSR AP28
AF34 DP_VDDR Jet : DP_VSSR AW24
(330mA) AG34 DP_VDDR
NC PIN DP_VSSR AW26
L18 EV_O@PBY160808T-501Y-N_1.2A DPEF_VDD18 AM37 DP_VDDR DP_VSSR AN29
AL38 DP_VDDR DP_VSSR AP29
DP_VSSR AP30
C181 C165 C171 DP_VSSR AW30
EV_O@10u/6.3V_6 EV_O@1u/6.3V_4 EV_O@0.1u/10V_4 DP_VSSR AW32
DP_VSSR AN17
DP_VSSR AP16
DP_VSSR AP17
DP_VSSR AW14
DP_VSSR AW16
DP_VSSR AN19
DP_VSSR AP18
DP_VSSR AP19
Jet : DP_VSSR AW20
CALIBRATION NC PIN DP_VSSR AW22
DP_VSSR AN34
DP_VSSR AP39
AW28 DPAB_CALR Opal/Jet : DP_VSSR AR39
NC PIN DP_VSSR AU37
DP_VSSR AF39
DP_VSSR AH39
AW18 DPCD_CALR DP_VSSR AK39
DP_VSSR AL34
DP_VSSR AV27
DP_VSSR AR28
R297 EV_O@150/F_4 AM39 DPEF_CALR Jet : DP_VSSR AV17
NC PIN DP_VSSR AR18
DP_VSSR AN38
DP_VSSR AM35

EV_SP@GPU_M2

Quanta Computer Inc.

PROJECT : ZYV
Size Document Number Rev
C3A
Opal(Jet)_M2/ DP_Powers
Date: Monday, April 28, 2014 Sheet 16 of 40
<VGA>
U16F

PART 6 0F 9

AB39 PCIE_VSS GND A3

E39 PCIE_VSS GND A37
F34 PCIE_VSS GND AA16
F39 PCIE_VSS GND AA18
G33 PCIE_VSS GND AA2
G34 PCIE_VSS GND AA21
H31 PCIE_VSS GND AA23
H34 PCIE_VSS GND AA26
H39 PCIE_VSS GND AA28
J31 PCIE_VSS GND AA6
J34 PCIE_VSS GND AB12
K31 PCIE_VSS GND AB15
K34 PCIE_VSS GND AB17
K39 PCIE_VSS GND AB20
L31 PCIE_VSS GND AB22
L34 PCIE_VSS GND AB24
M34 PCIE_VSS GND AB27
M39 PCIE_VSS GND AC11
N31 PCIE_VSS GND AC13
N34 PCIE_VSS GND AC16
P31 PCIE_VSS GND AC18
P34 PCIE_VSS GND AC2
P39 PCIE_VSS GND AC21
R34 PCIE_VSS GND AC23
T31 PCIE_VSS GND AC26
T34 PCIE_VSS GND AC28
T39 PCIE_VSS GND AC6
U31 PCIE_VSS GND AD15
U34 PCIE_VSS GND AD17
V34 PCIE_VSS GND AD20
V39 PCIE_VSS GND AD22
W31 PCIE_VSS GND AD24
W34 PCIE_VSS GND AD27
Y34 PCIE_VSS GND AD9
Y39 PCIE_VSS GND AE2
GND AE6
GND AF10
GND AF16
GND AF18
GND GND AF21
GND AG17
F15 GND GND AG2
F17 GND GND AG20
F19 GND GND AG22
F21 GND GND AG6
F23 GND GND AG9
F25 GND GND AH21
F27 GND GND AJ10
F29 GND GND AJ11
F31 GND GND AJ2
F33 GND GND AJ28
F7 GND GND AJ6
F9 GND GND AK11
G2 GND GND AK31
G6 GND GND AK7
H9 GND GND AL11
J2 GND GND AL14
J27 GND GND AL17
J6 GND GND AL2
J8 GND GND AL20
K14 GND
K7 GND GND AL23
L11 GND GND AL26
L17 GND GND AL32
L2 GND GND AL6
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
N21 GND GND AP11
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND
U27 GND
U6 GND
V11 GND
V16 GND
V18 GND
V21 GND
V23 GND
V26 GND
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND VSS_MECH A39
Y24 GND VSS_MECH AW1
Y27 GND VSS_MECH AW39

EV_SP@GPU_M2

Quanta Computer Inc.

PROJECT : ZYV
Size Document Number Rev
C3A
Opal(Jet)_M2/ GND
Date: Monday, April 28, 2014 Sheet 17 of 40
<VGA>
VMB_DQ[63..0] OPAL/JET
OPAL only [20] VMB_DQ[63..0]
VMB_DM[7..0]
[20] VMB_DM[7..0] U16D
U16C VMB_RDQS[7..0]
[20] VMB_RDQS[7..0] PART 4 0F 9
PART 3 0F 9 VMB_WDQS[7..0]
VMA_DQ[63..0] [20] VMB_WDQS[7..0] VMB_DQ0 GDDR5/DDR3 VMB_MA0
GDDR5/DDR3 C5 DQB0_0 MAB0_0/MAB_0 P8
[19] VMA_DQ[63..0] VMA_DQ0 VMA_MA0 VMB_MA[15..0] VMB_DQ1 VMB_MA1
C37 DQA0_0 MAA0_0/MAA_0 G24 C3 DQB0_1 MAB0_1/MAB_1 T9
VMA_DM[7..0] VMA_DQ1 C35 J23 VMA_MA1 [20] VMB_MA[15..0] VMB_DQ2 E3 P9 VMB_MA2
DQA0_1 MAA0_1/MAA_1 DQB0_2 MAB0_2/MAB_2
[19] VMA_DM[7..0] VMA_DQ2 VMA_MA2 VMB_DQ3 VMB_MA3
A35 DQA0_2 MAA0_2/MAA_2 H24 E1 DQB0_3 MAB0_3/MAB_3 N7
VMA_RDQS[7..0] VMA_DQ3 E34 DQA0_3 MAA0_3/MAA_3 J24 VMA_MA3 VMB_DQ4 F1 DQB0_4 MAB0_4/MAB_4 N8 VMB_MA4
[19] VMA_RDQS[7..0] VMA_DQ4 VMA_MA4 VMB_BA0 VMB_DQ5 VMB_MA5
G32 DQA0_4 MAA0_4/MAA_4 H26 F3 DQB0_5 MAB0_5/MAB_5 N9
VMA_WDQS[7..0] VMA_DQ5 VMA_MA5 [20] VMB_BA0 VMB_BA1 VMB_DQ6 VMB_MA6
D33 DQA0_5 MAA0_5/MAA_5 J26 F5 DQB0_6 MAB0_6/MAB_6 U9
[19] VMA_WDQS[7..0] VMA_DQ6 F32 H21 VMA_MA6 [20] VMB_BA1 VMB_BA2 VMB_DQ7 G4 U8 VMB_MA7
DQA0_6 MAA0_6/MAA_6 DQB0_7 MAB0_7/MAB_7
VMA_DQ7 VMA_MA7 [20] VMB_BA2 VMB_DQ8 VMB_MA8
E32 DQA0_7 MAA0_7/MAA_7 G21 H5 DQB0_8 MAB1_0/MAB_8 Y9
VMA_DQ8 D31 H19 VMA_MA8 VMB_DQ9 H6 W9 VMB_MA9

MEMORY INTERFACE A
DQA0_8 MAA1_0/MAA_8 DQB0_9 MAB1_1/MAB_9
VMA_MA[15..0] VMA_DQ9 F30 DQA0_9 MAA1_1/MAA_9 H20 VMA_MA9 VMB_DQ10 J4 DQB0_10 MAB1_2/MAB_10 AC8 VMB_MA10
[19] VMA_MA[15..0] VMA_DQ10 VMA_MA10 VMB_DQ11 VMB_MA11
C30 DQA0_10 MAA1_2/MAA_10 L13 K6 DQB0_11 MAB1_3/MAB_11 AC9
VMA_DQ11 A30 DQA0_11 MAA1_3/MAA_11 G16 VMA_MA11 VMB_DQ12 K5 DQB0_12 MAB1_4/MAB_12 AA7 VMB_MA12
VMA_BA0 VMA_DQ12 F28 DQA0_12 MAA1_4/MAA_12 J16 VMA_MA12 VMB_DQ13 L4 DQB0_13 MAB1_5/BA2 AA8 VMB_BA2
[19] VMA_BA0 VMA_BA1 VMA_DQ13 C28 H16 VMA_BA2 VMB_DQ14 M6 Y8 VMB_BA0
DQA0_13 MAA1_5/MAA_BA2 DQB0_14 MAB1_6/BA0
[19] VMA_BA1 VMA_BA2 VMA_DQ14 VMA_BA0 VMB_DQ15 VMB_BA1
A28 DQA0_14 MAA1_6/MAA_BA0 J17 M1 DQB0_15 MAB1_7/BA1 AA9
[19] VMA_BA2 VMA_DQ15 VMA_BA1 VMB_DQ16
E28 DQA0_15 MAA1_7/MAA_BA1 H17 M3 DQB0_16
VMA_DQ16 VMB_DQ17 VMB_DM0

MEMORY INTERFACE B
D27 DQA0_16 M5 DQB0_17 WCKB0_0/DQMB_0 H3
VMA_DQ17 F26 DQA0_17 WCKA0_0/DQMA_0 A32 VMA_DM0 VMB_DQ18 N4 DQB0_18 WCKB0B_0/DQMB_1 H1 VMB_DM1
VMA_DQ18 C26 DQA0_18 WCKA0B_0/DQMA_1 C32 VMA_DM1 VMB_DQ19 P6 DQB0_19 WCKB0_1/DQMB_2 T3 VMB_DM2
VMA_DQ19 A26 DQA0_19 WCKA0_1/DQMA_2 D23 VMA_DM2 VMB_DQ20 P5 DQB0_20 WCKB0B_1/DQMB_3 T5 VMB_DM3
VMA_DQ20 F24 DQA0_20 WCKA0B_1/DQMA_3 E22 VMA_DM3 VMB_DQ21 R4 DQB0_21 WCKB1_0/DQMB_4 AE4 VMB_DM4
VMA_DQ21 C24 DQA0_21 WCKA1_0/DQMA_4 C14 VMA_DM4 VMB_DQ22 T6 DQB0_22 WCKB1B_0/DQMB_5 AF5 VMB_DM5
VMA_DQ22 A24 DQA0_22 WCKA1B_0/DQMA_5 A14 VMA_DM5 VMB_DQ23 T1 DQB0_23 WCKB1_1/DQMB_6 AK6 VMB_DM6
VMA_DQ23 E24 DQA0_23 WCKA1_1/DQMA_6 E10 VMA_DM6 VMB_DQ24 U4 DQB0_24 WCKB1B_1/DQMB_7 AK5 VMB_DM7
VMA_DQ24 C22 DQA0_24 WCKA1B_1/DQMA_7 D9 VMA_DM7 VMB_DQ25 V6 DQB0_25
VMA_DQ25 A22 DQA0_25
VMB_DQ26 V1 DQB0_26 EDCB0_0/QSB_0 F6 VMB_RDQS0
VMA_DQ26 F22 DQA0_26 EDCA0_0/QSA_0 C34 VMA_RDQS0 VMB_DQ27 V3 DQB0_27 EDCB0_1/QSB_1 K3 VMB_RDQS1
VMA_DQ27 D21 DQA0_27 EDCA0_1/QSA_1 D29 VMA_RDQS1 VMB_DQ28 Y6 DQB0_28 EDCB0_2/QSB_2 P3 VMB_RDQS2
VMA_DQ28 A20 DQA0_28 EDCA0_2/QSA_2 D25 VMA_RDQS2 VMB_DQ29 Y1 DQB0_29 EDCB0_3/QSB_3 V5 VMB_RDQS3
VMA_DQ29 F20 DQA0_29 EDCA0_3/QSA_3 E20 VMA_RDQS3 VMB_DQ30 Y3 DQB0_30 EDCB1_0/QSB_4 AB5 VMB_RDQS4
VMA_DQ30 D19 DQA0_30 EDCA1_0/QSA_4 E16 VMA_RDQS4 VMB_DQ31 Y5 DQB0_31 EDCB1_1/QSB_5 AH1 VMB_RDQS5
VMA_DQ31 E18 DQA0_31 EDCA1_1/QSA_5 E12 VMA_RDQS5 VMB_DQ32 AA4 DQB1_0 EDCB1_2/QSB_6 AJ9 VMB_RDQS6
VMA_DQ32 C18 DQA1_0 EDCA1_2/QSA_6 J10 VMA_RDQS6 VMB_DQ33 AB6 DQB1_1 EDCB1_3/QSB_7 AM5 VMB_RDQS7
VMA_DQ33 A18 DQA1_1 EDCA1_3/QSA_7 D7 VMA_RDQS7 VMB_DQ34 AB1 DQB1_2
VMA_DQ34 F18 DQA1_2 VMB_DQ35 AB3 DQB1_3 DDBIB0_0/QSB_0B G7 VMB_WDQS0
VMA_DQ35 D17 DQA1_3 DDBIA0_0/QSA_0B A34 VMA_WDQS0 VMB_DQ36 AD6 DQB1_4 DDBIB0_1/QSB_1B K1 VMB_WDQS1
VMA_DQ36 A16 DQA1_4 DDBIA0_1/QSA_1B E30 VMA_WDQS1 VMB_DQ37 AD1 DQB1_5 DDBIB0_2/QSB_2B P1 VMB_WDQS2
VMA_DQ37 F16 DQA1_5 DDBIA0_2/QSA_2B E26 VMA_WDQS2 VMB_DQ38 AD3 DQB1_6 DDBIB0_3/QSB_3B W4 VMB_WDQS3
VMA_DQ38 D15 DQA1_6 DDBIA0_3/QSA_3B C20 VMA_WDQS3 VMB_DQ39 AD5 DQB1_7 DDBIB1_0/QSB_4B AC4 VMB_WDQS4
VMA_DQ39 E14 DQA1_7 DDBIA1_0/QSA_4B C16 VMA_WDQS4 VMB_DQ40 AF1 DQB1_8 DDBIB1_1/QSB_5B AH3 VMB_WDQS5
VMA_DQ40 F14 DQA1_8 DDBIA1_1/QSA_5B C12 VMA_WDQS5 VMB_DQ41 AF3 DQB1_9 DDBIB1_2/QSB_6B AJ8 VMB_WDQS6
VMA_DQ41 D13 DQA1_9 DDBIA1_2/QSA_6B J11 VMA_WDQS6 VMB_DQ42 AF6 DQB1_10 DDBIB1_3/QSB_7B AM3 VMB_WDQS7
VMA_DQ42 F12 DQA1_10 DDBIA1_3/QSA_7B F8 VMA_WDQS7 VMB_DQ43 AG4 DQB1_11
VMA_DQ43 A12 DQA1_11
VMB_DQ44 AH5 DQB1_12 ADBIB0/ODTB0 T7
VMA_DQ44 VMB_DQ45 VMB_ODT0 [20]
D11 DQA1_12 ADBIA0/ODTA0 J21 AH6 DQB1_13 ADBIB1/ODTB1 W7
VMA_DQ45 VMA_ODT0 [19] VMB_DQ46 VMB_ODT1 [20]
F10 DQA1_13 ADBIA1/ODTA1 G19 AJ4 DQB1_14
VMA_DQ46 A10 VMA_ODT1 [19] VMB_DQ47 AK3 L9 VMB_CLK0
DQA1_14 DQB1_15 CLKB0
VMA_DQ47 VMB_CLK0 [20]
C10 DQA1_15 CLKA0 H27 VMA_CLK0 VMB_DQ48 AF8 DQB1_16 CLKB0B L8 VMB_CLK0#
VMA_DQ48 G13 G27 VMA_CLK0# VMA_CLK0 [19] VMB_DQ49 AF9 VMB_CLK0# [20]
DQA1_16 CLKA0B DQB1_17
VMA_DQ49 VMA_CLK0# [19] VMB_DQ50
H13 DQA1_17 AG8 DQB1_18 CLKB1 AD8 VMB_CLK1
VMA_DQ50 VMB_CLK1 [20]
J13 DQA1_18 CLKA1 J14 VMA_CLK1 VMB_DQ51 AG7 DQB1_19 CLKB1B AD7 VMB_CLK1#
VMA_DQ51 H11 H14 VMA_CLK1# VMA_CLK1 [19] VMB_DQ52 AK9 VMB_CLK1# [20]
DQA1_19 CLKA1B DQB1_20
VMA_DQ52 VMA_CLK1# [19] VMB_DQ53
G10 DQA1_20 AL7 DQB1_21 RASB0B T10 VMB_RAS0#
VMA_DQ53 G8 K23 VMA_RAS0# VMB_DQ54 AM8 Y10 VMB_RAS1# VMB_RAS0# [20]
Place MVREF dividers and Caps close to ASIC VMA_DQ54
DQA1_21 RASA0B
VMA_RAS0# [19] DQB1_22 RASB1B
VMB_RAS1# [20]
K9 DQA1_22 RASA1B K19 VMA_RAS1# VMB_DQ55 AM7 DQB1_23
VMA_DQ55 VMA_RAS1# [19] VMB_DQ56
K10 DQA1_23 AK1 DQB1_24 CASB0B W10 VMB_CAS0#
VMA_DQ56 G9 K20 VMA_CAS0# VMB_DQ57 AL4 AA10 VMB_CAS1# VMB_CAS0# [20]
DQA1_24 CASA0B DQB1_25 CASB1B
VMA_DQ57 VMA_CAS0# [19] VMB_CAS1# [20]
+1.5V_GFX A8 DQA1_25 CASA1B K17 VMA_CAS1# +1.5V_GFX VMB_DQ58 AM6 DQB1_26
VMA_DQ58 C8 VMA_CAS1# [19] VMB_DQ59 AM1 P10 VMB_CS0#
DQA1_26 DQB1_27 CSB0B_0
VMA_DQ59 VMB_CS0# [20]
(0.7*VDDR1) E8 DQA1_27 CSA0B_0 K24 VMA_CS0# (0.7*VDDR1) VMB_DQ60 AN4 DQB1_28 CSB0B_1 L10
VMA_DQ60 VMA_CS0# [19] VMB_DQ61
A6 DQA1_28 CSA0B_1 K27 AP3 DQB1_29
VMA_DQ61 C6 DQA1_29
VMB_DQ62 AP1 DQB1_30 CSB1B_0 AD10 VMB_CS1#
VMA_DQ62 VMB_CS1# [20]
R260 E6 DQA1_30 CSA1B_0 M13 VMA_CS1# R236 VMB_DQ63 AP5 DQB1_31 CSB1B_1 AC10
VMA_DQ63 A5 K16 VMA_CS1# [19]
EV_O@40.2/F_4 DQA1_31 CSA1B_1 EV@40.2/F_4
CKEB0 U10 VMB_CKE0
VMB_CKE0 [20]
MVREFDA L18 MVREFDA CKEA0 K21 VMA_CKE0 MVREFDB Y12 MVREFDB CKEB1 AA11 VMB_CKE1
L20 J20 VMA_CKE1 VMA_CKE0 [19] AA12 VMB_CKE1 [20]
MVREFSA MVREFSA CKEA1 MVREFSB MVREFSB
VMA_CKE1 [19]
WEB0B N10 VMB_WE0#
L27 K26 VMA_WE0# AB11 VMB_WE1# VMB_WE0# [20]
NC_MEM_CALRN0 WEA0B WEB1B
VMA_WE0# [19] VMB_WE1# [20]
R261 C503 N12 NC_MEM_CALRN1 WEA1B L15 VMA_WE1# R237 C485
VMA_WE1# [19]
EV_O@100/F_4 EV_O@1u/6.3V_4 AG12 NC_MEM_CALRN2 EV@100/F_4 EV@1u/6.3V_4
MAB0_8/MAB_13 T8 VMB_MA13
M12 NC_MEM_CALRP1 MAA0_8/MAA_13 H23 VMA_MA13 MAB1_8/MAB_14 W8 VMB_MA14
R41 EV@120/F_4 M27 MEM_CALRP0 MAA1_8/MAA_14 J19 VMA_MA14 MAB0_9/MAB_15 U12 VMB_MA15
AH12 MEM_CALRP2 MAA0_9/MAA_15 M21 VMA_MA15 MAB1_9/RSVD V12
MAA1_9/RSVD M20
+1.5V_GFX +1.5V_GFX DRAM_RST AH11 GPU_DRAM_RST

(0.7*VDDR1) (0.7*VDDR1)
EV_SP@GPU_M2
R292 R239
EV_O@40.2/F_4 EV_SP@GPU_M2 EV@40.2/F_4

R293 C516 R238 C491

EV_O@100/F_4 EV_O@1u/6.3V_4 EV@100/F_4 EV@1u/6.3V_4

25mm (max) 5mm (max) 25mm (max)

Place MVREF dividers and Caps close to ASIC

GPU_DRAM_RST R242 EV@10/F_4 DRST_R R243 EV@51/F_4
MEM_RST# [19,20]

C493
R241
EV@4.99K/F_4 EV@120p/50V_4

Place all these componets very close to GPU (within 25mm)

and keep all components close to each other
** This basic topology should be used for DRAM_RAT for DDR3/GDDR5

These Capacitors and Resistor values arre an example only

The series R and || cap values will depend on the DRAM loads
and will have to be calculated for differrent Memory, DRAM loads and board
to pass Reset Signal Spec

Quanta Computer Inc.

PROJECT : ZYV
Size Document Number Rev
C3A
Opal(Jet)_M2/ MEM Interface
Date: Monday, April 28, 2014 Sheet 18 of 40
 5 4 3 2 1

[18]

[18]
VMA_DQ[63..0]

VMA_DM[7..0]
VMA_DQ[63..0]

VMA_DM[7..0]
Jet don't use Channel A CHANNEL A: 1GB DDR3 (128M*16*4pcs) Jet don't use Channel A
[18] VMA_RDQS[7..0]
VMA_RDQS[7..0]

VMA_WDQS[7..0]
2GB DDR3 (256M*16*4pcs)
[18] VMA_WDQS[7..0]
U14 U4
U5 U17
VREFC_VMA3 M8 E3 VMA_DQ49 VREFC_VMA4 M8 E3 VMA_DQ62
VREFC_VMA1 M8 E3 VMA_DQ13 VREFC_VMA2 M8 E3 VMA_DQ2 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ53 VREFD_VMA4 H1 VREFCA DQL0 F7 VMA_DQ57
VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ12 VREFD_VMA2 H1 VREFCA DQL0 F7 VMA_DQ5 VREFDQ DQL1 F2 VMA_DQ48 VREFDQ DQL1 F2 VMA_DQ60
VREFDQ DQL1 F2 VMA_DQ11 VREFDQ DQL1 F2 VMA_DQ3 VMA_MA0 N3 DQL2 F8 VMA_DQ55 VMA_MA0 N3 DQL2 F8 VMA_DQ59
VMA_MA0 N3 DQL2 F8 VMA_DQ8 VMA_MA0 N3 DQL2 F8 VMA_DQ7 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ50 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ61
[18] VMA_MA0 VMA_MA1 A0 DQL3 VMA_DQ10 VMA_MA1 A0 DQL3 VMA_DQ0 VMA_MA2 A1 DQL4 VMA_DQ54 VMA_MA2 A1 DQL4 VMA_DQ56
P7 H3 P7 H3 P3 H8 P3 H8
[18] VMA_MA1 VMA_MA2 A1 DQL4 VMA_DQ9 VMA_MA2 A1 DQL4 VMA_DQ6 VMA_MA3 A2 DQL5 VMA_DQ51 VMA_MA3 A2 DQL5 VMA_DQ63
P3 H8 P3 H8 N2 G2 N2 G2
[18] VMA_MA2 VMA_MA3 A2 DQL5 VMA_DQ14 VMA_MA3 A2 DQL5 VMA_DQ1 VMA_MA4 A3 DQL6 VMA_DQ52 VMA_MA4 A3 DQL6 VMA_DQ58
N2 G2 N2 G2 P8 H7 P8 H7
D [18] VMA_MA3 VMA_MA4 A3 DQL6 VMA_DQ15 VMA_MA4 A3 DQL6 VMA_DQ4 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 D
P8 H7 P8 H7 P2 P2
[18] VMA_MA4 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA6 A5 VMA_MA6 A5
P2 P2 R8 R8
[18] VMA_MA5 VMA_MA6 A5 VMA_MA6 A5 VMA_MA7 A6 VMA_DQ38 VMA_MA7 A6 VMA_DQ40
R8 R8 R2 D7 R2 D7
[18] VMA_MA6 VMA_MA7 A6 VMA_DQ25 VMA_MA7 A6 VMA_DQ22 VMA_MA8 A7 DQU0 VMA_DQ35 VMA_MA8 A7 DQU0 VMA_DQ47
R2 D7 R2 D7 T8 C3 T8 C3
[18] VMA_MA7 VMA_MA8 A7 DQU0 VMA_DQ29 VMA_MA8 A7 DQU0 VMA_DQ19 VMA_MA9 A8 DQU1 VMA_DQ39 VMA_MA9 A8 DQU1 VMA_DQ42
T8 C3 T8 C3 R3 C8 R3 C8
[18] VMA_MA8 VMA_MA9 A8 DQU1 VMA_DQ27 VMA_MA9 A8 DQU1 VMA_DQ20 VMA_MA10 A9 DQU2 VMA_DQ32 VMA_MA10 A9 DQU2 VMA_DQ46
R3 C8 R3 C8 L7 C2 L7 C2
[18] VMA_MA9 VMA_MA10 A9 DQU2 VMA_DQ31 VMA_MA10 A9 DQU2 VMA_DQ16 VMA_MA11 A10/AP DQU3 VMA_DQ36 VMA_MA11 A10/AP DQU3 VMA_DQ43
L7 C2 L7 C2 R7 A7 R7 A7
[18] VMA_MA10 VMA_MA11 A10/AP DQU3 VMA_DQ24 VMA_MA11 A10/AP DQU3 VMA_DQ21 VMA_MA12 A11 DQU4 VMA_DQ34 VMA_MA12 A11 DQU4 VMA_DQ45
R7 A7 R7 A7 N7 A2 N7 A2
[18] VMA_MA11 VMA_MA12 A11 DQU4 VMA_DQ30 VMA_MA12 A11 DQU4 VMA_DQ17 VMA_MA13 A12/BC DQU5 VMA_DQ37 VMA_MA13 A12/BC DQU5 VMA_DQ41
N7 A2 N7 A2 T3 B8 T3 B8
[18] VMA_MA12 VMA_MA13 A12/BC DQU5 VMA_DQ26 VMA_MA13 A12/BC DQU5 VMA_DQ23 VMA_MA14 A13 DQU6 VMA_DQ33 VMA_MA14 A13 DQU6 VMA_DQ44
T3 B8 T3 B8 T7 A3 T7 A3
[18] VMA_MA13 VMA_MA14 A13 DQU6 VMA_DQ28 VMA_MA14 A13 DQU6 VMA_DQ18 VMA_MA15 A14 DQU7 VMA_MA15 A14 DQU7
T7 A3 T7 A3 M7 M7
[18] VMA_MA14 VMA_MA15 A14 DQU7 VMA_MA15 A14 DQU7 A15 A15
M7 M7 +1.5V_GFX +1.5V_GFX
[18] VMA_MA15 A15 A15
+1.5V_GFX +1.5V_GFX
VMA_BA0 M2 B2 VMA_BA0 M2 B2
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA1 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9
[18] VMA_BA0 VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2 VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9
N8 D9 N8 D9 M3 G7 M3 G7
[18] VMA_BA1 VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9 BA2 VDD#G7 BA2 VDD#G7
M3 G7 M3 G7 K2 K2
[18] VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 VDD#K2 VDD#K2
K2 K2 K8 K8
VDD#K2 K8 VDD#K2 K8 VDD#K8 N1 VDD#K8 N1
VDD#K8 N1 VDD#K8 N1 VMA_CLK1 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
VMA_CLK0 VDD#N1 VMA_CLK0 VDD#N1 [18] VMA_CLK1 VMA_CLK1# CK VDD#N9 VMA_CLK1# CK VDD#N9
J7 N9 J7 N9 K7 R1 K7 R1
[18] VMA_CLK0 VMA_CLK0# CK VDD#N9 VMA_CLK0# CK VDD#N9 [18] VMA_CLK1# VMA_CKE1 CK VDD#R1 VMA_CKE1 CK VDD#R1
K7 R1 K7 R1 K9 R9 K9 R9
[18] VMA_CLK0# VMA_CKE0 CK VDD#R1 VMA_CKE0 CK VDD#R1 [18] VMA_CKE1 CKE VDD#R9 CKE VDD#R9
K9 R9 K9 R9 +1.5V_GFX +1.5V_GFX
[18] VMA_CKE0 CKE VDD#R9 CKE VDD#R9
+1.5V_GFX +1.5V_GFX
VMA_ODT1 K1 A1 VMA_ODT1 K1 A1
VMA_ODT0 VMA_ODT0 [18] VMA_ODT1 VMA_CS1# ODT VDDQ#A1 VMA_CS1# ODT VDDQ#A1
K1 A1 K1 A1 L2 A8 L2 A8
[18] VMA_ODT0 VMA_CS0# ODT VDDQ#A1 VMA_CS0# ODT VDDQ#A1 [18] VMA_CS1# VMA_RAS1# CS VDDQ#A8 VMA_RAS1# CS VDDQ#A8
L2 A8 L2 A8 J3 C1 J3 C1
[18] VMA_CS0# VMA_RAS0# CS VDDQ#A8 VMA_RAS0# CS VDDQ#A8 [18] VMA_RAS1# VMA_CAS1# RAS VDDQ#C1 VMA_CAS1# RAS VDDQ#C1
J3 C1 J3 C1 K3 C9 K3 C9
[18] VMA_RAS0# VMA_CAS0# RAS VDDQ#C1 VMA_CAS0# RAS VDDQ#C1 [18] VMA_CAS1# VMA_WE1# CAS VDDQ#C9 VMA_WE1# CAS VDDQ#C9
K3 C9 K3 C9 L3 D2 L3 D2
[18] VMA_CAS0# VMA_WE0# CAS VDDQ#C9 VMA_WE0# CAS VDDQ#C9 [18] VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
L3 D2 L3 D2 E9 E9
[18] VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 VDDQ#E9 VDDQ#E9
E9 E9 F1 F1
VDDQ#E9 F1 VDDQ#E9 F1 VMA_RDQS6 F3 VDDQ#F1 H2 VMA_RDQS7 F3 VDDQ#F1 H2
VMA_RDQS1 F3 VDDQ#F1 H2 VMA_RDQS0 F3 VDDQ#F1 H2 VMA_RDQS4 C7 DQSL VDDQ#H2 H9 VMA_RDQS5 C7 DQSL VDDQ#H2 H9
VMA_RDQS3 C7 DQSL VDDQ#H2 H9 VMA_RDQS2 C7 DQSL VDDQ#H2 H9 DQSU VDDQ#H9 DQSU VDDQ#H9
DQSU VDDQ#H9 DQSU VDDQ#H9
VMA_DM6 E7 A9 VMA_DM7 E7 A9
VMA_DM1 E7 A9 VMA_DM0 E7 A9 VMA_DM4 D3 DML VSS#A9 B3 VMA_DM5 D3 DML VSS#A9 B3
C VMA_DM3 D3 DML VSS#A9 B3 VMA_DM2 D3 DML VSS#A9 B3 DMU VSS#B3 E1 DMU VSS#B3 E1 C
DMU VSS#B3 E1 DMU VSS#B3 E1 VSS#E1 G8 VSS#E1 G8
VSS#E1 G8 VSS#E1 G8 VMA_WDQS6 G3 VSS#G8 J2 VMA_WDQS7 G3 VSS#G8 J2
VMA_WDQS1 G3 VSS#G8 J2 VMA_WDQS0 G3 VSS#G8 J2 VMA_WDQS4 B7 DQSL VSS#J2 J8 VMA_WDQS5 B7 DQSL VSS#J2 J8
VMA_WDQS3 B7 DQSL VSS#J2 J8 VMA_WDQS2 B7 DQSL VSS#J2 J8 DQSU VSS#J8 M1 DQSU VSS#J8 M1
DQSU VSS#J8 M1 DQSU VSS#J8 M1 VSS#M1 M9 VSS#M1 M9
VSS#M1 M9 VSS#M1 M9 VSS#M9 P1 VSS#M9 P1
VSS#M9 P1 VSS#M9 P1 MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9
MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9 RESET VSS#P9 T1 RESET VSS#P9 T1
[18,20] MEM_RST# RESET VSS#P9 RESET VSS#P9 VMA_ZQ3 VSS#T1 VMA_ZQ4 VSS#T1
T1 T1 L8 T9 L8 T9
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9 ZQ VSS#T9 ZQ VSS#T9
ZQ VSS#T9 ZQ VSS#T9
B1 B1
B1 B1 VSSQ#B1 B9 VSSQ#B1 B9
VSSQ#B1 B9 VSSQ#B1 B9 R247 VSSQ#B9 D1 R36 VSSQ#B9 D1
R44 VSSQ#B9 D1 R264 VSSQ#B9 D1 EV_O@243/F_4 VSSQ#D1 D8 EV_O@243/F_4 VSSQ#D1 D8
EV_O@243/F_4 VSSQ#D1 D8 EV_O@243/F_4 VSSQ#D1 D8 VSSQ#D8 E2 VSSQ#D8 E2
VSSQ#D8 E2 VSSQ#D8 E2 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 100-BALL 100-BALL
100-BALL 100-BALL SDRAM DDR3 SDRAM DDR3
SDRAM DDR3 SDRAM DDR3 EV_SP@VRAM _DDR3 EV_SP@VRAM _DDR3
EV_SP@VRAM _DDR3 EV_SP@VRAM _DDR3

Group-A0 VREF Group-A1 VREF

+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
B B
R42 R46 R270 R280
EV_O@4.99K/F_4 EV_O@4.99K/F_4 EV_O@4.99K/F_4 EV_O@4.99K/F_4 R249 R254 R29 R25
EV_O@4.99K/F_4 EV_O@4.99K/F_4 EV_O@4.99K/F_4 EV_O@4.99K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2

VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4

R43 C139 R47 C156 R271 C507 R281 C509

R250 C500 R255 C501 R30 C73 R26 C45
EV_O@4.99K/F_4 EV_O@0.1u/10V_4 EV_O@4.99K/F_4 EV_O@0.1u/10V_4 EV_O@4.99K/F_4 EV_O@0.1u/10V_4 EV_O@4.99K/F_4 EV_O@0.1u/10V_4
EV_O@4.99K/F_4 EV_O@0.1u/10V_4 EV_O@4.99K/F_4 EV_O@0.1u/10V_4 EV_O@4.99K/F_4 EV_O@0.1u/10V_4 EV_O@4.99K/F_4 EV_O@0.1u/10V_4

Group-A0 decoupling CAP Group-A1 decoupling CAP

MEM_A0 CLK
MEM_A1 CLK
+1.5V_GFX +1.5V_GFX

VMA_CLK0 VMA_CLK1

VMA_CLK0# VMA_CLK1#
C527 C529 C504 C528 C525 C505 C526 C40 C130 C89 C58 C70 C53 C39 C41 C82
EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4
R274 R277
EV_O@40.2/F_4 EV_O@40.2/F_4 R244 R240
EV_O@40.2/F_4 EV_O@40.2/F_4
+1.5V_GFX +1.5V_GFX

C508
EV_O@0.01u/25V_4 C126 C495 C511 C167 C150 C175 C34 C185 C489 C36 C186 C38 C187 C490 C37 C35 C492
A EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@1u/6.3V_4 EV_O@0.01u/25V_4 A

+1.5V_GFX +1.5V_GFX

C182 C183 C93 C514 C513 C502 C33 C32 C515 C179
EV_O@4.7u/6.3V_6 EV_O@4.7u/6.3V_6 EV_O@4.7u/6.3V_6 EV_O@4.7u/6.3V_6 EV_O@4.7u/6.3V_6 EV_O@4.7u/6.3V_6 EV_O@4.7u/6.3V_6 EV_O@4.7u/6.3V_6 EV_O@4.7u/6.3V_6 EV_O@4.7u/6.3V_6 Quanta Computer Inc.
PROJECT : ZYV
Size Document Number Rev
C3A
Opal(Jet)_M2/VRAM_A
Date: Monday, April 28, 2014 Sheet 19 of 40
5 4 3 2 1
 5 4 3 2 1

[18]

[18]
VMB_DQ[63..0]

VMB_DM[7..0]
VMB_DQ[63..0]

VMB_DM[7..0] Jet use Channel B only CHANNEL B: 1GB DDR3 (128M*16*4pcs) Jet use Channel B only
[18] VMB_RDQS[7..0]
VMB_RDQS[7..0]

VMB_WDQS[7..0]
2GB DDR3 (256M*16*4pcs)
[18] VMB_WDQS[7..0]
U2 U12 U13 U3

VREFC_VMB1 M8 E3 VMB_DQ4 VREFC_VMB2 M8 E3 VMB_DQ9 VREFC_VMB3 M8 E3 VMB_DQ50 VREFC_VMB4 M8 E3 VMB_DQ62

VREFD_VMB1 H1 VREFCA DQL0 F7 VMB_DQ2 VREFD_VMB2 H1 VREFCA DQL0 F7 VMB_DQ13 VREFD_VMB3 H1 VREFCA DQL0 F7 VMB_DQ55 VREFD_VMB4 H1 VREFCA DQL0 F7 VMB_DQ59
VREFDQ DQL1 F2 VMB_DQ7 VREFDQ DQL1 F2 VMB_DQ10 VREFDQ DQL1 F2 VMB_DQ48 VREFDQ DQL1 F2 VMB_DQ61
VMB_MA0 N3 DQL2 F8 VMB_DQ1 VMB_MA0 N3 DQL2 F8 VMB_DQ14 VMB_MA0 N3 DQL2 F8 VMB_DQ53 VMB_MA0 N3 DQL2 F8 VMB_DQ58
[18] VMB_MA0 VMB_MA1 A0 DQL3 VMB_DQ5 VMB_MA1 A0 DQL3 VMB_DQ8 VMB_MA1 A0 DQL3 VMB_DQ49 VMB_MA1 A0 DQL3 VMB_DQ60
P7 H3 P7 H3 P7 H3 P7 H3
[18] VMB_MA1 VMB_MA2 P3 A1 DQL4 H8 VMB_DQ0 VMB_MA2 P3 A1 DQL4 H8 VMB_DQ15 VMB_MA2 P3 A1 DQL4 H8 VMB_DQ54 VMB_MA2 P3 A1 DQL4 H8 VMB_DQ56
[18] VMB_MA2 VMB_MA3 A2 DQL5 VMB_DQ6 VMB_MA3 A2 DQL5 VMB_DQ11 VMB_MA3 A2 DQL5 VMB_DQ51 VMB_MA3 A2 DQL5 VMB_DQ63
N2 G2 N2 G2 N2 G2 N2 G2
D [18] VMB_MA3 VMB_MA4 A3 DQL6 VMB_DQ3 VMB_MA4 A3 DQL6 VMB_DQ12 VMB_MA4 A3 DQL6 VMB_DQ52 VMB_MA4 A3 DQL6 VMB_DQ57 D
P8 H7 P8 H7 P8 H7 P8 H7
[18] VMB_MA4 VMB_MA5 P2 A4 DQL7 VMB_MA5 P2 A4 DQL7 VMB_MA5 P2 A4 DQL7 VMB_MA5 P2 A4 DQL7
[18] VMB_MA5 VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5
R8 R8 R8 R8
[18] VMB_MA6 VMB_MA7 R2 A6 D7 VMB_DQ18 VMB_MA7 R2 A6 D7 VMB_DQ29 VMB_MA7 R2 A6 D7 VMB_DQ46 VMB_MA7 R2 A6 D7 VMB_DQ33
[18] VMB_MA7 VMB_MA8 A7 DQU0 VMB_DQ23 VMB_MA8 A7 DQU0 VMB_DQ27 VMB_MA8 A7 DQU0 VMB_DQ42 VMB_MA8 A7 DQU0 VMB_DQ37
T8 C3 T8 C3 T8 C3 T8 C3
[18] VMB_MA8 VMB_MA9 A8 DQU1 VMB_DQ17 VMB_MA9 A8 DQU1 VMB_DQ28 VMB_MA9 A8 DQU1 VMB_DQ45 VMB_MA9 A8 DQU1 VMB_DQ34
R3 C8 R3 C8 R3 C8 R3 C8
[18] VMB_MA9 VMB_MA10 L7 A9 DQU2 C2 VMB_DQ20 VMB_MA10 L7 A9 DQU2 C2 VMB_DQ25 VMB_MA10 L7 A9 DQU2 C2 VMB_DQ40 VMB_MA10 L7 A9 DQU2 C2 VMB_DQ38
[18] VMB_MA10 VMB_MA11 A10/AP DQU3 VMB_DQ19 VMB_MA11 A10/AP DQU3 VMB_DQ30 VMB_MA11 A10/AP DQU3 VMB_DQ44 VMB_MA11 A10/AP DQU3 VMB_DQ32
R7 A7 R7 A7 R7 A7 R7 A7
[18] VMB_MA11 VMB_MA12 N7 A11 DQU4 A2 VMB_DQ22 VMB_MA12 N7 A11 DQU4 A2 VMB_DQ24 VMB_MA12 N7 A11 DQU4 A2 VMB_DQ41 VMB_MA12 N7 A11 DQU4 A2 VMB_DQ39
[18] VMB_MA12 VMB_MA13 A12/BC DQU5 VMB_DQ16 VMB_MA13 A12/BC DQU5 VMB_DQ31 VMB_MA13 A12/BC DQU5 VMB_DQ47 VMB_MA13 A12/BC DQU5 VMB_DQ35
T3 B8 T3 B8 T3 B8 T3 B8
[18] VMB_MA13 VMB_MA14 A13 DQU6 VMB_DQ21 VMB_MA14 A13 DQU6 VMB_DQ26 VMB_MA14 A13 DQU6 VMB_DQ43 VMB_MA14 A13 DQU6 VMB_DQ36
T7 A3 T7 A3 T7 A3 T7 A3
[18] VMB_MA14 VMB_MA15 M7 A14 DQU7 VMB_MA15 M7 A14 DQU7 VMB_MA15 M7 A14 DQU7 VMB_MA15 M7 A14 DQU7
[18] VMB_MA15 A15 A15 A15 A15
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

[18] VMB_BA0 VMB_BA1 BA0 VDD#B2 VMB_BA1 BA0 VDD#B2 VMB_BA1 BA0 VDD#B2 VMB_BA1 BA0 VDD#B2
N8 D9 N8 D9 N8 D9 N8 D9
[18] VMB_BA1 VMB_BA2 M3 BA1 VDD#D9 G7 VMB_BA2 M3 BA1 VDD#D9 G7 VMB_BA2 M3 BA1 VDD#D9 G7 VMB_BA2 M3 BA1 VDD#D9 G7
[18] VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
VMB_CLK0 J7 VDD#N1 N9 VMB_CLK0 J7 VDD#N1 N9 VMB_CLK1 J7 VDD#N1 N9 VMB_CLK1 J7 VDD#N1 N9
[18] VMB_CLK0 VMB_CLK0# K7 CK VDD#N9 R1 VMB_CLK0# K7 CK VDD#N9 R1 [18] VMB_CLK1 VMB_CLK1# K7 CK VDD#N9 R1 VMB_CLK1# K7 CK VDD#N9 R1
[18] VMB_CLK0# VMB_CKE0 CK VDD#R1 VMB_CKE0 CK VDD#R1 [18] VMB_CLK1# VMB_CKE1 CK VDD#R1 VMB_CKE1 CK VDD#R1
K9 R9 K9 R9 K9 R9 K9 R9
[18] VMB_CKE0 CKE VDD#R9 CKE VDD#R9 [18] VMB_CKE1 CKE VDD#R9 CKE VDD#R9
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

[18] VMB_ODT0 VMB_CS0# L2 ODT VDDQ#A1 A8 VMB_CS0# L2 ODT VDDQ#A1 A8 [18] VMB_ODT1 VMB_CS1# L2 ODT VDDQ#A1 A8 VMB_CS1# L2 ODT VDDQ#A1 A8
[18] VMB_CS0# VMB_RAS0# CS VDDQ#A8 VMB_RAS0# CS VDDQ#A8 [18] VMB_CS1# VMB_RAS1# CS VDDQ#A8 VMB_RAS1# CS VDDQ#A8
J3 C1 J3 C1 J3 C1 J3 C1
[18] VMB_RAS0# VMB_CAS0# K3 RAS VDDQ#C1 C9 VMB_CAS0# K3 RAS VDDQ#C1 C9 [18] VMB_RAS1# VMB_CAS1# K3 RAS VDDQ#C1 C9 VMB_CAS1# K3 RAS VDDQ#C1 C9
[18] VMB_CAS0# VMB_WE0# CAS VDDQ#C9 VMB_WE0# CAS VDDQ#C9 [18] VMB_CAS1# VMB_WE1# CAS VDDQ#C9 VMB_WE1# CAS VDDQ#C9
L3 D2 L3 D2 L3 D2 L3 D2
[18] VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 [18] VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMB_RDQS0 F3 VDDQ#F1 H2 VMB_RDQS1 F3 VDDQ#F1 H2 VMB_RDQS6 F3 VDDQ#F1 H2 VMB_RDQS7 F3 VDDQ#F1 H2
VMB_RDQS2 C7 DQSL VDDQ#H2 H9 VMB_RDQS3 C7 DQSL VDDQ#H2 H9 VMB_RDQS5 C7 DQSL VDDQ#H2 H9 VMB_RDQS4 C7 DQSL VDDQ#H2 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9

VMB_DM0 E7 A9 VMB_DM1 E7 A9 VMB_DM6 E7 A9 VMB_DM7 E7 A9

VMB_DM2 D3 DML VSS#A9 B3 VMB_DM3 D3 DML VSS#A9 B3 VMB_DM5 D3 DML VSS#A9 B3 VMB_DM4 D3 DML VSS#A9 B3
C C
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMB_WDQS0 G3 VSS#G8 J2 VMB_WDQS1 G3 VSS#G8 J2 VMB_WDQS6 G3 VSS#G8 J2 VMB_WDQS7 G3 VSS#G8 J2
VMB_WDQS2 B7 DQSL VSS#J2 J8 VMB_WDQS3 B7 DQSL VSS#J2 J8 VMB_WDQS5 B7 DQSL VSS#J2 J8 VMB_WDQS4 B7 DQSL VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9 MEM_RST# T2 VSS#P1 P9
[18,19] MEM_RST# RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1
VMB_ZQ1 L8 VSS#T1 T9 VMB_ZQ2 L8 VSS#T1 T9 VMB_ZQ3 L8 VSS#T1 T9 VMB_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R15 VSSQ#B9 D1 R235 VSSQ#B9 D1 R218 VSSQ#B9 D1 R24 VSSQ#B9 D1
EV@243/F_4 VSSQ#D1 D8 EV@243/F_4 VSSQ#D1 D8 EV@243/F_4 VSSQ#D1 D8 EV@243/F_4 VSSQ#D1 D8
VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
EV_SP@VRAM _DDR3 EV_SP@VRAM _DDR3 EV_SP@VRAM _DDR3 EV_SP@VRAM _DDR3

BOT Down TOP Down TOP Up BOT Up

Group-B1 VREF
Group-B0 VREF
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
B B
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

R216 R7 R215 R10

R17 R220 R222 R11 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4
EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4

VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4

VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2

R217 C459 R8 C7 R214 C456 R9 C8

R16 C12 R219 C462 R221 C465 R12 C9
EV@4.99K/F_4 EV@0.1u/10V_4 EV@4.99K/F_4 EV@0.1u/10V_4 EV@4.99K/F_4 EV@0.1u/10V_4 EV@4.99K/F_4 EV@0.1u/10V_4
EV@4.99K/F_4 EV@0.1u/10V_4 EV@4.99K/F_4 EV@0.1u/10V_4 EV@4.99K/F_4 EV@0.1u/10V_4 EV@4.99K/F_4 EV@0.1u/10V_4

Group-B0 decoupling CAP Group-B1 decoupling CAP

MEM_B0 CLK MEM_B1 CLK
+1.5V_GFX +1.5V_GFX

VMB_CLK1

VMB_CLK0 C13 C15 C16 C11 C19 C486 C14 C68 C25 C458 C23 C5 C6 C42 C457 VMB_CLK1#

VMB_CLK0# EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
R5 R6
EV@40.2/F_4 EV@40.2/F_4
R14 R13
EV@40.2/F_4 EV@40.2/F_4 +1.5V_GFX +1.5V_GFX

A C461 C20 C24 C26 C464 C463 C466 C460 C43 C21 C474 C477 C476 C488 C480 A
C4
C10 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@0.01u/25V_4
EV@0.01u/25V_4

+1.5V_GFX +1.5V_GFX

C28 C487 C455 C29 C3 C47 C18 C46 C48 C468 Quanta Computer Inc.
EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6
PROJECT : ZYV
Size Document Number Rev
C3A
Opal(Jet)_M2/VRAM_B
Date: Monday, April 28, 2014 Sheet 20 of 40
5 4 3 2 1
 1 2 3 4 5 6 7 8

BCD : AL002802002 C498 0.1u/10V_4

CRT DDS : AL002331000 Q23
+5V 3 1 CRTVDD5
IN OUT 2 CN3

16
GND
AP2331SA-7
6
CRT_R L7 BLM18BB470 CRT_R1 R33 0_6 CRT_R2 1 11 CRT_11
[4] CRT_R TP10
7
CRT_G L6 BLM18BB470 CRT_G1 R34 0_6 CRT_G2 2 12 DDCDAT_1
[4] CRT_G
8
CRT_B L8 BLM18BB470 CRT_B1 R35 0_6 CRT_B2 3 13 CRTHSYNC
[4] CRT_B
9
4 14 CRTVSYNC
R37 R38 R39 C105 C106 C107 C92 C91 C90 10
5 15 DDCCLK_1
150/F_4 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
A A
CRT CONN

17
+3V
C61 U15
CRTVDD5 1 16 CRT_VSYNC2 R32 *SHORT_4 CRTVSYNC C497 0.1u/10V_4 CRTVDD5
0.1u/10V_4 VCC_SYNC SYNC_OUT2 14 CRT_HSYNC2 R31 *SHORT_4 CRTHSYNC
7 SYNC_OUT1 C71 10p/50V_4 CRTVSYNC
C80 0.22u/25V_6 CRT_BYP 8 VCC_DDC
BYP 15 VSYNC C78 10p/50V_4 CRTHSYNC
SYNC_IN2 VSYNC [4]
2 13 HSYNC
+3V VCC_VIDEO SYNC_IN1 HSYNC [4] DDCCLK_1
C44 *10p/50V_4
C67
CRT_R2 3 10 DDCCLK C54 *10p/50V_4 DDCDAT_1
CRT_G2 4 VIDEO_1 DDC_IN1 11 DDCCLK [4]
0.1u/10V_4 DDCDATA
CRT_B2 VIDEO_2 DDC_IN2 DDCDATA [4]
5
VIDEO_3 9 DDCCLK_1 R27 2k/F_4 CRTVDD5
6 DDC_OUT1 12 DDCDAT_1 R28 2k/F_4
GND DDC_OUT2
CM2009-02QR

LCD CONNECTOR LCD Power

VIN +3V +5V BCD : AL002821000
GMT: AL005243001
+3V

C475 C479 C478 C481 U1

C454 C453
B 0.1u/10V_4_X7R 0.1u/10V_4_X7R 5 1 LCDVCC B
4.7u/25V_8 1000p/50V_4 1000p/50V_4 1000p/50V_4 IN OUT
2 C22 C17 C467 C469 C27
GND
4 3 *0.1u/10V_4 *2.2u/10V_6 0.1u/10V_4 0.01u/25V_4 22u/6.3V_8
IN EN

C30 G5243AT11U
1u/6.3V_4
APU_DISP_ON_R R22 *SHORT_4
EDP_HPD APU_DISP_ON [4]
[4] EDP_HPD
R21
R224
R213 *SHORT_6 LVDS CONN

G_5
R212 *SHORT_6 V_BLIGHT 100K_4
VIN 40
100K_4
39
38
LCDVCC R566 *SHORT_6 LCDVCC_R 37
36
35
34
CCD_PWR 33
+3V
CCD +3V R223 *SHORT_6
32
TPA_PWR 31 G_4
Touch panel +5V R226 *SHORT_6
30
29
R232 100K_4 EDP_AUX_C R234 *100K_4 R225 *SHORT_4 BRIGHT 28
EDP_AUX#_C [4] APU_DPST_PWM BL_ON 27
R231 *100K_4 R233 100K_4
EDP_HPD 26
25
EDP_AUX C484 0.1U/16V_4 EDP_AUX_C 24
[4] EDP_AUX EDP_AUX# EDP_AUX#_C 23
C483 0.1U/16V_4
[4] EDP_AUX# 22
EDP_TX1 C473 0.1U/16V_4 EDP_TX1_C 21
[4] EDP_TX1 EDP_TX1# EDP_TX1#_C 20
C472 0.1U/16V_4
[4] EDP_TX1# 19
C EDP_TX0 C471 0.1U/16V_4 EDP_TX0_C 18 C
[4] EDP_TX0 EDP_TX0# EDP_TX0#_C 17
R227 0_4 C470 0.1U/16V_4
[4] EDP_TX0# 16
L34 USBP1+_R 15
4 3 USBP1-_R USBP1-_R 14
[5] USBP1- 4 3 USBP1+_R 13
CCD [5] USBP1+
1
1 2
2
USBP3+_R 12
*MCM2012B900GBE/400mA/90ohm USBP3-_R 11
R228 0_4 10 G_1
TP67 TP_CLK 9
TP_DATA 8
I2C Touch TP66
7

[30] TOUCHPANEL_ON
TP65 TP_RST#
6
5 Backlight Control +3VPCU

USBP3-_R 4
[5] USBP3-
R229 *SHORT_4
USBP3+_R
I2C Touch 3
Touch panel [5] USBP3+
R230 *SHORT_4 Touch panel [5] BOARD_ID4 2 R1
1
G_0

*100K_4
CN2
+3VPCU +3V +3V LID591# LID591# [30]
LID591#,EC intrnal PU
D3
R4 1N4148WS

R567 R18 10K_4

BL_ON
10K_4 *10K_4

3
Power Switch. BL# 2 2
EC_FPBACK# [30]

3
Q4 Q1
2N7002K DTC144EUA

1
+3VPCU R19

1
D +3VPCU APU_BLEN_R 2 D
[4,30] APU_BLEN
R2 *SHORT_6 LID_POWER *SHORT_4 Q2
R3 AL009247000 -- BCD R20 2N7002K
10K_4 AL009132001 -- ANC

1
C1 1U/6.3V_4 AL008251000 -- YBT 100K_4
SW1
1

POWER_SW
NBSWON# 1 3
[30] NBSWON#
2 4 2 LID591#
1

Quanta Computer Inc.

2

C2 D2 MR1
5

0.1u/10V_4 *VPORT_6 YB8251ST23 D1

3

*VPORT_6
PROJECT : ZYV
2

Size Document Number Rev

1

C3A
CRT/LVDS/CAMERA/LID
Date: Monday, April 28, 2014 Sheet 21 of 40
1 2 3 4 5 6 7 8
 5 4 3 2 1

HDMI HDMI connector

CN7
*CM1225-04DE 20
C573 0.1u/10V_4 INT_HDMITX2P_C 5 6 INT_HDMITX2P_C INT_HDMITX2P_C 1 SHELL1
[4] INT_HDMITX2P INT_HDMITX2N_C 5 6 INT_HDMITX2N_C D2+
C572 0.1u/10V_4 4 7 2
[4] INT_HDMITX2N 4 7 INT_HDMITX2N_C D2 Shield
3 3
D GND_3/8 D2- D
C567 0.1u/10V_4 INT_HDMITX1P_C 2 9 INT_HDMITX1P_C INT_HDMITX1P_C 4
[4] INT_HDMITX1P INT_HDMITX1N_C 2 9 INT_HDMITX1N_C D1+
C563 0.1u/10V_4 1 10 5
[4] INT_HDMITX1N 1 10 INT_HDMITX1N_C D1 Shield
6
ESD2 INT_HDMITX0P_C 7 D1-
*CM1225-04DE 8 D0+
C558 0.1u/10V_4 INT_HDMITX0N_C 5 6 INT_HDMITX0N_C INT_HDMITX0N_C 9 D0 Shield 23
[4] INT_HDMITX0N INT_HDMITX0P_C 5 6 INT_HDMITX0P_C INT_HDMICLK+_C D0- GND
C557 0.1u/10V_4 4 7 10
[4] INT_HDMITX0P 4 7 CK+
3 11 22
C553 0.1u/10V_4 INT_HDMICLK+_C 2 GND_3/8 9 INT_HDMICLK+_C INT_HDMICLK-_C 12 CK Shield GND
[4] INT_HDMICLK+ INT_HDMICLK-_C 2 9 INT_HDMICLK-_C CK-
C552 0.1u/10V_4 1 10 13
[4] INT_HDMICLK- 1 10 +5V CE Remote
14
ESD1 HDMI_DDCCLK_MB 15 NC
HDMI_DDCDATA_MB 16 DDC CLK
R64 R66 R74 R78 R83 R85 R86 R93 Q27 17 DDC DATA
499_4 499_4 499_4 499_4 499_4 499_4 499_4 499_4 3 1 HDMI_5V 18 GND
IN OUT 2 19 +5V
GND HDMI_MB_HPD R60 *SHORT_4 HP_DET_CN HP DET 21
AP2331SA-7 C546 D21 SHELL2
*220p/50V_4 *EGA_4 HDMI connector

3
R61 D4 D6 D5
Q15 100K_4 *EGA_4 *EGA_4 *EGA_4
+5V R119 *SHORT_4 2
BCD : AL002802002
2N7002K DDS : AL002331000
R120

1
100K/F_4

C C

HDMI DDC Bus

HDMI-detect
+3V +5V

EMI
2

D13
RB501V-40
B +3V INT_HDMITX2P_C B
+5V
1

R92 *120/F_4

R117 R100 R102 INT_HDMITX2N_C

2

2.2K_4 2.2K_4 R101 10K_4

Q14 10K_4 INT_HDMITX1P_C
1 3 HDMI_DDCCLK_MB HDMI_HPD_R R103 *SHORT_4
[4] HDMI_DDCCLK_SW HDMI_HPD [4]
R84 *120/F_4

3
2N7002K
INT_HDMITX1N_C
Q17
2 INT_HDMITX0P_C
+3V +5V

3
R75 *120/F_4
2N7002K
2

Q16 INT_HDMITX0N_C

1
D26 HDMI_MB_HPD 2
RB501V-40 INT_HDMICLK+_C

2N7002K R65 *120/F_4

1

INT_HDMICLK-_C
R427 R417
2

2.2K_4 2.2K_4
Q30
1 3 HDMI_DDCDATA_MB
[4] HDMI_DDCDATA_SW
2N7002K

A A

Power trace tracking

Quanta Computer Inc.
[4,5,7,9,10,21,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38]
[21,25,26,28,32,36]
+3V
+5V
PROJECT : ZYV
Size Document Number Rev
C3A
HDMI (PS8101)
Date: Monday, April 28, 2014 Sheet 22 of 40
5 4 3 2 1
 5 4 3 2 1

LAN
XTAL2 C551 12p/50V_4

1
2
Y2

25MHZ +-30PPM
VDD10

3
4
XTAL1
C556 12p/50V_4
R349 2.49K/F_4 RSET
10 mils TP81
TP80 0116_B_change from 6.8p to 12p
TP79 +3V
D LANVCC D

R98 *10K/J_4

2
32
31
30
29
28
27
26
25
U23
3 1 PCIE_REQ_LAN#_R

AVDD33

AVDD10
CKXTAL2
CKXTAL1
LED0
RSET

LED1/GPO
LED2(LED1)
[5] PCIE_REQ_LAN#
33 Q12
GND
+3V
APU S0 *2N7002K LAN S0
Internal PU 10K R95 0/J_4

MDI_0+ 1 24 R390
MDI_0- MDIP0 REGOUT REGOUT +3V_S5
2 23 VDDREG/VDD33 1K_4
3 MDIN0 VDDREG(VDD33) 22
VDD10 MDI_1+ AVDD10(NC) DVDD10(NC) VDD10 PCIE_LAN_WAKE#_R
4 21 R97 *10K/J_4
MDI_1- 5 MDIP1 LANWAKEB 20 ISOLATEB
MDIN1 ISOLATEB

2
MDI_2+ 6 19
MDI_2- 7 MDIP2(NC) RTL8111GS-CG PERSTB 18 GPP_TX2N_LAN C568 0.1U/10V/X7R_4
PCIERST# [5,11,24,27]
MDIN2(NC) HSON GPP_TX2P_LAN PCIE_RXN2_LAN [3]
8 17 C560 0.1U/10V/X7R_4 R389
VDD10 AVDD10 HSOP PCIE_RXP2_LAN [3]
*15K_4 Q11
3 1 PCIE_LAN_WAKE#_R
[5,24] PCIE_LAN_WAKE#

AVDD33(NC)
*DTC144EUA

REFCLK_N
MDIN3(NC)
MDIP3(NC)

REFCLK_P
APU S5

CLKREQB
LANVCC LAN S5
+3V_S5 LANVCC Consider VCC33 may be connected to Main Internal PU 10K R388 0_4

HSIN
HSIP
Power or chipset/bios's GPO, the pull-low
resistor R14 can be NC only when Main Power
40 mils (Iout=1A) 40 mils (Iout=1A) or chipset/bios's GPO can ensure to drive the

9
10
11
12
13
14
15
16
R62 *SHORT_8 ISOLATEB pin to a voltage level < 0.8V at the
system state S1~S5.
MDI_3+ If the ISOLATEB pin can not be well-controlled to
C231 C230 MDI_3- a voltage level < 0.8V at S1~S5, the pull-low
0.1U/10V_4 10U/6.3V_6 LANVCC resistor R14 is needed to make sure the LAN
C chip is well isolated. C

CLK_PCIE_LANN [6]
CLK_PCIE_LANP [6]
PCIE_TXN2_LAN [3]
PCIE_TXP2_LAN [3]
PCIE_REQ_LAN#_R
Power trace tracking

[5,6,7,8,24,28,29,30,32,37] +3V_S5
,7,9,10,21,22,24,25,26,27,28,29,30,32,33,34,35,36,37,38] +3V

LANVCC
For RTL8111G(S) For RTL8111G(S)
RTL8111GS * Place 0.1uF CAP close to each * Place 1uF CAP close to each VDD10 pin-- 22 (reserve)
VDDREG/VDD33
40 mils (Iout=1A) REGOUT (SWR mode) support VDD10 pin-- 3, 8, 22, 30 VDD10
R394 *SHORT_8
40 mils (Iout=1A) 40 mils (Iout=1A)
C232 C200 C201 C203 40 mils (Iout=1A) C569 C576 L36 4.7uH

0.1U/10V_4 0.1U/10V_4 4.7U/6.3V_6 4.7U/6.3V_6 0.1U/10V_4 4.7U/6.3V_6

C240 C241 C235 C210 C211 C229 C236 C234

4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 0.1U/10V_4

For RTL8111GS
* Place 0.1uF,4.7uF CAP close to each Remove For Not Using SWR mode
VDD33 pin-- 11, 32 close to Pin23.

B
Tramsformer B

RJ45 Connector
U18

MDI_3+ R282 MDI_3+_C LAN_MX3+

Layout:All termination CN4
*SHORT_4 1 TD1+ MX1+ 24
signal should have 30
MDI_3- R284 *SHORT_4 MDI_3-_C 2 TD1- MX1- 23 LAN_MX3- mil trace
3 TCT1 MCT1 22 LANCT3

4 21 LAN_MX0+ 1
TCT2 MCT2 LAN_MX0- 2
MDI_2+ R287 *SHORT_4 MDI_2+_C 5 20 LAN_MX2+ LAN_MX1+ 3
TD2+ MX2+ LAN_MX2+ 4
MDI_2- R288 *SHORT_4 MDI_2-_C 6 19 LAN_MX2- LAN_MX2- 5
TD2- MX2- LAN_MX1- 6
LAN_MX3+ 7 9
LAN_MX3- 8 10
MDI_1+ R299 *SHORT_4 MDI_1+_C 7 18 LAN_MX1+
TD3+ MX3+
MDI_1- R302 *SHORT_4 MDI_1-_C 8 17 LAN_MX1-
TD3- MX3-
9 16
TCT3 MCT3
LAN_RJ45

10 15
TCT4 MCT4
MDI_0+ R308 *SHORT_4 MDI_0+_C 11 14 LAN_MX0+
TD4+ MX4+
A MDI_0- R316 *SHORT_4 MDI_0-_C 12 13 LAN_MX0- R48 A
TD4- MX4-
75/F_8
C188
0.01U/50V/X7R_4 D19
*BS4200N-C_1812
NS692417

R40
C506
*1M_8
220p/3KV_1808
Quanta Computer Inc.
PROJECT : ZYV
Size Document Number Rev
C3A
LAN (RTL8111GS)
Date: Monday, April 28, 2014 Sheet 23 of 40
5 4 3 2 1
 5 4 3 2 1

Mini Card 1 (MPC)

+WL_VDD
+WL_VDD +1.5V_WLAN
[30] BT_POWERON#

2
R437
Q33 10K_4 +3V +WL_VDD
DTC144EUA
CN8 R393 *SHORT_8 +WL_VDD
D 1 3 BT_PWRON R431 *SHORT_4 BT_PWRON_R 51 52 D
CL_RST1#_WLAN 49 Reserved +3.3V 50
TP87 Reserved GND
PLTRST# R433 *0_4 CL_DATA1_WLAN 47 48 C253 C577 C252 C250
[5,30] PLTRST# Reserved +1.5V
R434 *SHORT_4 CL_CLK1_WLAN 45 46 10u/6.3V_6 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
[6] CLK_LPC_DEBUG 43 Reserved LED_WPAN# 44
41 GND LED_WLAN# 42
+WL_VDD +3.3Vaux LED_WWAN#
Debug function need mount 39 40
R433 and R88(in page6 APU side) 37 +3.3Vaux GND 38 USBP7+_R R397 *SHORT_4
GND USB_D+ USBP7-_R USBP7+ [5]
35 36 R398 *SHORT_4
33 GND USB_D- 34 USBP7- [5]
[3] PCIE_TXP1 PETp0 GND WL_CLK_SDATA
31 32 R399 *0_4
[3] PCIE_TXN1 29 PETn0 SMB_DATA 30 WL_CLK_SCLK CLK_SDATA [5,9,10]
R400 *0_4
27 GND SMB_CLK 28 CLK_SCLK [5,9,10]
25 GND +1.5V 26
[3] PCIE_RXP1 23 PERp0 GND 24
[3] PCIE_RXN1 PERn0 +3.3Vaux
21 22
19 GND PERST# 20 RF_EN PCIERST# [5,11,23,27]
17 UIM_C4 W_DISABLE# 18 RF_EN [30]
R432 *SHORT_4 UIM_C8 GND
[6] CLK_PCIE_WLAN 15 16 A_LFRAME#_R
R438 *SHORT_4 R401 *SHORT_4
[6] CLK_PCIE_WLAN# CLK_PCIE_WLAN_C GND UIM_VPP A_LAD3_R LPC_LFRAME# [6,8,30]
13 14 R402 *SHORT_4 +1.5V
CLK_PCIE_WLAN#_C 11 REFCLK+ UIM_RESET 12 A_LAD2_R LPC_LAD3 [6,30]
R436 0_4 R403 *SHORT_4
REFCLK- UIM_CLK A_LAD1_R LPC_LAD2 [6,30]
9
GND UIM_DATA
10 R404 *SHORT_4
LPC_LAD1 [6,30] Debug
3 1 7 8 A_LAD0_R R405 *SHORT_4
C [5] PCIE_CLKREQ_WLAN# PCIE_CLKREQ_WLAN#_R 5 CLKREQ# UIM_PWR 6 LPC_LAD0 [6,30] +1.5V_WLAN C
R94 *0_6
*DTC144EUA 3 Reserved +1.5V 4

GND

GND
Q31 R439 1 Reserved GND 2 C245
WAKE# +3.3V C578 C251
*10K_4
MINI-CARD1 *1000p/50V_4 *0.1u/10V_4 *10u/6.3V_8
2

53

54
+WL_VDD
2

R435
Q32 *10K_4
*DTC144EUA
3 1 PCIE_WAKE#_R
[5,23] PCIE_LAN_WAKE#
R430 *0_4

TPM (TPM)
TPM_VDD

TPM_VDD R383 TPM@2.2_6

+3V
B B
R581 TPM_I@0_4 TPM_VDD
R582 TPM_N@0_4 TPM_VSB C571 C565 C574 C564 C705
TPM@10u/6.3V_6 TPM@0.1U/10V_4 TPM@0.1U/10V_4 TPM@0.1U/10V_4 TPM@0.1U/10V_4
24
19
10

U7
5

R572
VSB
VDD3
VDD2
VDD1

*TPM_N@10K_4

R68 TPM_I@4.7K_4
LPC_LAD3 17 7 R69 *TPM_I@4.7K_4 TPM_VSB
LPC_LAD2 20 LAD3 PP 6 R70 *TPM_I@20K_4 R579 *TPM_N@0_4
LAD2/SPI_IRQ GPX/GPIO2 TPM_VDD +3VSUS
LPC_LAD1 23 2 R580 TPM_N@0_4
LAD1/MOSI GPIO1 +3V_S5
LPC_LAD0 26 TP97
LAD0/MISO
LPC_LFRAME# 22
LFRAME/SCS GPIO0/XOR_OUT
1 TP98 SLB9665 PIN9 NC
[6,30] SERIRQ R575 TPM@0_4 27 9 R391 TPM_I@0_4 PLTRST#_R C704 C575
R576 TPM@0_4 21 SERIRQ GPIO3/BADD 8 R574 *TPM_N@10K_4 TPM_N@10u/6.3V_6
[6] PCLK_TPM LCLK/SCLK TEST TPM_N@0.1U/10V_4
C249 *TPM_I@10p/50V_4 15 3
PLTRST#_R 16 CLKRUN/GPIO04 NC1 12
R578 TPM_N@0_4 28 LRESET/SPI_RST NC2 13
[6,28,30] LPC_CLKRUN# LPCPD NC3 14
PLTRST# D31 TPM@RB500V-40 NC4
GND1
GND2
GND3
GND4

A A

[5,28] LPCPD# D32 TPM_N@RB500V-40 0114_B_change

SP@NPCT620/650_TSSOP28
Quanta Computer Inc.
4
11
18
25

AL000650K00 : NPCT650AA0WX
AL009655K01 : SNI SLB9655TT1.2
PROJECT : ZYV
Size Document Number Rev
0114_B_change C3A
Mini-Card / TPM
Date: Monday, April 28, 2014 Sheet 24 of 40
5 4 3 2 1
 5 4 3 2 1

Codec(ADO) Grounding circuit(ADO)

HP-R2
+3VRTC +3VPCU
HP-L2

LINE1-VREFO-L PIN1, PIN4, PIN3, PIN6 are ANALOG R203 R202

LINE1-VREFO-R +1.5V
Q37
placed close to codec
MIC2-VREFO *100K_4 100K_4
1 6 SLEEVE
R205
CODEC_VREF C662 2.2U/6.3V_4 2
ADOGND
INT_AMIC-VREFO C664 10u/6.3V_4
D ADOGND D

3
+5VA

C426

C421
4 3 RING2 *100K_4
R533 100K_4
C428 5
2 10K_4 PCH_AZ_CODEC_RST#

1u/10V_4
10u/6.3V_4
R211
1u/10V_4 C663 ADOGND Q21
C659 2N7002DW PJA138K
0.1u/10V_4 10u/6.3V_4 C449
*1u/10V_4

1
+AZA_VDD
Place next to pin 26

36

35

34

33

32

31

30

29

28

27

26

25
+1.5VA
U29
ADOGND

CPVEE

HP-OUT-L

LINE1-VREFO-L

MIC2-VREFO

LDO1-CAP

AVDD1

AVSS1
CPVDD

CBN

HP-OUT-R

LINE1-VREFO-R

VREF
C669
C665
10u/6.3V_4 0.1u/10V_4
ADOGND 37
CBP LINE2-L
24 LINE2-L
T2
D-Mic +3V
+3V

C681 10u/6.3V_4
38 23 LINE2-R T1 C682 0.1u/10V_4 R562
AVSS2 LINE2-R
ADOGND CO-LAYOUT U11
*0_4
Place next to pin 40 C668 10u/6.3V_4 39 22 LINE1-L
LDO2-CAP LINE1-L 6 1
40 21 VDD GND
Analog AVDD2 LINE1-R
LINE1-R
DMIC_DAT_L R564 *SHORT_4DMIC_DAT_C 5 2
+5V_PVDD DATA CS
Digital +5V L32
PBY160808T-600Y-N(60,3A)
41
PVDD1 NC
20
close to codec DMIC_CLK_L R563 *SHORT_4DMIC_CLK_C 4 3
L_SPK+ 42 19 C667 10u/6.3V_4 CLK GND R561
SPK-L+ MIC1-CAP ADOGND
C441 C431 D-MIC

10u/6.3V_4 0.1u/10V_4
L_SPK- 43
SPK-L-
ALC283 MIC2-R/SLEEVE
18 SLEEVE trace width of SLEEVE & RING2
0_4

R_SPK- 44 17 RING2 are required at least 40mil and

SPK-R- MIC2-L/RING2 its length should be asshort as possible
near Codec R_SPK+ 45 16
SPK-R+ MONO-OUT
46 15 CODEC_JDREF R540 20K/F_4
PVDD2 JDREF ADOGND
Low is power down +3V
GPIO0/DMIC-DATA

amplifier output PD# 47 GPIO1/DMIC-CLK 14

C C433 PDB Sense B C
48 13 SENSEA R546 39.2K/F_4 HP_JD# CN19
SDATA-OUT
TP94 SPDIFO/GPIO2 Sense A DMIC_DAT_L DMIC_DATA_R

LDO3-CAP
0.1u/10V_4 *0_4 R560

SDATA-IN
4

DVDD-IO

PCBEEP
RESETB
BIT-CLK
Placement near Audio Codec 3
DVDD

49

SYNC
DVSS

1
DGND 26
Analog D28
15
near Codec
Digital *DMIC
1

10

11

12
*TVS/6pF_4

2
DMIC_CLK

C670

DMIC_CLK_L *0_4 R559 DMIC_CLK_R

1.6Vrms

1
R204 *SHORT_6 +AZA_VDD D29
+3V BEEP_1
10u/6.3V_4

PCBEEP C672 0.1u/10V_4 R557 47K_4 D18 1N4148WS

SPKR [5]
C445 C675 R555 D17 1N4148WS *TVS/6pF_4
PCBEEP_EC [30]

2
C446 4.7K_4
0.1u/10V_4 10u/6.3V_4 100p/50V_4

+3V +1.5V
close to codec

Place next to pin 1

PCH_AZ_CODEC_RST#

DMIC_DAT_L
PCH_AZ_CODEC_RST#

PCH_AZ_CODEC_SYNC
[5]

[5]
R556 *0_4
HEADPHONE/MIC/LINE combo (AMP)
Tied at one point only under DMIC_CLK_L R552 22_4 DVDD_IO R558 *SHORT_4
the codec or near the codec
R549 *0_4 C678 C677 ACZ_SDIN R551 33_4 C673 C676
MIC2-VREFO R183 2.2K/J_4 FB1/FB2(SLEEVE/RING2) should choose DC resistance (Rdc) < 30m-ohm
R532 *0_4 *10p/50V_4 10p/50V_4
PCH_AZ_CODEC_SDIN0 [5]
R200 2.2K/J_4 to get the best audio performance for HP crosstalk
R181 *0_4 PCH_AZ_CODEC_BITCLK [5] 0.1u/10V_4 10u/6.3V_4 Combo Jack
R531 *0_4 SLEEVE L28 BLM15AG121SS1/0.5A/120ohm_4 SLEEVE_R
R182 *0_4 reserve for EMI C671 *22p/50V_4 CN18
R186 *SHORT_4 RING2 L31 BLM15AG121SS1/0.5A/120ohm_4 RING2_R 4
C448 *1000p/50V_4
need check with PCH_AZ_CODEC_SDOUT [5] Place next to pin 9 3
HP-L2 HP-L3 R198 56/F_4 HP-L4 1
C661 *0.1u/10V_4 DMIC vender L30 BLM15AG121SS1/0.5A/120ohm_4
HP-R2 HP-R3 R185 56/F_4 HP-R4 2
B B
L29 BLM15AG121SS1/0.5A/120ohm_4 5
ADOGND HP_JD# 6 7

1
Cap need near AVDD1 and AVDD2 D15
SIT_2SJ3080-002111F
power source input LINE1-L C430 4.7U/6.3V_6 C419 C444 C432 C427
*MLVS0402K11
LINE1-VREFO-L R197 4.7K_4 100p/50V_4 100p/50V_4 100p/50V_4 100p/50V_4

2
ADOGND
LINE1-VREFO-R R184 4.7K_4

LINE1-R C429 4.7U/6.3V_6 ADOGND ADOGND

Codec PWR 5V(ADO) Mute(ADO) Codec PWR 1.5V(ADO)

+AZA_VDD +1.5V

R554
1K_4
2

DIGITAL ANALOG
L33 HCB2012KF220T60/6A/22ohm_8 PD# D30 *RB500V-40 3 1 PCH_AZ_CODEC_RST#
+5V +5VA +1.5VA
U30 R553
3 4 *10K/J_4 Q22 DIGITAL ANALOG
IN OUT *PJA138K
2
GND C447 C674 D16 RB500V-40 L27 HCB1608KF-121T30_3A
AMP_MUTE# [30] +1.5V
1 5 R550 *29.4K/F_4
SHDN SET *10u/6.3V_6 *0.1u/10V_4 C412
*G923-330T1UF
C679 C680 R548 1U/6.3V_4
A *10K/F_4 A
*0.1u/10V_4 *10u/6.3V_6 ADOGND
Internal Speaker
R201 *0_4

close pin3
ADOGND 40mil for each signal CN20
R_SPK+ R547 0_6 R_SPK+_1
R_SPK- R541 0_6 R_SPK-_1 1
L_SPK- R539 0_6 L_SPK-_1 2
L_SPK+ R538 0_6 L_SPK+_1 3 5
4 6
SPK_CONN_4P Quanta Computer Inc.
C452 C451 C450 C683

1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4

PROJECT : ZYV
Size Document Number Rev
C3A
Place these EMI components next to codec
ALC283 / HP / SPK / DMIC
Date: Monday, April 28, 2014 Sheet 25 of 40
5 4 3 2 1
 5 4 3 2 1

2.5" SATA HDD (HDD)

D SATA_CONN D

Reference design "DNI" RD_POWER 12 10

11 9 SATA_TXP0_C C666 0.01u/25V_4 SATA_TXP0_PS_R
8 SATA_TXN0_C C660 0.01u/25V_4 SATA_TXN0_PS_R
A_EQ1 R494 *RD@4.7K/J_4 Equalization level setting for Channel x(x=A/B),internally 7
A_EQ2 R493 *RD@4.7K/J_4 pulled down 6 SATA_RXN0_C C657 0.01u/25V_4 SATA_RXN0_PS_R +5V
[x_EQ2, x_EQ1] == 5 SATA_RXP0_C C656 0.01u/25V_4 SATA_RXP0_PS_R
EN C616 *RD@0.1u/10V_4 R511 *RD@4.7K/J_4 B_EQ1 R510 *RD@4.7K/J_4 L/L: for channel loss up to 7.4dB 4
B_EQ2 R495 *RD@4.7K/J_4 L/H: for channel loss up to 14.4dB 3 60mil +5V_HDD R175 *SHORT_0805
H/L: for channel loss up to 11.2dB 2
H/H: for channel loss up to 5dB 1
C418 C417 C422 C425 C413 C652
CN17 +
De-emphasis level setting for Channel x(x=A/B), internally 0.01u/25V_4 0.01u/25V_4 *0.1u/10V_4 *0.1u/10V_4 10u/6.3V_6 100u/6.3V_3528
A_DE R443 *RD@4.7K/J_4 pulled down
B_DE R442 *RD@4.7K/J_4 [x_DE] ==
L: -3.5 dB
2013/11/29 H: -1.5dB
FEA suggest A-SMT use defalut setting (DNI)

C C

RD_POWER

R158 *RD@SHORT_4 RD_POWER

+1.5V
B_EQ1
A_EQ2
A_EQ1
B_EQ2
C407 C406
RD@10u/6.3V_6 RD@0.1u/10V_4 C642
RD@0.1u/10V_4
21

20
19
18
17
16

U27
VDD
B_EQ1
A_EQ2
A_EQ1
B_EQ2

GND
22 25

[6] SATA_TXP0
C628 RD@0.01u/25V_4 SATA_TXP0C 1
GND GND
15 SATA_TXP0_PS C700 RD@0.01u/25V_4 SATA_TXP0_PS_R
SATA ODD Connector
C625 RD@0.01u/25V_4 SATA_TXN0C 2 A_INp A_OUTp 14 SATA_TXN0_PS C701 RD@0.01u/25V_4 SATA_TXN0_PS_R
[6] SATA_TXN0 3 A_INn A_OUTn 13
4 GND GND 12
C622 RD@0.01u/25V_4 SATA_RXN0C 5 B_OUTn B_INn 11 SATA_RXN0_PS C703 RD@0.01u/25V_4 SATA_RXN0_PS_R CN9
[6] SATA_RXN0 B_OUTp B_INp
B [6] SATA_RXP0 C619 RD@0.01u/25V_4 SATA_RXP0C SATA_RXP0_PS C702 RD@0.01u/25V_4 SATA_RXP0_PS_R 14 B
23 GND14
REXT
B_DE
A_DE
VDD

GND 24 1
EN

GND 0114_B_change GND1 2 SATA_TXP1_C C607 0.01u/25V_4

RXP SATA_TXP1 [6]
RD_POWER 3 SATA_TXN1_C C604 0.01u/25V_4
RD@PS8527A SATA_TXN1 [6]
6
7
8
9
10

RXN 4
GND2 5 SATA_RXN1_C C596 0.01u/25V_4
TXN 6 SATA_RXP1_C SATA_RXN1 [6]
C595 0.01u/25V_4
TXP SATA_RXP1 [6]
7
B_DE
A_DE

C615 GND3 +5V_ODD +5V

EN

RD@0.1u/10V_4
8 SATA_DP R426 *1K_4
DP 9 R440
R444 +5V 10 *SHORT_0805
+5V 11 C583 C582 C589 C588 C590 C581

+
RD@10K_4 RSVD 12
GND 13 0.01u/25V_4 0.01u/25V_4 *0.1u/10V_4 *0.1u/10V_4 10u/6.3V_6 *100u/6.3V_3528
0114_B_change GND
15
GND15
C185Q2-11311-L
EC_ODD_EJ [30]

R424 10K_4 +3V

A A

SATA_TXP0 R482 NRD@0/J_4 SATA_TXP0_R R484 NRD@0/J_4 SATA_TXP0_PS_R

SATA_TXN0 R467 NRD@0/J_4 SATA_TXN0_R R476 NRD@0/J_4 SATA_TXN0_PS_R
Quanta Computer Inc.
SATA_RXN0 SATA_RXN0_R R465 SATA_RXN0_PS_R
SATA_RXP0
R462
R453
NRD@0/J_4
NRD@0/J_4 SATA_RXP0_R R455
NRD@0/J_4
NRD@0/J_4 SATA_RXP0_PS_R PROJECT : ZYV
Size Document Number Rev
C3A
SATA HDD / ODD
Date: Monday, April 28, 2014 Sheet 26 of 40
5 4 3 2 1
 5 4 3 2 1

USB 3.0 Connector R140 0_4

HOLE(OTH)
L22
2 1 USBP9-_R
[5] USBP9- 3 2 1 4 USBP9+_R
[5] USBP9+ 3 4 HOLE16 HOLE18 HOLE17 HOLE19
*MCM2012B900GBE/400mA/90ohm USBPWR1 EV@MBZRQ001010_GPU EV@MBZRQ001010_GPU EV@MBZRQ001010_GPU FBFM8001010_MINI PCIE
R142 0_4 CN10
USB3.0 CONN USBP9-_R RV3 1 2 *EGA_4
1
1 VBUS USBP9+_R
2 RV4 1 2 *EGA_4
2 D-
C374 *1.6P/50V_4 3

1
4 3 D+ USB30_RX1-_R RV6 1 2 *EGA_4
R148 *SHORT_4 USB30_RX1-_R 5 4 GND
[5] USB30_RX1- USB30_RX1+_R 6 5 SSRX- USB30_RX1+_R RV5 1 2 *EGA_4
R146 *SHORT_4
[5] USB30_RX1+ 6 SSRX+
7
D
C364 *1.6P/50V_4 8 7 GND D
9 8 SSTX- USB30_TX1-_R RV2 1 2 *EGA_4
9 SSTX+ HOLE14 HOLE7 HOLE11 HOLE8 HOLE9 HOLE4 HOLE1 HOLE5

13
12
11
10
C317 0.1u/10V_4 USB30_TX1-_C R134 *SHORT_4 USB30_TX1-_R USB30_TX1+_R RV1 1 2 *EGA_4 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2
[5] USB30_TX1- USB30_TX1+_C USB30_TX1+_R
C311 0.1u/10V_4 R129 *SHORT_4 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6
[5] USB30_TX1+

13
12
11
10
8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4 9 4 9 4 9 4
C318 C306
*1.6P/50V_4 *1.6P/50V_4

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3
HOLE13 HOLE2 HOLE12
HOLE10 HOLE6 HOLE15 HOLE3 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2
*CPU-BKT *H-C315D110P2 *hg-tc236bc315d110p2 *h-c110d110n 7 6 7 6 7 6
7 6 8 5 8 5 8 5
8 5 9 4 9 4 9 4
9 4

1
2
3
4

1
2
3

1
2
3

1
2
3
R159 0_4

1
2
3

1
L25
2 1 USBP8-_R
[5] USBP8- 3 2 1 4 USBP8+_R
[5] USBP8+ 3 4
*MCM2012B900GBE/400mA/90ohm USBPWR1
R170 0_4 CN11
USB3.0 CONN USBP8-_R RV9 1 2 *EGA_4
1
1 VBUS

Card Reader and POWER LED DB

2 USBP8+_R RV101 2 *EGA_4
3 2 D-
C411 *1.6P/50V_4
4 3 D+ USB30_RX0-_R RV121 2 *EGA_4
R176 *SHORT_4 USB30_RX0-_R 5 4 GND
[5] USB30_RX0- USB30_RX0+_R 6 5 SSRX- USB30_RX0+_R RV111 2 *EGA_4
R173 *SHORT_4
[5] USB30_RX0+ 6 SSRX+
C 7 C
C408 *1.6P/50V_4 8 7 GND
9 8 SSTX- USB30_TX0-_R RV8 1 2 *EGA_4
9 SSTX+

13
12
11
10
C397 0.1u/10V_4 USB30_TX0-_C R151 *SHORT_4 USB30_TX0-_R USB30_TX0+_R RV7 1 2 *EGA_4
[5] USB30_TX0-
C396 0.1u/10V_4 USB30_TX0+_C R150 *SHORT_4 USB30_TX0+_R
[5] USB30_TX0+
13
12
11
10
C404 C403
*1.6P/50V_4 *1.6P/50V_4

CN14
LED_POWER +3VPCU 1 13
Cardreader_POWER +3V 2 14
3
POWER_BLUE [30] PWRLED# 4
SLEEP_AMBER [30] SUSLED# 5
FULLY_BLUE [30] BATLED0# 6
CHARGING_AMBER [30] BATLED1# 7
[5,11,23,24] PCIERST# 8
9
[5] USBP6- 10
+5V_S5 [5] USBP6+ 11
0114_B_change 12

IO_DB

C699 C614 U25 USBPWR1

*10U/6.3V_8 1u/6.3V_4 Close USB3.0
5 1
IN OUT
2
GND
USBON# 4 3 C592 C621 C620 C698
B [30] USBON# /EN /OC B
470P/50V_4 0.1u/10V_4 100U/6.3V_1206 10U/6.3V_8
0114_B_change
G524B2T11U
[5] USB_OC1#

G524B2T11U: Enable: Low Active /2.5A

USB DB
USBPWR2
CN16
1
2 13
3
4
5
6
D/B USB Port [5] USBP5- 7
[5] USBP5+ 8
9
D/B USB Port [5] USBP0- 10
[5] USBP0+ 11 14
12
USB_DB

+5V_S5

A A

1u/6.3V_4 U10 USBPWR2

C415
5 1
IN OUT
2
GND C424 C423 C658
USBON# 4 3
/EN /OC 470P/50V_4 0.1u/10V_4 *100U/6.3V_1206

G524B2T11U Quanta Computer Inc.

[5] USB_OC2#
PROJECT : ZYV
Size Document Number Rev
G524B2T11U: Enable: Low Active /2.5A C3A
USB/DB/Card Reader
Date: Monday, April 28, 2014 Sheet 27 of 40
5 4 3 2 1
 5 4 3 2 1

KEYBOARD (KBC) CPU FAN CTRL(THM)

CN13
<EMI>
1 MX0
MX0 [30]
2 MX1 MX4 1 2
3 MX1 [30] 3 4 +3VPCU
MX2 MX5 CP1
4 MX2 [30] 5 6
MX3 MX6 *220P_8P4R
MX3 [30]
5 MX4 MX7 7 8 +5V +5V
6 MX4 [30] 1 2 +3V +3V
MX5 MY3 RP1
D MX5 [30] D
7 MX6 MY2 3 4 CP3 10 1 MX0
8 MX6 [30] 5 6 9 2
MX7 MY1 *220P_8P4R MX7 MX1 R328 *SHORT_6 C536 10U/6.3V_8
9 MX7 [30] 7 8 8 3
MY17 MY0 MX6 MX2
MY17 [30] R347 R327 R326
10 MY16 MY7 1 2 MX5 7 4 MX3 C540 0.1u/10V_4
11 MY16 [30] 3 4 6 5
MY15 MY6 CP4 MX4
MY15 [30] 10K_4 10K_4 10K_4
12 MY14 MY5 5 6 *220P_8P4R
13 MY14 [30] 7 8
MY13 MY4 *10K_10P8R R346 *0_4
14 MY13 [30] 1 2 [4] THERM_ALERT#
MY12 MY11 CN6
MY12 [30] +5V_FANVCC
15 MY11 MY10 3 4 CP5 FANSIG [30]
MY11 [30] 4 6

2
16 MY10 MY9 5 6 *220P_8P4R
MY10 [30] 3 5
17 MY9 MY8 7 8
18 MY9 [30] 1 2 1 3 FAN_PWM_CN 2
MY8 MX0 CPUFAN#
19 MY8 [30] 3 4 [30] CPUFAN# 1
MY7 MX1 CP2 Q26 METR3904-G
MY7 [30]
20 MY6 MX2 5 6 *220P_8P4R EC PWM SIGNAL FAN CONN
21 MY6 [30] 7 8
MY5 MX3
MY5 [30]
22 MY4 MY15 1 2 C539 C538
23 MY4 [30] 3 4
MY3 MY14 CP6 *220p/50V_4 *220p/50V_4
24 MY3 [30] 5 6
MY2 MY13 *220P_8P4R
MY2 [30]
25 MY1 MY12 7 8
26 MY1 [30]
MY0
MY0 [30]

27 For EMI
28
C C

KB CONN

KB_BL LED (KBC)

+5V +5V LPC Power down
C414 *KBL@2.2u/10V_6 +3V_S5
1

R180
Q20
KBL@10K/J_4
KBL@AO3413
2

CN15
3

R55 R54
3

2 +5V_KB R512 *KBL@SHORT_4 +5V_KB_R 1

[30] KB_BL_LED 2 5 *100K_4 22K/F_4
Q19 C654 C651 3 6
4 LPCPD#
KBL@DTC144EUA LPCPD# [5,24]
1

KBL@4.7u/6.3V_6 KBL@0.01u/25V_4

3
B KBL@KB_backlight B

Q8
SYS_PWRGD_Q 2
EMI Stitching cap

3
+1.5V_SUS
*2N7002K

1
2 Q9
[5,8] SYS_PWRGD
C256 C279 C402 C401 C689 C691 C692 *FDV301N
1000p/50V_4 1000p/50V_4 1000p/50V_4 1000p/50V_4 *1000p/50V_4 *1000p/50V_4 *1000p/50V_4
VIN

3
+1.5V_SUS
+SMDDR_VREF Q7
C398 C31 C174 C202 2
[6,24,30] LPC_CLKRUN#
*0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4

C693 C694 C695 C697 C696 *2N7002K

*1000p/50V_4 *1000p/50V_4 *1000p/50V_4 *1000p/50V_4 *1000p/50V_4

1
+3VPCU +VDDNB_CORE +VDD_CORE +VDDNB_CORE +VGPU_CORE
A A
+5V +SMDDR_VREF

C348 C420 C405 C136

*0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 Quanta Computer Inc.
C687
*1000p/50V_4
C686 C690
*1000p/50V_4 *1000p/50V_4 +VDD_CORE +PCIE_VDDC_GFX PROJECT : ZYV
Size Document Number Rev
C3A
KB/FAN/EMI
Date: Monday, April 28, 2014 Sheet 28 of 40
5 4 3 2 1
 5 4 3 2 1

I2C translator need check P/N (F/W REV) 0116_B_change from I2C_PWR to TP_PWR

U26 MCU_65211-24LTXI TP_PWR I2C_PWR

C632 1U/10V_4 12 3
VCCD VSSD1 13
VSSD2 16 R585 R584
I2C_PWR VSSD3 17 *0_4 0_4
VSSA 25
R446 *0_4 EPAD 0212_C_change
D +3V_S5 D
+3V R445 0_4 24 15
VDDD VBUS
0114_B_change C617 C618 CY7C65211-24TXI C635
0212_C_Chabge C636
4.7U/6.3V_6 0.1u/10V_4 4.7U/6.3V_6 0.1u/10V_4
18
GPIO_0

I2C_INT# 4
5 GPIO_8
6 GPIO_9 10 USBP2+_R R461 *SHORT_4
GPIO_10 USBDP 11 USBP2-_R USBP2+ [5]
R456 2.2K_4 R473 *SHORT_4
1 USBDM USBP2- [5]
I2C_PWR R466 2.2K_4
20 SCB_0_GPIO_6
I2C_SCL 21 SCB_0_GPIO_2 7
I2C_SDA 22 SCB_0_GPIO_3 GPIO_11 19
23 SCB_0_GPIO_4 GPIO_1 8 0114_B_Del R454, R474
2 SCB_0_GPIO_5 SUSPEND 9
SCB_0_GPIO_7 WAKEUP 14
XRES

C C

TOUCH PAD(TPD) TP_PWR

TP_PWR I2C_PWR

TP_PWR I2C_PWR B: MASTE(EN)

A: SLAVE R179 R171
Q18 2.2K_4 2.2K_4
R152 R153 C399 C400 5
*2.2K_4 *2.2K_4 *0.1u/10V_4 *0.1u/10V_4
R479 R490 U9 I2C_SCL 3 4 I2C_CL
2

10K_4 10K_4 1 8
VCC(A) VCC(B) C712
I2C_INT#_TP 3 1 I2C_INT# I2C_SCL_TP 2 7 I2C_SCL 2 150P/50V_4
Q34 SCLA SCLB
2N7002K I2C_SDA_TP 3 6 I2C_SDA I2C_SDA 6 1 I2C_DA
SDAA SDAB
4 5
R160 *0_4 GND EN 2N7002KDW
*PCA9517ADP
0114_B_change R178 *0_4
R457 *0_4 R172 *0_4
B R463 *0_4 B
0114_B_change
0114_B_change

R587 *0_4
TP_PWR
Q40

+3V_S5 R583 0_4 1 3

+3VSUS R166 *0_4
C706 AO3413
+ C639

2
*0.1U/10V_4 C707 0.1u/10V_4
TP_PWR 0.22u/25V_6
R586
[30] PTP_PWR_EN#
10K/J_4
R154 R155 C708
*1000p/50V_4
10K_4 10K_4 CN12
0211_C_Add EC GPIO to control PTP PWR MOS 1 10
R165 0_4 TPCLK_CN 2 9
[30] TPCLK TPDATA_CN
R164 0_4 3
A
[30] TPDATA 4 A
I2C_DA R491 0_4 CLK_SDATA_R R157 *SHORT_4 I2C_DATA 5
C638 C637 I2C_CL R489 0_4 CLK_SCLK_R R156 *SHORT_4 I2C_CLK 6
7
*10p/50V_4 *10p/50V_4
I2C_SDA_TP R481 *0_4
8 Quanta Computer Inc.
I2C_SCL_TP
I2C_INT#_TP
R480
R161
*0_4
0_4
C711 TP CONN
PROJECT : ZYV
R163 0_4 *10p/50V_4 0304_C Size Document Number Rev
[30] TPD_INT# reserve C711 C3A
[30] SENSOR_OFF 0114_B_change I2C translator/TP
Date: Monday, April 28, 2014 Sheet 29 of 40
5 4 3 2 1
 5 4 3 2 1

+3VPCU

S5_ON R113 10K_4

L39 BLM15AG121SS1/0.5A/120ohm_4 +A3VPCU +3VPCU_ECPLL L37 BLM15AG121SS1/0.5A/120ohm_4 BOARD_ID R565 10K_4 BOARD_ID: PU 17'', PD 14''
EC(KBC) C594 C584
+3VPCU_EC

(For PLL Power)

0.1u/10V_4
0.1u/10V_4
ECAGND 12 mils +3V_S5
+3VRTC HWPG
R149 2.2_6 SIO_EXT_SMI# R133 *10K_4
1 2
12 mils +3VPCU_EC SUSC# [5] SIO_EXT_SCI#
+3VPCU C273 R144 *10K_4
SUSB# [5,8]
C377 C602 C587 C598 C586 C585 0.1u/10V_4 TP48
+3VPCU_EC and +3V_RTC TP49
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 +3V
minimum trace width 12mils. TP24
KBRST# R118 10K_4
D USB_CHG_MODE PTP_PWR_EN# [29] D
TP34 SERIRQ R123 *10K_4
R125 *SHORT_6 +3V_EC USB_BC_ON TP37
+3V
LPC_CLKRUN# [6,24,28]
C305 R368 *8.2K MAINON R139 100K_4
+3V
VRON R145 *100K_4 VRON : Power side has PD 100K
0.1u/10V_4 PLTRST# R143 100K_4

114
121

127
11
26
50
92

74

84
83
82

19
20

99
98
97
96
93
3
U8
10 110

VCC

AVCC
VBAT

EGCLK/WUI27/GPE3(Dn)
EGCS#/WUI26/GPE2(Dn)
EGAD/WUI25/GPE1(Dn)

L80HLAT/BAO/WUI24/GPE0(Dn)
L80LLAT/WUI7/GPE7(Up)

CLKRUN#/WUI16/GPH0/ID0(Dn)
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY

VSTBY

WUI42/GPH6/ID6(Dn)
WUI41/GPH5/ID5(Dn)
WUI40/GPH4/ID4(Dn)
WUI19/GPH3/ID3(Dn)
[6,24] LPC_LAD0 LAD0/GPM0(X) SMCLK0/GPB3(X) MBCLK [31]
9 111
[6,24] LPC_LAD1 LAD1/GPM1(X) SMDAT0/GPB4(X) MBDATA [31]
8 115
[6,24] LPC_LAD2 LAD2/GPM2(X) SMCLK1/GPC1(X) 2ND_MBCLK [4,12]
7 116
[6,24] LPC_LAD3 LAD3/GPM3(X) SMDAT1/GPC2(X) 2ND_MBDATA [4,12]
22 117 TP27
+3VPCU [5,24] PLTRST# LPCRST#/WUI4/GPD2(Up) PECI/SMCLK2/WUI22/GPF6(Up) SM BUS PU(KBC)

SM BUS
13 118 +3VPCU
[6] CLK_PCI_775 LPCCLK/GPM4(X) SMDAT2/WUI23/GPF7(Up) EC_FPBACK# [21]
6
[6,8,24] LPC_LFRAME# LFRAME#/GPM5(X) BOARD_ID
85 MBCLK R106 4.7K_4
PROCHOT_EC 17 PS2CLK0/TMB0/CEC/GPF0(Up) 86 MBDATA R105 4.7K_4
LPCPD#/WUI6/GPE6(Dn) PS2DAT0/TMB1/GPF1(Up) LID591# [21]
2

89
126 PS2CLK2/WUI20/GPF4(Up) 90 TPCLK [29]
D14
[5] SIO_A20GATE GA20/GPB5(X) PS2DAT2/WUI21/GPF5(Up) TPDATA [29]

PS/2
R141 SDMK0340L-7-F 5
[6,24] SERIRQ SERIRQ/GPM6(X)
100K_4 15 +3V_S5
[5] SIO_EXT_SMI# 23 ECSMI#/GPD4(Up)
[5] SIO_EXT_SCI# ECSCI#/GPD3(Up) LPC
1

WRST# 14 GPIO 2ND_MBCLK R52 4.7K_4

R121 *SHORT_4 4 WRST# 2ND_MBDATA R51 4.7K_4
[5] KBRST# HWPG_1.05V_EC# KBRST#/GPB6(X)
TP44 16
C335 PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)/SMCLK2ALT
1u/6.3V_4 24
PWM0/GPA0(Up) PWRLED# [27]
25

[4,21] APU_BLEN
[32,33] SUSON
R116 *SHORT_4 119
123 CRX0/GPC0(Dn)
CTX0/TMA0/GPB2(Dn) CIR
IT8587 PWM1/GPA1(Up)
PWM2/GPA2(Up)
PWM3/GPA3(Up)
PWM4/GPA4(Up)
28
29
30 TP56
BATLED1#
SUSLED#
BATLED0#
[27]
[27]
[27]
31 CPUFAN2#
PWM5/GPA5(Up) TP55

CLK_PCI_775
PWM CORE_PWM_PROCHOT# [4,5,31,35]
80
[33,36] MAINON DAC4/DCD0#/GPJ4(X)

3
104 47
[24] BT_POWERON# 33 DSR0#/GPG6(X) TACH0A/GPD6(Dn) 48 FANSIG [28]
FAN2SIG Q13
[8] PWROK_EC GINT/CTS0#/GPD5(Up) TACH1A/TMA1/GPD7(Dn)
C 88 TP57 C
[28] KB_BL_LED 81 PS2DAT1/RTS0#/GPF3(Up) 120 PROCHOT_EC 2
R136 TP43
DAC5/RIG0#/GPJ5(X) TMRI0/WUI2/GPC4(Dn) DNBSWON# [5]
87 124
[29] SENSOR_OFF E51_TXD PS2CLK1/DTR0#/GPF2(Up) TMRI1/WUI3/GPC6(Dn)
*22_4 TP28 109 TP22
108 TXD/SOUT0/GPB1(Up) R114 2N7002K
[25] AMP_MUTE# RXD/SIN0/GPB0(Up)

1
TP53 71 125 100K_4
ADC5/DCD1#/WUI29/GPI5(X) PWRSW/GPE4(Up) dGPU_OPP# NBSWON# [21]
C327 72 UART port 18 TP54
[31] ACIN ADC6/DSR1#/WUI30/GPI6(X) RI1#/WUI0/GPD0(Up) +1.1V_DUAL_EN
*10p/50V_4 73 21
[31] TEMP_MBAT 35 ADC7/CTS1#/WUI31/GPI7(X) RI2#/WUI1/GPD1(Up)
[21] TOUCHPANEL_ON RTS1#/WUI5/GPE5(Dn) WAKE UP TP51
34
[25] PCBEEP_EC 107 PWM7/RIG1#/GPA7(Up) 112
[31] D/C# DTR1#/SBUSY/GPG1/ID7(Dn) RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn) PCH_RSMRST# [5]
95
[26] EC_ODD_EJ ODD_PWRER CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn)
94
TP38 CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn)
R107 *SHORT_4 SPI_SCK_UR_R 105
[6] SPI_SCK SPI_CS0#_UR 101 FSCK/GPG7
R112 *SHORT_4
[6] SPI_CS SPI_SDI_UR FSCE#/GPG3 RF_EN [24]
R111 *SHORT_4 102 EXTERNAL SERIAL FLASH
[6] SPI_SDI SPI_SDO_UR FMOSI/GPG4 ICM [31]
R108 *SHORT_4 103 66
SPI_SDI_UR [6] SPI_SDO FMISO/GPG5 ADC0/GPI0(X) 67
R110 *10K_4 C600 10u/6.3V_6 ECAGND
R109 *10K_4 SPI_SDO_UR 56 ADC1/GPI1(X) 68
[28] MY16 57 KSO16/SMOSI/GPC3(Dn) ADC2/GPI2(X) 69 TPD_INT# [29]
VRON R147 *SHORT_4
[28] MY17 KSO17/SMISO/GPC5(Dn) ADC3/GPI3(X) dGPU_FB_CLAMP_REQ# VDDA_PWRGD [35]
32 70
[28] CPUFAN# PWM6/SSCK/GPA6(Up) ADC4/WUI28/GPI4(X)
Please do not place any S5_ON
TP52
100 A/D D/A
pull-up resistor [32,34,36] S5_ON 1.2V_ON 106 SSCE0#/GPG2(X)
on GPG0, GPG2, and GPG6
TP31
SSCE1#/GPG0(X) SPI ENABLE
76
TACH2/GPJ0(X) DGPU_AC_DC# [12]
(Reserved [28] MY0
36
KSO0/PD0 GPJ1(X)
77 dGPU_FB_CLAMP
hardware strapping). 37 78 TP46
[28] MY1 38 KSO1/PD1 DAC2/TACH0B/GPJ2(X) 79 TP47
[28] MY2 KSO2/PD2 DAC3/TACH1B/GPJ3(X) USBON# [27]
39
[28] MY3 40 KSO3/PD3
[28] MY4 KSO4/PD4 KBMX
41
[28] MY5 KSO5/PD5
42
[28] MY6 43 KSO6/PD6
[28]
[28]
MY7
MY8
44
45
KSO7/PD7
KSO8/ACK#
HWPG(KBC)
[28] MY9 KSO9/BUSY
46
B [28] MY10 KSO10/PE B
51 2 TP35 +3V
[28] MY11 KSO11/ERR# CK32KE/GPJ7
KSI3/SLIN#
KSI1/AFD#
KSI0/STB#

52
KSI2/INIT#

128 R115 *SHORT_4

[28] MY12 KSO12/SLCT CK32K/GPJ6
53
VCORE

[28] MY13 KSO13

AVSS

54 CLOCK R87
KSI4
KSI5
KSI6
KSI7

[28] MY14
VSS

VSS
VSS
VSS
VSS
VSS

55 KSO14
[28] MY15 KSO15
IT8587E/FX 10K_4
SM BUS ARRANGEMENT TABLE
58
59
60
61
62
63
64
65

27
49
91
113
122

75

12

D10 1N4148WS HWPG

[35] VRM_PWRGD HWPG [8]
SM Bus 1 Battery D9 *1N4148WS
[28] MX0 [36] HWPG_1.8VS5
C313
[28] MX1
D11 *1N4148WS
ECAGND

[28] MX2 [33] HWPG_1.5V

0.1u/10V_4 SM Bus 2 PCH/VGA
[28] MX3
D8 *1N4148WS
[28] MX4 [34] HWPG_0.95VS5
[28] MX5
SM Bus 3 N/A D7 *1N4148WS
[28] MX6 [32] SYS_HWPG
L38 BLM15AG121SS1/0.5A/120ohm_4
[28] MX7
SM Bus 4 N/A

Power sequence 3/5VPCU reset switch (CLG)

NBSWON# TP26
DNBSWON# TP21
SUSON TP29 SW2
3/5V_SW
A SUSB# TP42 1 3 SYS_SHDN# [12,32,36,37] A
2 4
1

PWROK_EC
TP58
C623 D27
5

PLTRST# TP50 0.1u/16V_4 *MLVS0402K11

2

HWPG TP40
MAINON TP45
PCH_RSMRST#

S5_ON
TP30
Quanta Computer Inc.
TP25
PROJECT : ZYV
Size Document Number Rev
C3A
IT8587
Date: Monday, April 28, 2014 Sheet 30 of 40
5 4 3 2 1
 5 4 3 2 1

VA2 PR27 0212_C_change

VA1 PQ1 PD1 0.02/F_0612 PQ45
PJ1 AOL1413 SBR1045SP5-13 VIN AOL1413
1 1 1 1
2 2 5 3 2 5
3 2 3
3 PR25

1
PC7 PC1 *SHORT_4
0.1u/50V_6 2200p/50V_4 PC63 PR119 24737_ACN PC10 PC11 PR76
7
6
5
4

4
0.1u/50V_6 220K_4 0.1u/50V_6 2200p/50V_4 33K/F_4
PC2 PD4
0.1u/50V_6 P4SMAFJ20A 24737_ACP

2
dcjk-2dc2003-000111-3p-v
D POWER_JACK PR26 D
1 6 *SHORT_4

PR117 2 5 PR75
D/C# [30]
recommend 200mA at least. 220K_4 10K_4
3 4

PQ20

3
PD5 IMD2AT108
1N4148WS
2
24737_ACP
PQ18
2N7002K
24737_ACN

1
PC38 PC123 PC37
0.1u/50V_6 0.1u/50V_6 0.1u/50V_6

PR173
63.4K/F_4

1
VIN
PR170 PC29

ACP

ACN
10K/F_4 1u/16V_6
+3VPCU +3VPCU 24737_ACDET 6 16 24737_REGN
ACDET REGN
C C

PD2
24737_VCC 20 RB500V-40 PC113 PC112
PR73 PR71 VCC 2200p/50V_4 4.7u/25V_6
100K_4 100K_4 PR174
20_1206 PC36 17 24737_BST
BTST

5
0.47u/25V_6
[30] ACIN
PC33
3

47n/50V_6
PQ40
18 24737_DH 4 MDV1528
2 5 HIDRV
ACOK#
PQ17 19 24707_LX

3
2
1
2N7002K PHASE PR189
0.01/F_0612
1

MBDATA 8 PU3 PL8

SDA BQ24737RGRR 6.8uH_7X7X3
15 24737_DL
LCDRV
MBCLK 9
SCL

5
+3VPCU
14 PR171
PGND *4.7_6
PR64 10K_4 24737_BM# 11 4
BM# PQ39
B
MDV1528 B
BAT-V PR70 *10K_4 24737_CMPOUT 3 PC115

3
2
1
CMPOUT 13 24737_SRP 0.1u/25V_4 24737_SRP PC135 PC137 PC144
SRP PC117 2200p/50V_4 10u/25V_8 10u/25V_8
PC42 PR65 316K/F_4 24737_ILIM 10 PC28 *680p/50V_6 BAT-V
PJ2 ILIM 0.1u/25V_4
0.1u/50V_6
9 8 PR79 24737_CMPIN 4 12 BAT-V
7 BATT_EN# 100_4 CMPIN SRN PC116
6 TEMP_MBAT 0.1u/25V_4

IOUT

GND
GND
GND
GND
GND
5 TEMP_MBAT [30]
4
3 PR78 PR245 PR172
2

21
22
23
24
25
1M_4 *100K_4 *100K_4
10 1
+3VPCU
Batt_Conn PC41 PC40
*47p/50V_4 *47p/50V_4 0303_C_change
+3V Asking from ACER Sophie.
PR67 PC32
100K/F_4 0.01u/25V_4
REGN MAX voltage 6.5V
3

PR247
PR77
*SHORT_4
PR81
100_4
PR80
100_4 PR246
*100K_4 V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
24737_BM# 2
MBCLK [30]
*1.62K/F_4 PR244
*0_4
=0.793V for 3.965A current limit
CORE_PWM_PROCHOT# [4,5,30,35]
PQ72

3
MBDATA [30] *2N7002K
Pin10 ILIM=0.793V
A-stage stuff [30] ICM ICM
Rsr = 0.01ohm
1

A A
B-stage if no external switch control=> stuff 24737_CMPOUT 2
if has external switch control=> DNI
PU4 PQ71
*CM1293A-04SO *2N7002K
1 6 MBDATA PC119
CH1 CH4 Quanta Computer Inc.
1
100p/50V_4
2 5
VN VP +3VPCU
TEMP_MBAT 3 4 MBCLK PROJECT :
CH2 CH3 Size Document Number Rev
Add ESD diode base on EC FAE suggestion C3A
Charger(BQ24737RGRR)
Embedded battery not need stuff
Date: Monday, April 28, 2014 Sheet 31 of 40
5 4 3 2 1
 5 4 3 2 1

MAIND SYS_SHDN#
MAIND [33,34,36] SYS_SHDN# [12,30,36,37]

PR182
*SHORT_6

+3VPCU VL 3V_LDO
PR72
10K/F_4
D [30] SYS_HWPG D
VIN VIN
SYS_SHDN#

10u/6.3V_6

0.1u/25V_4

4.7u/6.3V_6
1

+
PC118 PC139 PC140 PC124 PC122
33u/25V_6x4.5 4.7u/25V_6 2200p/50V_4 PR192 PR176 PR177 2200p/50V_4 4.7u/25V_6
2

*SHORT_4 *SHORT_4 *100K/F_4

PC130

PC127
51225_VIN

PC129
+5VPCU

5
5
+5VPCU PQ37 +3VPCU
5 Volt +/- 5% MDV1528 3.3 Volt +/- 5%

13

12

3
4
TDC : 6.2A PQ48 4 TDC : 5.1A

VREG5

VIN

VREG3
MDV1528 +3VPCU
PEAK : 8.3A 7 6 SYS_SHDN# PEAK : 6.8A

3
2
1
PGOOD EN2
OCP : 10A OCP : 9A

1
2
3
51225_EN1 20 10 51225_DH2
Width : 260mil EN1 DRVH2 PR179 PC125 Width : 220mil
PL9 51225_DH1 16 9 51225_VBST2 PL5
3.3uH_7X7X3 PC141 PR196 DRVH1 VBST2 3.3uH_7X7X3
51225_VBST1 17 8 51225_SW2 1/F_6 0.1u/50V_6
VBST1 PU10 SW 2
0.1u/50V_6 1/F_6 51225_SW1 18 TPS51225RUKR 11 51225_DL2
SW 1 DRVL2

5
C PR188 51225_DL1 15 4 51225_FB2 PR180 C
15.4K/F_4 DRVL1 VFB2 PQ38 6.49K/F_4
PQ43 51225_FB1 2 21 MDV1595S PR66
+ PR74 MDV1595S 4 VFB1 GND 4 *4.7_6 +
*4.7_6 14 22
PC145 PC147 VO1 GND PC109 PC108

VCLK

GND

GND

GND

GND
CS1

CS2
220u/6.3V_6X4.2 0.1u/50V_6 0.1u/50V_6 220u/6.3V_6X4.2
1
2
3

3
2
1
PC30
PR187 *680p/50V_6 PR184

19

26

25

24

23
10K/F_4 PC39 10K/F_4
*680p/50V_6

51225_CS1

51225_CS2
51225_VCLK
OCP:9A
L(ripple current)
PR183 =(9-3.3)*3.3/(3.3u*0.355M*9)
*SHORT_6 ~1.784A

100K/F_4

100K/F_4
PC142
Iocp=9-(1.784/2)=8.108A
2 0.1u/50V_6 Vth=(8.108A*14mOhm)+1mV=114.512mV
PD6 1/13 Adding +3VSUS power for touch pad R(Ilim)=(114.512mV*8)/10uA
3
OCP:10A 1PS302
PR195
(By acer request) =91.609K
1 *SHORT_6
L(ripple current) VIN +15V VIN +3VPCU

PR190

PR181
PC148 +3VSUS
=(9-5)*5/(3.3u*0.3M*9) 0.1u/50V_6
=2.244A 2
Iocp=10-(2.244/2)=8.877A PD7 PR231 PR229 PR232 PR233
B Vth=(8.877A*14mOhm)+1mV=125.287mV 1PS302 3 PC143 *TP@1M_6 *TP@22_8 *TP@1M_6 *TP@1M_6
B

3
R(Ilim)=(125.287mV*8)/10uA 1
0.1u/50V_6
~100.23K
+15V_ALWP SUSD 2
+15V

3
PR199
22_8 PC149 PQ67
0.1u/50V_6 2 *TP@AO3404
[30,33] SUSON

1
2 2
+3VSUS
PR230 PQ65 PQ64

1
PQ66 *TP@1M_6 *TP@2N7002K
*TP@DTC144EU *TP@2N7002K PC172
TDC : 0.038A

1
*TP@2.2n/50V_4
PEAK : 0.05A
Width : 20mil
VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU +3VPCU

PR186 PR197 PR185 PR194 PR193

5

1M_6 22_8 22_8 1M_6 *1M_6

3
S5D 4 MAIND 4 MAIND 2 S5D 2
A PQ44 PQ41 A
3

MDV1528Q MDV1528Q
PQ35 PQ34
3
2
1

3
2
1

2 AO3404 AO3404
[30,34,36] S5_ON
1

1
2 2 2
+5V_S5 +5V +3V +3V_S5
PR191 PQ49 PQ42 PQ46 PC138
Quanta Computer Inc.
1

PQ47 1M_6 2N7002K 2N7002K 2N7002K *2200p/50V_4

DTC144EU
TDC : 3A TDC : 3.2A TDC : 1.8A TDC : 0.3A
1

PEAK : 4A PEAK : 4.3A PEAK : 2.4A PEAK : 0.4A PROJECT :

Size Document Number Rev
Width : 120mil Width : 140mil Width : 80mil Width : 20mil SYSTEM 5V/3V (TPS51225) C3A

Date: Monday, April 28, 2014 Sheet 32 of 40

5 4 3 2 1
 5 4 3 2 1

TDC : 0.75A +SMDDR_VTT

PEAK : 1A +1.5V_SUS

Width : 40mil

3
PC106 PC107
10u/6.3V_6 10u/6.3V_6
TDC : 0.64A
D TDC : 0.38A MAIND 2 PEAK : 0.85A D
[32,34,36] MAIND
PEAK : 0.5A +SMDDR_VREF
Width : 20mil
Width : 20mil PQ16
AO3404

1
Greater than or equal 40mil
PC110
+1.5V
0.22u/10V_4

+5V_S5

+3V

PC104 PC105

22

21
10u/6.3V_6 1u/10V_4

2
PR164
VIN
100K/F_4

PAD

PAD

VTTGND

VLDOIN
VTTSNS
VTTREF

VTT

5
20 12 PC101 PC102
[30] HWPG_1.5V PGOOD V5IN
C
2200p/50V_4 4.7u/25V_6 C

51216_S3 17 14 51216_DRVH 4
[30,36] MAINON S3 DRVH
PR162 *SHORT_4 PR165 PC103
2_6 0.1u/50V_6 PQ33

1
2
3
51216_S5 16 15 51216_VBST AON6414AL
[30,32] SUSON S5 VBST
PR160 *SHORT_4 PU8 PL6
TPS51216RUKR 0.68uH_7X7X3
51216_MODE 19 13 51216_SW +1.5V_SUS
PR59 200K/F_4 MODE SW

51216_TRIP 18 11 51216_DRVL
TRIP DRVL

5
PR58 53.6K/F_4
+1.5V_SUS
VDDQSNS

PR60
26
PAD PGND
10 *4.7_6 1.5 Volt +/- 5%
REFIN

4
TDC : 10.42A

GND
PAD

PAD

PAD
REF

+
PQ36 PC24 PC100
PEAK : 13.85A

1
2
3
VREF=1.8V AON6756 PC25 0.1u/50V_6 330u/2.5V_6X4.2
OCP : 18A
6

25

24

23

7 *680p/50V_6

51216_REF Width : 415mil

51216_REFIN

PR62 RDSon=4.3mohm
B PC27 *SHORT_6 B
51216_S3 PR161 51216_S5 0.1u/10V_4
*0_4 PC111 PR166
PR63 *0.1u/50V_6 0_4
10K/F_4
PR167
SUSON PR163 *100_4
100K_4
VDDIO_MEM_S_SENSE [4]

PR61 PC26
51K/F_4 0.01u/25V_4 Mode Frequency Discharge mode

200K 400K Tracking Discharge

OCP=18A
L ripple current 100K 300K Tracking Discharge
=(19-1.5)*1.5/(0.68u*400k*19)
=5.079A
A
Vtrip=18-(5.079/2)*4.3mohm A
=0.06647V S3 S5 +1.5VSUS REF VTT
Rlimit=0.06647/10uA*8~53.183Kohm
S0 1 1 ON ON ON Quanta Computer Inc.
S3 (mainon off) 0 1 ON ON OFF PROJECT :
Size Document Number Rev
C3A
S4/S5 0 0 OFF OFF OFF DDR 1.5V(TPS51216)
Date: Monday, April 28, 2014 Sheet 33 of 40
5 4 3 2 1
 5 4 3 2 1

VIN
D D
+5VPCU
PC82 PC81
2200p/50V_4 4.7u/25V_6
+3V

PC16
1u/10V_4

5
PR149
100K/F_4

7
PQ30
MDV1528

V5IN
51211V_DRVH 4
1 9 PR36 PC18 +0.95V_S5
[30] HWPG_0.95VS5 PGOOD DRVH 0_6 0.1u/50V_6
3 10 51211V_VBST PL3
[30,32,36] S5_ON

3
2
1
PR143 *SHORT_4 EN VBST 2.2uH_7X7X3
2 PU2 8 51211V_SW
PR147 73.2K/F_4 TRIP TPS51211DSCR SW
PR144 5 6 51211V_DRVL
*100K/F_4 PR142 464K/F_4 TST DRVL

5
12 11 +
C GND GND PR32 PR145 PC85 PC90 PC87 +0.95V_S5 C

GND

GND

GND

GND
*4.7_6 0_4 *0.1u/50V_6 0.1u/50V_6 330u/2.5V_6X4.2 0.95 Volt +/- 5%

FB
4 TDC : 3.9A

13

14

15

16

4
51211V_FB PEAK : 5.2A
PQ29 PC17 OCP : 7A

3
2
1
VFB=0.7V MDV1595S *680p/50V_6
Width : 160mil
PR31
3.65K/F_4

OCP=7A PR34
*100_4
L ripple current PR30
=(19-0.95)*0.95/(2.2u*290k*19) VDD_095_FB_H [4]
9.76K/F_4
=1.415A
Vtrip=[7-(1.415/2)]*14mohm 0116_B_change from 10k to 9.76k
VDD_095_FB_L [4]
=88.097mV PR33
B Rlimit=88.097mV/10uA*8=70.48Kohm PR35 *0_4 B
*SHORT_4

+0.95V_S5

5
MAIND 4
[32,33,36] MAIND
PQ31
MDV1528Q +0.95V
TDC : 2.7A

3
2
1
PEAK : 3.6A
Width : 120mil
+0.95V
A A

Quanta Computer Inc.

PROJECT :
Size Document Number Rev
+0.95V_S5(TPS51211) C3A

Date: Monday, April 28, 2014 Sheet 34 of 40

5 4 3 2 1
 5 4 3 2 1

+VDDNB_CORE

PC164
PR202 330p/50V_4
10_4

PR200 Load line setting

*SHORT_4 PR85
[4] APU_VDDNB_RUN_FB_H 2.2/F_6 VIN
+5V_S5 BOOT_NB
PR91
1.54K/F_4

2200p/50V_4
0.1u/50V_6

4.7u/25V_6

4.7u/25V_6
5

PC157

PC154

PC150

PC151
Close to the RC time PC44
D CPU side. constant 0.22u/25V_6 D
PC57 PR94
1000p/50V_4 300/F_4 VSUMG+ UGATE_NB 4

1
2
3
PR87

PR86
PC59 PR96

1/F_6
PR222 PQ51 PL10 DCR=1.1mOhm

0_6
680p/50V_4 2K/F_4

47n/16V_4
2.61K/F_4 AON6414AL 0.36uH_10X10X4

0.15u/10V_4
PHASE_NB 1 2

PC58

PC56
+VDDNB_CORE

PR97
11K/F_4

5
PR212 PC50 PR92 Close with

4
PR84
41.2K/F_4 390p/50V_4 133K/F_4 PHASE_NB inductor
+ +

1000p/50V_6 2.2_6
LGATE_NB 4

1u/10V_4

1u/10V_4
PR198 PC131 PC146

0.1u/10V_4

10u/6.3V_6
PC51 PR93 10K/F_4_3435NTC 330u/2V_7343 *330u/2V_7343

62771_VSEN_NB

PC136

PC134
100p/50V_4 330_4

1
2
3
62771_FB_NB

PC43
VSUMG- PQ50

62771_VDDP
62771_EN

62771_VDD
AON6752

PC159

PC158
OCP

ISUMN_NB
PC169
62771_COMP_NB 0.1u/10V_4

PR218 +3V
VSUMG+ PR98 3.65K/F_4

36

37

38

25

26

40

39
100K/F_4

VDD
COMP_NB

FB_NB

VSEN_NB

VDDP

ISUMP_NB

ISUMN_NB
PR209
10K/F_4 VSUMG- PR217 1/F_4
PR213
*SHORT_4
35 34 LGATE_NB
PGOOD_NB LGATE_NB

VRM_PWRGD 20 33 PHASE_NB
[30] VRM_PWRGD PGOOD PHASE_NB

PR99 *SHORT_4 62771_SVC 3 32 UGATE_NB

[4] APU_SVC SVC UGATE_NB
C C

4 31 BOOT_NB
[4,5,30,31] CORE_PWM_PROCHOT# VR_HOT_L BOOT_NB

PR100 *SHORT_4 62771_SVD 5 30

[4,7]
[4] APU_SVD

APU_VDD_18 PR101 *SHORT_4 62771_VDDIO 6

SVD BOOT2

29
AMD Beema 25W
VDDIO UGATE2
PU5
PR102 *SHORT_4 62771_SVT 7 ISL62771HRZ-T 28
[4] APU_SVT SVT PHASE2
+VDD_CORE +VDDNB_CORE
PR103 *SHORT_4 62771_EN 8 27
[30] VDDA_PWRGD ENABLE LGATE2 TDC : 20A TDC : 13A
[4] APU_PWRGD_SVID_REG
PR104 *SHORT_4 62771_PWROK 9
PWROK LGATE1
24 LGATE_1 PEAK : 25A PEAK : 17A
OCP : 31A OCP : 22A
NTC_NB PHASE_1
1
NTC_NB PHASE1
23
Width : 840mil Width : 680mil
NTC 11 22 UGATE_1 Load Line = -4mV/A Load Line = -4mV/A
NTC UGATE1
27.4K/F_4

27.4K/F_4
470K_4_4700NTC

470K_4_4700NTC

IMON_NB 2 21 BOOT_1
PR201

PR83

PR224

PR107

IMON_NB BOOT1

IMON 10 41
IMON EP
0.1u/10V_4

0.1u/10V_4

ISUMN

ISUMP
COMP

ISEN1

ISEN2
VSEN
PC170

PC168
133K/F_4

133K/F_4

RTN
PR220

PR219

Add 9 GND VIAs

FB
10K/F_4

10K/F_4
PR82

PR225

for thermal pad

19

18

16

17

15

14

13

12

PR105 +5V_S5
B B
1K_4
62771_VSEN

62771_RTN

ISEN2
62771_FB

ISUMN

Place NTC close to the Place NTC close to the 62771_COMP PR215 PR88
VDDNB Hot-Spot. VDDCORE Hot-Spot. 10K_4 2.2/F_6 VIN
PC47 ISEN1 BOOT_1
OCP=100'C OCP=100'C
100p/50V_4

33u/25V_6x4.5
1
2200p/50V_4
0.1u/50V_6

4.7u/25V_6

4.7u/25V_6
5
+

PC48

PC46

PC152
PC45

PC167

PC166
PR208 PC49 PR89 0.22u/25V_6
*0_4 390p/50V_4 133K/F_4

2
UGATE_1 4

PC160 PR211

1
2
3
680p/50V_4 2K/F_4 PQ53 PL11 DCR=1.1mOhm
VSUM+ AON6414AL 0.36uH_10X10X4
PHASE_1 1 2
+VDD_CORE

PR207
PC163 PR214

4
2.2_6
1000p/50V_4 300/F_4 PR221
+VDD_CORE
47n/16V_4

2.61K/F_4
0.15u/10V_4

LGATE_1 4 + +
PC54

PC55

PR95
11K/F_4

0.1u/10V_4

10u/6.3V_6
PC162 PR210 PC52 PC53

PC156

PC153
330p/50V_4 2.26K/F_4 330u/2V_7343 *330u/2V_7343

1000p/50V_6
1
2
3

PC155
PR205 Close with PQ52
10_4 PR223 phase1 inductor AON6752
PR203 Load line setting PR90 10K/F_4_3435NTC
*SHORT_4 487/F_4
[4] APU_VDD_RUN_FB_H VSUM-

1Phase VSUM+ PR106 3.65K/F_4

OCP PC165
[4] APU_VDD_RUN_FB_L 1Phase 0.1u/10V_4
RC time
PR204
constant
*SHORT_4
A PR206 VSUM- PR216 1/F_4 A
Parallel 10_4
PC161
0.01u/25V_4

Close to the
CPU side.

Quanta Computer Inc.

PROJECT :
Size Document Number Rev
VDD / VDDNB CORE (ISL62771) C3A
Date: Monday, April 28, 2014 Sheet 35 of 40
5 4 3 2 1
 5 4 3 2 1

+3VPCU
+1.8V_S5 +1.8V_S5
+1.8V_S5
1.8 Volt +/- 5%
TDC : 2.26A

3
PC121 PC120
+3V 10u/6.3V_6 0.1u/25V_6
PEAK : 3A
PU9 TPS54318RTER Width : 90mil TDC : 1.13A
16
VIN PH
10 MAIND 2 PEAK : 1.5A
D
PR168 1
VIN PH
11 PL7 Width : 50mil D

100K/F_4 1uH_7X7X3 PQ19

2 12 AO3404

1
VIN PH
14 13
[30] HWPG_1.8VS5 PWRGD BOOT +1.8V
15 6 PC114
[30,32,34] S5_ON PR169 EN VSNS 0.1u/50V_6 PR178
*SHORT_4 7 3
R1 100K/F_4
COMP GND PC128 PC133 PC132
PC31 8 4 0.1u/10V_4 10u/6.3V_6 10u/6.3V_6
1000p/50V_4 RT/CLK GND 1.8V_VSNS

PAD
PAD
PAD
PAD
PAD
PAD
9 5
SS AGND
PR69
10K/F_4
PR68
121K/F_4 VFB=0.8V R2 PR175

22
21
20
19
18
17
78.7K/F_4

PC35 PC34 PC126

*100p/50V_4 1200p/50V_4 0.01u/25V_4

Vo=0.8*[(R1+R2)/R2]

C C

VIN

PD3
DA2J10100L

Thermal protection PR108

1M_6

1
PQ23
AO3409
2

3
S5_ON 2
B
NTC_R for setting TEMP. B

887/F_4 for 86'C --->now PQ21 PR122

(CS18872FB01)

1
DTC144EU *SHORT_6
1.5K/F_4 for 70'C
(CS21502FB14) VL VL
SYS_SHDN# [12,30,32,37]

15W CPU, PR113=3.65K

(when PR159 T=54.5℃, than PR159=3.65K)
PR110 PC70 PR121
25W CPU, PR1133 = ?? PR113 200K/F_4 0.1u/50V_6 200K_6

3
(when PR159 T=??℃, than PR159=??K) SP@3.65K/F_4

8
VIN +3V +5V +1.8V +1.5V +0.95V +15V
PR159 2.469V 3
10K/F_4_3435NTC + 1 2
2
PR50 PR51 PR52 PR53 PR54 PR55 PR49 - PQ24

3
1M_4 22_8 22_8 22_8 22_8 22_8 1M_4 PU6A 2N7002K

4
AS393MTR-E1 PC69

1
0.1u/50V_6
MAINON_ON_G MAIND S5_ON 2
MAIND [32,33,34] PR109
3

PQ22 200K/F_4
3

2N7002K
PR56

1
2 PQ9 1M_4 2 2 2 2 2 2
[30,33] MAINON DTC144EU PC23
PQ11 PQ12 PQ13 PQ14 PQ15 PQ10 *2200p/50V_4
2N7002K 2N7002K 2N7002K 2N7002K 2N7002K 2N7002K
1

PR57
1

*100K/F_6 5
+ 7
6
-
A A
PU6B
AS393MTR-E1

For EC control thermal protection (output 3.3V)

Quanta Computer Inc.

PROJECT :
Size Document Number Rev
C3A
+1.8V/Thermal
Date: Monday, April 28, 2014 Sheet 36 of 40
5 4 3 2 1
 5 4 3 2 1

+3V_GFX Default 0.9V

H_VID0
PR22 *EV@10K/F_4
+3V_S5 H_VID1
PR17 PR21 *EV@10K/F_4
*EV@100K_4 H_VID2
PR18 *EV@10K/F_4
H_VID3

2
PR15 *EV@10K/F_4
PQ2 H_VID4 VIN
*EV@PDTC143TT PR13 EV@10K/F_4 PR23
D H_VID5 D
EV@2.2/F_6
THAL_GPU_VR 1 3 SYS_SHDN# [12,30,32,36] 51728_VBST2

EV@2200p/50V_4
EV@10K/F_4

EV@10K/F_4

EV@10K/F_4

EV@10K/F_4
PR11 EV@10K/F_4

*EV@10K/F_4

*EV@10K/F_4

EV@0.1u/50V_6

EV@4.7u/25V_6

EV@4.7u/25V_6
5

PC15

PC77

PC80

PC79
PC75
+3V EV@0.22u/25V_6

51728_DRVH2 4

PR115

PR124

PR125

PR131

PR132

PR133
EV@100K/F_4
*EV@10K/F_4

*EV@100K/F_4

EV@200_4
PR140

1
2
3
1/14 modify *EV@10K/F_4 PQ28
EV@AON6414AL
PL1
EV@0.24uH_7X7X3 DCR=1.1mOhm
follow ZQN +3V_GFX +5V_S5
51728_LL2 1 2
+VGPU_CORE
PR14,PR16 DNS

EV@1000p/50V_6 EV@2.2_6

4
5

PR28

EV@10u/6.3V_6
EV@16.2K/F_4
PR14

PR16

PR1

PR7
PR227 +
51728_DRVL2

EV@0_4
EV@10K/F_4 4 PC86

EV@0.1u/10V_4
PC84

PC88
EV@330u/2V_7343
PC72

1
2
3

PC13
EV@2.2u/10V_6 PQ27
GPU_PG_EN EV@AON6752
[38] GPU_PG_EN

PR37

PR39
26
[12] GPU_DPRSLPVR

V5IN
PR118 *EV@100K/F_4 33 30 51728_DRVH2
PGD DRVH2 51728_CSP2
reserve 0.01uF for RC Delay PR116 EV@2.2K_4 34 29 51728_VBST2

EV@28.7K/F_4
C C
1.8v_GFX > GPU CORE 10us PG VBST2
51728_PCNT 13 28 51728_LL2

PR151
PR127 EV@100K/F_4
PCNT LL2
PC67
*EV@0.1u/25V_4 Opal-XT 25W/Jet-XT 25W

EV@0.015u/16V_4
Check EN level 12 27 51728_DRVL2

EV@412K/F_4
PC9 *EV@0.01u/25V_4 Close to the
SLP DRVL2

PC60
51728_EN 51728_CSP2
VR side.
35 3

PR111
PR19 EV@0_4
[38] 0.95_GFX_EN EN CSP2 +VGPU_CORE
THAL_GPU_VR 10 4 51728_CSN2 51728_CSN2
1/14 modify THAL CSN2 Countinue current:32A
follow ZQN [12] PWRCNTRL0
H_VID0 20
VID0
PC66
Peak current:42.6A
PR141 *EV@SHORT_4 *EV@0.1u/25V_4
H_VID1 19 21 51728_DRVH1
[12] PWRCNTRL1 PR137 *EV@SHORT_4 VID1 DRVH1 OCP:52A
H_VID2 18 22 51728_VBST1 PR153
[12] PWRCNTRL2 PR134 *EV@SHORT_4 VID2 VBST1 EV@100K/F_4_4250NTC Load Line=0mV/A
H_VID3 17 23 51728_LL1
[12] PWRCNTRL3 PR128 *EV@SHORT_4 VID3 LL1
H_VID4 16 24 51728_DRVL1
[12] PWRCNTRL4 PR126 *EV@SHORT_4 VID4 DRVL1
H_VID5 15 6 51728_CSP1
[12] PWRCNTRL5 PR120 *EV@SHORT_4 VID5 CSP1
14 5 51728_CSN1
VID6 PU1 CSN1 +3V
51728_DROOP EV@TPS51728RHAR
PC8 PR4 25
EV@68p/50V_4 EV@8.2K/F_4 PGND
39 PR20 PR24
PC6 DROOP *EV@0_4 EV@2.2/F_6 VIN
EV@1200p/50V_4 51728_VBST1
B B
36 51728_TONSEL

EV@2200p/50V_4
EV@0.1u/50V_6

EV@4.7u/25V_6

EV@4.7u/25V_6
TONSEL

1
51728_V5FILT +3V 51728_VREF 40
VREF

5
31 51728_TRIPSEL +

PC12

PC76

PC78

PC73
PC74
PC62 TRIPSEL EV@0.22u/25V_6 PC71
EV@0.22u/10V_6 PR6 32 51728_OSRSEL EV@33U/25V_6x4.5

2
*EV@0_4 OSRSEL 51728_DRVH1 4
PR123 PR135
EV@316K/F_4 EV@0_4 PR139

1
2
3
51728_SLEW37 *EV@10K/F_4 PQ25 PL2
PR129 PR12 PR10 SLEW EV@AON6414AL EV@0.24uH_7X7X3
51728_LL1 1 2
DCR=1.1mOhm
*EV@0_4 *EV@0_4 PR138 +VGPU_CORE
EV@0_4 9 EV@0_4
THRM 1

EV@2.2_6
PR146

EV@330u/2.5V_6X4.2
EV@16.2K/F_4
3

4
PU

5
*EV@0_4

*EV@0_4

PR29
EV@4.02K/F_4

EV@0.1u/10V_4

EV@10u/6.3V_6
51728_TONSEL PR148 38 51728_V5FILT + +
V5FILT

EV@0_4
TPAD10
TPAD11
TPAD12
TPAD13
TPAD14
TPAD15
TPAD16

EV@100K/F_4_4250NTC PC91
TPAD1
TPAD2
TPAD3
TPAD4
TPAD5
TPAD6
TPAD7
TPAD8
TPAD9

51728_DRVL1 4

EV@1000p/50V_6
EV@330u/2V_7343
PwPd
IMON

GND
GFB
VFB

PC89

PC83

PC92
THRM=0.75V/60uA=12.5K

PC14
TEMP=87C

1
2
3
PR130

PR136

PC68 PQ26
8

11

41

42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

+VGPU_CORE

PR38

PR40
EV@2.2u/10V_6 EV@AON6752

51728_CSP1
PR2

EV@28.7K/F_4
EV@100_4 51728_IMON

PR150
PR8 PR114 *EV@SHORT_8 PC64

EV@0.015u/16V_4
*EV@SHORT_4 *EV@0.1u/25V_4
51728_VFB

EV@412K/F_4
A [15] GPUVDDC_SENSE Close to the A

PC61
51728_GFB
VR side.

PR112
[15] GPUVSS_SENSE
PR9 PR5 PC5
*EV@SHORT_4 EV@12.4K/F_4 EV@3300p/50V_4
Parallel PR3 PC65
EV@100_4 *EV@0.1u/25V_4
51728_CSN1
Quanta Computer Inc.
PR152 PROJECT :
Close to the PC3 PC4 EV@100K/F_4_4250NTC Size Document Number Rev
EV@1000p/50V_4 EV@1000p/50V_4 C3A
GPU side. +VGPU CORE(TPS51728)
Date: Monday, April 28, 2014 Sheet 37 of 40
5 4 3 2 1
 5 4 3 2 1

+3VPCU

+PCIE_VDDC_GFX
+0.95V
0.95 Volt +/- 5%
1/14 modify PC98 PC99 TDC : 1.64A
follow ZQN +3V_GFX EV@10u/6.3V_6 EV@0.1u/25V_6
PEAK : 2.18A
D PU7 EV@TPS54318RTER D
change PR156 16 10 Width : 90mil
VIN PH
to 10K PR156 1 11 PL4
EV@10K/F_4 VIN PH EV@1uH_7X7X3
2 12
VIN PH
PR155 HWPG_+PCIE_VDDC_GFX 14 13
[37] 0.95_GFX_EN PWRGD BOOT
*EV@SHORT_4
+3V_GFX PR158 15 6 PC96 PC95
*EV@SHORT_4 EN VSNS EV@0.1u/50V_6 PR154 EV@10u/6.3V_6
7 3
R1 EV@78.7K/F_4
COMP GND
PC97 8 4
EV@1000p/50V_4 RT/CLK GND 1.5V_SN PC93 PC94

PAD
PAD
PAD
PAD
PAD
PAD
9 5 EV@0.1u/10V_4 EV@10u/6.3V_6
PR42 PR41 SS AGND
EV@10K/F_4 EV@121K/F_4 VFB=0.8V R2 PR157

22
21
20
19
18
17
EV@412K/F_4

PC19
EV@0.01u/25V_4
PC20 PC21
*EV@100p/50V_4 EV@1200p/50V_4

Vo=0.8*[(R1+R2)/R2]
C C

VIN +1.5V_GFX +15V +1.5V_SUS

VIN +1.8V_GFX +3V_GFX +15V +1.8V_S5 1/14 modify
follow ZQN
add PR239,PQ8,

5
PR238 PR226 PR228
PR46 PR44 PR45 PR48 PR238,PR237,PR226, EV@1M_4 EV@22_8 EV@1M_4

3
EV@1M_4 EV@22_8 EV@22_8 EV@1M_4
PQ54,PR228,PQ58,PC171
4
PX_MODE_D 2 PQ32

3
EV@MDV1528Q
3

3
PR239

3
2
1
PQ8 *EV@SHORT_4
PR47 EV@AO3404 [37] GPU_PG_EN 2 2 2 PC171

1
0.95_GFX_EN 2 EV@1M_4 2 2 2 *EV@2200p/50V_4
PC22 PQ68 PR237 PQ54 PQ58 +1.5V_GFX
PQ4 PQ6 PQ7 PQ5 *EV@2200p/50V_4 EV@2N7002K EV@1M_4 EV@2N7002K EV@2N7002K
1/14 modify EV@2N7002K EV@2N7002K EV@2N7002K EV@2N7002K
+1.8V_GFX TDC : 2.57A

1
follow ZQN
1

1 PEAK : 3.42A
TDC : 0.75A
PEAK : 1A Width : 100mil
B
Width : 40mil B

1/14 modify TDC : 0.02A 1/14 modify

follow ZQN,delete PQ3 PEAK : 0.025A follow ZQN +3V +3V_GFX

add Q42,Q43,R569,PR240,PR241 Width : 20mil add PR234,PR235,PR236,PQ56,PQ57

+3V +3V_GFX PR235
PQ69 PR234 EV@10K/F_4
EV@AO3413 EV@10K/F_4

1 3
PE_PWRGD [5]

3
+3V
2

PC173
PR242 EV@100K_4 EV@0.1u/10V_4 2
PR240
3

EV@10K/F_4 +1.5V_GFX PQ57

PR236 EV@2N7002K

3
EV@1K_4

1
A PR243 EV@10K/F_4 2 2 A
[5] DGPU_PWREN
PQ70
PC174
1

PR241 EV@0.1u/10V_4 EV@2N7002K PQ56

EV@100K/F_6 EV@MMBT3904-7-F_200MA
Quanta Computer Inc.
1

0225_C_change PROJECT :
Size Document Number Rev
GPU_POWER/VDDC_GFX C3A

Date: Monday, April 28, 2014 Sheet 38 of 40

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Quanta Computer Inc.

PROJECT : ZYV
Size Document Number Rev
Power tree C3A

Date: Monday, April 28, 2014 Sheet 39 of 40

5 4 3 2 1