2020 International Symposium on Computer, Consumer and Control (IS3C)

10-Bit Successive Approximation Register Analog-

to-Digital Converter for BLDC Motor Drive
Guo-Ming Sung Po-En Wu Jun-Min Xu
Department of Electrical Engineering Department of Electrical Engineering Department of Electrical Engineering
National Taipei University of Technology National Taipei University of Technology National Taipei University of Technology
Taipei, Taiwan Taipei, Taiwan Taipei, Taiwan
gmsung@ntut.edu.tw a50705a50705@gmail.com aary456@gmail.com

Abstract—This paper presents a 2.27 MS/s 10-bit successive Section II elucidates the circuit design of the proposed
approximation register (SAR) analogue-to-digital converter for SAR ADC and its relational circuits. Section III presents the
BLDC motor drive by using a TSMC 0.25 μm 1P3M CMOS post-layout simulation and measurement results, and the
2020 International Symposium on Computer, Consumer and Control (IS3C) | 978-1-7281-9362-5/20/$31.00 ©2020 IEEE | DOI: 10.1109/IS3C50286.2020.00065

process. The sample-and-hold (S/H) circuit operates with two
sampling modes. One is individually sampling eight channels in
sequence with an S/H circuit and the other is sampling four
channels simultaneously with four S/H circuits. All sampled
data will be digitized with high-speed SAR ADC in time division
multiplexing (TDM). In TSMC 0.25μm 1P3M CMOS process,
the N-type buried layer (NBL) is applied to boost the
withstanding voltage at the expense of shorting all PMOS bodies
and failing in design a buffer circuit. Those faults limits the
circuit design to avoid from connecting the source with body for
PMOS. Then the single-end input topology is a superior choice.
Post-layout-simulated results show that the signal-to-noise-and-
distortion ratio (SNDR), effective number of bits (ENOB),
power consumption, and chip area are 65.88 dB, 10.65 bits, 833
PW, and 1.35 u 0.98 mm2, respectively.
conclusion is drawn in Section IV.
II. CIRCUIT DESIGNED OF THE PROPOSED SAR ADC
Fig. 2 shows the schematic of the proposed 10-bit SAR
ADC with multiple inputs for BLDC motor drive. The
proposed SAR ADC can be divided into four subcircuits,
including the sample and hold (S/H) circuit, comparator,
successive approximation register (SAR) controller, and
digital-to-analog converter (DAC). The operational principle
of the proposed SAR ADC is a binary search algorithm. It
operates in three modes, including the sampling mode, hold
mode, and charge redistribution mode.

Keywords—SAR ADC, dynamic comparator, sample-and-hold

circuit, digital-to-analog converter, BLDC motor.
Controller
I. INTRODUCTION
The brushless direct current (BLDC) motor is generally Detectors
characterized by higher efficiency, lower maintenance, Gate Driver Average Current
10-bit 2.27 MS/s
higher cost, and small volume [1]. A new digital control Peak Current SAR ADC with 2 Channel
Sampling Modes
Over Current
concept for BLDC machines has been introduced, Inverter and an 8-Channel Register
Temperature Switch
experimentally verified, and implemented in a low-cost Sensors Speed
application-specific integrated circuit (ASIC). The FPGA-
based PWM controller results in a considerable reduction of
BLDC
size and the cost of the control system for BLDC motor drives Motor
DC-DC Buck Converter
[1]. Besides, the optical sensor can be used to measure the
rotation speed of BLDC motor using the pulse width
modulation (PWM) and the serial interface can be
implemented using an energy-effective 8-bit SAR ADC [2]. Fig. 1 Proposed control circuit of electric vehicle for BLDC motor.
To improve the performance of BLDC motor, integrating the
analog-to-digital converter (ADC) with the control circuit is
S/H Circuit Comparator
a good idea for electric vehicle, especially for high-voltage Vin1 +
process. This idea had been published in [3] by integrating CS
-
the permanent-magnet synchronous motor (PMSM) with a
ġ

Vin2 +
10-bit SAR ADC. CS
-
Digital
SAR Output
ġ

Fig. 1 shows the proposed control circuit of electric Vin3 + Controller

CS 10
vehicle for BLDC motor, which is composed of digital -
ġ

controller, gate driver, detectors, SAR ADC, channel register, Vin4 +

Input Data
DC-DC buck converter, and brushless DC motor (BLDC CS
-
ġ

Motor) with inverter. The multi-channel detectors are used to

VDAC
detect and monitor those useful parameters, including average C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
DAC
current, peak current, over current, temperature, speed, and so S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
reset
on. After those sensing data have been digitalized with SAR
ADC, the digital control code can be fed into the controller Ť
ġ

Vref
and generates an appropriate pulse-width modulation (PWM)
signal to control the gate driver and to drive the BLDC motor Fig. 2 Schematic of the proposed SAR ADC with multiple inputs for BLDC
motor drive.
smoothly. The rest of this paper is organized as follows.

978-1-7281-9362-5/20/$31.00 ©2020 IEEE 224

DOI 10.1109/IS3C50286.2020.00065

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 Fig. 3 depicts the proposed sample and hold circuit, which P-type Pre-amplifier
is a constant Vgs switch. It is made of a sampling capacitor VDD
Vbias_P
CS and a simple NMOS MA9 driven by the boosted driver to MP9
achieve both low power and a wide bandwidth. The boosted
driver produces a periodical output switching between CLK
MP10
VDD+Vin and the input voltage Vin. Two PMOSs, MA3 and VINN VINP
MA5, are utilized to alleviate the errors induced by the charge MP11
0 1
injection and clock feed-through because they conduct PN 1 0
MP12
PP
interactively. If clk = 0, then MA4 and MA8 turn on CLK
MP14
simultaneously. Next, the MA3 turns on because MA7 and MP13
MA8 are connected to ground. The sampling capacitor C S is

ġ
charged to VDD rapidly. Besides, MA5 turns off by PNĨ PPĨ
connecting to VDD through MA1 and two NMOSs, MA6 and
MA9, are off by setting to ground through MA7 and MA8. VDD
Contrarily, if clk = 1, the MA5 turns on by setting the gate of ML2 ML4
MA5 to ground through MA2 and the source of MA5 to VDD, 1
0
simultaneously. Note that both voltages, VDD and ground, are VOUTN
0 1
ML7 ML8 ML9 ML10 V 1
stored in the sampling capacitor CS in previous clock (clk = 1 OUTP
0 0
0). After the MA5 turns on, the MA6 will be turned on. Thus,
CLK CLK
the lower plate of Cs is connected to the input voltage Vin
ML1 ML3
through MA6, and the upper plate of C S will be lifted up to ML5 ML6 Latch

ġ
VDD+Vin. Passing through MA5, the gate-source voltage Vgs
of MA9 is fixed to VDD regardless of the variation of input VDD
voltage Vin. That is, the output voltage Vout would not be
adversely affected by the errors of MA6 and MA9, which are MN13
MN14
induced by charge injection and clock feed-through [2]. NN NP
1 0
A binary-weighted capacitive digital analog converter
VINN MN11 VINP
(DAC) is considered to complete the required DAC circuit. 0 1
The capacitive DAC architecture performs with high density MN12
CLK
and high accuracy by combining the properties of the binary- MN10
weighted and the serial charge-redistribution DACs [4]. This Vbias_N
MN9
architecture operates with low integral nonlinearity (INL),

VDD ġ
N-type Pre-amplifier

Fig. 5 Complementary-input double-tail latch-type voltage comparator.

MA3 clk

MA5 good matching, and high tolerance to parasitic capacitance

MA1 [4]. The designed DAC allows an efficient optimization
MA7 MA8 based on the specifications of chip area, conversion speed,
ġ

GND and linearity. Fig. 4 shows the adopted 10-bit binary-

weighted capacitive DAC with 11 capacitors denoted by C =
MA2 {C0, C1, …, C10} with a ratio of C0: C1: C2: …: C10 be 1: 1:
CS MA6 MA9 21: 22: …: 29, respectively [5].
Vout Fig. 5 presents the proposed complementary-input
double-tail latch-type voltage comparator. If the clock signal
MA4 Vin CLK is set to 0, both NMOS transistors, ML5 and ML6, turn
clk clk on simultaneously and the differential outputs, VOUTN and
VOUTP, are connected to ground. The reset function is
ġ

GND completed. In the meantime, MN10, MN13, and MN14 turn

Fig. 3 Schematic of the proposed sample and hold circuit. off, on, and on, respectively. Both outputs, NN and NP, are
pulled up to VDD. Similarly, MP10, MP13, and MP14 turn
VDAC To comparator off, on, and on, respectively, and both P N and PP are
connected to ground. Next, PN’ is connected to VDD, so does
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
PP’. Then four PMOS transistor, ML7-ML10, turn off. Both
outputs, VOUTN and VOUTP, are connected to ground stably and
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 save the static power consumption. In the comparing mode,
the clock signal (CLK) is set to VDD (1). Both MP10 and
MN10 turn on and those outputs, P N, PP, NN, and NP, can be
ġ

VREF determined with two inputs, VINN and VINP. If VINP > VINN,
Fig. 4 10-bit binary-weighted capacitive DAC. then the voltage of NP is low (0) and ML10 conducts. Thus,
the positive output VOUTP is high (1) and ML1 conducts. The

225

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negative output VOUTN is low (0). Note that the discharge
speeds of outputs, NN, NP, PN’ and PP’, are different due to
the voltage difference between two inputs, V INN and VINP.
Besides, if the input VINP is high (1) and the VINN is low (0),
then the output VOUTP is high (1) and the VOUTN is low (0).
This result verifies that the proposed comparator performs
with positive feedback to achieve the latch function quickly.
Fig. 6 presents the signal generation circuit of DAC
switch Sn with integer n from 1 to 10. As shown in Fig. 6, the
Q0 and Qn are generated. The input signal of comp_end is the
exclusive OR (XOR) function of VOUTP and VOUTN, which are
shown in Fig. 5. The RST signal is generated with clock
signal (clk), logic circuit, and nonoverlap circuit. Fig. 7
shows the simulated waveforms of DAC switches. The
proposed circuit works correctly.
Qn
VOUTP
D Q
Comp_end
Qn
clr
Q0 RST
Fig. 6 Signal generation circuit of DAC switch Sn.
Fig. 7 Simulated waveforms of DAC switches.
Fig. 8 Simulated power spectrum density (PSD) of the proposed sample and
hold circuit.
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III. SIMULATED RESULTS
Fig. 8 shows the simulated power spectrum density (PSD)
of the proposed sample and hold circuit. The 8192-point FFT
simulation presents that the simulated SFDR is 71.51 dB,
which is equal to 11.59 bits, at the input frequency of 100
kHz, the sampling frequency of 5 MS/s, the power supply of
3.3 V, and the power consumption of 10.89 PW.
Fig. 9 shows the post-layout-simulated PSD of the
proposed SAR ADC. The simulated SNDR is about 65.88 dB
and the ENOB is roughly 10.65 bits at the input frequency of
100 kHz. The simulation also presents that the differential
non-linearity (DNL) is +0.062/-0.501 dB, the integral non-
linearity (INL) is +0.936/-0.081 dB, the power consumption
is 833 PW, and the chip area is roughly 1.35 u 0.98 mm2 at
TT corner. The proposed SAR ADC operates without missing
code. Table I summarizes the post-layout-simulated results of
the proposed SAR ADC with three design corners. The
SNDR and ENOB perform uniformly. The simulated
Sn performance of the proposed SAR ADC satisfies the required
specification without missing code.
Fig. 10 shows the measured ENOBs with respect to the
input frequency at the sampling frequency of 0.909 MS/s.
The measured ENOBs perform uniformly from 10 kHz to 110
kHz and the maximum SNDR occurs at 110 kHz. Note that
the post-layout-simulated SNDR of 65.88 dB can be
compared with the measured SNDR of 50.56 dB; the main
difference was generated from the complementary-input
double-tail latch-type voltage comparator. This was achieved
by setting two bias voltages, Vbias_N and Vbias_P, to 0.8 V and
2.5 V, respectively. The measured DNL varies from +0.99
LSB to -0.625 LSB and the measured INL changes from
+1.28 LSB to -0.173 LSB. The proposed SAR ADC operates
without missing code even though the measured INL is larger
than 1.0 LSB.ġ The sampled-and-held voltage VS/H was
seriously affected by the clock feedthrough phenomenon
from N-type and P-type input stages. This impact caused the
discrepancy between the measured and simulated SNDRs.
All the characteristics of the proposed 10-bit 0.909-MHz
dual-mode SAR ADC for BLDC motor drive are successfully
verified. The performance comparison presented that the
measured ENOB of this study is superior to those of refs. [6]
-[8] and the power consumption of this chip is lower than
those of SAR ADCs in [9]-[11].
TABLE I
POST-LAYOUT-SIMULATED RESULTS OF THE PROPOSED SAR ADC WITH
THREE DESIGN CORNERS
Corners TT FF SS
Supply Voltage (V) 3.3 3.96 2.64
SNDR (dB) 65.88 64.19 65.74
ENOB (bits) 10.65 10.37 10.63
DNL (LSB) 0.062/-0.501 0.062/-0.500 0.068/-0.500
INL (LSB) 0.936/-0.081 0.979/-0.040 0.936/-0.080
Power (μW) 833 1259 556
Sampling Cap. (pF) 2.01
Chip Area (mm2) 1.35 u 0.98
Max. Frequency (MHz) 25.0
226

Fig. 9 Post-layout-simulated PSD of the proposed SAR ADC.
Fig. 10 Measured ENOBs with respect to the input frequency from 10 kHz
to 110 kHz at the sampling frequency of 0.909 MS/s.
IV. CONCLUSION
In this study, we proposed a 10-bit 2.27-MHz dual-mode
SAR ADC for BLDC motor drive. The proposed sample and
hold circuit is made of a sampling capacitor and a simple
NMOS driven by the boosted driver to achieve both low
power and a wide bandwidth. A dynamic latch-type
comparator is utilized to latch the output at upper or lower
level. The advantage of the designed comparator is that it
performs with positive feedback to quickly complete the latch
function. The double-tail latch-type architecture is utilized to
mitigate the significant kickback effect by separating the pre-
amplifier stage from the latch. By integrating an input NMOS
transistor with an input PMOS transistor, the designed latch-
type comparator can perform with full-swing input voltage.
By integrating the sample and hold circuit, digital-to-analog
converter, latch-type voltage comparator, and successive
approximation register (SAR) into a whole chip of SAR ADC,
the post-layout simulation proved that the SNR was 65.88 dB
and the ENOB was 10.65 bits at an input frequency of 100
kHz and a sampling rate of 2.27 MHz. The main advantages
of the proposed dual-mode SAR ADC are its low power
consumption of 833 PW and high measured resolution of
8.11 bits. Owing to the industrial requirement, this study was
limited to design in TSMC 0.25 μm 1P3M CMOS process. In
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future projects, we not only significantly improve the
performance of the proposed SAR ADC in an advanced
CMOS process, but also effectively mitigate the effects of
clock feedthrough error, process variation, and thermal noise.
ACKNOWLEDGMENT
The authors would like to thank the Ministry of Science
and Technology, Taiwan, for financially supporting this
research under Contract MOST 108-2221-E-027-092. They
are grateful to the Taiwan Semiconductor Research Institute
(TSRI), Taiwan, for fabricating the test chip.
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