TABLE 6.

3
Field Effect Transistors

Symbol and Input Resistance

Type Basic Relationships Transfer Curve and Capacitance
JFET
(n-channel)

Ri 7 100 M
Ci: (1 - 10) pF

MOSFET
depletion type
(n-channel)

Ri 7 1010 
Ci: (1 - 10) pF

MOSFET
enhancement type
(n-channel)

Ri 7 1010 
Ci: (1 - 10) pF

MESFET
depletion type
(n-channel)

Ri 7 1012 
Ci: (1 - 5) pF

MESFET
enhancement type
(n-channel)

Ri 7 1012 
Ci: (1 - 5) pF
416 FIELD-EFFECT 6. The transfer characteristics (ID versus VGS) are characteristics of the device itself and
TRANSISTORS are not sensitive to the network in which the JFET is employed.
7. When VGS = VP>2, ID = IDSS >4; and at a point where ID = IDSS >2, VGS ⬵ 0.3 V.
8. Maximum operating conditions are determined by the product of the drain-to-source
voltage and the drain current.
9. MOSFETs are available in one of two types: depletion and enhancement.
10. The depletion-type MOSFET has the same transfer characteristics as a JFET for drain
currents up to the IDSS level. At this point the characteristics of a depletion-type MOSFET
continue to levels above IDSS, whereas those of the JFET will end.
11. The arrow in the symbol of n-channel JFETs or MOSFETs will always point in to the
center of the symbol, whereas those of a p-channel device will always point out of
the center of the symbol.
12. The transfer characteristics of an enhancement-type MOSFET are not defined by
Shockley’s equation but rather by a nonlinear equation controlled by the gate-to-source
voltage, the threshold voltage, and a constant k defined by the device employed. The
resulting plot of ID versus VGS rises exponentially with incrseasing values of VGS.
13. Always handle MOSFETs with additional care due to the static electricity that exists
in places we might least suspect. Do not remove any shorting mechanism between the
leads of the device until it is installed.
14. A CMOS (complementary MOSFET) device employs a unique combination of a p-
channel and an n-channel MOSFET with a single set of external leads. It has the
advantages of a very high input impedance, fast switching speeds, and low operating
power levels, all of which make it very useful in logic circuits.
15. A depletion-type MESFET includes a metal–semiconductor junction, resulting in char-
acteristics that match those of an n-channel depletion-type JFET. Enhancement-
type MESFETs have the same characteristics as enhancement-type MOSFETs. The
result of this similarity is that the same type of dc and ac analysis techniques can be
applied to MESFETs as was applied to JFETs.

Equations
JFET:
VGS 2
ID = IDSS a 1 - b
VP
IDSS
ID = IDSS 0 VGS = 0 V, ID = 0 mA 0 VGS = VP, ID = ` , VGS ⬵ 0.3VP 0 ID = IDSS>2
4 VGS = VP>2
ID
VGS = VP a 1 - b
A IDSS
PD = VDSID
ro
rd =
(1 - VGS >VP)2
MOSFET (enhancement):
ID = k(VGS - VT)2
ID(on)
k =
(VGS(on) - VT)2

6.15 COMPUTER ANALYSIS

●
PSpice Windows
The characteristics of an n-channel JFET can be displayed using the same procedure
employed for the transistor in Section 3.13. The series of curves across the characteristics
plotted against various values of voltage requires a nested sweep within the sweep for the
drain-to-source voltage. The required configuration of Fig. 6.51 is constructed using pro-
cedures described in the previous chapters. In particular, note the complete absence of
resistors since the input impedance is assumed to be infinite, resulting in a gate current of 0 A.
 TABLE 7.1
FET Bias Configurations

Type Configuration Pertinent Equations Graphical Solution

VDD ID
RD IDSS
JFET VGSQ = - VGG
Fixed-bias RG VDS = VDD - IDRS Q-point
VGG –
+ VP VGG 0 VGS

ID
VDD
IDSS
RD
JFET VGS = - IDRS
I'D
Self-bias VDS = VDD - ID(RD + RS) Q-point
RG RS
VP V' 0 VGS
GS

VDD ID
R2VDD IDSS
JFET R1 RD VG =
R1 + R2 VG
Voltage-divider
VGS = VG - IDRS Q-point RS
bias R2 RS
VDS = VDD - ID(RD + RS)
VP 0 VG VGS

VDD ID
RD IDSS
JFET VGS = VSS - IDRS VSS
Q-point
Common-gate VDS = VDD + VSS - ID(RD + RS) RS
RS
–VSS VP 0 VSS VGS

ID
VDD VGS = - IDRS IDSS
RD
JFET VD = VDD
(RD = 0 ⍀) VS = IDRS I'D
Q-point
VDS = VDD - ISRS
VP V'GS 0 VGS

VDD ID
RD Q-point IDSS
JFET
VGSQ = 0 V
Special case VGS = 0 V
IDQ = IDSS Q
(VGSQ = 0 V) RG
VGG
VP 0 VGS

ID
VDD
Depletion-type Q-point
MOSFET VGSQ = + VGG IDSS
Fixed-bias RG VDS = VDD - IDRS
RS
(and MESFETs)
VP 0 VGG VGS

VG ID
Depletion-type VDD R2VDD
MOSFET R1 RD VG = RS Q-point
R1 + R2 IDSS
Voltage-divider
R2 VGS = VG - ISRS
bias RS
VDS = VDD - ID(RD + RS)
(and MESFETs) VP 0 VG VGS

VDD ID
Enhancement VDD
RD RD
type MOSFET RG ID(on)
VGS = VDS
Feedback Q-point
VGS = VDD - IDRD
configuration
(and MESFETs) 0 VGS(Th) VDD VGS
VGS(on)

Enhancement VDD VG ID
R2VDD RS
type MOSFET RD
R1 VG =
Voltage-divider R1 + R2 Q-point
bias R2 RS VGS = VG - IDRS
(and MESFETs) 0 VGS(Th) VG VGS

450
 6. The method of analysis applied to depletion-type MOSFETs is the same as applied to COMPUTER ANALYSIS 471
JFETs, with the only difference being a possible operating point with an ID level
above the IDSS value.
7. The characteristics and method of analysis applied to enhancement-type MOSFETs
are entirely different from those of JFETs and depletion-type MOSFETs. For values
of VGS less than the threshold value, the drain current is 0 A.
8. When analyzing networks with a variety of devices, first work with the region of the
network that will provide a voltage or current level using the basic relationships asso-
ciated with those devices. Then use that level and the appropriate equations to find other
voltage or current levels of the network in the surrounding region of the system.
9. The design process often requires finding a resistance level to establish the desired volt-
age or current level. With this in mind, remember that a resistance level is defined by the
voltage across the resistor divided by the current through the resistor. In the design
process, both of these quantities are often available for a particular resistive element.
10. The ability to troubleshoot a network requires a clear, firm understanding of the termi-
nal behavior of each of the devices in the network. That knowledge will provide an
estimate of the working voltage levels of specific points of the network, which can be
checked with a voltmeter. The ohmmeter section of a multimeter is particularly helpful
in ensuring that there is a true connection between all the elements of the network.
11. The analysis of p-channel FETs is the same as that applied to n-channel FETs except
for the fact that all the voltages will have the opposite polarity and the currents the
opposite direction.

Equations
JFETs/depletion-type MOSFETs:
Fixed@bias configuration: VGS = -VGG = VG
Self@bias configuration: VGS = -ID RS
R2VDD
Voltage@divider biasing: VG =
R1 + R2
VGS = VG - ID RS
Enhancement-type MOSFETs:
Feedback biasing: VDS = VGS
VGS = VDD - ID RD
R2VDD
Voltage@divider biasing: VG =
R1 + R2
VGS = VG - ID RS

7.17 COMPUTER ANALYSIS

●
PSpice Windows
JFET Voltage-Divider Configuration The results of Example 7.19 will now be verified
using PSpice Windows. The network of Fig. 7.72 is constructed using computer methods
described in the previous chapters. The J2N3819 JFET is obtained from the EVAL library,
and Edit-PSpice model is used to set Beta to 0.222 mA/V2 and Vto to -6 V. The Beta
value is determined using beta = IDSS > VP2 Eq. (6.17) and the provided IDSS and VP. The
results of the Simulation appear in Fig. 7.73 with the dc bias voltage and current levels.
The resulting drain current is 4.225 mA, compared to the calculated level of 4.24 mA—an
excellent match. The voltage VGS is 3.504 V - 5.070 V = -1.57 V versus the calculated
level of -1.56 V in Example 7.19—another excellent match.

Combination Network Next, the result of Example 7.12 with both a transistor and JFET
will be verified. For the transistor Bf is set to 180, whereas for the JFET, Beta is set to
0.333 mA/V2 and Vto to -6 V as called for in the example. The results for all the dc levels
appear in Fig. 7.73. Note again the excellent comparison with the calculator solution, with
VD at 11.44 V compared to 11.07 V, VS = VC at 7.138 V compared to 7.32 V, and VGS at
3.380 V - 7.138 V = ⫺3.76 V compared to -3.7 V.
 TABLE 8.1
Zi, Zo, and Av for various FET configurations

Configuration Zi Zo Vo
Av =
Vi
Fixed-bias
[JFET or D-MOSFET]
Fixed-bias +VDD
[JFET or D-MOSFET] Medium (2 k) Medium (- 10)
RD
C2 High (10 M)
C1
Vo = RD 储 r d = - gm(rd 储 RD)
Vi = RG
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
RG (rd Ú 10 RD)
Zi
–V
GG
+
Self-bias
bypassed RS
[JFET or D-MOSFET]
Self-bias +VDD
bypassed RS Medium (2 k) Medium (- 10)
[JFET or D-MOSFET] RD High (10 M)
C2
Vo = RD 储 r d = - gm(rd 储 RD)
C1 = RG
Vi
Zo ⬵ RD ⬵ - gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Zi
RG
RS CS

Self-bias
unbypassed RS
[JFET or D-MOSFET]
Low (- 2)
Self-bias +VDD RS
unbypassed RS c 1 + gmRS + dR
rd D gmRD
[JFET or D-MOSFET] RD High (10 M) = =
C2 RS RD RD + RS
Vo c 1 + gmRS + + d 1 + gmRS +
C1 = RG rd rd rd
Vi
Zo
= RD gmRD
Zi rd Ú 10 RD or rd =   ⬵ -
RG 1 + gmRS 3 rd Ú 10 (RD + RS)4
RS

Voltage-divider bias
[JFET or D-MOSFET]
Voltage-divider bias +VDD
[JFET or D-MOSFET]
Medium (2 k) Medium (- 10)
RD High (10 M)
C2
R1
Vo = RD 储 r d = - gm(rd 储 RD)
C1
Vi = R1 储 R2
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
(rd Ú 10 RD)
Zi
R2
RS CS

514
 TABLE 8.1
(Continued)

Configuration Zi Zo Vo
Av =
Vi
Common-gate
[JFET or D-MOSFET]
Medium (+ 10)
Common-gate +VDD Low (1 k⍀)
[JFET or D-MOSFET] Medium (2 k⍀) RD
RD r d + RD gmRD +
C1 Q1 C2 = RS 储 c d rd
1 + gmrd = RD 储 r d =
Vi Vo RD
1 +
⬵ RD rd
1
Zi RS Zo ⬵ RS 储 (Rd Ú 10 RD)

RG CS gm ⬵ gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Source-follower
[JFET or D-MOSFET]
Low ( 6 1)
Source-follower Low (100 k⍀)
[JFET or D-MOSFET] +VDD
High (10 M⍀) gm(rd 储 RS)
C1 = rd 储 RS 储 1>gm =
Vi 1 + gm(rd 储 RS)
C2 = RG
Zi RG
Vo ⬵ RS 储 1>gm gmRS
RS
(rd Ú 10 RS)
⬵
Zo
1 + gmRS
(rd Ú 10 RS)

Drain-feedback bias
E-MOSFET
Drain-Feedback bias +VDD Medium (1 M⍀)
E-MOSFET Medium (2 k⍀) Medium (- 10)
RD RF + r d 储 RD
RF C2 = = RF 储 r d 储 RD = - gm(RF 储 rd 储 RD)
Vo 1 + gm(rd 储 RD)
C1
Vi RF ⬵ RD ⬵ - gmRD
(RF, rd Ú 10RD)
Zo ⬵ (RF, rd Ú 10RD)
1 + gmRD
Zi (rd Ú 10 RD)

Voltage-divider bias
E-MOSFET
Voltage-divider bias +VDD
E-MOSFET
Medium (2 k⍀) Medium (−10)
RD
C2 Medium (1 M⍀)
R1 D Vo
= RD 储 r d = - gm(rd 储 RD)
C1
G = R1 储 R2
Vi
Zo ⬵ RD ⬵ - gmRD
S (rd Ú 10 RD) (rd Ú 10 RD)
Zi R2 RS

515
518 FET AMPLIFIERS and

AvS =
Vo
= # = c RG d [-gm(rd 储 RD 储 RL)]
Vi Vo
(8.64)
Vs Vs Vi RG + Rsig

which for most applications where RG W Rsig and RD 储 RL V rd results in

AvS ⬵ -gm(RD 储 RL) (8.65)

If we now turn to the two-port approach for the same network, the equation for the overall
gain becomes
RL RL
AvL = AvNL = [-gm(rd 储 RD)]
RL + Ro RL + Ro
but Ro = RD 储 rd,
RL (rd 储 RD)(RL)
so that AvL = [-gm(rd 储 RD] = -gm
RL + RD 储 rd (rd + RD) + RL
and AvL = -gm(rd 储 RD 储 RL)
matching the previous result.
The above derivation was included to demonstrate that the same result will be obtained
using either approach. If numerical values for Ri, Ro, and AvNLwere available, it would
simply be a matter of substituting the values into Eq. (8.57).
Continuing in the same manner for the most common configurations results in the equa-
tions of Table 8.2.

8.15 CASCADE CONFIGURATION

●
The cascade configuration introduced in Chapter 5 for BJTs can also be used with JFETs
or MOSFETs, as shown for JFETs in Fig. 8.47. Recall that the output of one stage appears
as the input for the following stage. The input impedance for the second stage is the load
impedance for the first stage.
The total gain is the product of the gain of each stage including the loading effects of
the following stage.
Too often, the no-load gain is employed and the overall gain is an unrealistic result. For
each stage the loading effect of the following stage must be included in the gain calcula-
tions. Using the results of the previous sections of this chapter results in the following
equation for the overall gain of the configuration of Fig. 8.47:

Av = Av1Av2 = (-gm1RD1)(-gm2RD2) = gm1gm2 RD1RD2 (8.66)

FIG. 8.47
Cascaded FET amplifier.
518
 TABLE 8.2

Configuration AvL ⴝ Vo 储 Vi Zi Zo

- gm(RD 储 RL) RG RD

+
Vss Including rd:
–
- gm(RD 储 RL 储 rd) RG RD 储 r d

- gm(RD 储 RL) RG RD
1 + gmRS 1 + gmRS

Including rd:
+
Vs - gm(RD 储 RL) RD
– RG ⬵
RD + RS 1 + gmRS
1 + gmRS +
rd

- gm(RD 储 RL) R 1 储 R2 RD

+
Vs Including rd:
–
- gm(RD 储 RL 储 rd) R 1 储 R2 RD 储 r d ;

gm(RS 储 RL) RG RS 储 1>gm

1 + gm(RS 储 RL)

+ Including rd:
Vs RS
– gmrd(RS 储 RL) gmrdRS
= RG 1 +
rd + RD + gmrd (RS 储 RL) r d + RD

gm(RD 储 RL) RS RD
1 + gmRS
+
Including rd: RS
Vs Zi = RD 储 r d
– gmrdRS
⬵ gm(RD 储 RL) 1 +
r d + RD 储 RL

519