ADDC LAB Question Bank-21EC34

1 a Realize Binary adder/ subtractor using IC-7483.

b Design 4-bit Johnson using Verilog and implement using FPGA.

2 a Realize the given Boolean expression using IC-74153 on IC-trainer

kit.
F1=∑m(2,3,4,6,7)
F1=∑m(0,1,5,7)
b Design of 3-bit Synchronous up counter using Verilog and perform
functional simulation.

3 a Realize the full adder using IC-74139 on IC-trainer kit.

b Realize D,T flip flops using Verilog code.

4 a Design and write VERILOG code for Universal shift register for the
following operations and perform functional simulation.
S(S1S0) Operation Description
00 Q=Q Hold
01 Q=Q[2:0],SDL Shift left
10 Q=SDR,Q[3:1] Shift right
11 Q=D Parallel Load
b Design a full adder using IC-74139 on IC -trainer kit.

5 a Realize JK flip flop in Verilog using behavioural modelling and

implement using FPGA board.
b Realize Binary subtractor using NAND gates on IC trainer Kit.
6 a Design of synchronous 3-bit up counter using IC-74112 on IC trainer
kit.
b Realize 1X4 DEMUX in Verilog code.

7 a Design of a synchronous counter for the following count sequence:

4-6-7-3-1----4-6……. (Avoid Lock out condition) using IC trainer kit.
b Design an 8X1 multiplexer using Verilog code.

8 a Design mod-10 counter using IC74192.

b Design a 4-bit ripple carry adder using Verilog code and implement
using FPGA.

9 a Design mod-16 counter using IC74193.

b Design a 4-bit carry lookahead adder using Verilog code and
implement using FPGA.

10 a Design 8:3 Priority encoder using Verilog code.

b Design of synchronous 3-bit up counter using IC-74112 on IC trainer
kit.

11 a Design and write VERILOG code for 4 - bit BCD counter with
Asynchronous Reset.
b Realize the given Boolean expressions using IC-74153 and perform
functional simulation.
F1=∑m( 1,2,4,7) and F2=∑m( 0,4,5,6)
12 a Design and write VERILOG code for 4 - bit Synchronous binary
counter.
b Realize the given Boolean expressions using IC-74139 and perform
functional simulation.
F1=∑m( 1,2,4,7) and F2=∑m( 0,4,5,6)

13 a Design and write VERILOG code for Universal shift register for the
following operations and perform functional simulation.

S(S1S0) Operation Description

00 Q=Q Hold
01 Q=Q[2:0],SDL Shift left
10 Q=SDR,Q[3:1] Shift right
11 Q=D Parallel Load
b Design a full adder using NAND gates on IC trainer kit. And verify
the functionality.

14 a Design 2:4 decoder and 8:3 encoder using Verilog code.

b Design of synchronous 3-bit up counter using IC-74112 on IC trainer
kit.

15 a Realize T flip flop in Verilog using behavioural modelling and

implement using FPGA board.
b Realize Binary adder/ subtractor using IC-7483 on IC trainer kit.

16 a Design a sequence detector to detect 101 using Verilog code.

b Realize the given Boolean expressions using IC-74153 and perform
functional simulation.
F1=∑m( 1,2,4,7).
3. Realize the full adder using IC-74139 on IC-trainer kit.
https://youtu.be/55fhIff9d4g?si=fxkLXwE6ldMgrm9A

S(A, B, Cin)= (A’B’C) + (A’BC’) + (AB’C’) +(ABC)

Cout(A,B,Cin) = (A’BC) + (AB’C) + (ABC’) + (ABC)
which is,
S(A,B,Cin) = ∑(1,2,4,7)
Cout(A,B,Cin) = ∑(3,5,6,7)