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20200409_
20200409_
SZ FAE Lori
Mar. 2020
rev 20180504
Outlines
• Basic terminologies
1.6
1.55
0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 160.0 180.0 200.0
Load Current (A)
Protocols: SVID/SVI2/3/OVR/PVID/AVS/PMBUS
• SVID Intel
• SVI2/3 AMD
• OVR NVidia
• AVS Arm-base IC
Digital PID
Remote sense
s s
VOSEN 1 1 PWM
G
X1 ADC z1 z2
DPWM
s
VORTN s 1
p
Non-Linear Transient
Loop
Dual Loop COT Control
• One fast loop takes care of both steady state and load transient
• MPS patented Technology-Simple, Fast and Fully Digital.
VID
DAC
Remote sense Digital Ramp
VOSEN set PWM
Digital
X1 Cmp
TON
VORTN
200MHz
Clock
DAC
DC Calibration
Digital COT Control – Steady State
Digital COT Control – Load Step Up
Digital COT Control – Load Step Down
Multiphase VR Current Balance
Intelli-Phase Current Sense Principle
VTEMP/FLT
AGND
SYNC
PWM
VCC
BST
CS
21 20 19 18 17 16 15
VIN 1 14 VIN
SW 2
13 PGND
SW 3
12 PGND
SW 4
5 6 7 8 9 10 11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
On-Die Current Sense Advantages
On-Die Current Sense Advantages
Current Balance Introduce
Current Balance Introduce
• Why dynamic current sharing for multiphase is difficult for voltage and current control
• In load step up mode, the leading phase would increase PWM on time dramatically, but
due to PWM switching cycle delay, the lagging phase supports less current
• Huge current stress on one phase during fast load step up
Load
Current
VOUT
COMP
IL1 IL2
Current Balance Introduce
Vref
Phase
Fixed On Min off time
blanking time
• PWMs are evenly distributed to each Time