Malnad College of Engineering, HASSAN-573202

(An Autonomous Institution Affiliated to VTU, Belagavi)

VLSI VALUE ADDED COURSE

Report on

DESIGN OF POWER AND AREA EFFICIENCY CODE

FOR REAL TIME DIGITAL CLOCK WITH HOURS,
MINUTES AND SECONDS DISPLAY

BY
MOHITH AM - 4MC21EC061
RAGHUVEER - 4MC21EC080
MALLIKARJUN - 4MC21EC055
RITESH PATIL - 4MC21EC082

TO
PRATHIK MEHTA,
VLSI TRINER,
CRANES VARSITY.
 NOTES

DIGITAL CLOCK MODULE DESIGN

AND IMPLEMENTATION

Table of Contents

Introduction
Design Specifications
Clock Divider Circuit
Seconds Counter
Minutes Counter
Hours Counter
Simulation Results and Verification
Conclusion
1. INTRODUCTION

The digital clock module presented in this report is designed to provide a real-time display of
hours, minutes, and seconds. It operates based on a system clock input (clk) and incorporates
an asynchronous reset (reset) to initialize the time to zero when activated. The module
outputs three registers: hours, minutes, and seconds, each with specific bit widths to
accommodate the time format (5 bits for hours, and 6 bits each for minutes and seconds).

This report details the design methodology, implementation strategy, and verification steps
of the digital clock module using Verilog hardware description language. It covers the clock
divider circuit used to generate a 1 Hz pulse from the system clock, as well as the counters for
seconds, minutes, and hours.

2. Design Specifications

Input and Outputs

Inputs:

clk: System clock input.

reset: Asynchronous reset input.

Outputs:

hours: 5-bit output representing hours (0-23).

minutes: 6-bit output representing minutes (0-59).
seconds: 6-bit output representing seconds (0-59).

Operation:

The digital clock module operates as follows:

Clock Divider: Converts the high-frequency system clock (clk) into a 1 Hz pulse
(second_tick), which serves as the basis for updating the seconds counter and triggering
updates for minutes and hours.

Seconds Counter: Increments the seconds register on each rising edge of second_tick. Resets
to zero on a reset signal or when reaching 59 seconds.
Minutes Counter: Increments the minutes register when seconds reaches 59. Resets to zero on
reaching 59 minutes.

Hours Counter: Increments the hours register when both minutes and seconds reach 59.
Resets to zero after 23 hours (rolling over to 0).

3. Clock Divider Circuit

The clock divider circuit is essential for generating a 1 Hz signal (second_tick) from the
system clock (clk). This ensures that the seconds counter increments once per second.

Implementation:

reg [31:0] clk_divider;

wire second_tick;

always @(posedge clk or posedge reset) begin

if (reset) begin
clk_divider <= 32'b0;
second_tick <= 1'b0;
end else begin
if (clk_divider == 32'd49999999) begin // Assuming 50 MHz system clock
clk_divider <= 32'b0;
second_tick <= 1'b1;
end else begin
clk_divider <= clk_divider + 1;
second_tick <= 1'b0;
end
end
end

Description:

Reset Condition: Initializes clk_divider and second_tick to zero on reset.

Increment Condition: Checks if clk_divider has reached the desired count (50 million
cycles for a 50 MHz clock) to toggle second_tick high.

Resetting clk_divider: Resets clk_divider to zero after reaching the count threshold to
restart the counting process.
4. Seconds Counter

The seconds counter increments the seconds register on each rising edge of second_tick. It
resets to zero on a reset signal or when seconds reaches 59.

Implementation:

always @(posedge second_tick or posedge reset) begin

if (reset) begin
seconds <= 6'b0;
end else if (seconds == 6'd59) begin
seconds <= 6'b0;
end else begin
seconds <= seconds + 1;
end
end

Description:

Reset Condition: Initializes seconds to zero on reset.

Increment Condition: Increments seconds by 1 when second_tick occurs, unless seconds

is already at 59, in which case it resets seconds to zero.

5. Minutes Counter

The minutes counter increments the minutes register when seconds reaches 59. It resets to
zero on a reset signal or when minutes reaches 59.

Implementation:

always @(posedge second_tick or posedge reset) begin

if (reset) begin
minutes <= 6'b0;
end else if (seconds == 6'd59) begin
if (minutes == 6'd59) begin
minutes <= 6'b0;
end else begin
minutes <= minutes + 1;
end
end
end
 NOTES
Description:

Reset Condition: Initializes minutes to zero on reset.

Increment Condition: Increments minutes by 1 when seconds reaches 59, and resets
minutes to zero when it reaches 59.

6. Hours Counter

The hours counter increments the hours register when both minutes and seconds reach 59. It
resets to zero after 23 hours (rolling over).

Implementation:

always @(posedge second_tick or posedge reset) begin

if (reset) begin
hours <= 5'b0;
end else if (seconds == 6'd59 && minutes == 6'd59) begin
if (hours == 5'd23) begin
hours <= 5'b0;
end else begin
hours <= hours + 1;
end
end
end

Description:

Reset Condition: Initializes hours to zero on reset.

Increment Condition: Increments hours by 1 when both minutes and seconds reach 59.
Resets hours to zero after reaching 23.
7. Simulation Results and Verification

Simulation Environment:
The digital clock module was simulated using a Verilog simulation environment to verify its
functionality and correctness.

Test Cases:

Reset Test: Verify that the clock initializes to 00:00:00 after a reset signal.
Counting Test: Check that the seconds, minutes, and hours counters increment correctly
over time.
Rollover Test: Ensure that the clock correctly rolls over from 23:59:59 back to 00:00:00
after reaching 23 hours.

Simulation Waveforms:

Verification:

Functionality: The simulation confirmed that the digital clock module accurately
increments seconds, minutes, and hours according to the specified design.
Reset Handling: The clock resets correctly to 00:00:00 upon activation of the reset signal.
Rollover Behavior: The clock properly rolls over from 23:59:59 back to 00:00:00 without
errors.
TESTBENCH

module testbench;

reg clk;
reg reset;
wire [3:0] q;

// Instantiate the counter

synchronous_counter uut (
.clk(clk),
.reset(reset),
.q(q)
);

// Generate clock
initial begin
clk = 0;
forever #5 clk = ~clk; // 10 time units period
end

// Test sequence
initial begin
// Apply reset
reset = 1;
#10;
reset = 0;

// Run the simulation for some time

#100;

// Finish the simulation

$finish;
end

// Monitor the output

initial begin
$monitor("At time %t, q = %b", $time, q);
end

endmodule
Explanation:

1. Module Declaration:
Inputs (reg): clk (clock input), reset (asynchronous reset).
Output (wire): q (4-bit output from the synchronous counter).

1. Counter Instantiation:
The synchronous_counter module (uut) is instantiated with connections to clk,
reset, and q.

1. Clock Generation:
An initial block generates a clock (clk) with a period of 10 time units (5 units high,
5 units low) using a forever loop.

1. Test Sequence:
An initial block initiates the reset (reset = 1), holds it for 10 time units (#10), and
then releases the reset (reset = 0).
The simulation runs for an additional 100 time units (#100) to observe the behavior
of the counter.

1. Simulation Termination:
The simulation is terminated using $finish after the specified time (#100), ensuring
the simulation ends after sufficient observation time.

2. Output Monitoring:
An initial block with $monitor displays the time ($time) and the value of q in
binary (%b) whenever there is a change in q.
This provides real-time monitoring of the counter's output during simulation.

Simulation and Verification:

Functionality: The testbench verifies that the synchronous counter correctly increments
and resets in response to the clock and reset signals.
Output Display: $monitor statements provide visibility into the counter's behavior
throughout the simulation, showing how q changes over time.
Timing and Resets: The test sequence ensures that the counter resets properly and
counts correctly after reset release (reset = 0).
8. Conclusion

The digital clock module designed and implemented in Verilog successfully meets the specified
requirements for timekeeping accuracy and functionality. By leveraging a clock divider circuit
and sequential logic for counting seconds, minutes, and hours, the module effectively
generates and maintains a real-time display.

Key features of the design include:

Clock Divider: Generates a 1 Hz signal from the system clock.

Seconds Counter: Increments seconds and resets at 59.
Minutes and Hours Counters: Increment minutes and hours based on seconds reaching 59
and reset appropriately.

Future enhancements could include:

Additional Time Formats: Support for 12-hour format and AM/PM indication.
Clock Adjustments: Capability to set and adjust the clock time programmatically.
In conclusion, the digital clock module represents a foundational component for integrating
real-time clock functionality into larger digital systems.