1.

BAUD RATE GENERATOR

Signal Name Direction Description

rst input Synchronous reset, active low

ckht input Synchronous clock.

tick output Generate pulse:

● Determine the data sampling position.
● Determine the data shift position when the transmitter
is active.

● Baud rate is the amount of time it takes for one bit to be transmitted over a UART
channel. It is expressed in bits per second (bps - bits per second).
● Baud rate divisor is calculated based on the frequency of the clock signal and the
desired Baud rate.
● Thus, the baud counter plays an important role in maintaining synchronization and
ensuring accurate data transmission speed via UART communication.

2. PROGRAM

module baudrate_generator
#(
parameter N = 8,
M = 163
)
(
input wire clk, reset,
 output wire s_tick
);

reg [N-1:0] r_reg,r_next;

always@(posedge clk, posedge reset)

begin
if(reset)
r_reg <= 8'b0;
else
r_reg <= r_next;
end

always @*
begin
if(r_reg <= M)
r_next = r_reg + 1;
else
r_next = 0;
end
assign s_tick = (r_reg == (M)) ? 1'b1 : 1'b0;
endmodule

*Program explanation

This module has two main parts:

● Frequency Counter: It uses the register r_reg to count the clock frequency.
● Baud Rate Signal Generation: Based on the value of r_reg, it generates a clock
signal with the desired frequency.
Specifically:

● In the always @(posedge clk, posedge reset) block, r_reg is updated based on
the clock signal and the reset signal.
● In the always @* block, r_next is computed based on the current value of
r_reg. If r_reg is less than or equal to M, r_next increments by 1; otherwise, it
is reset to 0.
● Finally, the s_tick signal is calculated based on the value of r_reg. If r_reg
equals M, s_tick is set to 1; otherwise, it is 01."

3. TESTBENCH

`timescale 1ns / 1ps

 module baudrate_generator_test();
localparam T = 2;
localparam N = 8;
reg clk, reset;
wire s_tick;
baudrate_generator #(.M(163), .N(8))
DUT(.clk(clk), .reset(reset), .s_tick(s_tick));
always
begin
clk = 1'b1;
#(T/2);
clk = 1'b0;
#(T/2);
end

initial
begin
reset = 1'b1;
#(T/2);
reset = 1'b0;
end

initial
begin
repeat(500) @(negedge clk);
end
endmodule

*Program explanation

Timescale 1ns / 1ps: This is a directive that sets the time unit for simulation. It defines that 1
time unit in simulation corresponds to 1 nanosecond (ns) and 1 picosecond (ps).

Module baudrate_generator_test();: This is the declaration of the baudrate_generator_test

module. In this module, you will perform testing for the baudrate_generator module.

Local parameter T = 2;: This declares a local parameter named T with a value of 2. This
parameter is used to define the clock cycle time.

Local parameter N = 8;: This declares another local parameter named N with a value of 8.
This parameter can be used within the module.

Signal declarations:
 ● reg clk, reset;: Declares two signals, clk (clock signal) and reset (reset signal).
● wire s_tick;: Declares a wire signal s_tick, which can be connected to other modules.
Instantiation of baudrate_generator module:

● baudrate_generator #(.M(163), .N(8)) DUT(.clk(clk), .reset(reset), .s_tick(s_tick));

Here, an instance of the baudrate_generator module is created. The parameters M and N are
set to 163 and 8, respectively. The signals clk, reset, and s_tick are connected to this instance.

Behavioral blocks:

● always begin ... end: Defines an infinite loop. Inside it, the clk signal toggles between
1 and 0 with a time delay of T/2.
● initial begin ... end: Defines a block executed only once. Inside it, the reset signal
toggles between 1 and 0 with a time delay of T/2.

Another initial begin ... end block: Similar to the previous one, but this time the clk signal
toggles between 1 and 0 with a time delay of T/2, followed by the reset signal toggling.
repeat(500) @(negedge clk);: This command generates 500 clock cycles with the clk signal
falling from 1 to 0.

In summary, this program generates clock and reset signals in cycles and tests the
baudrate_generator module with the given parameters. You can modify the values of M and
N to test with different settings."

4. RESULT AND EXPLANATION

The baudrate block will set the s_tick signal at a rate of 307200 ticks per second. This means
that with an input clock frequency of 50 MHz, the time interval between two ticks will be
approximately 3.255 microseconds. Additionally, we need to check whether the s_reg register
has a value of 163, whether the s_tick signal is equal to 1, and whether the counter is reset.
From this, the evaluation criteria will include the following three points:

● Each s_tick should be set approximately every 3.3 microseconds.

● s_tick should be equal to 1 when the counter reaches 163.
● The counter should reset when it reaches 163.